Define standard IOCTL commands to enable and disable analog comparator
devices from user-space applications.
Assisted-by: Gemini:gemini-2.5-pro
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Add a standalone tool to create AHAB container for imxrt118x. This can
generate a trivial unsigned image without appending ELE.
The tool can be used to create bootable images for m33. To do anything
more complicated, the user needs to use the official SPSDK tool from
NXP.
Assisted-by: Claude Code:claude-opus-5-0
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add the documentation for the new supported board configurations and for the architecture,
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This adds the initial board configurattions for building NuttX for imxrt1189-evk.
Also add a script building the NXP container image for bootloaders (m33 images)
The board boots on Cortex-M33 core, for which there are two m33 targets: nsh-m33 and bl.
- "bl" target does basic initialization of ELE and TRDC and just releases the M7 to run
at 0x20080000.
- "nsh-m33" target just boots nuttx into nsh shell on m33
- The "nsh" target is for M7 core. It can be flashed at 0x20080000, and
it boots to nsh shell with a proper bootloader on m33 (the bl target does this).
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add a function which can be called from M33 core on imx118x to start
executing on M7 core.
The function:
- Configures the M7 clock root
- Releases M7 from reset
- Asks the secure element to release the M7 (ENABLE_APC)
- Enables the M7 clock
The function is compiled in when a configuration flag
CONFIG_IMXRT_CM7_BOOT=y
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Add driver supporting the DMA3 and DMA4 in iMXRT118x chips. The driver is first copied
from imx93, and then changed just the relevant parts (function names, clocking and
irq handling) to match the imx118x configuration.
- Add the DMA channel numbering in hardware/rt118x/imxrt118x_dmamux.h from RM
by claude.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add a few !defined(CONFIG_ARCH_FAMILY_IMXRT118x) gates similar to 1176 to
buid the common drivers also for 118x variants.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Move/make sure that ep0buf is in usb dma capable memory. Especially if
.data/.bss are in TCM, the buffers need to be placed in another section.
If the section .dmamemory doesn't exist, they will end up in .data like before
- change "#ifdef CONFIG_ARCH_FAMILY_IMXRT117x" into
"#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || defined(CONFIG_ARCH_FAMILY_IMXRT118x)"
- In imxrt_epcomplete dtd->buffer0 must NOT be used to compute the data buffer's
cache-maintenance address range. The hardware advances buffer0 (and its
"current offset" low-order bits) as the transfer progresses, so by completion
time it points *past* the start of the buffer (at start + xfer_len), not at
the buffer itself. Instead, use the original privreq->req.buf when the transfer
is complete.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Small additions to existing drivers to support more UARTs
- Properly invalidate the cache over DMA RX buffer initially
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Add imxrt118x compatible IOMUX definitions, named as IOMUX_VER3. This is the
same IP as what is used for example for IMX9. Instead of directly copying the support
from imx9, pack the padconfig into the same 32-bit value used for GPIO for easy use.
- Add imxrt118x compatible rgpio driver. This is the same GPIO block as what has been used
in imx9. Instead of directly copying the support from IMX9, add pin muxing directly
into GPIO driver as well, to keep the usage compatible with existing IMXRT boards.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Initialize the internal secure element, if configured
- Initialize the TRDC, if configured
- Disable the TCM enabling code when compiling for other than Cortex-M7 chip.
This needs to be skipped for M33 core on imx118x
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
iMXRT118x uses the same security element as the imx93. Just add iMXRT specific
register definitions and port over the driver code.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The trdc driver has been copied from arm64/imx93, and modified to fit imxrt118x.
The relevant register definitions have been generated by AI from the RM.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add IMXRT AONMIX register addresses and bit definitions in a separate header file
"imxrt118x_blkctrl.h".
The header is generated using AI from imxrt118x reference manual.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Support reading the OCOTP via the shadow register on imxrt chips with integrated
ELE. On these chips, writing is done via ELE, this is not yet implemented.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add register definitions for IMXRT118x Analog-Digital top level block.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Port the ccm / clock configuration from iMX93 to iMXRT118x.
Register definitions are generated from RM using AI
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add interrupt numbering for imxrt118x in imxrt118x_irq.h, and support
for more interrupts in imxrt_irq.c and imxrt_clrpend.c.
The interrupt numbers are generated from the Reference Manual by AI
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add imxrt118x memorymaps as hardware/rt118x/imxrt118x_memorymap.h
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Only submit and account for a wrapped second TX segment when scatter/gather descriptors
are available. Without in-memory TCDs, submitting the second segment overwrites the
active hardware descriptor and incorrectly advances the serial buffer past unsent data.
- Invalidate DMA RX buffer initially
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Some SoCs have a single timer group, so a hardcoded GROUP_ID of 1
overflowed soc_timg_gptimer_signals and crashed in
periph_rcc_acquire_enter. Guard gptimer group 1 behind
TIMG_LL_GET(INST_NUM) as well.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Support USART waking from low power modes, allow keeping
HSI running in STOP mode, allow specifying clock source
for USARTs, add some missing register and field definitions.
stm32 common Kconfigs:
Add common STM32 UART config options USARTx_WAKE_FROM_LOW_POWER and USARTx_WUS
for USART to cause wake up from low power modes.
stm32h5 board configs:
Allow board.h to choose the clock source of each USART.
Allow board.h to express that HSI should continue running
in low power modes.
stm32h5 RCC:
Set the clock source for each USART if specified in the
board configs (STM32_RCC_CCIPR1_USARTxSEL).
Keep HSI on in STOP mode if specified in the board configs
(STM32_BOARD_HSIKERON_ENABLE).
stm32h5 serial driver:
Use the new USARTx_WAKE_FROM_LOW_POWER and USARTx_WUS in
stm32h5 serial driver to wake from low power modes.
Use the USART clock source specified by board configs.
Enable FIFOs.
Clear UE bit before initialization.
Co-authored-by: Javier Casas <javiercasas@geotab.com>
Co-authored-by: daniellizewski <daniellizewski@geotab.com>
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Use the HAL line-fitting APIs when curve fitting is not available.
Assisted-by: Cursor:Grok 4.6
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Fix coding style issues flagged by nxstyle in files touched by the
SO_TIMESTAMPING series. These are pre-existing issues, not introduced
by the SO_TIMESTAMPING patches:
- inet_sockif.c: missing blank lines after declarations
- ipv4_input.c: missing blank line after declaration, bad comment alignment
- can_input.c: bad indentation inside #ifdef block
- getsockopt.c: bad comment block alignment, bad brace alignment
- setsockopt.c: wrong column position of comment
- sim_netdriver.c: missing blank lines after declarations
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Add TX timestamp loopback support to the simulator network driver.
When a packet tagged with io_conn (SO_TIMESTAMPING TX) is sent,
the driver clones the packet, generates a software timestamp, and
queues it for loopback through the RX path. The protocol layer
(UDP/PKT) then delivers the timestamp via MSG_ERRQUEUE.
- Add tstampq IOB queue to sim_netdev_s for loopback packets.
- In netdriver_send(), clone timestamped packets with realtime
clock and notify RX ready.
- In netdriver_recv(), return loopback packets before reading
from the tap device.
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Add missing SCM_TIMESTAMPNS and SCM_TIMESTAMPING control message type
definitions mapped to their corresponding SO_TIMESTAMPNS and
SO_TIMESTAMPING socket options. Also align whitespace of existing
SCM_* definitions for consistency.
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Consolidate the two separate timestamp Kconfig options into a single
CONFIG_NET_TIMESTAMP option that covers SO_TIMESTAMP, SO_TIMESTAMPNS
and SO_TIMESTAMPING socket options.
Previously CONFIG_NET_TIMESTAMPING was a separate option only used by
PKT sockets for hardware TX/RX timestamps and error queue support.
Since both options guard the same io_time field in iob_s and share
the s_options bitmask, merging them simplifies configuration without
functional impact.
Changes:
- Replace all CONFIG_NET_TIMESTAMPING with CONFIG_NET_TIMESTAMP in
pkt_input.c, pkt_recvmsg.c, pkt_sendmsg_buffered.c,
pkt_sendmsg_unbuffered.c, pkt_sockif.c, pkt_netpoll.c, pkt.h,
setsockopt.c, getsockopt.c
- Simplify iob.h conditional from OR of both to single option
- Remove NET_TIMESTAMPING Kconfig entry, update NET_TIMESTAMP
description to cover all three socket options
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Remove the redundant `timestamp` field from `udp_conn_s` and use the
existing `s_options` bitmask to track SO_TIMESTAMP/SO_TIMESTAMPNS state.
The socket-level setsockopt/getsockopt already handles SO_TIMESTAMP via
_SO_SETOPT/_SO_GETOPT on s_options. The protocol-level handlers in
inet_sockif.c were intercepting the option before the socket layer,
causing s_options to never be set. This also meant SO_TIMESTAMPNS was
broken since inet_sockif.c only handled SO_TIMESTAMP.
Changes:
- Remove udp_conn_s.timestamp field from udp.h
- Remove SO_TIMESTAMP get/set handlers from inet_sockif.c, letting
them fall through to the socket-level handler
- Simplify udp_recvfrom.c to call cmsg_store_timestamp() directly,
which already checks s_options internally
- Align pkt_input.c software timestamp generation with ipv4/can by
removing per-socket SO_TIMESTAMP option check, only checking
hardware timestamp capability
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Fix a scheduling issue where MSG_ERRQUEUE readiness was
not properly waking poll waiters in pkt_netpoll.c.
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Add SO_TIMESTAMPING TX path for PKT sockets. Tagged TX
packets loop back through the driver with io_conn set,
are routed into conn->errahead, and delivered to userspace
via recvmsg(MSG_ERRQUEUE) with SO_TIMESTAMPING cmsg.
Add poll(POLLPRI) notification when errahead is non-empty.
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Replace compile-time CONFIG_ARCH_HAVE_NETDEV_TIMESTAMP with
a runtime NETDEV_RX_STAMP bit in net_driver_s.d_features.
Drivers providing hardware RX timestamps set the flag at
probe time; the stack checks it at runtime.
Signed-off-by: OceanfromXiaomi <zhaohaiyang1@xiaomi.com>
Extract a common cmsg_store_timestamp() helper that checks
SO_TIMESTAMP/SO_TIMESTAMPNS via s_options and appends the
appropriate cmsg. Replaces per-protocol timestamp formatting
in CAN, PKT, and UDP receive paths.
Signed-off-by: OceanfromXiaomi <zhaohaiyang1@xiaomi.com>
Move RX timestamp storage from net_driver_s.d_rxtime into
iob_s.io_time so each IOB carries its own timestamp through
the stack. Remove old iob_trycopyin/iob_copyout timestamp
packing in CAN/PKT/UDP paths. Fix iob_clone_partial to copy
io_time before source pointer advances to NULL.
Signed-off-by: OceanfromXiaomi <zhaohaiyang1@xiaomi.com>
Signed-off-by: wenquan1 <wenquan1@xiaomi.com>
Switch CONFIG_INIT_ENTRYPOINT from nsh_main to nxinit's init_main for
the shell-capable configs (nsh, usbnsh) of waveshare-rp2040-zero and
waveshare-rp2040-lcd-1.28. nsh now runs as a "console sh" service
started by init.rc instead of being the top-level init task.
Add etc/init.d/init.rc to the shared common/src RCSRCS, gated on
CONFIG_ETC_ROMFS && CONFIG_SYSTEM_NXINIT, so one copy covers both
boards, plus a .gitignore for the etctmp files Board.mk generates from
it. The four defconfigs also set CONFIG_SYSTEM_NXINIT=y with its
Kconfig deps, CONFIG_ETC_ROMFS=y and CONFIG_FS_ROMFS=y.
nsh_main connected the CDC/ACM gadget itself via
boardctl(BOARDIOC_USBDEV_CDCACM); init_main does not, so the usbnsh
configs would otherwise come up with no USB console. Run sercon from
init.rc and enable CONFIG_SYSTEM_CDCACM in those two defconfigs to keep
that step.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add board-level configuration and driver support for differential input
channels and auto-calibration on STM32 ADC IPv2 and IPv2G4 (STM32F3,
STM32G4), following the STM32H5 architecture pattern requested in review:
- In hardware headers (stm32_adc_v2.h and stm32_adc_v2g4.h), fix register
comments and define ADC_DIFSEL register shift and masks.
- In stm32_adc_m3m4_v1v2.c:
- Add difsel field to struct stm32_dev_s initialized from
BOARD_ADCx_DIFSEL if defined, falling back to ADC_DIFSEL_DEFAULT (0).
- Configure DIFSEL before enabling the ADC in adc_configure().
- Fix and enable adc_calibrate() for HAVE_IP_ADC_V2, supporting both
single-ended calibration (ADCALDIF=0) and differential calibration
(ADCALDIF=1) based on the channel selection.
Verified on Nucleo-G431KB (single-ended and differential channel 1).
Assisted-by: Gemini:gemini-2.5-pro
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
uart_writev() queues output one byte at a time via uart_putxmitchar().
Add uart_putxmitbuf() that memcpy()s a whole run into the TX ring buffer
and use it when no per-byte processing is needed (OPOST and ECHO clear,
not a console). On a full buffer fall back to uart_putxmitchar(), which
keeps the blocking and error handling unchanged.
8 MiB write() to /dev/ttyACM0 on nRF52840: 455 -> 573 KB/s.
Guarded by CONFIG_SERIAL_TXBULK, default !DEFAULT_SMALL.
Assisted-by: Claude Code
Signed-off-by: raiden00pl <raiden00@railab.me>
Add an API for OTP (one-time programmable) memory on stm32h5.
There are OTP APIs for non-STM32 platforms.
There is no other API for STM32 so far with these names.
Implement it in stm32h563xx_flash.c since the progmem abstraction
also lives there.
int stm32_otp_write(const uint16_t *data, uint16_t len, uint32_t offset);
int stm32_otp_read(uint16_t *data, uint16_t len, uint32_t offset);
The API allows cross-block reads/writes that don't necessarily
start/end at block boundaries.
The type of `data` is uint16_t * to express to the caller that the
pointer should be 2-aligned. The natural size of OTP words is 16 bits.
`len` is uint16_t for no strong reason. Preserve author's work.
uint32_t stm32_otp_getlockstatus(void);
Get a mask of blocks that are locked. A block being locked
is considered as being one-time programmed.
Co-authored-by: Mykhailo Sopiha <mykhailosopiha@geotab.com>
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Record the eCAP1 and eCAP2 APWM outputs in the board's Peripheral
Support list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds a PWM lower-half using the eCAP modules in APWM mode as single-channel
generators rather than capture units.
start() reprograms the time base only when the frequency changes, so a
duty-only update does not stop or zero a live counter.
t3-gem-o1 registers /dev/ecap1 and /dev/ecap2; output pad selection is left to
the board, as the candidates collide with I2C0.
Verified on t3-gem-o1: examples/pwm runs a 1 kHz, 50% duty train on both
instances and accepts a duty-only change (25% then 75%). The output pins have
not been measured on copper, as no pad is assigned to them on this board.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
