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arch/arm/imxrt: Add a function imxrt118x_release_cm7 to start M7 core
Add a function which can be called from M33 core on imx118x to start executing on M7 core. The function: - Configures the M7 clock root - Releases M7 from reset - Asks the secure element to release the M7 (ENABLE_APC) - Enables the M7 clock The function is compiled in when a configuration flag CONFIG_IMXRT_CM7_BOOT=y Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen
Xiang Xiao
parent
5b7d69307c
commit
e71c9c799a
4 changed files with 285 additions and 0 deletions
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@ -456,6 +456,11 @@ config IMXRT_ELE
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(arch/arm/src/imxrt/imxrt118x_ele.c). Present on RT118x-class
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SoCs.
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config IMXRT_CM7_BOOT
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bool
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default n
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depends on ARCH_CHIP_MIMXRT1189CVM8C_CM33
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menu "i.MX RT Peripheral Selection"
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config IMXRT_EDMA
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@ -173,3 +173,7 @@ endif
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ifeq ($(CONFIG_IMXRT_ELE),y)
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CHIP_CSRCS += imxrt118x_ele.c
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endif
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ifeq ($(CONFIG_IMXRT_CM7_BOOT),y)
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CHIP_CSRCS += imxrt118x_start_cm7.c
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endif
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236
arch/arm/src/imxrt/imxrt118x_start_cm7.c
Normal file
236
arch/arm/src/imxrt/imxrt118x_start_cm7.c
Normal file
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@ -0,0 +1,236 @@
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/****************************************************************************
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* arch/arm/src/imxrt/imxrt118x_start_cm7.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/arch.h>
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#include "arm_internal.h"
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#include "imxrt118x_ele.h"
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#include "imxrt118x_start_cm7.h"
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#include "hardware/imxrt_ccm.h"
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#include "hardware/rt117x/imxrt117x_dcdc.h"
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#include "hardware/rt118x/imxrt118x_anadig.h"
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#include "hardware/rt118x/imxrt118x_blkctrl.h"
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#include "hardware/rt118x/imxrt118x_gpc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CCM_M7_ROOT_CONFIG (CCM_CR_CTRL_MUX_SRCSEL(2) | \
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CCM_CR_CTRL_DIV(1))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: imxrt118x_pmu_enable_body_bias_fbb_cm7
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*
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* Description:
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* Enable forward body bias (FBB) on the LVT core logic. FBB is required
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* for the M7 to reach its 800 MHz HSRUN (OverDrive) frequency
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* (IMXRT1180RM Rev. 10 sec. 2.1.3).
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*
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* Follows the "PMU Well Bias Enable Sequence" of RM sec. 24.3.2.3.3.2.
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* FBB is implemented in the Cortex-M7 platform only (RM sec. 19.3.3),
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* and the second step turns on the CM7 well-bias power switch, so this
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* belongs to the M7 release path rather than to generic clock setup.
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* The RM requires VDD_SOC_IN and VDD_AON_ANA to be settled beforehand;
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* imxrt_clockconfig() has already raised VDD1P0 to 1.125 V by this
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* point.
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*
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****************************************************************************/
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static int imxrt118x_pmu_enable_body_bias_fbb_cm7(void)
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{
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int timeout;
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uint32_t regval;
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/* Step 1/2: configure the well bias. */
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regval = getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL);
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regval &= ~(ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK |
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ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK |
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ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8_MASK);
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regval |= ANADIG_PMU_BIAS_CTRL_WB_CFG_1P8(ANADIG_PMU_WB_CFG_NWELL_FBB |
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ANADIG_PMU_WB_CFG_PULLDOWN_EN |
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ANADIG_PMU_WB_CFG_AREA(
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ANADIG_PMU_WB_AREA_90UA) |
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ANADIG_PMU_WB_CFG_ADAPTIVE_DIS |
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ANADIG_PMU_WB_CFG_OSC(
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ANADIG_PMU_WB_OSC_FULL)) |
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ANADIG_PMU_BIAS_CTRL_WB_NW_LVL_1P8(1) |
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ANADIG_PMU_BIAS_CTRL_WB_PW_LVL_1P8(1);
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putreg32(regval, IMXRT_ANADIG_PMU_BIAS_CTRL);
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/* Step 3: turn on the CM7 FBB switch and the well-bias regulator. */
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regval = getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL2);
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regval |= ANADIG_PMU_BIAS_CTRL2_WB_EN |
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ANADIG_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8;
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putreg32(regval, IMXRT_ANADIG_PMU_BIAS_CTRL2);
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/* Step 4: wait for the well bias to stabilise. */
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for (timeout = 10000; timeout != 0; timeout--)
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{
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if ((getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL2) &
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ANADIG_PMU_BIAS_CTRL2_WB_OK) != 0)
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{
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return 0;
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}
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up_udelay(1);
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}
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syslog(LOG_ERR, "bootloader: FBB not stable (BIAS_CTRL2=0x%08" PRIx32
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")\n", getreg32(IMXRT_ANADIG_PMU_BIAS_CTRL2));
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return -ETIMEDOUT;
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}
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/****************************************************************************
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* Name: prepare_m7_power
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****************************************************************************/
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static int prepare_m7_power(void)
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{
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uint32_t rootctrl;
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/* Forward body bias is required for HSRUN (IMXRT1180RM Rev. 10
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* Table 128).
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*/
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if (imxrt118x_pmu_enable_body_bias_fbb_cm7() < 0)
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{
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return -ETIMEDOUT;
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}
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/* Stop root0 before selecting ARM_PLL / 1. Keep it stopped until the
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* status register reflects the requested mux and divider, then restart
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* it and wait for the transition to complete.
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*/
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putreg32(CCM_CR_CTRL_OFF, IMXRT_CCM_CR_CTRL_SET(CCM_CR_M7));
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while ((getreg32(IMXRT_CCM_CR_STAT0(CCM_CR_M7)) &
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(CCM_CR_STAT0_OFF | CCM_CR_STAT0_CHANGING)) != CCM_CR_STAT0_OFF);
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rootctrl = getreg32(IMXRT_CCM_CR_CTRL(CCM_CR_M7));
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rootctrl &= ~(CCM_CR_CTRL_MUX_MASK | CCM_CR_CTRL_DIV_MASK);
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rootctrl |= CCM_M7_ROOT_CONFIG;
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putreg32(rootctrl, IMXRT_CCM_CR_CTRL(CCM_CR_M7));
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while ((getreg32(IMXRT_CCM_CR_STAT0(CCM_CR_M7)) &
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(CCM_CR_STAT0_MUX_MASK | CCM_CR_STAT0_DIV_MASK |
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CCM_CR_STAT0_OFF | CCM_CR_STAT0_CHANGING)) !=
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(CCM_M7_ROOT_CONFIG | CCM_CR_STAT0_OFF));
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putreg32(CCM_CR_CTRL_OFF, IMXRT_CCM_CR_CTRL_CLR(CCM_CR_M7));
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while (getreg32(IMXRT_CCM_CR_STAT0(CCM_CR_M7)) &
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(CCM_CR_STAT0_OFF | CCM_CR_STAT0_CHANGING));
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putreg32(DCDC_REG3_REG_FBK_SEL(2) |
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DCDC_REG3_DISABLE_IDLE_SKIP |
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DCDC_REG3_DISABLE_PULSE_SKIP,
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IMXRT_DCDC_REG3);
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: imxrt118x_release_cm7
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****************************************************************************/
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int imxrt118x_release_cm7(uintptr_t vtor)
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{
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uint32_t cfg;
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int ret;
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/* Prepare the M7 power domain and core clock root. ARM_PLL is configured
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* by the M33's imxrt_clockconfig().
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*/
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if (prepare_m7_power() < 0)
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{
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return -ETIMEDOUT;
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}
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/* Keep the M7 platform in RUN during WFI so core exceptions such as
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* SysTick can wake it without requiring a GPC wakeup source. This is
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* done before reset release because the bootloader owns the M7 power
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* setup.
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*/
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modifyreg32(IMXRT_GPC_CM7_MODE_CTRL,
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GPC_CM_MODE_CTRL_TARGET_MASK,
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GPC_CM_MODE_CTRL_TARGET(GPC_CM_MODE_TARGET_RUN));
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modifyreg32(IMXRT_GPC_CM_MISC(1),
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GPC_CM_MISC_SLEEP_HOLD_EN, 0);
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/* Program the M7 initial VTOR and force its clocks on. */
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cfg = getreg32(IMXRT_AON_M7_CFG);
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cfg = (cfg & ~AON_M7_CFG_INITVTOR_MASK) |
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AON_M7_CFG_INITVTOR(vtor >> AON_M7_CFG_INITVTOR_SHIFT) |
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AON_M7_CFG_HCLK_FORCE_ON |
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AON_M7_CFG_CORECLK_FORCE_ON;
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putreg32(cfg, IMXRT_AON_M7_CFG);
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/* Release the M7 from reset (write-once). */
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putreg32(getreg32(IMXRT_SRC_SCR) | SRC_SCR_BT_RELEASE_M7, IMXRT_SRC_SCR);
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/* Ask ELE to release the M7. */
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ret = imxrt118x_ele_enable_apc();
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if (ret < 0)
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{
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return ret;
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}
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/* Kick the M7 by toggling its clock around WAIT deassertion.
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*/
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putreg32(0, IMXRT_CCM_LPCG_DIR(0));
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putreg32(getreg32(IMXRT_AON_M7_CFG) & ~AON_M7_CFG_WAIT, IMXRT_AON_M7_CFG);
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putreg32(CCM_LPCG_DIR_ON, IMXRT_CCM_LPCG_DIR(0));
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return 0;
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}
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40
arch/arm/src/imxrt/imxrt118x_start_cm7.h
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40
arch/arm/src/imxrt/imxrt118x_start_cm7.h
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@ -0,0 +1,40 @@
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/****************************************************************************
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* arch/arm/src/imxrt/imxrt118x_start_cm7.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT118X_START_CM7_H
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#define __ARCH_ARM_SRC_IMXRT_IMXRT118X_START_CM7_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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int imxrt118x_release_cm7(uintptr_t vtor);
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#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT118X_START_CM7_H */
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