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arch/arm/imxrt: Add iMXRT118x capable eDMA driver
- Add driver supporting the DMA3 and DMA4 in iMXRT118x chips. The driver is first copied from imx93, and then changed just the relevant parts (function names, clocking and irq handling) to match the imx118x configuration. - Add the DMA channel numbering in hardware/rt118x/imxrt118x_dmamux.h from RM by claude. Assisted-by: Claude Code:claude-opus-4-7 Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen
Xiang Xiao
parent
a3fb91e0ba
commit
5b7d69307c
8 changed files with 2347 additions and 4 deletions
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@ -96,7 +96,11 @@ if(CONFIG_BUILD_PROTECTED)
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endif()
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if(CONFIG_IMXRT_EDMA)
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list(APPEND SRCS imxrt_edma.c)
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if(CONFIG_IMXRT_EDMA_VER2)
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list(APPEND SRCS imxrt_edma_ver2.c)
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else()
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list(APPEND SRCS imxrt_edma.c)
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endif()
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endif()
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if(CONFIG_IMXRT_USDHC)
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@ -237,6 +237,7 @@ config ARCH_FAMILY_IMXRT118x
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select IMXRT_CLOCKCONFIG_VER3
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select IMXRT_IOMUX_VER3
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select IMXRT_RGPIO
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select IMXRT_EDMA_VER2
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---help---
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i.MX RT1180 dual-core Crossover Processors (Cortex-M33 + Cortex-M7).
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@ -432,6 +433,13 @@ config IMXRT_RGPIO
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Selects the RGPIO driver (arch/arm/src/imxrt/imxrt_rgpio.c) that
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targets the RGPIO IP block used on RT118x.
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config IMXRT_EDMA_VER2
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bool
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default n
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---help---
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Selects the RT118x eDMA driver variant
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(arch/arm/src/imxrt/imxrt_edma_ver2.c) used by RT118x.
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config IMXRT_TRDC
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bool
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default n
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@ -92,8 +92,12 @@ CHIP_CSRCS += imxrt_userspace.c
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endif
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ifeq ($(CONFIG_IMXRT_EDMA),y)
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ifeq ($(CONFIG_IMXRT_EDMA_VER2),y)
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CHIP_CSRCS += imxrt_edma_ver2.c
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else
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CHIP_CSRCS += imxrt_edma.c
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endif
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endif
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ifdef CONFIG_IMXRT_USDHC
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CHIP_CSRCS += imxrt_usdhc.c
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@ -39,6 +39,8 @@
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#elif defined(CONFIG_ARCH_FAMILY_IMXRT117x)
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# include "hardware/rt117x/imxrt117x_dmamux.h"
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#define IMXRT_DMAMUX_BASE IMXRT_DMAMUX0_BASE
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#elif defined(CONFIG_ARCH_FAMILY_IMXRT118x)
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# include "hardware/rt118x/imxrt118x_dmamux.h"
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#else
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# error Unrecognized i.MX RT architecture
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#endif
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329
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h
Normal file
329
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h
Normal file
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@ -0,0 +1,329 @@
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/****************************************************************************
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* arch/arm/src/imxrt/hardware/rt118x/imxrt118x_dmamux.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_DMAMUX_H
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#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_DMAMUX_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdint.h>
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#include "hardware/imxrt_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* eDMA3/eDMA4 request source constants (IMXRT1180RM Ch. 5) */
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#define IMXRT_DMA_ENGINE_EDMA3 (0)
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#define IMXRT_DMA_ENGINE_EDMA4 (1)
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#define IMXRT_DMA_SRC_ENGINE_SHIFT (8)
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#define IMXRT_DMA_SRC_ENGINE_MASK (0xff << IMXRT_DMA_SRC_ENGINE_SHIFT)
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#define IMXRT_DMA_SRC_MUX_SHIFT (0)
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#define IMXRT_DMA_SRC_MUX_MASK (0xff << IMXRT_DMA_SRC_MUX_SHIFT)
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#define EDMA_MUX_MASK IMXRT_DMA_SRC_MUX_MASK
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#define IMXRT_DMA_SRC(_engine, _mux) \
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(((_engine) << IMXRT_DMA_SRC_ENGINE_SHIFT) | \
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((_mux) << IMXRT_DMA_SRC_MUX_SHIFT))
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#define IMXRT_DMA_SRC_ENGINE(_v) \
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(((_v) & IMXRT_DMA_SRC_ENGINE_MASK) >> IMXRT_DMA_SRC_ENGINE_SHIFT)
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#define IMXRT_DMA_SRC_MUX(_v) \
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(((_v) & IMXRT_DMA_SRC_MUX_MASK) >> IMXRT_DMA_SRC_MUX_SHIFT)
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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static inline uintptr_t imxrt_dmamux_get_dmabase(uint16_t dmamux)
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{
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return (IMXRT_DMA_SRC_ENGINE(dmamux) == IMXRT_DMA_ENGINE_EDMA3) ?
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IMXRT_DMA3_BASE : IMXRT_DMA4_BASE;
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}
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#endif /* __ASSEMBLY__ */
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/* eDMA3 (AONMIX) request sources */
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#define IMXRT_DMACHAN_CAN1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 1)
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#define IMXRT_DMACHAN_GPIO1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 3)
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#define IMXRT_DMACHAN_GPIO1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 4)
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#define IMXRT_DMACHAN_I3_C1_TO_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 5)
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#define IMXRT_DMACHAN_I3_C1_FROM_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 6)
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#define IMXRT_DMACHAN_LPI2_C1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 7)
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#define IMXRT_DMACHAN_LPI2_C1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 8)
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#define IMXRT_DMACHAN_LPI2_C2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 9)
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#define IMXRT_DMACHAN_LPI2_C2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 10)
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#define IMXRT_DMACHAN_LPSPI1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 11)
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#define IMXRT_DMACHAN_LPSPI1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 12)
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#define IMXRT_DMACHAN_LPSPI2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 13)
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#define IMXRT_DMACHAN_LPSPI2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 14)
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#define IMXRT_DMACHAN_LPTMR1_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 15)
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#define IMXRT_DMACHAN_LPUART1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 16)
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#define IMXRT_DMACHAN_LPUART1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 17)
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#define IMXRT_DMACHAN_LPUART2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 18)
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#define IMXRT_DMACHAN_LPUART2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 19)
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#define IMXRT_DMACHAN_EDGELOCK_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 20)
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#define IMXRT_DMACHAN_SAI1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 21)
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#define IMXRT_DMACHAN_SAI1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 22)
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#define IMXRT_DMACHAN_TPM1_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 23)
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#define IMXRT_DMACHAN_TPM1_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 24)
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#define IMXRT_DMACHAN_TPM1_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 25)
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#define IMXRT_DMACHAN_TPM2_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 26)
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#define IMXRT_DMACHAN_TPM2_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 27)
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#define IMXRT_DMACHAN_TPM2_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 28)
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#define IMXRT_DMACHAN_LPUART7_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 29)
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#define IMXRT_DMACHAN_LPUART7_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 30)
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#define IMXRT_DMACHAN_FLEX_SPI2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 33)
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#define IMXRT_DMACHAN_FLEX_SPI2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 34)
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#define IMXRT_DMACHAN_CAN3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 38)
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#define IMXRT_DMACHAN_LPUART12_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 31)
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#define IMXRT_DMACHAN_LPUART12_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA3, 32)
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/* eDMA4 (WAKEUPMIX / MEGAMIX) request sources */
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#define IMXRT_DMACHAN_GPIO2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 2)
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#define IMXRT_DMACHAN_GPIO2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 3)
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#define IMXRT_DMACHAN_GPIO3_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 4)
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#define IMXRT_DMACHAN_GPIO3_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 5)
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#define IMXRT_DMACHAN_I3_C2_TO_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 6)
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#define IMXRT_DMACHAN_I3_C2_FROM_BUS_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 7)
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#define IMXRT_DMACHAN_LPI2_C3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 8)
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#define IMXRT_DMACHAN_LPI2_C3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 9)
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#define IMXRT_DMACHAN_LPI2_C4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 10)
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#define IMXRT_DMACHAN_LPI2_C4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 11)
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#define IMXRT_DMACHAN_LPSPI3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 12)
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#define IMXRT_DMACHAN_LPSPI3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 13)
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#define IMXRT_DMACHAN_LPSPI4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 14)
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#define IMXRT_DMACHAN_LPSPI4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 15)
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#define IMXRT_DMACHAN_LPUART3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 17)
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#define IMXRT_DMACHAN_LPUART3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 18)
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#define IMXRT_DMACHAN_LPUART4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 19)
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#define IMXRT_DMACHAN_LPUART4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 20)
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#define IMXRT_DMACHAN_LPUART5_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 21)
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#define IMXRT_DMACHAN_LPUART5_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 22)
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#define IMXRT_DMACHAN_LPUART6_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 23)
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#define IMXRT_DMACHAN_LPUART6_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 24)
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#define IMXRT_DMACHAN_TPM3_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 25)
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#define IMXRT_DMACHAN_TPM3_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 26)
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#define IMXRT_DMACHAN_TPM3_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 27)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 37)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 38)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 39)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 40)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 41)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST5 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 42)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST6 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 43)
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#define IMXRT_DMACHAN_FLEX_IO1_REQUEST7 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 44)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 45)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 46)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 47)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 48)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 49)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST5 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 50)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST6 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 51)
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#define IMXRT_DMACHAN_FLEX_IO2_REQUEST7 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 52)
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#define IMXRT_DMACHAN_FLEX_SPI1_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 53)
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#define IMXRT_DMACHAN_FLEX_SPI1_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 54)
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#define IMXRT_DMACHAN_ADC1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 57)
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#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 74)
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#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 75)
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#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 76)
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#define IMXRT_DMACHAN_FLEX_PWM3_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 77)
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#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 78)
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#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 79)
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#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 80)
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#define IMXRT_DMACHAN_FLEX_PWM3_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 81)
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#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 82)
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#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 83)
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#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 84)
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#define IMXRT_DMACHAN_FLEX_PWM4_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 85)
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#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 86)
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#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 87)
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#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 88)
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#define IMXRT_DMACHAN_FLEX_PWM4_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 89)
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#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 90)
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#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 91)
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#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 92)
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#define IMXRT_DMACHAN_QTIMER1_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 93)
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#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 94)
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#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 95)
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#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 96)
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#define IMXRT_DMACHAN_QTIMER1_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 97)
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#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 98)
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#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 99)
|
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#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 100)
|
||||
#define IMXRT_DMACHAN_QTIMER2_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 101)
|
||||
#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 102)
|
||||
#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 103)
|
||||
#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 104)
|
||||
#define IMXRT_DMACHAN_QTIMER2_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 105)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 106)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 107)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 108)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 109)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 110)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 111)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 112)
|
||||
#define IMXRT_DMACHAN_QTIMER3_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 113)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 114)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 115)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 116)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 117)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 118)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 119)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 120)
|
||||
#define IMXRT_DMACHAN_QTIMER4_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 121)
|
||||
#define IMXRT_DMACHAN_XBAR1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 154)
|
||||
#define IMXRT_DMACHAN_XBAR1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 155)
|
||||
#define IMXRT_DMACHAN_XBAR1_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 156)
|
||||
#define IMXRT_DMACHAN_XBAR1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 157)
|
||||
#define IMXRT_DMACHAN_ADC2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 158)
|
||||
#define IMXRT_DMACHAN_EQDC1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 159)
|
||||
#define IMXRT_DMACHAN_EQDC2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 160)
|
||||
#define IMXRT_DMACHAN_EQDC3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 161)
|
||||
#define IMXRT_DMACHAN_EQDC4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 162)
|
||||
#define IMXRT_DMACHAN_LPI2_C5_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 163)
|
||||
#define IMXRT_DMACHAN_LPI2_C5_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 164)
|
||||
#define IMXRT_DMACHAN_LPSPI5_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 167)
|
||||
#define IMXRT_DMACHAN_LPSPI5_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 168)
|
||||
#define IMXRT_DMACHAN_LPSPI6_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 169)
|
||||
#define IMXRT_DMACHAN_LPSPI6_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 170)
|
||||
#define IMXRT_DMACHAN_LPUART8_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 178)
|
||||
#define IMXRT_DMACHAN_LPUART8_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 179)
|
||||
#define IMXRT_DMACHAN_DAC IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 186)
|
||||
#define IMXRT_DMACHAN_CMP3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 189)
|
||||
#define IMXRT_DMACHAN_ASRC_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 191)
|
||||
#define IMXRT_DMACHAN_ASRC_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 192)
|
||||
#define IMXRT_DMACHAN_ASRC_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 193)
|
||||
#define IMXRT_DMACHAN_ASRC_REQUEST4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 194)
|
||||
#define IMXRT_DMACHAN_ASRC_REQUEST5 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 195)
|
||||
#define IMXRT_DMACHAN_ASRC_REQUEST6 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 196)
|
||||
#define IMXRT_DMACHAN_SPDIF_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 197)
|
||||
#define IMXRT_DMACHAN_SPDIF_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 198)
|
||||
#define IMXRT_DMACHAN_PDM_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 199)
|
||||
#define IMXRT_DMACHAN_GPIO4_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 200)
|
||||
#define IMXRT_DMACHAN_GPIO4_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 201)
|
||||
#define IMXRT_DMACHAN_GPIO5_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 202)
|
||||
#define IMXRT_DMACHAN_GPIO5_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 203)
|
||||
#define IMXRT_DMACHAN_GPIO6_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 204)
|
||||
#define IMXRT_DMACHAN_GPIO6_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 205)
|
||||
#define IMXRT_DMACHAN_SINC3_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 216)
|
||||
#define IMXRT_DMACHAN_SINC3_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 217)
|
||||
#define IMXRT_DMACHAN_SINC3_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 218)
|
||||
#define IMXRT_DMACHAN_SINC3_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 219)
|
||||
#define IMXRT_DMACHAN_ADC1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 220)
|
||||
#define IMXRT_DMACHAN_ADC2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 221)
|
||||
#define IMXRT_DMACHAN_LPTMR2_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 16)
|
||||
#define IMXRT_DMACHAN_TPM4_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 28)
|
||||
#define IMXRT_DMACHAN_TPM4_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 29)
|
||||
#define IMXRT_DMACHAN_TPM4_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 30)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 58)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 59)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 60)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 61)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 62)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 63)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 64)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM1_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 65)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 66)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 67)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 68)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_CAPTURE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 69)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 70)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 71)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 72)
|
||||
#define IMXRT_DMACHAN_FLEX_PWM2_VALUE_SUB3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 73)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 122)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 123)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 124)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 125)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 126)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 127)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 128)
|
||||
#define IMXRT_DMACHAN_QTIMER5_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 129)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 130)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 131)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 132)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 133)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 134)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 135)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 136)
|
||||
#define IMXRT_DMACHAN_QTIMER6_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 137)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 138)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 139)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 140)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 141)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 142)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 143)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 144)
|
||||
#define IMXRT_DMACHAN_QTIMER7_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 145)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 146)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 147)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 148)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CAPT_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 149)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER0_CMPLD2_TIMER1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 150)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER1_CMPLD2_TIMER0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 151)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER2_CMPLD2_TIMER3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 152)
|
||||
#define IMXRT_DMACHAN_QTIMER8_CMPLD1_TIMER3_CMPLD2_TIMER2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 153)
|
||||
#define IMXRT_DMACHAN_LPI2_C6_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 165)
|
||||
#define IMXRT_DMACHAN_LPI2_C6_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 166)
|
||||
#define IMXRT_DMACHAN_LPTMR3_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 171)
|
||||
#define IMXRT_DMACHAN_SAI2_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 180)
|
||||
#define IMXRT_DMACHAN_SAI2_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 181)
|
||||
#define IMXRT_DMACHAN_SAI4_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 184)
|
||||
#define IMXRT_DMACHAN_SAI4_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 185)
|
||||
#define IMXRT_DMACHAN_SINC1_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 208)
|
||||
#define IMXRT_DMACHAN_SINC1_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 209)
|
||||
#define IMXRT_DMACHAN_SINC1_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 210)
|
||||
#define IMXRT_DMACHAN_SINC1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 211)
|
||||
#define IMXRT_DMACHAN_SINC2_REQUEST0 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 212)
|
||||
#define IMXRT_DMACHAN_SINC2_REQUEST1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 213)
|
||||
#define IMXRT_DMACHAN_SINC2_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 214)
|
||||
#define IMXRT_DMACHAN_SINC2_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 215)
|
||||
#define IMXRT_DMACHAN_CAN2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 1)
|
||||
#define IMXRT_DMACHAN_TPM5_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 31)
|
||||
#define IMXRT_DMACHAN_TPM5_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 32)
|
||||
#define IMXRT_DMACHAN_TPM5_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 33)
|
||||
#define IMXRT_DMACHAN_TPM6_REQUEST0_REQUEST2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 34)
|
||||
#define IMXRT_DMACHAN_TPM6_REQUEST1_REQUEST3 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 35)
|
||||
#define IMXRT_DMACHAN_TPM6_OVERFLOW_REQUEST IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 36)
|
||||
#define IMXRT_DMACHAN_LPUART9_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 172)
|
||||
#define IMXRT_DMACHAN_LPUART9_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 173)
|
||||
#define IMXRT_DMACHAN_LPUART10_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 174)
|
||||
#define IMXRT_DMACHAN_LPUART10_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 175)
|
||||
#define IMXRT_DMACHAN_LPUART11_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 176)
|
||||
#define IMXRT_DMACHAN_LPUART11_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 177)
|
||||
#define IMXRT_DMACHAN_SAI3_TX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 182)
|
||||
#define IMXRT_DMACHAN_SAI3_RX IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 183)
|
||||
#define IMXRT_DMACHAN_CMP1 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 187)
|
||||
#define IMXRT_DMACHAN_CMP2 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 188)
|
||||
#define IMXRT_DMACHAN_CMP4 IMXRT_DMA_SRC(IMXRT_DMA_ENGINE_EDMA4, 190)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_DMAMUX_H */
|
||||
444
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h
Normal file
444
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h
Normal file
|
|
@ -0,0 +1,444 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/imxrt/hardware/rt118x/imxrt118x_edma.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_EDMA_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_EDMA_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "hardware/imxrt_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define EDMA_CONFIG_SWSTART (1 << 6) /* Start by software trigger */
|
||||
|
||||
/* eDMA3 / eDMA4 Register Offsets */
|
||||
|
||||
#define IMXRT_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
|
||||
#define IMXRT_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
|
||||
#define IMXRT_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
|
||||
|
||||
/* eDMA3 only */
|
||||
|
||||
#define IMXRT_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
|
||||
#define IMXRT_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
|
||||
|
||||
/* eDMA4 only */
|
||||
|
||||
#define IMXRT_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */
|
||||
#define IMXRT_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */
|
||||
#define IMXRT_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */
|
||||
#define IMXRT_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */
|
||||
|
||||
/* eDMA3 / eDMA4 Register Addresses */
|
||||
|
||||
#define IMXRT_EDMA_CSR(n) ((n) + IMXRT_EDMA_CSR_OFFSET)
|
||||
#define IMXRT_EDMA_ES(n) ((n) + IMXRT_EDMA_ES_OFFSET)
|
||||
#define IMXRT_EDMA_CH_GRPRI(n,c) ((n) + IMXRT_EDMA_CH_GRPRI_OFFSET(c))
|
||||
|
||||
/* eDMA3 only */
|
||||
|
||||
#define IMXRT_EDMA_INT (IMXRT_DMA3_BASE + IMXRT_EDMA_INT_OFFSET)
|
||||
#define IMXRT_EDMA_HRS (IMXRT_DMA3_BASE + IMXRT_EDMA_HRS_OFFSET)
|
||||
|
||||
/* eDMA4 only */
|
||||
|
||||
#define IMXRT_EDMA_INT_LOW (IMXRT_DMA4_BASE + IMXRT_EDMA_INT_LOW_OFFSET)
|
||||
#define IMXRT_EDMA_INT_HIGH (IMXRT_DMA4_BASE + IMXRT_EDMA_INT_HIGH_OFFSET)
|
||||
#define IMXRT_EDMA_HRS_LOW (IMXRT_DMA4_BASE + IMXRT_EDMA_HRS_LOW_OFFSET)
|
||||
#define IMXRT_EDMA_HRS_HIGH (IMXRT_DMA4_BASE + IMXRT_EDMA_HRS_HIGH_OFFSET)
|
||||
|
||||
/* eDMA Transfer Control Descriptor (TCD) Register Offsets */
|
||||
|
||||
#define IMXRT_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
|
||||
#define IMXRT_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
|
||||
#define IMXRT_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
|
||||
#define IMXRT_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
|
||||
#define IMXRT_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
|
||||
#define IMXRT_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */
|
||||
#define IMXRT_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */
|
||||
#define IMXRT_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
|
||||
#define IMXRT_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
|
||||
#define IMXRT_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
|
||||
#define IMXRT_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
|
||||
#define IMXRT_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
|
||||
#define IMXRT_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
|
||||
#define IMXRT_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
|
||||
#define IMXRT_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
|
||||
#define IMXRT_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
|
||||
#define IMXRT_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
|
||||
#define IMXRT_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
|
||||
|
||||
/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */
|
||||
|
||||
#define IMXRT_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */
|
||||
#define IMXRT_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */
|
||||
#define IMXRT_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */
|
||||
#define IMXRT_EDMA_TCD_BASE(n) ((n) + IMXRT_EDMA_TCD_BASE_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_INST_OFFSET(n) ((n) == IMXRT_DMA3_BASE ? IMXRT_EDMA3_TCD_INST_OFFSET : IMXRT_EDMA4_TCD_INST_OFFSET)
|
||||
#define IMXRT_EDMA_TCD(n,t) (IMXRT_EDMA_TCD_BASE(n) + (t) * IMXRT_EDMA_TCD_INST_OFFSET(n))
|
||||
|
||||
/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
|
||||
|
||||
#define IMXRT_EDMA_CH_CSR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_CSR_OFFSET)
|
||||
#define IMXRT_EDMA_CH_ES(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_ES_OFFSET)
|
||||
#define IMXRT_EDMA_CH_INT(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_INT_OFFSET)
|
||||
#define IMXRT_EDMA_CH_SBR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_SBR_OFFSET)
|
||||
#define IMXRT_EDMA_CH_PRI(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_PRI_OFFSET)
|
||||
#define IMXRT_EDMA_CH_MUX(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_CH_MUX_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_SADDR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_SADDR_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_SOFF(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_SOFF_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_ATTR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_ATTR_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_NBYTES(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_NBYTES_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_SLAST_SDA(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_SLAST_SDA_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_DADDR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_DADDR_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_DOFF(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_DOFF_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_CITER(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_CITER_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_DLAST_SGA(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_DLAST_SGA_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_CSR(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_CSR_OFFSET)
|
||||
#define IMXRT_EDMA_TCD_BITER(n,t) (IMXRT_EDMA_TCD(n,t) + IMXRT_EDMA_TCD_BITER_OFFSET)
|
||||
|
||||
/* eDMA Register Bitfield Definitions ***************************************/
|
||||
|
||||
/* Management Page Control Register (CSR) */
|
||||
|
||||
/* Bit 0: Reserved */
|
||||
#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
|
||||
#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
|
||||
/* Bit 3: Reserved */
|
||||
#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
|
||||
#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
|
||||
#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
|
||||
#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
|
||||
#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
|
||||
#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
|
||||
/* Bits 10-23: Reserved */
|
||||
#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
|
||||
#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
|
||||
/* Bits 29-30: Reserved */
|
||||
#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
|
||||
|
||||
/* Management Page Error Status Register (ES) */
|
||||
|
||||
#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
|
||||
#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
|
||||
#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
|
||||
#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
|
||||
#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
|
||||
#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
|
||||
#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
|
||||
#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
|
||||
#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
|
||||
/* Bits 9-23: Reserved */
|
||||
#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
|
||||
#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
|
||||
/* Bits 29-30: Reserved */
|
||||
#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
|
||||
|
||||
/* Management Page Interrupt Request Status Register (INT) */
|
||||
|
||||
#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
|
||||
|
||||
/* Management Page Hardware Request Status Register (HRS) */
|
||||
|
||||
#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
|
||||
|
||||
/* Channel n Arbitration Group Register (CHn_GRPRI) */
|
||||
|
||||
#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
|
||||
#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
|
||||
/* Bits 5-31: Reserved */
|
||||
|
||||
/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
|
||||
|
||||
/* Channel n Control and Status Register (CHn_CSR) */
|
||||
|
||||
#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
|
||||
#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
|
||||
#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
|
||||
#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
|
||||
/* Bit 4-29: Reserved */
|
||||
#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
|
||||
#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
|
||||
|
||||
/* Channel n Error Status Register (CHn_ES) */
|
||||
|
||||
#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
|
||||
#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
|
||||
#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
|
||||
#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
|
||||
#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
|
||||
#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
|
||||
#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
|
||||
#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
|
||||
/* Bit 8-30: Reserved */
|
||||
#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
|
||||
|
||||
/* Channel n Interrupt Status Register (CHn_INT) */
|
||||
|
||||
#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
/* Channel n System Bus Register (CHn_SBR) */
|
||||
|
||||
#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
|
||||
#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
|
||||
/* Bits 4-13: Reserved */
|
||||
#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */
|
||||
#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
|
||||
#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
|
||||
#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
|
||||
#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
|
||||
/* Bits 20-31: Reserved */
|
||||
|
||||
/* Channel n Priority Register (CHn_PRI) */
|
||||
|
||||
#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
|
||||
#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
|
||||
/* Bits 3-29: Reserved */
|
||||
#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
|
||||
#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
|
||||
|
||||
/* Channel Multiplexor Configuration (CHn_MUX). On RT1180 the mux source
|
||||
* ID field is 8-bit for eDMA4 (up to 256 sources) and 6-bit for eDMA3.
|
||||
* Using the wider mask is safe since unused high bits are reserved.
|
||||
*/
|
||||
|
||||
#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-7: Service Request Source */
|
||||
#define EDMA_CH_SRC_MASK (0xff << EDMA_CH_SRC_SHIFT)
|
||||
|
||||
/* TCDn Source Address Register (TCDn_SADDR) */
|
||||
|
||||
#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
|
||||
#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
|
||||
|
||||
/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
|
||||
|
||||
#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
|
||||
#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
|
||||
|
||||
/* TCDn Transfer Attributes (TCDn_ATTR) */
|
||||
|
||||
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
|
||||
#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
|
||||
#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
|
||||
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
|
||||
#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
|
||||
#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
|
||||
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
|
||||
#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
|
||||
#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
|
||||
# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
|
||||
# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
|
||||
# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
|
||||
|
||||
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
|
||||
#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
|
||||
#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
|
||||
|
||||
/* TCDn Transfer Size (TCDn_NBYTES) */
|
||||
|
||||
#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
|
||||
#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
|
||||
#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
|
||||
#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
|
||||
#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
|
||||
#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
|
||||
#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
|
||||
|
||||
/* TCDn Last Source Address Adjustment / Store DADDR Address Register
|
||||
* (TCDn_SLAST_SDA)
|
||||
*/
|
||||
|
||||
#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
|
||||
#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
|
||||
|
||||
/* TCDn Destination Address Register (TCDn_DADDR) */
|
||||
|
||||
#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
|
||||
#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
|
||||
|
||||
/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
|
||||
|
||||
#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
|
||||
#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
|
||||
|
||||
/* TCDn Current Major Loop Count Register (TCDn_CITER) */
|
||||
|
||||
#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
|
||||
#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
|
||||
#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
|
||||
#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
|
||||
#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
|
||||
#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
|
||||
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
|
||||
|
||||
/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
|
||||
* (TCDn_DLAST_SGA)
|
||||
*/
|
||||
|
||||
#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
|
||||
#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
|
||||
|
||||
/* TCDn Control and Status Register (TCDn_CSR) */
|
||||
|
||||
#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
|
||||
#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
|
||||
#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
|
||||
#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
|
||||
#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
|
||||
#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
|
||||
#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
|
||||
#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
|
||||
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
|
||||
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
|
||||
#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
|
||||
/* Bit 13: Reserved */
|
||||
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
|
||||
#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
|
||||
# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
|
||||
# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */
|
||||
# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */
|
||||
# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */
|
||||
|
||||
/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */
|
||||
|
||||
#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */
|
||||
#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT)
|
||||
#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
|
||||
#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
|
||||
#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
|
||||
#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
|
||||
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
|
||||
|
||||
/* Amount of channels */
|
||||
|
||||
#define DMA3_CHANNEL_COUNT (32)
|
||||
#define DMA4_CHANNEL_COUNT (64)
|
||||
#define IMXRT_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT)
|
||||
|
||||
/* Amount of interrupt sources */
|
||||
|
||||
#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */
|
||||
#define DMA4_IRQ_COUNT (16) /* Error interrupt not counted;
|
||||
* 4 channels share one IRQ */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* In-memory representation of the 32-byte Transfer Control Descriptor
|
||||
* (TCD)
|
||||
*/
|
||||
|
||||
struct imxrt_edmatcd_s
|
||||
{
|
||||
uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
|
||||
uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
|
||||
uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
|
||||
uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
|
||||
uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
|
||||
uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
|
||||
uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
|
||||
uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
|
||||
uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
uint16_t csr; /* Offset: 0x001c TCD Control and Status */
|
||||
uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_edma_tcdhasmux
|
||||
*
|
||||
* Description:
|
||||
* Check if DMA TCD has TCD.MUX register.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dmabase - The eDMA base.
|
||||
*
|
||||
* Returned Value:
|
||||
* true if TCD.MUX exists; false if not.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline bool imxrt_edma_tcdhasmux(uintptr_t dmabase)
|
||||
{
|
||||
/* On RT1180 both eDMA3 and eDMA4 have per-channel CH_MUX registers. */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_edma_choffset
|
||||
*
|
||||
* Description:
|
||||
* Channel offset in global channel list for dma base.
|
||||
*
|
||||
* Input Parameters:
|
||||
* base - The eDMA base.
|
||||
*
|
||||
* Returned Value:
|
||||
* Channel offset.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t imxrt_edma_choffset(uintptr_t base)
|
||||
{
|
||||
return base == IMXRT_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_edma_chmax
|
||||
*
|
||||
* Description:
|
||||
* Max channel in global channel list for dma base.
|
||||
*
|
||||
* Input Parameters:
|
||||
* base - The eDMA base.
|
||||
*
|
||||
* Returned Value:
|
||||
* Channel max.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t imxrt_edma_chmax(uintptr_t base)
|
||||
{
|
||||
return base == IMXRT_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMXRT_EDMA_NCHANNELS;
|
||||
}
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_EDMA_H */
|
||||
|
|
@ -99,7 +99,12 @@
|
|||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include "hardware/imxrt_edma.h"
|
||||
|
||||
#ifdef CONFIG_IMXRT_EDMA_VER2
|
||||
# include "hardware/rt118x/imxrt118x_edma.h"
|
||||
#else
|
||||
# include "hardware/imxrt_edma.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
@ -138,13 +143,26 @@ typedef void *DMACH_HANDLE;
|
|||
typedef void (*edma_callback_t)(DMACH_HANDLE handle,
|
||||
void *arg, bool done, int result);
|
||||
|
||||
/* eDMA transfer sizes */
|
||||
/* eDMA transfer type */
|
||||
|
||||
enum kinetis_edma_sizes_e
|
||||
enum imxrt_edma_xfrtype_e
|
||||
{
|
||||
EDMA_MEM2MEM = 0, /* Transfer from memory to memory */
|
||||
EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */
|
||||
EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */
|
||||
};
|
||||
|
||||
/* eDMA transfer sises */
|
||||
|
||||
enum imxrt_edma_sizes_e
|
||||
{
|
||||
EDMA_8BIT = 0, /* Transfer data size 8 */
|
||||
EDMA_16BIT = 1, /* Transfer data size 16 */
|
||||
EDMA_32BIT = 2, /* Transfer data size 32 */
|
||||
EDMA_64BIT = 3, /* Transfer data size 64 */
|
||||
EDMA_16BYTE = 4, /* Transfer data size 16-byte */
|
||||
EDMA_32BYTE = 5, /* Transfer data size 32-byte */
|
||||
EDMA_64BYTE = 6, /* Transfer data size 64-byte */
|
||||
};
|
||||
|
||||
/* This structure holds the source/destination transfer attribute
|
||||
|
|
@ -166,6 +184,11 @@ struct imxrt_edma_xfrconfig_s
|
|||
#else
|
||||
uint32_t nbytes; /* Bytes to transfer in a minor loop */
|
||||
#endif
|
||||
#ifdef CONFIG_IMXRT_EDMA_VER2
|
||||
uint8_t smod;
|
||||
uint8_t dmod;
|
||||
uint8_t bwc;
|
||||
#endif
|
||||
#ifdef CONFIG_IMXRT_EDMA_ELINK
|
||||
DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */
|
||||
#endif
|
||||
|
|
|
|||
1529
arch/arm/src/imxrt/imxrt_edma_ver2.c
Normal file
1529
arch/arm/src/imxrt/imxrt_edma_ver2.c
Normal file
File diff suppressed because it is too large
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