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boards/arm/imxrt/imxrt1180-evk: Add imxrt1189 evaluation board configurations

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This adds the initial board configurattions for building NuttX for imxrt1189-evk.
Also add a script building the NXP container image for bootloaders (m33 images)

The board boots on Cortex-M33 core, for which there are two m33 targets: nsh-m33 and bl.

- "bl" target does basic initialization of ELE and TRDC and just releases the M7 to run
  at 0x20080000.
- "nsh-m33" target just boots nuttx into nsh shell on m33

- The "nsh" target is for M7 core. It can be flashed at 0x20080000, and
  it boots to nsh shell with a proper bootloader on m33 (the bl target does this).

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen 2026-09-18 08:45:13 +03:00 • committed by Xiang Xiao
parent c5e2c4b3f7
commit fae67d1608
22 changed files with 2197 additions and 0 deletions
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11
boards/Kconfig
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@ -1004,6 +1004,13 @@ config ARCH_BOARD_IMX93_QSB
This is the board configuration for the port of NuttX to the NXP i.MX93 QSB
(Quick Start Board), targeting the M33 core of the i.MX93 MCU.
config ARCH_BOARD_IMXRT1180_EVK
bool "NXP i.MX RT 1180 EVK"
depends on ARCH_CHIP_MIMXRT1189CVM8C || ARCH_CHIP_MIMXRT1189CVM8C_CM33
---help---
This is the board configuration for the port of NuttX to the NXP i.MXRT
evaluation kit, MIMXRT1180-EVK. This board features the IMXRT1189 MCU.
config ARCH_BOARD_IMX95_EVK
bool "NXP i.MX 95 EVK"
depends on ARCH_CHIP_IMX9_CORTEX_M
@ -3983,6 +3990,7 @@ config ARCH_BOARD
default "imxrt1060-evk" if ARCH_BOARD_IMXRT1060_EVK
default "imxrt1064-evk" if ARCH_BOARD_IMXRT1064_EVK
default "imxrt1170-evk" if ARCH_BOARD_IMXRT1170_EVK
default "imxrt1180-evk" if ARCH_BOARD_IMXRT1180_EVK
default "imx93-qsb" if ARCH_BOARD_IMX93_QSB
default "imx95-evk" if ARCH_BOARD_IMX95_EVK
default "mr-navq95b" if ARCH_BOARD_MR_NAVQ95B
@ -4476,6 +4484,9 @@ endif
if ARCH_BOARD_IMXRT1170_EVK
source "boards/arm/imxrt/imxrt1170-evk/Kconfig"
endif
if ARCH_BOARD_IMXRT1180_EVK
source "boards/arm/imxrt/imxrt1180-evk/Kconfig"
endif
if ARCH_BOARD_IMX93_QSB
source "boards/arm/imx9/imx93-qsb/Kconfig"
endif

22
boards/arm/imxrt/imxrt1180-evk/Kconfig Normal file
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@ -0,0 +1,22 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_IMXRT1180_EVK
config IMXRT1180_EVK_BOOTLOADER
bool "Cortex-M33 bootloader application"
default n
depends on ARCH_CORTEXM33
select IMXRT_CM7_BOOT
---help---
Build the minimal Cortex-M33 bootloader application
(src/imxrt_bootloader.c) instead of a normal NuttX application.
Its bootloader_main() entry point only releases the Cortex-M7,
which then runs the M7 NuttX image XIP'd at 0x28080000.
Set CONFIG_INIT_ENTRYPOINT="bootloader_main" when this is
enabled (see the imxrt1180-evk:bl configuration).
endif

32
boards/arm/imxrt/imxrt1180-evk/configs/bl/defconfig Normal file
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@ -0,0 +1,32 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_DEBUG_WARN is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="imxrt1180-evk"
CONFIG_ARCH_BOARD_IMXRT1180_EVK=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_FEATURES=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_IMXRT1180_EVK_BOOTLOADER=y
CONFIG_IMXRT_LPUART1=y
CONFIG_INIT_ENTRYPOINT="bootloader_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_LOCALTIME=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_BACKTRACE=y
CONFIG_START_MONTH=9

67
boards/arm/imxrt/imxrt1180-evk/configs/nsh-m33/defconfig Normal file
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@ -0,0 +1,67 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_DEBUG_WARN is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="imxrt1180-evk"
CONFIG_ARCH_BOARD_IMXRT1180_EVK=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_BULKIN_REQLEN=96
CONFIG_CDCACM_PRODUCTID=0x0061
CONFIG_CDCACM_PRODUCTSTR="IMXRT1180-EVK-M33"
CONFIG_CDCACM_RXBUFSIZE=600
CONFIG_CDCACM_TXBUFSIZE=12000
CONFIG_CDCACM_VENDORID=0x1FC9
CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS"
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_FS_NAMED_SEMAPHORES=y
CONFIG_FS_PROCFS=y
CONFIG_GRAN=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_IMXRT_LPUART1=y
CONFIG_IMXRT_USBDEV=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_LOCALTIME=y
CONFIG_LINE_MAX=64
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_BACKTRACE=y
CONFIG_SCHED_EVENTS=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_SPORADIC=y
CONFIG_SCHED_THREAD_LOCAL=y
CONFIG_SCHED_WAITPID=y
CONFIG_SIG_EVTHREAD=y
CONFIG_START_MONTH=9
CONFIG_SYSTEM_CDCACM=y
CONFIG_SYSTEM_NSH=y
CONFIG_TESTING_OSTEST=y
CONFIG_TLS_NCLEANUP=4
CONFIG_TLS_NELEM=4
CONFIG_USBDEV=y
CONFIG_USBDEV_DMA=y
CONFIG_USBDEV_DMAMEMORY=y
CONFIG_USBDEV_DUALSPEED=y

76
boards/arm/imxrt/imxrt1180-evk/configs/nsh/defconfig Normal file
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@ -0,0 +1,76 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_DEBUG_WARN is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="imxrt1180-evk"
CONFIG_ARCH_BOARD_IMXRT1180_EVK=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1189CVM8C=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=159610
CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_BULKIN_REQLEN=96
CONFIG_CDCACM_PRODUCTID=0x0060
CONFIG_CDCACM_PRODUCTSTR="IMXRT1180-EVK"
CONFIG_CDCACM_RXBUFSIZE=600
CONFIG_CDCACM_TXBUFSIZE=12000
CONFIG_CDCACM_VENDORID=0x1FC9
CONFIG_CDCACM_VENDORSTR="NXP SEMICONDUCTORS"
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_BUSFAULT=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_HARDFAULT_ALERT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEBUG_USAGEFAULT=y
CONFIG_FS_NAMED_SEMAPHORES=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=4096
CONFIG_IMXRT_EDMA=y
CONFIG_IMXRT_LPUART1=y
CONFIG_IMXRT_USBDEV=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=8192
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_LOCALTIME=y
CONFIG_LINE_MAX=64
CONFIG_LPUART1_RXDMA=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXDMA=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PTHREAD_MUTEX_TYPES=y
CONFIG_PTHREAD_STACK_DEFAULT=8192
CONFIG_RAM_SIZE=491520
CONFIG_RAM_START=0x20484000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_BACKTRACE=y
CONFIG_SCHED_EVENTS=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_SPORADIC=y
CONFIG_SCHED_THREAD_LOCAL=y
CONFIG_SCHED_WAITPID=y
CONFIG_SIG_EVTHREAD=y
CONFIG_START_MONTH=9
CONFIG_SYSTEM_CDCACM=y
CONFIG_SYSTEM_NSH=y
CONFIG_TESTING_OSTEST=y
CONFIG_TESTING_OSTEST_STACKSIZE=16384
CONFIG_TLS_NCLEANUP=4
CONFIG_TLS_NELEM=4
CONFIG_USBDEV=y
CONFIG_USBDEV_DMA=y
CONFIG_USBDEV_DUALSPEED=y

130
boards/arm/imxrt/imxrt1180-evk/include/board.h Normal file
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@ -0,0 +1,130 @@
/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/include/board.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_BOARD_H
#define __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/rt118x/imxrt118x_iomuxc.h"
#include "hardware/rt118x/imxrt118x_pinmux.h"
#include "imxrt_iomuxc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* Both cores share ARM_PLL at its supported 798 MHz maximum:
*
* M7 = CLOCK_ROOT0 = ARM_PLL / 1 = 798 MHz
* M33 = CLOCK_ROOT1 = ARM_PLL / 3 = 266 MHz
*
* Both are within the HSRUN maxima of 800 / 300 MHz (IMXRT1180RM Rev. 10
* Table 128).
*
* BOARD_CPU_FREQUENCY is the frequency of the core this image runs on: it
* drives the SysTick reload value, so it must match the core actually
* executing or the whole system time base is scaled wrong.
*/
#define BOARD_XTAL_FREQUENCY 24000000
#define BOARD_CCM_DOMAIN_CM33 2
#define BOARD_CCM_DOMAIN_CM7 4
#ifdef CONFIG_ARCH_CHIP_MIMXRT1189CVM8C_CM33
# define BOARD_CPU_FREQUENCY 266000000
# define BOARD_CCM_DOMAIN_ID BOARD_CCM_DOMAIN_CM33
#else
# define BOARD_CPU_FREQUENCY 798000000
# define BOARD_CCM_DOMAIN_ID BOARD_CCM_DOMAIN_CM7
#endif
/* LPUART1 pin configuration. The MIMXRT1180-EVK routes LPUART1 to
* GPIO_AON_08 (TX) and GPIO_AON_09 (RX) via the MCU-Link VCOM
* (verified against schematic SCH-50577_C4: net LPUART1_TXD -> RT1180
* ball B1).
*
* The pad configuration flags are common to peripheral use of the
* LPUART: no pull, high drive strength.
*/
#define IOMUX_LPUART_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_NONE)
#define GPIO_LPUART1_TX IOMUX_PIN(IOMUXC_PAD_GPIO_AON_08_LPUART1_TX, \
IOMUX_LPUART_DEFAULT, 0)
#define GPIO_LPUART1_RX IOMUX_PIN(IOMUXC_PAD_GPIO_AON_09_LPUART1_RX, \
IOMUX_LPUART_DEFAULT, IOMUXC_MUX_SION_ON)
/* User LEDs: D6 (green) on GPIO_AD_27 = RGPIO4.27,
* D7 (red) on GPIO_AD_26 = RGPIO4.26.
*/
#define IOMUX_LED_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_NONE)
#define GPIO_LED1 IOMUX_GPIO(IOMUXC_PAD_GPIO_AD_27_GPIO4_IO27, \
IOMUX_LED_DEFAULT, \
GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT4 | GPIO_PIN27)
#define GPIO_LED2 IOMUX_GPIO(IOMUXC_PAD_GPIO_AD_26_GPIO4_IO26, \
IOMUX_LED_DEFAULT, \
GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT4 | GPIO_PIN26)
/* LPI2C2: routed to on-board sensors, ENET PHY ID EEPROM etc.
* GPIO_AON_15 -> LPI2C2_SDA
* GPIO_AON_16 -> LPI2C2_SCL
*/
#define IOMUX_LPI2C_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_UP | \
IOMUXC_PAD_ODE_ON)
#define GPIO_LPI2C2_SDA IOMUX_PIN(IOMUXC_PAD_GPIO_AON_15_LPI2C2_SDA, \
IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON)
#define GPIO_LPI2C2_SCL IOMUX_PIN(IOMUXC_PAD_GPIO_AON_16_LPI2C2_SCL, \
IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON)
/* LPSPI1: routed to the on-board LPSPI NOR flash (U12 companion).
* GPIO_AON_04 -> LPSPI1_SCK
* GPIO_AON_05 -> LPSPI1_PCS0
* GPIO_AON_06 -> LPSPI1_SDO
* GPIO_AON_07 -> LPSPI1_SDI
*/
#define IOMUX_LPSPI_DEFAULT (IOMUXC_PAD_PDRV_HIGH | IOMUXC_PAD_PULL_NONE)
#define GPIO_LPSPI1_SCK IOMUX_PIN(IOMUXC_PAD_GPIO_AON_04_LPSPI1_SCK, \
IOMUX_LPSPI_DEFAULT, 0)
#define GPIO_LPSPI1_CS IOMUX_PIN(IOMUXC_PAD_GPIO_AON_05_LPSPI1_PCS0, \
IOMUX_LPSPI_DEFAULT, 0)
#define GPIO_LPSPI1_MOSI IOMUX_PIN(IOMUXC_PAD_GPIO_AON_06_LPSPI1_SDO, \
IOMUX_LPSPI_DEFAULT, 0)
#define GPIO_LPSPI1_MISO IOMUX_PIN(IOMUXC_PAD_GPIO_AON_07_LPSPI1_SDI, \
IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON)
#endif /* __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_BOARD_H */

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boards/arm/imxrt/imxrt1180-evk/include/imxrt118x_trdc_config.h Normal file
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@ -0,0 +1,257 @@
/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/include/imxrt118x_trdc_config.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_IMXRT118X_TRDC_CONFIG_H
#define __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_IMXRT118X_TRDC_CONFIG_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SP(X) ((X) << 12)
#define SU(X) ((X) << 8)
#define NP(X) ((X) << 4)
#define NU(X) ((X) << 0)
#define LK (1 << 31)
#define RWX 7
#define RW 6
#define RX 5
#define R 4
#define X 1
#define TRDC_FULL_ACCESS_GLBAC(id, mbc_mrc) \
{ mbc_mrc, id, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) }
/* Domain identifiers used by the TRDC setup. */
#define DID_CM33 BOARD_CCM_DOMAIN_CM33
#define DID_EDMA3_RESET 4
#define DID_CM7 BOARD_CCM_DOMAIN_CM7
#define DID_USDHC1 5
#define DID_USDHC2 6
#define DID_DMA 7
#define DID_EDMA3 DID_DMA
#define DID_EDMA4 DID_DMA
#define DID_CORESIGHT 8
#define DID_DAP 9
#define DID_NETC 10
#define DID_FLEXSPI_FLR DID_NETC
#define DID_USB 11
#define TRDC_VALID_DOMAINS_MBC(mbc, mem) \
{ mbc, DID_CM33, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_CM7, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_USDHC1, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_USDHC2, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_DMA, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_CORESIGHT, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_DAP, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_NETC, mem, MBC_BLK_ALL, 0, true }, \
{ mbc, DID_USB, mem, MBC_BLK_ALL, 0, true }
#define TRDC_VALID_DOMAINS_MRC(mrc, base, size) \
{ mrc, DID_CM33, 0, base, size, 0, true }, \
{ mrc, DID_CM7, 0, base, size, 0, true }, \
{ mrc, DID_USDHC1, 0, base, size, 0, true }, \
{ mrc, DID_USDHC2, 0, base, size, 0, true }, \
{ mrc, DID_DMA, 0, base, size, 0, true }, \
{ mrc, DID_CORESIGHT, 0, base, size, 0, true }, \
{ mrc, DID_DAP, 0, base, size, 0, true }, \
{ mrc, DID_NETC, 0, base, size, 0, true }, \
{ mrc, DID_USB, 0, base, size, 0, true }
#define TRDC_CM33_ROM_BASE 0x00000000
#define TRDC_CM33_ROM_SIZE 0x00028000
#define TRDC_FLEXSPI2_BASE 0x04000000
#define TRDC_FLEXSPI2_SIZE 0x04000000
#define TRDC_FLEXSPI1_BASE 0x28000000
#define TRDC_FLEXSPI1_SIZE 0x08000000
#define TRDC_CM7_TCM_BASE 0x203c0000
#define TRDC_CM7_TCM_SIZE 0x00080000
#define TRDC_OCRAM1_BASE 0x20480000
#define TRDC_OCRAM1_SIZE 0x00080000
#define TRDC_OCRAM2_BASE 0x20500000
#define TRDC_OCRAM2_SIZE 0x00040000
#define TRDC_SEMC_BASE 0x80000000
#define TRDC_SEMC_SIZE 0x10000000
#define TRDC_NETC_BASE 0x60000000
#define TRDC_NETC_SIZE 0x01000000
/* TRDC1 MBC access policy. */
struct trdc_glbac_config trdc_a_mbc_glbac[] =
{
TRDC_FULL_ACCESS_GLBAC(0, 0), /* MBC0 */
TRDC_FULL_ACCESS_GLBAC(1, 0),
TRDC_FULL_ACCESS_GLBAC(2, 0),
TRDC_FULL_ACCESS_GLBAC(3, 0),
TRDC_FULL_ACCESS_GLBAC(4, 0),
TRDC_FULL_ACCESS_GLBAC(5, 0),
TRDC_FULL_ACCESS_GLBAC(6, 0),
TRDC_FULL_ACCESS_GLBAC(7, 0),
TRDC_FULL_ACCESS_GLBAC(0, 1), /* MBC1 */
TRDC_FULL_ACCESS_GLBAC(1, 1),
TRDC_FULL_ACCESS_GLBAC(2, 1),
TRDC_FULL_ACCESS_GLBAC(3, 1),
TRDC_FULL_ACCESS_GLBAC(4, 1),
TRDC_FULL_ACCESS_GLBAC(5, 1),
TRDC_FULL_ACCESS_GLBAC(6, 1),
TRDC_FULL_ACCESS_GLBAC(7, 1),
};
/* TRDC1 MBC block assignments. */
struct trdc_mbc_config trdc_a_mbc[] =
{
TRDC_VALID_DOMAINS_MBC(0, 0), /* MBC_A0 AIPS1 */
TRDC_VALID_DOMAINS_MBC(0, 2), /* MBC_A0 GPIO1 */
TRDC_VALID_DOMAINS_MBC(1, 0), /* MBC_A1 CM33 Code-TCM */
TRDC_VALID_DOMAINS_MBC(1, 1), /* MBC_A1 CM33 System-TCM */
};
struct trdc_glbac_config trdc_a_mrc_glbac[] =
{
TRDC_FULL_ACCESS_GLBAC(0, 0), /* MRC0 */
TRDC_FULL_ACCESS_GLBAC(1, 0),
TRDC_FULL_ACCESS_GLBAC(2, 0),
TRDC_FULL_ACCESS_GLBAC(3, 0),
TRDC_FULL_ACCESS_GLBAC(4, 0),
TRDC_FULL_ACCESS_GLBAC(5, 0),
TRDC_FULL_ACCESS_GLBAC(6, 0),
TRDC_FULL_ACCESS_GLBAC(7, 0),
TRDC_FULL_ACCESS_GLBAC(0, 1), /* MRC1 */
TRDC_FULL_ACCESS_GLBAC(1, 1),
TRDC_FULL_ACCESS_GLBAC(2, 1),
TRDC_FULL_ACCESS_GLBAC(3, 1),
TRDC_FULL_ACCESS_GLBAC(4, 1),
TRDC_FULL_ACCESS_GLBAC(5, 1),
TRDC_FULL_ACCESS_GLBAC(6, 1),
TRDC_FULL_ACCESS_GLBAC(7, 1),
};
struct trdc_mrc_config trdc_a_mrc[] =
{
TRDC_VALID_DOMAINS_MRC(0, TRDC_CM33_ROM_BASE, TRDC_CM33_ROM_SIZE),
TRDC_VALID_DOMAINS_MRC(1, TRDC_FLEXSPI2_BASE, TRDC_FLEXSPI2_SIZE),
};
/* TRDC2 MBC access policy. */
struct trdc_glbac_config trdc_w_mbc_glbac[] =
{
TRDC_FULL_ACCESS_GLBAC(0, 0), /* MBC0 */
TRDC_FULL_ACCESS_GLBAC(1, 0),
TRDC_FULL_ACCESS_GLBAC(2, 0),
TRDC_FULL_ACCESS_GLBAC(3, 0),
TRDC_FULL_ACCESS_GLBAC(4, 0),
TRDC_FULL_ACCESS_GLBAC(5, 0),
TRDC_FULL_ACCESS_GLBAC(6, 0),
TRDC_FULL_ACCESS_GLBAC(7, 0),
TRDC_FULL_ACCESS_GLBAC(0, 1), /* MBC1 */
TRDC_FULL_ACCESS_GLBAC(1, 1),
TRDC_FULL_ACCESS_GLBAC(2, 1),
TRDC_FULL_ACCESS_GLBAC(3, 1),
TRDC_FULL_ACCESS_GLBAC(4, 1),
TRDC_FULL_ACCESS_GLBAC(5, 1),
TRDC_FULL_ACCESS_GLBAC(6, 1),
TRDC_FULL_ACCESS_GLBAC(7, 1),
};
/* TRDC2 MBC block assignments. */
struct trdc_mbc_config trdc_w_mbc[] =
{
TRDC_VALID_DOMAINS_MBC(0, 0), /* MBC_W0 AIPS2 */
TRDC_VALID_DOMAINS_MBC(0, 1), /* MBC_W0 GPIO2/4/6 */
TRDC_VALID_DOMAINS_MBC(0, 2), /* MBC_W0 GPIO3/5 */
TRDC_VALID_DOMAINS_MBC(0, 3), /* MBC_W0 DAP */
TRDC_VALID_DOMAINS_MBC(1, 0), /* MBC_W1 AIPS3 */
TRDC_VALID_DOMAINS_MBC(1, 1), /* MBC_W1 AHB_ISPAP */
TRDC_VALID_DOMAINS_MBC(1, 2), /* MBC_W1 NIC_MAIN GPV */
TRDC_VALID_DOMAINS_MBC(1, 3), /* MBC_W1 SRAMC */
};
struct trdc_glbac_config trdc_w_mrc_glbac[] =
{
TRDC_FULL_ACCESS_GLBAC(0, 1), /* MRC1 */
TRDC_FULL_ACCESS_GLBAC(1, 1),
TRDC_FULL_ACCESS_GLBAC(2, 1),
TRDC_FULL_ACCESS_GLBAC(3, 1),
TRDC_FULL_ACCESS_GLBAC(4, 1),
TRDC_FULL_ACCESS_GLBAC(5, 1),
TRDC_FULL_ACCESS_GLBAC(6, 1),
TRDC_FULL_ACCESS_GLBAC(7, 1),
TRDC_FULL_ACCESS_GLBAC(0, 2), /* MRC2 */
TRDC_FULL_ACCESS_GLBAC(1, 2),
TRDC_FULL_ACCESS_GLBAC(2, 2),
TRDC_FULL_ACCESS_GLBAC(3, 2),
TRDC_FULL_ACCESS_GLBAC(4, 2),
TRDC_FULL_ACCESS_GLBAC(5, 2),
TRDC_FULL_ACCESS_GLBAC(6, 2),
TRDC_FULL_ACCESS_GLBAC(7, 2),
TRDC_FULL_ACCESS_GLBAC(0, 3), /* MRC3 */
TRDC_FULL_ACCESS_GLBAC(1, 3),
TRDC_FULL_ACCESS_GLBAC(2, 3),
TRDC_FULL_ACCESS_GLBAC(3, 3),
TRDC_FULL_ACCESS_GLBAC(4, 3),
TRDC_FULL_ACCESS_GLBAC(5, 3),
TRDC_FULL_ACCESS_GLBAC(6, 3),
TRDC_FULL_ACCESS_GLBAC(7, 3),
TRDC_FULL_ACCESS_GLBAC(0, 4), /* MRC4 */
TRDC_FULL_ACCESS_GLBAC(1, 4),
TRDC_FULL_ACCESS_GLBAC(2, 4),
TRDC_FULL_ACCESS_GLBAC(3, 4),
TRDC_FULL_ACCESS_GLBAC(4, 4),
TRDC_FULL_ACCESS_GLBAC(5, 4),
TRDC_FULL_ACCESS_GLBAC(6, 4),
TRDC_FULL_ACCESS_GLBAC(7, 4),
TRDC_FULL_ACCESS_GLBAC(0, 5), /* MRC5 */
TRDC_FULL_ACCESS_GLBAC(1, 5),
TRDC_FULL_ACCESS_GLBAC(2, 5),
TRDC_FULL_ACCESS_GLBAC(3, 5),
TRDC_FULL_ACCESS_GLBAC(4, 5),
TRDC_FULL_ACCESS_GLBAC(5, 5),
TRDC_FULL_ACCESS_GLBAC(6, 5),
TRDC_FULL_ACCESS_GLBAC(7, 5),
TRDC_FULL_ACCESS_GLBAC(0, 6), /* MRC6 */
TRDC_FULL_ACCESS_GLBAC(1, 6),
TRDC_FULL_ACCESS_GLBAC(2, 6),
TRDC_FULL_ACCESS_GLBAC(3, 6),
TRDC_FULL_ACCESS_GLBAC(4, 6),
TRDC_FULL_ACCESS_GLBAC(5, 6),
TRDC_FULL_ACCESS_GLBAC(6, 6),
TRDC_FULL_ACCESS_GLBAC(7, 6),
};
/* TRDC2 MRC region assignments. */
struct trdc_mrc_config trdc_w_mrc[] =
{
TRDC_VALID_DOMAINS_MRC(1, TRDC_FLEXSPI1_BASE, TRDC_FLEXSPI1_SIZE),
TRDC_VALID_DOMAINS_MRC(2, TRDC_CM7_TCM_BASE, TRDC_CM7_TCM_SIZE),
TRDC_VALID_DOMAINS_MRC(3, TRDC_OCRAM1_BASE, TRDC_OCRAM1_SIZE),
TRDC_VALID_DOMAINS_MRC(4, TRDC_OCRAM2_BASE, TRDC_OCRAM2_SIZE),
TRDC_VALID_DOMAINS_MRC(5, TRDC_SEMC_BASE, TRDC_SEMC_SIZE),
TRDC_VALID_DOMAINS_MRC(6, TRDC_NETC_BASE, TRDC_NETC_SIZE),
};
#endif /* __BOARDS_ARM_IMXRT_IMXRT1180_EVK_INCLUDE_IMXRT118X_TRDC_CONFIG_H */

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############################################################################
# boards/arm/imxrt/imxrt1180-evk/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
# Select the right Toolchain.defs (ARMv7-M for the M7 build, ARMv8-M for the
# M33 build) and the matching per-core linker script.
ifeq ($(CONFIG_ARCH_CORTEXM33),y)
include $(TOPDIR)/arch/arm/src/armv8-m/Toolchain.defs
LDSCRIPT = flash-m33.ld
else
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = flash.ld
endif
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
# Post-build: assemble the flashable image "flash.bin" for CM33 builds.
#
# CM33 builds
# flash.bin = FCB (0x400)
# + AHAB container (this NuttX image) at 0x1000
# Programmed at FlexSPI offset 0 (flash address 0x28000000). The M33
# image is confined to the first 512 KB of NOR.
#
# The AHAB container is assembled by NXP SPSDK "nxpimage". The build
# script bootstraps a private SPSDK venv on first run (see
# tools/imxrt1180/build_flash_image.sh for the license note and cache
# location).
FLASH_BUILDER = $(TOPDIR)$(DELIM)tools$(DELIM)imxrt1180$(DELIM)build_flash_image.sh
ifeq ($(CONFIG_ARCH_CORTEXM33),y)
define POSTBUILD
$(Q) echo "Assembling MIMXRT1180-EVK FlexSPI NOR image (CM33 target)"
$(Q) $(OBJCOPY) -O binary -R .bss -R .initstack $(BIN) nuttx.bin
$(Q) $(FLASH_BUILDER) \
--m33 nuttx.bin \
--out flash.bin
$(Q) echo "flash.bin" >> nuttx.manifest
endef
else
define POSTBUILD
$(Q) echo "Building MIMXRT1180-EVK Cortex-M7 payload (nuttx.bin)"
$(Q) $(OBJCOPY) -O binary -R .bss -R .initstack $(BIN) nuttx.bin
endef
endif

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Linker script for the imxrt1180-evk NuttX build targeting the Cortex-M33
* core (nsh-m33 config). This is a fully independent image; there is no
* M33 stub in front of it — the ROM's AHAB flow loads NuttX itself onto
* the M33.
*
* Layout of flash.bin (assembled by tools/imxrt1180/build_flash_image.sh):
*
* 0x2800_0400 FCB (baked into this image via .boot_hdr.conf)
* 0x2800_1000 NXP ELE FW AHAB container (injected by build script)
* 0x2800_?000 Our AHAB container header (injected by build script)
* 0x2800_B000 This image's .vectors and .text (XIP)
*
* The M33 image is confined to the first 512 KB of FlexSPI1 NOR; the
* Cortex-M7 image (scripts/flash.ld) starts at 0x2808_0000.
*
* Data/BSS live in the M33 System TCM at 0x2000_0000 (128 KB). Code TCM
* (0x0FFE_0000, 128 KB) is left alone for possible ramfuncs.
*
* USB DMA buffers cannot live in System TCM, since it is not reachable
* by the USB controller's DMA engine. These buffers are placed in the
* `.dmamemory` section in OCRAM2 instead (see imxrt_dma_alloc.c).
*/
MEMORY
{
flash (rx) : ORIGIN = 0x28000000, LENGTH = 512K /* FlexSPI XIP window reserved for the M33 image */
systcm (rwx): ORIGIN = 0x20000000, LENGTH = 128K /* CM33 private System TCM */
ocram2 (rw) : ORIGIN = 0x20500000, LENGTH = 16K /* OCRAM2 (DMA/TRDC accessible); USB DMA buffers only */
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
EXTERN(g_flash_config)
ENTRY(_stext)
SECTIONS
{
/* FCB slot at the ROM-mandated offset. */
.fcb 0x28000400 : ALIGN(4)
{
KEEP(*(.boot_hdr.conf))
. = ALIGN(4);
} > flash
/* Vector table + code at the fixed XIP address the ROM's AHAB flow
* will jump to after loading the ELE FW and validating our container.
*/
.text 0x2800B000 : ALIGN(4)
{
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section :
{
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab :
{
*(.ARM.extab*)
} > flash
.ARM.exidx :
{
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > flash
.tdata :
{
_stdata = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*)
_etdata = ABSOLUTE(.);
} > flash
.tbss :
{
_stbss = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon)
_etbss = ABSOLUTE(.);
} > flash
_eronly = ABSOLUTE(.);
.data :
{
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > systcm AT > flash
.ramfunc ALIGN(4):
{
_sramfuncs = ABSOLUTE(.);
*(.ramfunc .ramfunc.*)
_eramfuncs = ABSOLUTE(.);
} > systcm AT > flash
_framfuncs = LOADADDR(.ramfunc);
.bss :
{
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} > systcm
/* USB DMA-reachable buffers (endpoint queue heads/transfer
* descriptors, etc). See the OCRAM2 rationale above.
*/
.dmamemory (NOLOAD) :
{
_sdmamemory = ABSOLUTE(.);
*(.dmamemory .dmamemory.*)
. = ALIGN(4);
_edmamemory = ABSOLUTE(.);
} > ocram2
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_boot_loadaddr = ORIGIN(flash);
_boot_size = LENGTH(flash);
_ram_size = LENGTH(systcm);
}
/* The M7 image starts at 0x2808_0000. Fail the link rather than silently
* producing an M33 image that runs into it.
*/
ASSERT(ORIGIN(flash) + LENGTH(flash) <= 0x28080000,
"M33 flash region overlaps the M7 image at 0x28080000")

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/scripts/flash.ld
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The Cortex-M7 image is a raw XIP payload; it carries no FCB and no AHAB
* container of its own. The M33 image (the "bl" bootloader config, or any
* other M33 build) owns the first 512 KB of FlexSPI1 NOR and releases the
* M7 with INITVTOR pointing at this payload.
*
* FlexSPI1 NOR layout:
*
* 0x2800_0000 .. 0x2807_FFFF M33 image (512 KB reserved)
* 0x2808_0000 .. 0x287F_FFFF M7 image (this script, 7.5 MB window)
*
* NuttX's stack, .data, .ramfunc and .bss live in OCRAM1, which the M33
* grants the M7 R/W/X through TRDC2 MRC_W3 before releasing it. DTCM and
* ITCM are declared above but are not used by any section; they are
* tightly-coupled to the M7 core and have no TRDC in the access path, so
* they remain available for opt-in placement.
*/
MEMORY
{
flash (rx) : ORIGIN = 0x28080000, LENGTH = 4M /* Cortex-M7 XIP window (after the 512K M33/bl reserve) */
ocram (rwx) : ORIGIN = 0x20484000, LENGTH = 480K /* OCRAM1 minus ROM patch (0x20480000..0x20483fff) and M33 reserve (0x204fc000..0x204fffff) */
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* M7 DTCM (opt-in) */
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 256K /* M7 ITCM (opt-in) */
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text : ALIGN(4)
{
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section :
{
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash
.ARM.extab :
{
*(.ARM.extab*)
} > flash
.ARM.exidx :
{
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > flash
.tdata :
{
_stdata = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*)
_etdata = ABSOLUTE(.);
} > flash
.tbss :
{
_stbss = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon)
_etbss = ABSOLUTE(.);
} > flash
_eronly = ABSOLUTE(.);
.data :
{
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ocram AT > flash
.ramfunc ALIGN(4):
{
_sramfuncs = ABSOLUTE(.);
*(.ramfunc .ramfunc.*)
_eramfuncs = ABSOLUTE(.);
} > ocram AT > flash
_framfuncs = LOADADDR(.ramfunc);
.bss :
{
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} > ocram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_boot_loadaddr = ORIGIN(flash);
_boot_size = LENGTH(flash);
_ram_size = LENGTH(ocram);
}

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############################################################################
# boards/arm/imxrt/imxrt1180-evk/src/Makefile
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = imxrt_boot.c imxrt_bringup.c imxrt_appinit.c
# On the M33 target the ROM boots our image directly, so we must supply the
# FlexSPI Configuration Block ourselves. The M7 image is a raw XIP payload
# and carries no flash headers.
ifeq ($(CONFIG_ARCH_CORTEXM33),y)
CSRCS += imxrt_flash_headers.c
endif
ifeq ($(CONFIG_IMXRT1180_EVK_BOOTLOADER),y)
CSRCS += imxrt_bootloader.c
endif
ifeq ($(CONFIG_USBDEV_DMAMEMORY),y)
CSRCS += imxrt_dma_alloc.c
endif
# TRDC descriptors can only be programmed by the core that owns them, which
# is the M33 (CONFIG_IMXRT_TRDC is selected only by the M33 chip choice).
# There is no weak fallback for the board hook: if TRDC is enabled the board
# must supply an access policy, or the link fails.
ifeq ($(CONFIG_IMXRT_TRDC),y)
endif
include $(TOPDIR)/boards/Board.mk

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt1180-evk.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_ARM_IMXRT_IMXRT1180_EVK_SRC_IMXRT1180_EVK_H
#define __BOARDS_ARM_IMXRT_IMXRT1180_EVK_SRC_IMXRT1180_EVK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <stdint.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
int imxrt_bringup(void);
#ifdef CONFIG_USBDEV_DMAMEMORY
int imxrt_dma_alloc_init(void);
#endif
#endif /* __BOARDS_ARM_IMXRT_IMXRT1180_EVK_SRC_IMXRT1180_EVK_H */

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt_appinit.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <errno.h>
#include "imxrt1180-evk.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application-specific initialization.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifdef CONFIG_BOARD_LATE_INITIALIZE
return 0;
#else
return imxrt_bringup();
#endif
}

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt_boot.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "imxrt_iomuxc.h"
#include "imxrt_gpio.h"
#include "imxrt_clockconfig.h"
#include "imxrt1180-evk.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_boardinitialize
*
* Description:
* All i.MX RT architectures must provide the following entry point. This
* entry point is called early in the initialization -- after clocking and
* memory have been configured but before caches have been enabled and
* before any devices have been initialized.
*
****************************************************************************/
void imxrt_boardinitialize(void)
{
/* Configure the two user LEDs */
imxrt_clockall_gpio4();
imxrt_config_gpio(GPIO_LED1);
imxrt_config_gpio(GPIO_LED2);
imxrt_gpio_write(GPIO_LED2, true);
}
/****************************************************************************
* Name: board_late_initialize
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
imxrt_bringup();
}
#endif

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt_bootloader.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdlib.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <arch/irq.h>
#include "imxrt118x_start_cm7.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define M7_ENTRY 0x28080000u
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: bootloader_main
*
* Description:
* Release the Cortex-M7 and sleep forever.
*
****************************************************************************/
int bootloader_main(int argc, char *argv[])
{
/* Hand over LPUART1 to the M7: disable the IRQ on the M33 NVIC and
* detach its handler.
*/
up_disable_irq(IMXRT_IRQ_LPUART1);
irq_detach(IMXRT_IRQ_LPUART1);
if (imxrt118x_release_cm7(M7_ENTRY) < 0)
{
return EXIT_FAILURE;
}
while (1)
{
usleep(10000);
}
return 0;
}

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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt_bringup.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/mount.h>
#include <syslog.h>
#include <nuttx/fs/fs.h>
#include "imxrt1180-evk.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_bringup
*
* Description:
* Bring up board resources. For the minimal MIMXRT1180-EVK NSH
* configuration this only mounts /proc when procfs is enabled.
*
****************************************************************************/
int imxrt_bringup(void)
{
int ret = OK;
#ifdef CONFIG_USBDEV_DMAMEMORY
ret = imxrt_dma_alloc_init();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to initialize DMA allocator: %d\n",
ret);
}
#endif
#ifdef CONFIG_FS_PROCFS
ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount procfs: %d\n", ret);
}
#endif
return ret;
}

160
boards/arm/imxrt/imxrt1180-evk/src/imxrt_dma_alloc.c Normal file
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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt_dma_alloc.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/mm/gran.h>
#include <nuttx/compiler.h>
#include "imxrt1180-evk.h"
#if defined(CONFIG_GRAN)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* On the imxrt1180-evk M33 image, .data/.bss/heap live in the CM33's
* private System TCM, which the USB controller's DMA engine cannot reach
* (it isn't part of the TRDC-controlled shared memory map). The USB
* class driver's request buffers (imxrt_epallocbuffer()/usbdev_dma_alloc())
* must therefore come from a separate, DMA-reachable pool. We put that
* pool in the same OCRAM2 `.dmamemory` linker section already used for the
* USB controller's endpoint queue heads/transfer descriptors and EP0
* buffer (see arch/arm/src/imxrt/imxrt_usbdev.c and
* boards/arm/imxrt/imxrt1180-evk/scripts/flash-m33.ld).
*
* The pool must be big enough for all buffers that can be concurrently
* allocated by the bound class driver. For CDC/ACM with the default
* config (4 read + 4 write requests) this is roughly:
* 1 x CDCACM_MXDESCLEN (ctrlreq, 64B)
* CONFIG_CDCACM_NRDREQS x CONFIG_CDCACM_BULKOUT_REQLEN (4 x 512 = 2048B)
* CONFIG_CDCACM_NWRREQS x CONFIG_CDCACM_BULKIN_REQLEN (4 x 96 = 384B)
* i.e. ~2.5KB; round up generously to leave headroom for granule/alignment
* overhead and other endpoints.
*/
#define IMXRT_DMA_POOL_SIZE (6 * 1024)
/****************************************************************************
* Private Data
****************************************************************************/
static GRAN_HANDLE g_dma_allocator;
static uint8_t g_dma_heap[IMXRT_DMA_POOL_SIZE]
locate_data(".dmamemory")
aligned_data(32);
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_dma_alloc_init
*
* Description:
* Initialize the DMA-reachable memory pool used to back board USB
* device request buffers. Called once from board bringup, before any
* USB device activity.
*
****************************************************************************/
int imxrt_dma_alloc_init(void)
{
g_dma_allocator = gran_initialize(g_dma_heap,
sizeof(g_dma_heap),
5, /* 32-byte granule */
5); /* 32-byte alignment */
return g_dma_allocator == NULL ? -ENOMEM : OK;
}
/****************************************************************************
* Name: usbdev_dma_alloc
*
* Description:
* Allocate a DMA-reachable buffer for use by a USB device driver.
*
* gran_free() needs to know the size of the allocation being freed, but
* usbdev_dma_free() is not given a size (see include/nuttx/usb/usbdev.h).
* We work around this by prepending a small header that records the
* total granule allocation size.
*
****************************************************************************/
struct usbdma_header_s
{
size_t allocsize;
};
void *usbdev_dma_alloc(size_t size)
{
struct usbdma_header_s *hdr;
size_t allocsize;
DEBUGASSERT(g_dma_allocator != NULL);
allocsize = size + sizeof(struct usbdma_header_s);
hdr = gran_alloc(g_dma_allocator, allocsize);
if (hdr == NULL)
{
return NULL;
}
hdr->allocsize = allocsize;
return (void *)(hdr + 1);
}
/****************************************************************************
* Name: usbdev_dma_free
*
* Description:
* Free a DMA-reachable buffer previously allocated with
* usbdev_dma_alloc().
*
****************************************************************************/
void usbdev_dma_free(void *mem)
{
struct usbdma_header_s *hdr;
DEBUGASSERT(g_dma_allocator != NULL);
if (mem == NULL)
{
return;
}
hdr = ((struct usbdma_header_s *)mem) - 1;
gran_free(g_dma_allocator, hdr, hdr->allocsize);
}
#endif /* CONFIG_GRAN */

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boards/arm/imxrt/imxrt1180-evk/src/imxrt_flash_headers.c Normal file
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/****************************************************************************
* boards/arm/imxrt/imxrt1180-evk/src/imxrt_flash_headers.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
/* Flash headers baked into the M33 boot image at the offsets the RT1180
* ROM expects (IMXRT1180RM Ch. 12 Fig. 50):
*
* 0x0000_0400 Serial NOR Flash Configuration Block (FCB, 512 B)
*
* The AHAB container is NOT baked into this object file. It is added
* later by tools/imxrt1180/build_flash_image.sh, which invokes NXP's
* SPSDK "nxpimage" tool to assemble:
*
* 0x0000_?000 Application AHAB container (this M33 image)
*
* The Cortex-M7 image is flashed separately at offset 0x0008_0000 and is
* a raw XIP payload with no flash headers of its own.
*
* The M7 payload is not wrapped in an AHAB container: the M33 bootloader
* ("bl" configuration) points the M7 at raw flash offset 0x80000 (XIP
* address 0x28080000) and releases it by clearing M7_CFG.WAIT.
*
* The board fits a Winbond W25Q128JWSIQ (16 MB, 1.8 V QSPI) on
* FlexSPI1 Port A (verified in the MIMXRT1180-EVK schematic, ref U12).
*/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* FlexSPI Configuration Block (FCB) */
#define FLEXSPI_LUT_OPCODE0(x) ((uint32_t)((x) & 0x3f) << 10)
#define FLEXSPI_LUT_NUM_PADS0(x) ((uint32_t)((x) & 0x03) << 8)
#define FLEXSPI_LUT_OPERAND0(x) ((uint32_t)((x) & 0xff))
#define FLEXSPI_LUT_OPCODE1(x) ((uint32_t)((x) & 0x3f) << 26)
#define FLEXSPI_LUT_NUM_PADS1(x) ((uint32_t)((x) & 0x03) << 24)
#define FLEXSPI_LUT_OPERAND1(x) ((uint32_t)((x) & 0xff) << 16)
#define FLEXSPI_LUT_SEQ(c0, p0, o0, c1, p1, o1) \
(FLEXSPI_LUT_OPERAND0(o0) | FLEXSPI_LUT_NUM_PADS0(p0) | \
FLEXSPI_LUT_OPCODE0(c0) | FLEXSPI_LUT_OPERAND1(o1) | \
FLEXSPI_LUT_NUM_PADS1(p1) | FLEXSPI_LUT_OPCODE1(c1))
#define CMD_SDR 0x01
#define RADDR_SDR 0x02
#define DUMMY_SDR 0x0c
#define READ_SDR 0x09
#define WRITE_SDR 0x08
#define STOP 0x00
#define FLEXSPI_1PAD 0
#define FLEXSPI_4PAD 2
/****************************************************************************
* Private Types
****************************************************************************/
/* Layout matches IMXRT1180RM Ch. 12 Table 62/65 (identical to the RT1170
* FCB layout so we can reuse the flexspi_nor_config_s / flexspi_mem_config_s
* struct definitions from the imxrt1170-evk board without change).
*/
struct flexspi_lut_seq_s
{
uint8_t seq_num;
uint8_t seq_id;
uint16_t reserved;
};
struct flexspi_mem_config_s
{
uint32_t tag;
uint32_t version;
uint32_t reserved0;
uint8_t read_sample_clk_src;
uint8_t cs_hold_time;
uint8_t cs_setup_time;
uint8_t column_address_width;
uint8_t device_mode_cfg_enable;
uint8_t device_mode_type;
uint16_t wait_time_cfg_commands;
struct flexspi_lut_seq_s device_mode_seq;
uint32_t device_mode_arg;
uint8_t config_cmd_enable;
uint8_t config_mode_type[3];
struct flexspi_lut_seq_s config_cmd_seqs[3];
uint32_t reserved1;
uint32_t config_cmd_args[3];
uint32_t reserved2;
uint32_t controller_misc_option;
uint8_t device_type;
uint8_t sflash_pad_type;
uint8_t serial_clk_freq;
uint8_t lut_custom_seq_enable;
uint32_t reserved3[2];
uint32_t sflash_a1_size;
uint32_t sflash_a2_size;
uint32_t sflash_b1_size;
uint32_t sflash_b2_size;
uint32_t cs_pad_setting_override;
uint32_t sclk_pad_setting_override;
uint32_t data_pad_setting_override;
uint32_t dqs_pad_setting_override;
uint32_t timeout_in_ms;
uint32_t command_interval;
uint16_t data_valid_time[2];
uint16_t busy_offset;
uint16_t busy_bit_polarity;
uint32_t lookup_table[64];
struct flexspi_lut_seq_s lut_custom_seq[12];
uint32_t reserved4[4];
};
struct flexspi_nor_config_s
{
struct flexspi_mem_config_s mem_config;
uint32_t page_size;
uint32_t sector_size;
uint8_t ipcmd_serial_clk_freq;
uint8_t is_uniform_block_size;
uint8_t reserved0[2];
uint32_t block_size;
uint32_t reserved1[11];
};
#define FCB_TAG 0x42464346u /* 'FCFB' little endian */
#define FCB_VERSION 0x56010400u /* v1.4.0 */
/****************************************************************************
* Public Data
****************************************************************************/
/* Winbond W25Q128JW: 16 MB, 4 KB sector, 64 KB block, 256 B page.
* QSPI @ 133 MHz, DQS loopback, LUT provides 0xEB Quad I/O Read (24-bit
* address, 6 dummy cycles) — matches the MCUXpresso SDK reference config
* for evkmimxrt1180 (evkmimxrt1180_flexspi_nor_config.c).
*/
__attribute__((section(".boot_hdr.conf"), used))
const struct flexspi_nor_config_s g_flash_config =
{
.mem_config =
{
.tag = FCB_TAG,
.version = FCB_VERSION,
.read_sample_clk_src = 1, /* Loopback from DQS pad */
.cs_hold_time = 3,
.cs_setup_time = 3,
.controller_misc_option = 0x10,
.device_type = 1, /* Serial NOR */
.sflash_pad_type = 4, /* 4 pads (QSPI) */
.serial_clk_freq = 7, /* 133 MHz */
.sflash_a1_size = 16u * 1024u * 1024u,
.lookup_table =
{
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xeb,
RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06,
READ_SDR, FLEXSPI_4PAD, 0x04),
[4 * 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
READ_SDR, FLEXSPI_1PAD, 0x04),
[4 * 3] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06,
STOP, FLEXSPI_1PAD, 0x00),
[4 * 5] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20,
RADDR_SDR, FLEXSPI_1PAD, 0x18),
[4 * 8] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8,
RADDR_SDR, FLEXSPI_1PAD, 0x18),
[4 * 9] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02,
RADDR_SDR, FLEXSPI_1PAD, 0x18),
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04,
STOP, FLEXSPI_1PAD, 0x00),
[4 * 11] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60,
STOP, FLEXSPI_1PAD, 0x00),
},
},
.page_size = 256u,
.sector_size = 4u * 1024u,
.ipcmd_serial_clk_freq = 1,
.is_uniform_block_size = 0,
.block_size = 64u * 1024u,
};
/****************************************************************************
* Public Functions
****************************************************************************/
/* No functions in this file — boot header data only. The AHAB container
* that references this M33 image is generated separately by
* tools/imxrt1180/build_flash_image.sh using NXP SPSDK "nxpimage".
* The M7 NuttX payload is not part of any AHAB container: it is flashed
* raw at flash offset 0x80000 (XIP address 0x28080000) and started by the
* M33 bootloader with WAIT cleared.
*/

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#!/usr/bin/env sh
# SPDX-License-Identifier: Apache-2.0
#
# Flash a NuttX image to the MIMXRT1180-EVK using SEGGER J-Link.
#
# Usage:
# ./flash-jlink.sh <image.bin> <flash-offset>
#
# Arguments:
# image.bin Binary to program.
# flash-offset Offset within FlexSPI1 NOR, either as an absolute
# flash address (0x28080000) or as an offset from the
# flash base (0x80000). Both forms are accepted.
#
# The two images of the MIMXRT1180-EVK build are programmed with two
# separate invocations:
#
# # Cortex-M33 bootloader / application (imxrt1180-evk:bl, :nsh-m33)
# ./flash-jlink.sh flash.bin 0x0
#
# # Cortex-M7 NuttX payload (imxrt1180-evk:nsh)
# ./flash-jlink.sh nuttx.bin 0x80000
#
# J-Link only erases the sectors the image actually covers, so flashing
# one image leaves the other intact.
#
# The script assumes:
# * A SEGGER J-Link probe is attached to the EVK JTAG connector (J37)
# or an MCU-Link running SEGGER's "MCU-Link J-Link" firmware is used
# via J53.
# * SW5 = 0100 (FlexSPI Quad SPI NOR boot).
# * The J-Link software (v7.98a or later, which adds MIMXRT1189
# device support) is installed and JLinkExe is on PATH.
#
# Overrides via environment variables:
# JLINK_EXE - JLinkExe binary (default: JLinkExe)
# JLINK_SPEED - SWD speed in kHz (default: 4000)
# JLINK_IF - Debug interface (default: SWD)
set -eu
FLASH_BASE=0x28000000
usage() {
sed -n '4,39p' "$0" | sed 's/^# \{0,1\}//'
exit "${1:-1}"
}
# Programming targets the Cortex-M33 profile. On RT1180 the M33 is the
# boot core; the ROM initializes FlexSPI1 as part of the M33 boot, which
# is what the SEGGER flash loader needs. Connecting via the _M7 profile
# releases the M7 without running the M33/ROM init and leaves FlexSPI in
# a state where the RAM-side loader fails with "RAMCode-sided Prepare()".
# For interactive debugging of the running M7 use MIMXRT1189xxx8_M7
# (see gdbserver-jlink.sh).
JLINK_DEVICE=MIMXRT1189xxx8_M33
if [ $# -eq 0 ]; then
usage 0
fi
if [ $# -ne 2 ]; then
echo "Error: expected 2 arguments, got $#." >&2
echo >&2
usage 1
fi
FLASH_BIN="$1"
OFFSET_ARG="$2"
JLINK_EXE="${JLINK_EXE:-JLinkExe}"
JLINK_SPEED="${JLINK_SPEED:-4000}"
JLINK_IF="${JLINK_IF:-SWD}"
if [ ! -f "$FLASH_BIN" ]; then
echo "Error: $FLASH_BIN not found." >&2
echo " Run 'make' first to produce it, or pass the path as an" >&2
echo " argument to this script." >&2
exit 1
fi
if ! command -v "$JLINK_EXE" >/dev/null 2>&1; then
echo "Error: '$JLINK_EXE' not found on PATH." >&2
echo " Install the SEGGER J-Link Software Pack from" >&2
echo " https://www.segger.com/downloads/jlink/" >&2
exit 1
fi
# Resolve the offset to an absolute flash address. Values already inside
# the FlexSPI1 XIP window are taken as-is; anything smaller is treated as
# an offset relative to the flash base.
OFFSET=$(printf "%d" "$OFFSET_ARG" 2>/dev/null) || {
echo "Error: '$OFFSET_ARG' is not a valid numeric offset." >&2
exit 1
}
if [ "$OFFSET" -lt "$(printf "%d" $FLASH_BASE)" ]; then
ADDR=$((OFFSET + FLASH_BASE))
else
ADDR=$OFFSET
fi
ADDR_HEX=$(printf "0x%08X" "$ADDR")
# JLinkExe reads the commander script from -CommanderScript. Generate it
# on the fly so the load address can be parameterized, and stage both in
# a temp working directory that JLinkExe is invoked from.
WORK_DIR=$(mktemp -d)
trap 'rm -rf "$WORK_DIR"' EXIT
cp "$FLASH_BIN" "$WORK_DIR/image.bin"
cat > "$WORK_DIR/flash.jlink" <<JLINK
r
halt
loadbin image.bin, $ADDR_HEX
r
g
q
JLINK
FLASH_SIZE=$(stat -c%s "$FLASH_BIN")
echo "Flashing $FLASH_BIN ($FLASH_SIZE B) at $ADDR_HEX"
echo " via $JLINK_EXE ($JLINK_DEVICE, $JLINK_IF @ ${JLINK_SPEED}kHz)"
(cd "$WORK_DIR" && \
"$JLINK_EXE" -device "$JLINK_DEVICE" \
-if "$JLINK_IF" \
-speed "$JLINK_SPEED" \
-autoconnect 1 \
-CommanderScript "$WORK_DIR/flash.jlink")
echo "Done."

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boards/arm/imxrt/imxrt1180-evk/tools/gdbserver-jlink.sh Executable file
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#!/usr/bin/env sh
# SPDX-License-Identifier: Apache-2.0
#
# Start a J-Link GDB server attached to the Cortex-M7 on the
# MIMXRT1180-EVK. Once running, connect from another shell with:
#
# arm-none-eabi-gdb nuttx
# (gdb) target extended-remote localhost:2331
# (gdb) monitor reset
# (gdb) continue
#
# Overrides via environment variables (same as flash-jlink.sh):
# JLINK_GDBSERVER - JLinkGDBServer binary (default: JLinkGDBServer)
# JLINK_SPEED - SWD speed in kHz (default: 4000)
# JLINK_IF - Debug interface (default: SWD)
# JLINK_PORT - GDB listen port (default: 2331)
set -eu
# Fixed for the MIMXRT1180-EVK (MIMXRT1189CVM8C, Cortex-M7 target).
JLINK_DEVICE=MIMXRT1189xxx8_M7
JLINK_GDBSERVER="${JLINK_GDBSERVER:-JLinkGDBServer}"
JLINK_SPEED="${JLINK_SPEED:-4000}"
JLINK_IF="${JLINK_IF:-SWD}"
JLINK_PORT="${JLINK_PORT:-2331}"
if ! command -v "$JLINK_GDBSERVER" >/dev/null 2>&1; then
echo "Error: '$JLINK_GDBSERVER' not found on PATH." >&2
echo " Install the SEGGER J-Link Software Pack from" >&2
echo " https://www.segger.com/downloads/jlink/" >&2
exit 1
fi
exec "$JLINK_GDBSERVER" \
-device "$JLINK_DEVICE" \
-if "$JLINK_IF" \
-speed "$JLINK_SPEED" \
-port "$JLINK_PORT" \
-singlerun \
-nogui

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tools/imxrt1180/.cache/.gitignore vendored Normal file
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tools/imxrt1180/build_flash_image.sh Executable file
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#!/usr/bin/env bash
# SPDX-License-Identifier: Apache-2.0
#
# build_flash_image.sh - assemble the MIMXRT1180-EVK bootable FlexSPI NOR
# image (flash.bin) from the freshly built
# Cortex-M33 NuttX image, using NXP SPSDK to
# generate the AHAB container.
#
# Only the Cortex-M33 image is bootable: it carries the FCB and the AHAB
# container that the ROM consumes.
#
# Tools are downloaded / installed on first use into a private cache
# directory.
#
# Usage examples:
#
# tools/imxrt1180/build_flash_image.sh --m33 nuttx.bin --out flash.bin
# tools/imxrt1180/build_flash_image.sh --m33 nuttx.bin --out flash.bin \
# --ele-fw tools/imxrt1180/.cache/ele-fw/mxrt1180b0-ahab-container.img
#
# NXP EULA note:
#
# * The SPSDK Python package is BSD-3-Clause.
# * The ELE FW AHAB container is proprietary NXP object code covered by
# the LA_OPT NXP Software License (v56 April 2024).
#
# Running the script implies acceptance of the EULA
# (same convention as --auto-accept).
#
# ---------------------------------------------------------------------------
set -euo pipefail
# ---------------------------------------------------------------------------
# Configuration
# ---------------------------------------------------------------------------
# Pinned versions. Bumping these is a code review.
SPSDK_VERSION="3.11.0"
# Flash layout constants (must match flash-m33.ld).
M33_LOAD_ADDR="0x2800B000"
FLASH_ORIGIN="0x28000000"
# The M33 image is confined to the first 512 KB of NOR; the Cortex-M7
# image starts right after it (see boards/.../scripts/flash.ld).
M33_MAX_SIZE=$((512 * 1024))
# ---------------------------------------------------------------------------
# Argument parsing
# ---------------------------------------------------------------------------
M33_BIN=""
OUT_BIN="flash.bin"
ELE_FW_BIN=""
usage() {
sed -n '2,32p' "$0"
exit 0
}
err() { printf "error: %s\n" "$*" >&2; exit 1; }
while [ $# -gt 0 ]; do
case "$1" in
--m33) M33_BIN="$2"; shift 2 ;;
--out) OUT_BIN="$2"; shift 2 ;;
--ele-fw) ELE_FW_BIN="$2"; shift 2 ;;
-h|--help) usage ;;
*) err "unknown argument: $1" ;;
esac
done
# Only one mode: --m33 <nuttx.bin> produces FCB @ 0x400 + AHAB @ 0x1000,
# the AHAB container holding the M33 app image and, when --ele-fw is
# given, the NXP ELE firmware as a second image in the same container so
# that the RT118x ROM loads it automatically before the M33 app runs.
[ -n "${M33_BIN}" ] || err "--m33 <nuttx.bin> is required"
[ -f "${M33_BIN}" ] || err "M33 nuttx binary '${M33_BIN}' not found"
[ -z "${ELE_FW_BIN}" ] || [ -f "${ELE_FW_BIN}" ] || \
err "ELE firmware container '${ELE_FW_BIN}' not found"
# ---------------------------------------------------------------------------
# Paths
# ---------------------------------------------------------------------------
TOP_DIR="$(cd "$(dirname "$0")/../.." && pwd)"
CACHE_DIR="${TOP_DIR}/tools/imxrt1180/.cache"
VENV_DIR="${CACHE_DIR}/spsdk-venv"
WORK_DIR="${CACHE_DIR}/build-$$"
NXPIMAGE="${VENV_DIR}/bin/nxpimage"
mkdir -p "${CACHE_DIR}"
cleanup() { rm -rf "${WORK_DIR}"; }
trap cleanup EXIT
# ---------------------------------------------------------------------------
# 1. Bootstrap SPSDK into a private venv (idempotent)
# ---------------------------------------------------------------------------
if [ ! -x "${NXPIMAGE}" ] || \
! "${NXPIMAGE}" --version 2>/dev/null | grep -q "version ${SPSDK_VERSION}"
then
echo "Installing NXP SPSDK ${SPSDK_VERSION} into ${VENV_DIR}"
rm -rf "${VENV_DIR}"
python3 -m venv "${VENV_DIR}"
"${VENV_DIR}/bin/pip" install --quiet --upgrade pip
"${VENV_DIR}/bin/pip" install --quiet "spsdk==${SPSDK_VERSION}"
fi
# ---------------------------------------------------------------------------
# 2. (nothing to do here — when requested, the ELE FW container fetched via
# tools/imxrt1180/Config.mk is packed directly into the AHAB image
# below, as a second image entry in the same container)
# ---------------------------------------------------------------------------
# ---------------------------------------------------------------------------
# 3. Extract the FCB + XIP code from the input image
#
# The M33 linker script places the FCB at VMA 0x28000400 and the XIP code at VMA 0x2800B000.
# arm-none-eabi-objcopy lays these out as a flat binary starting from the
# lowest section VMA, so inside the input binary the FCB sits at file
# offset 0 and the code sits at 0xB000 - 0x400 = 0xAC00.
# ---------------------------------------------------------------------------
mkdir -p "${WORK_DIR}"
FCB_BIN="${WORK_DIR}/fcb.bin"
CODE_BIN="${WORK_DIR}/code.bin"
SRC_BIN="${M33_BIN}"
LOAD_ADDR="${M33_LOAD_ADDR}"
SRC_SIZE="$(stat -c%s "${SRC_BIN}")"
# FCB: 512 B at file offset 0
dd if="${SRC_BIN}" of="${FCB_BIN}" bs=1 count=512 status=none
# XIP code: everything from file offset 0xAC00 (= 0xB000 - 0x400) onward.
CODE_OFF=$((0xB000 - 0x400))
CODE_SIZE=$((SRC_SIZE - CODE_OFF))
[ "${CODE_SIZE}" -gt 0 ] || \
err "input binary shorter than expected (code offset 0x${CODE_OFF})"
dd if="${SRC_BIN}" of="${CODE_BIN}" bs=1 skip=${CODE_OFF} count=${CODE_SIZE} \
status=none
# ---------------------------------------------------------------------------
# 4. Emit the AHAB config YAML
#
# When --ele-fw is given, the output holds *two* AHAB containers back to
# back: container 0 is the raw NXP ELE FW AHAB container (embedded as-is
# via "binary_container" - it is already a complete, signed AHAB
# container in its own right, so it must be its own container, not an
# image inside ours), and container 1 is our own container holding the
# M33 app image. This is the layout the RT118x ROM understands for
# auto-loading ELE FW: it walks the container list, loads/starts the ELE
# container first, then processes ours.
#
# Because the code is linked for FlexSPI XIP at 0x2800B000, the code
# must physically land at flash offset 0xB000 = load_address -
# 0x28000000. nxpimage's "image_offset" is measured from the start of
# the AHAB image (not the container header), so:
#
# flash origin : 0x28000000
# AHAB blob starts : 0x00001000 (see step 5)
# code flash target : 0xB000
# image_offset in AHAB : 0xB000 - 0x1000 = 0xA000
# ---------------------------------------------------------------------------
AHAB_FLASH_OFFSET=0x1000
CODE_FLASH_OFFSET=$(( LOAD_ADDR - FLASH_ORIGIN ))
IMAGE_OFFSET=$(( CODE_FLASH_OFFSET - AHAB_FLASH_OFFSET ))
if [ "${IMAGE_OFFSET}" -le 0 ]; then
err "computed image_offset (${IMAGE_OFFSET}) is not positive - \
the XIP address must be greater than the AHAB blob's flash offset."
fi
AHAB_YAML="${WORK_DIR}/ahab.yaml"
AHAB_BIN="${WORK_DIR}/ahab.bin"
cat > "${AHAB_YAML}" <<EOF
# Auto-generated by tools/imxrt1180/build_flash_image.sh.
#
# When the NXP EdgeLock Enclave firmware is included, it is packaged as
# its own AHAB container (container 0), separate from the M33 app's
# container (container 1). The RT118x boot ROM loads the ELE FW
# container automatically as part of its AHAB processing, before the
# M33 core is released - no runtime LOAD_FW handshake is required in
# that case (see CONFIG_IMXRT_ELE_LOAD_FW in arch/arm/src/imxrt/Kconfig
# for the fallback path that still does it from NuttX).
family: mimxrt1189
revision: latest
target_memory: standard
output: ${AHAB_BIN}
output_format: bin
containers:
EOF
if [ -n "${ELE_FW_BIN}" ]; then
cat >> "${AHAB_YAML}" <<EOF
- binary_container:
path: ${ELE_FW_BIN}
EOF
fi
cat >> "${AHAB_YAML}" <<EOF
- container:
srk_set: none
fuse_version: 0
sw_version: 0
images:
- image_path: ${CODE_BIN}
image_offset: '$(printf '0x%X' "${IMAGE_OFFSET}")'
load_address: '${LOAD_ADDR}'
entry_point: '${LOAD_ADDR}'
image_type: executable
core_id: cortex-m33
is_encrypted: false
hash_type: sha256
EOF
echo "Building AHAB image (nxpimage)"
"${NXPIMAGE}" ahab export -c "${AHAB_YAML}"
# ---------------------------------------------------------------------------
# 5. Assemble flash.bin
#
# flash.bin = zero pad ... (FCB @ 0x400) ... AHAB image @ 0x1000 ...
#
# nxpimage's AHAB image is already laid out with the internal
# padding-to-1KB alignment between containers per RM Table 80.
# ---------------------------------------------------------------------------
AHAB_SIZE="$(stat -c%s "${AHAB_BIN}")"
TOTAL=$((0x1000 + AHAB_SIZE))
# The M7 image lives at flash offset 0x80000; refuse to build an M33 image
# that would run into it.
if [ "${TOTAL}" -gt "${M33_MAX_SIZE}" ]; then
err "M33 image (${TOTAL} B) exceeds the ${M33_MAX_SIZE} B reserve; \
it would overlap the Cortex-M7 image at flash offset 0x80000."
fi
rm -f "${OUT_BIN}"
dd if=/dev/zero of="${OUT_BIN}" bs=1 count="${TOTAL}" status=none
dd if="${FCB_BIN}" of="${OUT_BIN}" bs=1 seek=1024 conv=notrunc status=none
dd if="${AHAB_BIN}" of="${OUT_BIN}" bs=1 seek=4096 conv=notrunc status=none
if [ -n "${ELE_FW_BIN}" ]; then
echo "Wrote ${OUT_BIN} (FCB@0x400, AHAB@0x1000 [M33 app + ELE FW], ${TOTAL} B)"
else
echo "Wrote ${OUT_BIN} (FCB@0x400, M33 AHAB@0x1000, ${TOTAL} B)"
fi