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arch/arm/imxrt: Add register definitions for imxrt118x general power controller
Add a header file defining the imxrt118x GPC registers Assisted-by: Claude Code:claude-opus-4-7 Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
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arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h
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arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h
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/****************************************************************************
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* arch/arm/src/imxrt/hardware/rt118x/imxrt118x_gpc.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPC_H
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#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware/imxrt_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* GPC_CPU_CTRL (IMXRT1180RM Ch. 34). Two instances share the same base:
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* index 0 (offset 0x000) - Cortex-M33
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* index 1 (offset 0x800) - Cortex-M7
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*/
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#define IMXRT_GPC_CM_STEP (0x800)
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#define IMXRT_GPC_CM_AUTHEN_CTRL(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x004 + \
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(idx) * IMXRT_GPC_CM_STEP)
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#define IMXRT_GPC_CM_MISC(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x00c + \
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(idx) * IMXRT_GPC_CM_STEP)
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#define IMXRT_GPC_CM_MODE_CTRL(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x010 + \
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(idx) * IMXRT_GPC_CM_STEP)
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#define IMXRT_GPC_CM_MODE_STAT(idx) (IMXRT_GPC_CPU_CTRL_BASE + 0x014 + \
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(idx) * IMXRT_GPC_CM_STEP)
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/* Convenience aliases */
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#define IMXRT_GPC_CM33_MODE_CTRL IMXRT_GPC_CM_MODE_CTRL(0)
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#define IMXRT_GPC_CM33_MODE_STAT IMXRT_GPC_CM_MODE_STAT(0)
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#define IMXRT_GPC_CM7_MODE_CTRL IMXRT_GPC_CM_MODE_CTRL(1)
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#define IMXRT_GPC_CM7_MODE_STAT IMXRT_GPC_CM_MODE_STAT(1)
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/* CM_MODE_CTRL bit fields */
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#define GPC_CM_MODE_CTRL_TARGET_SHIFT (0)
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#define GPC_CM_MODE_CTRL_TARGET_MASK (0x3u << GPC_CM_MODE_CTRL_TARGET_SHIFT)
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#define GPC_CM_MODE_CTRL_TARGET(x) (((x) << GPC_CM_MODE_CTRL_TARGET_SHIFT) & \
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GPC_CM_MODE_CTRL_TARGET_MASK)
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#define GPC_CM_MODE_TARGET_RUN (0)
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#define GPC_CM_MODE_TARGET_WAIT (1)
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#define GPC_CM_MODE_TARGET_STOP (2)
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#define GPC_CM_MODE_TARGET_SUSPEND (3)
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#define GPC_CM_MODE_CTRL_WFE_EN (1u << 4) /* WFE can trigger low power */
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/* CM_MODE_STAT bit fields */
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#define GPC_CM_MODE_STAT_CURRENT_SHIFT (0)
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#define GPC_CM_MODE_STAT_CURRENT_MASK (0x3u << GPC_CM_MODE_STAT_CURRENT_SHIFT)
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#define GPC_CM_MODE_STAT_PREVIOUS_SHIFT (2)
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#define GPC_CM_MODE_STAT_PREVIOUS_MASK (0x3u << GPC_CM_MODE_STAT_PREVIOUS_SHIFT)
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/* CM_MISC bit fields */
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#define GPC_CM_MISC_NMI_STAT (1u << 0)
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#define GPC_CM_MISC_SLEEP_HOLD_EN (1u << 1)
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#define GPC_CM_MISC_SLEEP_HOLD_STAT (1u << 2)
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#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_GPC_H */
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