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arch/arm/imxrt: Add imxrt118x blkctrl definitions
Add IMXRT AONMIX register addresses and bit definitions in a separate header file "imxrt118x_blkctrl.h". The header is generated using AI from imxrt118x reference manual. Assisted-by: Claude Code:claude-opus-4-7 Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
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Jukka Laitinen
Xiang Xiao
parent
e24158d38f
commit
09db067af0
1 changed files with 137 additions and 0 deletions
137
arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h
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arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h
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/****************************************************************************
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* arch/arm/src/imxrt/hardware/rt118x/imxrt118x_blkctrl.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H
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#define __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware/imxrt_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* BLK_CTRL_S_AONMIX registers (IMXRT1180RM Ch. 15.4.1).
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*
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* The AON secure block controls the CM33 and CM7 interrupt masks, initial
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* vector table pointers, low-power handshakes, DAP access sticky bits and
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* NMI routing. Bases for the non-secure alias are provided in
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* hardware/rt118x/imxrt118x_memorymap.h.
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*/
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#define IMXRT_AON_CM33_IRQ_MASK(n) (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x000 + \
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((n) << 2)) /* 8 x 32b IRQ mask */
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#define IMXRT_AON_CM7_IRQ_MASK(n) (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x020 + \
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((n) << 2))
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#define IMXRT_AON_EDGELOCK_RESET_MASK (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x058)
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#define IMXRT_AON_EDGELOCK_IRQ_MASK (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x05c)
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#define IMXRT_AON_M33_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x060)
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#define IMXRT_AON_M33_INITSVTOR (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x064)
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#define IMXRT_AON_M33_INITNSVTOR (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x068)
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#define IMXRT_AON_M7_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x080)
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#define IMXRT_AON_AXBS_AON_CTRL (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x090)
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#define IMXRT_AON_DAP_ACCESS_STKYBIT (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x100)
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#define IMXRT_AON_LP_HANDSHAKE (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x110)
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#define IMXRT_AON_EDGELOCK_HALT_ST (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x114)
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#define IMXRT_AON_ECC_MEM_INIT (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x120)
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#define IMXRT_AON_IOMUXC_DOMAIN_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x148)
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#define IMXRT_AON_IOMUXC_AON_DOMAIN_CFG (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x14c)
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#define IMXRT_AON_NMI_CTRL (IMXRT_BLK_CTRL_S_AONMIX_BASE + 0x154)
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/* M33_CFG bit fields */
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#define AON_M33_CFG_LOCK_NSVTOR (1u << 0)
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#define AON_M33_CFG_LOCK_SVTOR (1u << 1)
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#define AON_M33_CFG_TCM_SIZE_SHIFT (3)
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#define AON_M33_CFG_TCM_SIZE_MASK (0x3u << AON_M33_CFG_TCM_SIZE_SHIFT)
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/* M7_CFG bit fields */
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#define AON_M7_CFG_TCM_SIZE_SHIFT (0)
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#define AON_M7_CFG_TCM_SIZE_MASK (0x7u)
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#define AON_M7_CFG_WAIT (1u << 4)
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#define AON_M7_CFG_CORECLK_FORCE_ON (1u << 5)
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#define AON_M7_CFG_HCLK_FORCE_ON (1u << 6)
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#define AON_M7_CFG_INITVTOR_SHIFT (7)
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#define AON_M7_CFG_INITVTOR_MASK (0x01ffffffu << AON_M7_CFG_INITVTOR_SHIFT)
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#define AON_M7_CFG_INITVTOR(x) (((x) << AON_M7_CFG_INITVTOR_SHIFT) & \
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AON_M7_CFG_INITVTOR_MASK)
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/* NMI_CTRL bit fields */
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#define AON_NMI_CTRL_M7_NMI_MASK (1u << 0)
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#define AON_NMI_CTRL_M33_NMI_MASK (1u << 1)
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/* SRC general registers (IMXRT1180RM Ch. 27) *******************************/
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#define IMXRT_SRC_AUTHEN_CTRL (IMXRT_SRC_BASE + 0x004)
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#define IMXRT_SRC_SCR (IMXRT_SRC_BASE + 0x010) /* Control */
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#define IMXRT_SRC_SRTMR (IMXRT_SRC_BASE + 0x014) /* Reset Trigger */
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#define IMXRT_SRC_SRMASK (IMXRT_SRC_BASE + 0x018) /* Reset Mask */
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#define IMXRT_SRC_SBMR1 (IMXRT_SRC_BASE + 0x040) /* Boot Mode 1 */
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#define IMXRT_SRC_SBMR2 (IMXRT_SRC_BASE + 0x044) /* Boot Mode 2 */
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#define IMXRT_SRC_SRSR_BBSM (IMXRT_SRC_BASE + 0x04c)
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#define IMXRT_SRC_SRSR (IMXRT_SRC_BASE + 0x050) /* Reset Status */
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/* SRC.SCR bit fields */
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#define SRC_SCR_BT_RELEASE_M7 (1u << 0) /* Release M7 from boot hold */
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/* SRC MIX_SLICE registers (IMXRT1180RM Ch. 27, per power domain slice).
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* Bases for each slice (AON/WAKEUP/MEGA/NETC/CM33/CM7 platforms) are in
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* hardware/rt118x/imxrt118x_memorymap.h.
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*/
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#define IMXRT_SRC_SLICE_AUTHEN_CTRL(base) ((base) + 0x004)
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#define IMXRT_SRC_SLICE_SW_CTRL(base) ((base) + 0x010)
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#define IMXRT_SRC_SLICE_FUNC_STAT(base) ((base) + 0x014)
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#define IMXRT_SRC_SLICE_UPI_STAT_0(base) ((base) + 0x020)
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#define IMXRT_SRC_SLICE_UPI_STAT_1(base) ((base) + 0x024)
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#define IMXRT_SRC_SLICE_LPM_SETTING_0(base) ((base) + 0x030)
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#define IMXRT_SRC_SLICE_LPM_SETTING_1(base) ((base) + 0x034)
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#define IMXRT_SRC_SLICE_LPM_SETTING_2(base) ((base) + 0x038)
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#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_CTRL(base) ((base) + 0x040)
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#define IMXRT_SRC_SLICE_EDGELOCK_HDSK_STAT(base) ((base) + 0x044)
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#define IMXRT_SRC_SLICE_PSW_CTRL(base) ((base) + 0x05c)
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#define IMXRT_SRC_SLICE_PSW_STAT(base) ((base) + 0x060)
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#define IMXRT_SRC_SLICE_MLPL_CFG(base) ((base) + 0x084)
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#define IMXRT_SRC_SLICE_MLPL_STAT(base) ((base) + 0x088)
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/* SLICE_SW_CTRL bit fields */
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#define SRC_SLICE_SW_CTRL_PSW_OFF_SOFT (1u << 0) /* 1 = software power off */
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#define SRC_SLICE_SW_CTRL_RST_CTRL_SOFT (1u << 2) /* 1 = software reset assert */
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#define SRC_SLICE_SW_CTRL_ISO_ON_SOFT (1u << 4) /* 1 = software isolation on */
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#define SRC_SLICE_SW_CTRL_EDGELOCK_HDSK_SOFT (1u << 6) /* Edgelock handshake */
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#define SRC_SLICE_SW_CTRL_PDN_SOFT (1u << 31) /* 1 = SW power-down sequence */
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/* FUNC_STAT bit fields (all read-only) */
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#define SRC_SLICE_FUNC_STAT_PSW_STAT (1u << 0) /* 0 = power on, 1 = power off */
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#define SRC_SLICE_FUNC_STAT_RST_STAT (1u << 2) /* 0 = reset held, 1 = released */
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#define SRC_SLICE_FUNC_STAT_ISO_STAT (1u << 4) /* 0 = isolation off */
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#define SRC_SLICE_FUNC_STAT_EDGELOCK_HDSK (1u << 6) /* Edgelock handshake done */
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#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_RT118X_IMXRT118X_BLKCTRL_H */
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