lm3s6965-ek:qemu-flat used 261952 of its 262144 bytes of flash, so
almost any growth of common code made its build fail with "region
`flash' overflowed".
Disable the wget example and the web client library it needs (which
also removes the NSH wget command). This frees 5180 bytes. The
configuration keeps its other network tools (ping, DHCP, DNS, NTP,
telnetd, tftp, netcat), and wget is still built by 10 other
configurations.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
nucleo-g431rb:cansock and b-g431b-esc1:cansock fill their 128 KB of
flash to the last few hundred bytes, and the capability checks overflow
them.
Signed-off-by: Royyan Zahir <royzah@gmail.com>
Use init_main as the init entry point and enable SYSTEM_NXINIT with the
/etc ROMFS, so nxinit starts nsh as the console service.
Assisted-by: OpenCode:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
This commit adds board support for connecting an external Winbond W25
SPI NOR flash memory via SPI1 on the Nucleo-L432KC:
- Define W25_SPI1_CS on PA11.
- Configure SPI1 chip select and presence detection in stm32_spi.c.
- Add stm32_w25initialize() to initialize SPI1, bind the W25 driver,
and register /dev/mtd0, /dev/mtdblock0 (FTL), and optionally /dev/smart0.
- Call stm32_w25initialize() during bringup when CONFIG_MTD_W25 is enabled.
Assisted-by: gemini-3.8-flash
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
The I- and D-Caches were disabled, so all code ran from flash through
the prefetch buffer and all data accesses went to SRAM. Enable both
caches in nsh and netnsh, and link the data memory in KSEG0 instead of
KSEG1 so that it goes through the D-Cache (KSEG0 is uncached when the
caches are disabled). CONFIG_BOARD_LOOPSPERMSEC is recalibrated with
calib_udelay for the cached configuration.
CoreMark (XC32 v6.00, -O2) goes from 82.5 to 544.6 iterations/s. The
average ping round trip time drops from 0.74 to 0.56 ms for 64-byte
packets and from 1.92 to 0.93 ms for 1400-byte packets.
Tested on the EV49N51A with XC32: 5000 pings of 1472 bytes at 2 ms
intervals with payload checking, ifdown/ifup cycles, telnet sessions
and CoreMark. With Pinguino GCC: 2000 pings of 1472 bytes and 1000
small pings at 3 ms intervals.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Add CONFIG_EV49N51A_PHY_INTERRUPT, which provides arch_phy_irq() with
the LAN8720A nINT output on RK6 as a falling-edge change notification
interrupt. nINT reaches RK6 only through R309, which is not fitted on
the EV49N51A, so the option defaults to off.
With CONFIG_NETINIT_MONITOR the interface now goes down when the cable
is removed and comes back up when it is reconnected.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
- Reset the LAN8720A PHY (nRST on RA14) at boot, after the RMII
reference clock is running.
- Define BOARD_EMAC_MIIM_DIV for a 2.5 MHz MDC.
- Add the netnsh configuration: Ethernet, IPv4, TCP, UDP, ICMP, ping and
telnetd, with the default static address of the network initialization
and a locally administered MAC address (PIC32MZ-W1 has no factory MAC
address).
- Document the Ethernet interface, the RMII reference clock options and
the netnsh configuration.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
raspberrypi-pico-2:pm and pimoroni-pico-2-plus:pm enable the PM
standby and dormant states with the greedy governor, suspend to RAM
with the BOARDIOC_RP23XX_SUSPEND boardctl() command, and the RTC alarm.
The console receive pin (GPIO 1) wakes the chip, and the dormant state
is refused for 30 s after boot so that a debugger can attach. The Pico
Plus 2 configuration also adds its PSRAM to the heap.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
P1.0 powers the switched core off and keeps the XIP cache and SRAM.
Every peripheral loses its registers, so the chip comes back through
the bootrom and the ordinary boot, not from the WFI. The idle governor
never selects it: an application asks for it with the new
BOARDIOC_RP23XX_SUSPEND boardctl() command (arch/chip/pm.h, handled by
the common rp23xx board_ioctl()).
rp23xx_pm_suspend():
- saves the NVIC, writes a marker to POWMAN SCRATCH0, and arms the
wake: the RP23XX_PM_WAKEUP_GPIO pin in a POWMAN power-up detector,
and the always-on timer alarm for a timed wake. An armed RTC alarm
that comes first powers the chip up itself, so an application can
set the wake with RTC_SET_ALARM. Otherwise the RTC alarm is saved
with the new rp23xx_rtc_savealarm() and given back after the wake
with rp23xx_rtc_restorealarm().
- cleans the XIP cache, with the RP2350-E11 workaround, because the
resume discards it and PSRAM can hold task stacks.
- requests P1.0 and waits in WFI.
On the next boot, __start asks rp23xx_pm_resume_pending() (the marker
and CHIP_RESET.HAD_SWCORE_PD) before .bss and .data are touched. For a
resume it moves to its own stack, because the idle thread still runs on
the idle stack, sets up the hardware with the cold boot code (now
rp23xx_hwinit()), and longjmps back to the suspended thread. The UARTs
are set up from the driver state in RAM, the PSRAM format is applied
again without detection (the part is still in quad mode), the dormant-
wake GPIOs are armed again (the IO bank lost them, and the next dormant
period could then never end), and the time of day is taken from the
always-on timer.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Map the NuttX PM states onto the RP2350 low-power modes:
- PM_STANDBY is the RP2350 SLEEP state: a WFI with the clocks of the
blocks that have no driver in the configuration gated (SLEEP_EN0/1).
- PM_SLEEP is the DORMANT state: clk_sys moves to the crystal
oscillator, the PLLs and then the oscillator stop, and the clock tree
is restored after the wake, as pico-extras does. Only the GPIO
dormant-wake detector can wake the chip, so PM_SLEEP gives the
standby state when no wake GPIO is configured. The wake GPIO also
raises a one-shot interrupt, so that the core leaves its WFI and
restores the PLLs at once. The time of day is taken back from the
always-on timer after the wake.
The dormant state stops the UARTs. A PM_STANDBY wakelock
(pm_staytimeout()) is held for RP23XX_PM_WAKE_HOLD_MS after a dormant
wake and after each character a UART receives. The serial driver
refuses PM_SLEEP in its prepare callback while a UART transmits. A
dormant chip does not answer SWD, so the pm configurations use
PM_GOVERNOR_EXPLICIT_RELAX to stay out of it for a time after boot.
With RP23XX_PM_QUIESCE_PADS, arm_pminitialize() also isolates the
unused pads and holds the blocks with no driver in reset. A floating
bank 0 input settles near 2.2V (erratum RP2350-E9) and its input
buffer then draws a static current in every state.
Also select ARCH_HAVE_PM, and fix the LED PM callbacks of three boards,
which used BOARD_LED where the boards define BOARD_LED1. They did not
build with CONFIG_PM.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Add the blank line after the declarations in up_putc() and in
rp23xx_led_pminitialize() of three boards. Whitespace only.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Add uSD card driver configuration for 4-bit, HS mode 50MHz
- Add root clock configuration for the uSDHC
- Add pin muxing for the uSD card
- Add fat_dma_alloc and fat_dma_free functions
- Initialize the usdhc driver in board's init
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Use init_main as the init entry point and enable SYSTEM_NXINIT with the
/etc ROMFS, so nxinit starts nsh as the console service.
Assisted-by: OpenCode:claude-sonnet-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add etc/init.d/init.rc and build it into the /etc ROMFS for Make and
CMake. The kernel-build romfs image uses the same ROM disk minor, so
skip it with CONFIG_ETC_ROMFS and register it only with BUILD_KERNEL.
Assisted-by: OpenCode:claude-sonnet-5 Kiro:claude-opus-5
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Add the Microchip EV49N51A Ethernet to Wi-Fi Bridge board, built around
the WFI32E01PE module (PIC32MZ-W1) with a LAN8720A Ethernet PHY.
The nsh configuration runs SYSCLK at 200 MHz with the console on UART1
(dedicated pins RA8/RA9, header J203, 115200 8N1) and drives the red and
green user LEDs on RK1/RK3. It selects PGC2/PGD2 as the debug channel.
The SST26VF032B serial flash on SPI1 (dedicated pins, CS on RA1) is
exported as /dev/mtdblock0. Its SPI frequency is set to 20 MHz: the SST26
driver's 64 MHz default is above PBCLK3/2 (25 MHz), which pic32mz_spi.c
does not handle.
mips-debug.ld is used with every toolchain. It has no OUTPUT_FORMAT,
because XC32 and Pinguino name their little-endian ELF targets
differently; the board passes -EL to the linker instead. With XC32 the
board builds with -mno-dsp -mno-dspr2: NuttX does not enable or save the
DSP ASE state.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
board_spisd_initialize() logged "ERROR: Failed to mount the SDCARD" at
every boot when the mount failed. The two usual causes are no card in
the slot and a card with no filesystem. Neither is an error: the block
device is registered, and the card can be formatted with mkfatfs and
mounted later.
Log -EINVAL and -ENODEV from nx_mount() with finfo(). Other errors
are still logged with ferr(), as the rest of the file does.
Also include errno.h, which the file used without including it.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Expose the RTL8730E I2C controllers through the shared Ameba I2C driver
(arch/arm/src/common/ameba/ameba_i2c.c) by adding the chip-specific
glue, build wiring and a board bus table. The change is gated by
CONFIG_AMEBA_I2C (default disabled).
Chip glue (ameba_i2c_chip.h) supplies the three controller register
bases, the APB function/clock masks -- amebasmart encodes these in
bit 25/26/27 with the group selector bit30=0, unlike the (bit30 |
bit10/11) layout of the KM4-based parts -- and the pad-mux code.
amebasmart has a single generic PINMUX_FUNCTION_I2C shared by every I2C
pad instead of per-signal SCL/SDA crossbar codes, and its
I2C_InitTypeDef omits the DMA request-level fields, so
AMEBA_I2C_HAS_DMA_FIELDS stays undefined. The whole I2C fwlib lives in
ram_common/ameba_i2c.c rather than lib_rom.a, so it is compiled into
libameba_fwlib.a when I2C is enabled.
The shared driver gains an optional per-controller IP-clock hook,
AMEBA_I2C_IPCLK_FN(bus). amebasmart needs it because its
I2C_StructInit() fills in a 10 MHz placeholder rather than the real
reference clock (the other Ameba parts fill in a correct XTAL_ClkGet()
/ PLL_GetHBUSClk() / HPERI_ClkGet()), which makes I2C_SetSpeed()
miscompute the SCL counts. The hook resolves the rate at run time: the
two HS controllers sit on HS_AHB, i.e. NP_PLL divided by
REG_LSYS_CKD_GRP0.CKD_HBUS, so it is a PLL/board setting and not a
constant -- an EVB measured CKD_HBUS=8 (div9, 88.9 MHz) while the SDK's
own I2CCLK_TABLE claims a flat 100 MHz and the register reset value
would imply 80 MHz. The LP-domain I2C0 keeps its fixed 20 MHz. Chips
that leave the macro undefined use the fwlib default and are
unaffected; regression-tested on pke8721daf:i2c.
All three controllers are registered: /dev/i2c0 on PA9/PA10, /dev/i2c1
on PA3/PA4 and /dev/i2c2 on PB10/PB11. Pad choice is constrained on
this chip -- a pad reaches exactly one controller (SDA fixed per
controller, SCL the next pad up), and the pads inside the analogue
audio ranges (PA20-PA29, PA30-PB2, PB3-PB6) are driven by the codec and
leave the bus stuck idle. Both rules are noted in the table's
comment.
Also add a weak DiagVprintf stub: the I2C fwlib logs through RTK_LOGx()
-> rtk_log_write(), and unlike DiagPrintf that symbol is not in the AP
ROM symbol table. It is weak so the strong definition in
rtl8730e_wifi_stubs.c still wins when WiFi is enabled; both route to
vprintf.
Hardware-verified on an RTL8730E EVB against a second board running an
I2C slave: register read, write, write/read round-trip, multi-byte dump
and a full address scan, on all three buses at 100 kHz.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Documentation/os/binfmt/fdpic.rst covers what an FDPIC module is and what
it adds over the position independent ELF support already in the tree, how
the loader places one, where shared libraries come from and how they are
found, which entry points resolve a function descriptor and the rules for
adding another, and how to build a module and a library. A comparison
table places it against NXFLAT and PIC ELF, and the reference section
records the object layout and the relocations.
pimoroni-pico-2-plus:xipfs-fdpic is the configuration the series was tested
on: xipfs on the board's QSPI flash, the ELF loader with CONFIG_FDPIC, and
apps/examples/fdpicxip with apps/testing/fs/xipfs.
CONFIG_DEFAULT_TASK_STACKSIZE is 4096 there rather than the rp23xx default
of 2048. Both sides of the loader need it: a module that calls into the
firmware's printf family overflows 2048, and with no MPU that is a lockup
rather than a diagnostic. CONFIG_ELF_STACKSIZE follows it, and
apps/testing/fs/xipfs sizes its own task from it.
CONFIG_HAVE_CXXINITIALIZE is set because crt0 runs the constructors of a
module only with it, and the xipfs suite checks that they ran.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
The linker scripts of the board name the bounds of .init_array the way the
Pico SDK does, __init_array_start and __init_array_end, and do not
define _sinit and _einit. lib_cxx_initialize() walks _sinit to _einit,
so a configuration with CONFIG_HAVE_CXXINITIALIZE does not link:
"undefined reference to `_sinit'".
Define _sinit and _einit at the same places in the three scripts.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Change the imxrt1180-evk M7 NSH configuration to use the SoC memories
more efficiently:
- Place .data, .bss, idle stack and primary heap into DTCM
- Allocate available OCRAM as a secondary heap
- Add a separate .dmamemory section in OCRAM for USB device DMA
allocations
- Place .ramfunc into ITCM, together with hand-picked "hot" functions.
The section is copied to ITCM at boot by the ramfunc copy.
The eDMA accesses DTCM through the SoC's dedicated bus window.
This configuration acts as an example of performance optimization for
imxrt1180 based boards.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add support for Cortex-M33 code to initialize the M7 TCM memories before
releasing it to run. The TCM has ECC, which needs to be initialized before
the memory is usable for M7.
Specifically, the TCM needs to be initialized sequentially in 64-bit writes.
Use eDMA4 for this; this is the same mechanism which the NXP MCUXpresso SDK
code does.
Split imxrt118x_release_cm7() into imxrt118x_prepare_cm7() and
imxrt118x_start_cm7(). The TCM ECC initialization is done in
imxrt118x_prepare_cm7(), after the M7 has been released from reset and
before the M7 is started. Also reset M7_CFG[TCM_SIZE] to the default
256 KiB ITCM / 256 KiB DTCM layout.
Co-Authored-By: Jukka Laitinen <jukka.laitinen@tii.ae>
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The always-on timer has an alarm comparator, but the RTC driver did not
use it: rp23xx_rtc.c implemented only up_rtc_initialize(),
up_rtc_time() and up_rtc_settime().
Add the alarm and an RTC lower half for /dev/rtc0:
- rp23xx_rtc_setalarm(), rp23xx_rtc_cancelalarm() and
rp23xx_rtc_rdalarm() on the ALARM_TIME registers and the POWMAN
timer interrupt.
- An RTC lower half with rdtime, settime, setalarm, setrelative,
cancelalarm and rdalarm, registered by the common board bringup.
The comparator asserts while the time is past the alarm time, not on
a transition. So the interrupt handler disables the alarm before it
does anything else; clearing only the status makes the interrupt
repeat. The arming sequence is the one of
powman_timer_enable_alarm_at_ms() in the Pico SDK.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Indent the flash MTD block as nxstyle wants. Whitespace only; git diff
-w is empty.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
The board set LDELFFLAGS to "-r -e main" after it included Toolchain.defs.
This replaced the flags that Toolchain.defs sets for a loadable module.
With CONFIG_FDPIC, a module then links as a relocatable object and not as
an FDPIC shared object. A module that names a library does not link at
all: "attempted static link of dynamic object".
9ed93c6b1e moved these flags into Toolchain.defs for all boards, and
dae3b8e551 removed the same lines from mps3-an547. Remove them here
too.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
The OTP, read-only (UID, flash size, package) and high-cycle data (EDATA)
flash areas only accept 16/32-bit accesses and return a bus error
otherwise (RM0481 Table 77). The manual requires the MPU to disable local
cacheability for them (RM0481 7.3.2); with the ICACHE enabled and no such
region, reading them raises a precise bus error.
Until now this was worked around piecemeal: the driver disabled the
ICACHE around stm32_get_uniqueid() and the OTP and EDATA word reads, and
nucleo-h563zi mapped the 4 KB OTP/RO area non-cacheable in its board
code. Other reads, for example stm32_otp_read() or an application
reading the OTP on another board, still raised a precise bus error when
the ICACHE was enabled.
Map 0x08fff000-0x09017fff, which covers the three contiguous areas, as
Normal non-cacheable and execute-never with a single MPU region before
the ICACHE is enabled. STM32_ICACHE now selects ARM_MPU so that
stm32_mpuinitialize() has reset and enabled the MPU by then.
Remove the nucleo-h563zi OTP region in the same commit: the Armv8-M MPU
faults on an address that matches more than one region, so keeping both
would make OTP and UID reads fault on that board.
Assisted-by: Claude:claude-sonnet-5-5
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Ricardo Maurizio Paul <ricardopaul@geotab.com>
board.h gains GPIO_SCI0_RX/TX (P610/P609, SCI0 pin group 3), needed to
exercise CONFIG_RA_SCI0_UART on this board at all -- previously only
SCI9's console pins existed.
The new serial-test defconfig builds on nsh with SCI0 enabled as
/dev/ttyS1 with its FIFO (CONFIG_RA_SCI0_FIFO, measured on hardware as
the best overrun-resistant setting: TTRG=15, RXTRG=0), 1024-byte RX/TX
ring buffers (up from the 256-byte default, to better absorb bursts
during testing), CONFIG_SERIAL_TERMIOS + apps/system/stty (to change
its baud rate live), and apps/examples/serialblaster + serialrx
pointed at it, for exercising the SCI_B driver's FIFO/overrun-recovery
paths independently of the SCI9 console.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: leocafonso <leocafonso@gmail.com>
Add stm32h7s8-dk board support for nsh running out of internal flash,
including LEDs and user button.
Signed-off-by: Peter Barada <peter.barada@gmail.com>
Select the cache line size from either ARMV7M_DCACHE_LINESIZE or
ARMV8M_DCACHE_LINESIZE, so the driver can also be used with D-cache
enabled on the i.MX RT1180 Cortex-M33.
Also fix the imxrt1180-evk USB DMA allocator alignment. Pad the header
to the 32-byte DMA alignment, so that the buffer remains aligned.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Register GPT0 (32-bit) as /dev/timer0 and GPT9 (16-bit) as /dev/timer1
during bring-up.
Register the Arduino Uno shield header's D2-D5 as inputs and D6-D13 as
outputs through the generic GPIO expander driver, as /dev/gpio0-3 and
/dev/gpio4-11.
Add the ek-ra8m1:timer-gpio configuration (nsh plus both GPT channels,
the GPIO support above, and apps/examples/gpio and
apps/examples/timer_gpio), used to validate the GPT timer driver on
hardware with an oscilloscope.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: leocafonso <leocafonso@gmail.com>
There were some bits erroneously copied from imx9. For IMXRT1180, the
GPIO_AD* and GPIO_AON* pads should have SRE, DSE, PUE, PUS and ODE bits
on SW_PAD_CTL_PAD register.
The GPIO_EMC_*, GPIO_SD_*, GPIO_B1_* and GPIO_B2_* have a bit different fields,
PDRV, PULL and ODE.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The PMS grants and refuses physical addresses, so it never sees an access
that no MMU entry translates. The cache answered such an access with zeros
and raised nothing, and the task carried on with a value it never should
have had.
Enable EXTMEM_MMU_ENTRY_FAULT and route the Cache Invalid Access interrupt
to the handler that already serves the PMS monitors. An unprivileged task
that makes the access is terminated with SIGSEGV; a privileged one still
panics. The latch is level triggered, so it is cleared with the others.
Read the cause before the clear, so the log tells the two apart: a PMS
violation is a refused translation, an MMU entry fault is an access that was
never translated.
Give the kernel_oct configuration the addresses that examples/sandbox needs
to name its targets.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
When an unprivileged task takes a fault the system cannot recover from, it
now gets a fatal SIGSEGV and only that task ends. A fault in privileged code
still panics.
What decides it is the interrupted context, not the cause: the saved PS says
whether the fault was taken in User Mode. A list of causes would leave every
cause off the list as a way for a user task to stop the machine, and there
are many -- a divide by zero, a privileged instruction, a load/store error,
and an illegal instruction, which is how a refused fetch from kernel text
arrives on this chip (TRM v1.8 p.699: a denied external-memory access is
answered with 0xdeadbeaf instead of trapping). PS.UM is clear in a kernel
thread, in a system call made on the user's behalf and in an interrupt
handler, so those still panic. If the recoverable-fault dispatcher is
enabled it still gets first refusal on causes 28, 29 and 20, the only ones
re-executing can help.
esp32s3_userfault_abort() records the exception frame as the task's context,
dispatches SIGSEGV, and returns the redirected frame, so the vector's RFE
resumes the task in the signal trampoline, whose default action exits it.
CONFIG_ESP32S3_USERFAULT_ABORT enables it, default y wherever there is an
unprivileged world, and selects SIG_DEFAULT and SIG_SIGKILL_ACTION.
Verified on an ESP32-S3 DevKitC with a WROOM-2 module,
esp32s3-devkit:kernel_oct: a user task that writes through NULL, reads a wild
address, divides by zero, calls into a buffer of garbage or branches into
kernel text is terminated on its own, while an unrelated task keeps running.
Stack overflow is not contained. On the windowed ABI it faults inside the
window overflow handler and arrives as a double exception with PS.UM already
clear; guard pages are the answer, and separate work.
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Separate the world split from the protected user image, give WORLD1 its own
vector table and its own PMS permissions -- including the PSRAM -- clean up
the user cache-MMU windows, and stop keeping the page pool mapped.
Folds in:
xtensa/esp32s3: separate the world split from the protected user image
xtensa/esp32s3: give the unprivileged world its own vector table
xtensa/esp32s3: give the unprivileged world its permissions
xtensa/esp32s3: clean up the user cache-MMU windows
xtensa/esp32s3: stop keeping the page pool mapped
xtensa/esp32s3: give the PSRAM its own PMS permissions
Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Implement the same initial clock configuration as what imxrt1176 has. Make an own table
for PLL and root clock configurations for m33 and m7 targets. For the PLLs the code still
only supports configuring the ARM_PLL.
The difference to imxrt1176 is, that instead of just boolean .enable field, this table
uses an .action field with 3 states: CONFIGURE, DISABLE and IGNORE. The reason is,
that some root clocks can't be just forcefully stopped, but need a root-clock-specific
sequence. This is solved by just leaving these clocks marked as IGNORE, so they retain
their current state.
Specifically, disabling the SEMC and NETC roots by M33 will prevent the M7 from booting.
Also FLEXSPI shouldn't be touched, if the code is being executed from there.
Also add a function for enabling 24 MHz oscillator clock, and an extendable function to
enable the clock sources based on the clock configuration table.
Assisted-by: Claude Code
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add board support for the EK-RA8M1 evaluation kit with nsh and
nsh-leds configurations, linker script, LED support and bring-up.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Signed-off-by: leocafonso <leocafonso@gmail.com>
