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arch/arm/imxrt: Make performance optimized memory configuration for M7 NSH
Change the imxrt1180-evk M7 NSH configuration to use the SoC memories more efficiently: - Place .data, .bss, idle stack and primary heap into DTCM - Allocate available OCRAM as a secondary heap - Add a separate .dmamemory section in OCRAM for USB device DMA allocations - Place .ramfunc into ITCM, together with hand-picked "hot" functions. The section is copied to ITCM at boot by the ramfunc copy. The eDMA accesses DTCM through the SoC's dedicated bus window. This configuration acts as an example of performance optimization for imxrt1180 based boards. Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This commit is contained in:
Jukka Laitinen
Xiang Xiao
parent
23ae7e4073
commit
9cf38e7fbe
4 changed files with 65 additions and 22 deletions
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@ -204,7 +204,19 @@ extern const uint32_t _ram_size[]; /* See linker script */
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* already been assigned as the primary RAM.
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*/
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#if defined(CONFIG_IMXRT_OCRAM_HEAP) && !defined(IMXRT_OCRAM_ASSIGNED)
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#if defined(CONFIG_IMXRT_TCM_PRIMARY) && \
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defined(CONFIG_IMXRT_OCRAM_HEAP)
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/* With TCM as primary RAM, the linker defines the usable OCRAM range so
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* that board-reserved and DMA-only storage is excluded.
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*/
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extern const uint8_t _socramheap[];
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extern const uint8_t _eocramheap[];
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# define REGION1_RAM_START ((uintptr_t)_socramheap)
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# define REGION1_RAM_SIZE ((uintptr_t)_eocramheap - \
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(uintptr_t)_socramheap)
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# define IMXRT_OCRAM_ASSIGNED 1
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#elif defined(CONFIG_IMXRT_OCRAM_HEAP) && !defined(IMXRT_OCRAM_ASSIGNED)
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# define REGION1_RAM_START IMXRT_OCRAM_START
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# define REGION1_RAM_SIZE IMXRT_OCRAM_SIZE
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# define IMXRT_OCRAM_ASSIGNED 1
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@ -135,7 +135,7 @@ static inline void imxrt_tcmenable(void)
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UP_MB();
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#ifdef CONFIG_ARMV7M_ITCM
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#if defined(CONFIG_ARMV7M_ITCM) && !defined(CONFIG_ARCH_FAMILY_IMXRT118x)
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/* Copy TCM code from flash to ITCM */
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#warning Missing logic
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@ -212,7 +212,7 @@ void __start(void)
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}
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/* Copy any necessary code sections from FLASH to RAM. The correct
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* destination in OCRAM is given by _sramfuncs and _eramfuncs. The
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* destination in RAM is given by _sramfuncs and _eramfuncs. The
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* temporary location is in flash after the data initialization code
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* at _framfuncs. This should be done before imxrt_clockconfig() is
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* called (in case it has some dependency on initialized C variables).
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@ -41,10 +41,13 @@ CONFIG_EXAMPLES_BUTTONS_NAMES=y
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CONFIG_EXAMPLES_BUTTONS_QTD=1
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CONFIG_FS_NAMED_SEMAPHORES=y
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CONFIG_FS_PROCFS=y
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CONFIG_GRAN=y
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CONFIG_IDLETHREAD_STACKSIZE=4096
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CONFIG_IMXRT_EDMA=y
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CONFIG_IMXRT_GPIO_IRQ=y
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CONFIG_IMXRT_LPUART1=y
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CONFIG_IMXRT_OCRAM_HEAP=y
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CONFIG_IMXRT_TCM_PRIMARY=y
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CONFIG_IMXRT_USBDEV=y
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INIT_STACKSIZE=8192
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@ -57,14 +60,15 @@ CONFIG_LINE_MAX=64
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CONFIG_LPUART1_RXDMA=y
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CONFIG_LPUART1_SERIAL_CONSOLE=y
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CONFIG_LPUART1_TXDMA=y
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CONFIG_MM_REGIONS=2
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_READLINE=y
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CONFIG_PTHREAD_MUTEX_TYPES=y
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CONFIG_PTHREAD_STACK_DEFAULT=8192
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CONFIG_RAM_SIZE=491520
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CONFIG_RAM_START=0x20484000
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CONFIG_RAM_SIZE=262144
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CONFIG_RAM_START=0x20000000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_BACKTRACE=y
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@ -83,4 +87,5 @@ CONFIG_TLS_NCLEANUP=4
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CONFIG_TLS_NELEM=4
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CONFIG_USBDEV=y
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CONFIG_USBDEV_DMA=y
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CONFIG_USBDEV_DMAMEMORY=y
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CONFIG_USBDEV_DUALSPEED=y
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@ -30,18 +30,17 @@
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* 0x2800_0000 .. 0x2807_FFFF M33 image (512 KB reserved)
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* 0x2808_0000 .. 0x287F_FFFF M7 image (this script, 7.5 MB window)
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*
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* NuttX's stack, .data, .ramfunc and .bss live in OCRAM1, which the M33
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* grants the M7 R/W/X through TRDC2 MRC_W3 before releasing it. DTCM and
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* ITCM are declared above but are not used by any section; they are
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* tightly-coupled to the M7 core and have no TRDC in the access path, so
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* they remain available for opt-in placement.
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* NuttX's .data, .bss, idle stack and primary heap live in DTCM. OCRAM1,
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* which the M33 grants the M7 R/W/X through TRDC2 MRC_W3 before releasing
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* it, holds USB DMA storage and the secondary heap. ITCM holds the
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* .ramfunc section, including selected hot code.
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*/
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MEMORY
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{
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flash (rx) : ORIGIN = 0x28080000, LENGTH = 4M /* Cortex-M7 XIP window (after the 512K M33/bl reserve) */
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ocram (rwx) : ORIGIN = 0x20484000, LENGTH = 480K /* OCRAM1 minus ROM patch (0x20480000..0x20483fff) and M33 reserve (0x204fc000..0x204fffff) */
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dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* M7 DTCM (opt-in) */
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dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 256K /* M7 DTCM primary RAM */
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 256K /* M7 ITCM (opt-in) */
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}
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@ -51,10 +50,34 @@ ENTRY(_stext)
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SECTIONS
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{
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.text : ALIGN(4)
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.vectors :
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{
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_stext = ABSOLUTE(.);
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*(.vectors)
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KEEP(*(.vectors))
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} > flash
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.ramfunc :
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{
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. = ALIGN(8);
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_sramfuncs = ABSOLUTE(.);
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FILL(0xff)
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. = 0x40;
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*(.text.exception_common)
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*(.text.arm_doirq)
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*(.text.arm_ack_irq)
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*(.text.irq_dispatch)
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*(.text.imxrt_gpio_interrupt)
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*(.text.memcpy)
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*(.text.memset)
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*(.ramfunc .ramfunc.*)
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. = ALIGN(8);
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_eramfuncs = ABSOLUTE(.);
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} > itcm AT > flash
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_framfuncs = LOADADDR(.ramfunc);
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.text : ALIGN(4)
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{
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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@ -111,16 +134,19 @@ SECTIONS
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > ocram AT > flash
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} > dtcm AT > flash
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.ramfunc ALIGN(4):
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.dmamemory (NOLOAD) :
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{
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_sramfuncs = ABSOLUTE(.);
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*(.ramfunc .ramfunc.*)
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_eramfuncs = ABSOLUTE(.);
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} > ocram AT > flash
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. = ALIGN(2048);
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_sdmamemory = ABSOLUTE(.);
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*(.dmamemory .dmamemory.*)
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. = ALIGN(32);
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_edmamemory = ABSOLUTE(.);
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} > ocram
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_framfuncs = LOADADDR(.ramfunc);
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_socramheap = ALIGN(8);
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_eocramheap = ORIGIN(ocram) + LENGTH(ocram);
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.bss :
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{
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@ -130,7 +156,7 @@ SECTIONS
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*(COMMON)
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. = ALIGN(8);
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_ebss = ABSOLUTE(.);
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} > ocram
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} > dtcm
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/* Stabs debugging sections. */
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@ -149,5 +175,5 @@ SECTIONS
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_boot_loadaddr = ORIGIN(flash);
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_boot_size = LENGTH(flash);
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_ram_size = LENGTH(ocram);
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_ram_size = LENGTH(dtcm);
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}
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