Aksal/nuttx
3
1
Fork 1
mirror of https://github.com/apache/nuttx.git synced 2026-10-10 07:40:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

boards/mips/pic32mz: add Microchip EV49N51A board.

Browse source 
Add the Microchip EV49N51A Ethernet to Wi-Fi Bridge board, built around
the WFI32E01PE module (PIC32MZ-W1) with a LAN8720A Ethernet PHY.

The nsh configuration runs SYSCLK at 200 MHz with the console on UART1
(dedicated pins RA8/RA9, header J203, 115200 8N1) and drives the red and
green user LEDs on RK1/RK3.  It selects PGC2/PGD2 as the debug channel.
The SST26VF032B serial flash on SPI1 (dedicated pins, CS on RA1) is
exported as /dev/mtdblock0.  Its SPI frequency is set to 20 MHz: the SST26
driver's 64 MHz default is above PBCLK3/2 (25 MHz), which pic32mz_spi.c
does not handle.

mips-debug.ld is used with every toolchain.  It has no OUTPUT_FORMAT,
because XC32 and Pinguino name their little-endian ELF targets
differently; the board passes -EL to the linker instead.  With XC32 the
board builds with -mno-dsp -mno-dspr2: NuttX does not enable or save the
DSP ASE state.

Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
This commit is contained in:
Daniel P. Carvalho 2026-10-03 13:44:56 -03:00 • committed by Alan C. Assis
parent 2fde85162c
commit 2ef6153047
15 changed files with 1422 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

BIN
Documentation/platforms/mips/pic32mz/boards/ev49n51a/ev49n51a.jpg Normal file
View file

Binary file not shown.
Side by side

After

Width:  |  Height:  |  Size: 44 KiB

283
Documentation/platforms/mips/pic32mz/boards/ev49n51a/index.rst Normal file
View file

@ -0,0 +1,283 @@
================================================
Microchip EV49N51A (Ethernet to Wi-Fi Bridge)
================================================
.. tags:: arch:mips, chip:pic32mz, vendor:microchip
.. figure:: ev49n51a.jpg
:figwidth: 40%
:align: center
:alt: The Microchip EV49N51A Ethernet to Wi-Fi Bridge board
The Microchip EV49N51A Ethernet to Wi-Fi Bridge board
This page documents the NuttX port to the Microchip EV49N51A, the
"Ethernet to Wi-Fi Bridge" reference design built around the WFI32E01PE
Wi-Fi module. The module contains a PIC32MZ1025W104132 (PIC32MZ-W1
family) microcontroller.
Features
========
* WFI32E01PE module (PCB antenna) with a PIC32MZ1025W104132:
* MIPS32 M-Class core at 200 MHz
* 1 MB program flash, 256 KB data RAM
* 40 MHz crystal inside the module
* 2.4 GHz IEEE 802.11 b/g/n Wi-Fi (not supported by NuttX)
* SST26VF032B 32 Mbit (4 MB) SPI serial flash (U202)
* LAN8720A 10/100 Ethernet PHY (U301, RMII) with RJ45 connector J301
* USB Type-C connector J202 (5 V power input only; the data lines are
not connected) and MCP1727 3.3 V regulator
* Debug UART header J203
* Two user LEDs and one user button
* ICSP header J204 (not fitted on the kit)
Supported hardware
==================
========================= ======= ====================================
Peripheral Status Notes
========================= ======= ====================================
UART1 Yes NSH console on J203
Timers Yes System tick
GPIO Yes
SPI1 Yes SST26VF032B; reads tested only
I2C1/I2C2 Build Not tested; no I2C device on board
Ethernet No
Wi-Fi No
========================= ======= ====================================
Pin mapping
===========
Module pads and chip pins as wired on the EV49N51A (schematic 02-01134
Rev 2):
============== ================ =============================================
Pin Signal Notes
============== ================ =============================================
RA8 U1RX Debug UART, dedicated pin (not PPS)
RA9 U1TX Debug UART, dedicated pin (not PPS)
RK1 LED D201 (red) Active high
RK3 LED D202 (green) Active high
RA10 SW202 User button, low when pressed
RA1 SST26 CS GPIO, active low
RPC6 SPI1 SCK Dedicated SPI1 pin (``DEVCFG1.HSSPIEN``)
RPC7 SPI1 SDI Dedicated SPI1 pin
RPC8 SPI1 SDO Dedicated SPI1 pin
RB4 / RB5 PGC2 / PGD2 ICSP (J204), debug channel 2
RA4 / RA5 I2C1 GPIO header footprint (not fitted)
============== ================ =============================================
The Ethernet PHY uses RPC9-RPC15, RPK6, RPK12-RPK14 and RPA14, but there
is no Ethernet driver yet.
Buttons and LEDs
================
The board has two user LEDs, both active high:
* D201 (red): RK1
* D202 (green): RK3
D203 (red) is the power LED and cannot be controlled by software.
When ``CONFIG_ARCH_LEDS`` is selected (the default), the LEDs are used by
the OS as follows:
================ ======================= ======= =======
SYMBOL MEANING GREEN RED
================ ======================= ======= =======
LED_STARTED NuttX has been started OFF OFF
LED_HEAPALLOCATE Heap has been allocated OFF OFF
LED_IRQSENABLED Interrupts enabled OFF OFF
LED_STACKCREATED Idle stack created ON OFF
LED_INIRQ In an interrupt N/C GLOW
LED_SIGNAL In a signal handler N/C GLOW
LED_ASSERTION An assertion failed N/C GLOW
LED_PANIC The system has crashed N/C FLASH
================ ======================= ======= =======
The user button SW202 (RA10) and the reset button SW203 (MCLR) are
present on the board, but there is no button driver yet.
Clocking
========
Unlike the PIC32MZ EC/EF families, the PIC32MZ-W1 does not configure its
PLLs from the configuration words. At boot, ``pic32mz_wfi32_pwrclk.c``:
#. On B0 silicon, after a power-on or brown-out reset, switches the
power management unit (PMU) from its power-on MLDO mode to buck mode,
using the factory trim values stored in the device.
``CONFIG_PIC32MZ_W1_PMU_MLDO=y`` skips this step and keeps the PMU in
MLDO mode.
#. Starts the 40 MHz primary oscillator inside the module.
#. Programs the system PLL (40 MHz / 5 * 150 / 6 = 200 MHz) and the
Ethernet/Wi-Fi PLL, and switches SYSCLK to the system PLL.
The peripheral bus clocks are set in ``include/board.h``:
======= ======= ========= =====================================
Clock Divider Frequency Used by
======= ======= ========= =====================================
PBCLK1 5 40 MHz Timers, UART3
PBCLK2 2 100 MHz I/O ports, I2C1, ADC, CAN
PBCLK3 4 50 MHz UART1/2, SPI1/2, I2C2
PBCLK4 10 20 MHz RTCC, DSCON
PBCLK5 2 100 MHz Flash, crypto, SQI
======= ======= ========= =====================================
PBCLK6 clocks the CPU on PIC32MZ-W1 and is not changed.
The program flash uses ``CONFIG_PIC32MZ_W1_FLASH_WAITSTATES`` wait states
(5 by default at 200 MHz).
Configuration words
-------------------
The build places the configuration words (DEVCFG0/1/2/4, FBCFG0, FCPN0 and
FSIGN0) in ``nuttx.hex``, so no separate configuration step is needed when
flashing. They are set through Kconfig (``PIC32MZ_*`` options in
``arch/mips/src/pic32mz/Kconfig``). The ``nsh`` configuration selects ICSP
channel 2 (``CONFIG_PIC32MZ_ICESEL_CH2``) and keeps the secondary
oscillator disabled: the 32.768 kHz crystal X401 is not fitted on the kit.
Toolchains
==========
The port builds with two toolchains:
* ``CONFIG_MIPS32_TOOLCHAIN_PINGUINOL``: the Pinguino p32-gcc toolchain,
also used by the NuttX CI for all MIPS boards. It can be downloaded from
https://github.com/PinguinoIDE/pinguino-compilers:
.. code:: console
$ curl -sSL -O https://github.com/PinguinoIDE/pinguino-compilers/releases/download/v20.10/pinguino-linux64-p32.zip
$ unzip pinguino-linux64-p32.zip
$ export PATH=$PWD/p32/bin:$PATH
* ``CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32``: Microchip MPLAB XC32 for
Linux (tested with v6.00), selected by the ``nsh`` defconfig.
XC32 v6 and later no longer include device support and need the
`PIC32MZ-W Device Family Pack
<https://packs.download.microchip.com/>`_ (DFP). Extract the
``Microchip.PIC32MZ-W_DFP`` ``.atpack`` file (a zip archive) to
``~/microchip/WFI32-W_DFP``, or point ``WFI32E01_DFP_DIR`` at another
location:
.. code:: console
$ make WFI32E01_DFP_DIR=/path/to/PIC32MZ-W_DFP
Flashing
========
The EV49N51A has no on-board programmer. The flash is programmed through
the ICSP header J204 (MCLR, PGC2/RB4, PGD2/RB5, 3.3 V, GND), which is not
fitted on the kit, using a Microchip programmer and MPLAB IPE. The port was
tested with a PICkit 3:
.. code:: console
$ cd /opt/microchip/mplabx/v6.20/mplab_platform/mplab_ipe
$ ./ipecmd.sh -P32MZ1025W104132 -TPPK3 -M -F/path/to/nuttx/nuttx.hex -Y -OL
``-M`` programs the whole device, ``-Y`` verifies it and ``-OL`` releases
the device from reset. For other programmers, change ``-TPPK3`` (for
example ``-TPPK4`` for a PICkit 4).
.. warning::
Programming erases the factory firmware. Read it back first with
MPLAB IPE if you want to restore it later.
.. note::
Debugging through a PICkit 3 does not work with this device
(MPLAB X marks PICkit 3 support for it as beta). Programming works.
For early boot problems, use ``CONFIG_PIC32MZ_W1_BOOTTRACE`` (see
below).
Configurations
==============
Each configuration is built with:
.. code:: console
$ ./tools/configure.sh -l ev49n51a:<config>
$ make
To build with the Pinguino toolchain instead of XC32:
.. code:: console
$ ./tools/configure.sh -l ev49n51a:nsh
$ kconfig-tweak --disable MIPS32_TOOLCHAIN_MICROCHIPL_XC32 \
--enable MIPS32_TOOLCHAIN_PINGUINOL
$ make olddefconfig
$ make
nsh
---
Basic NuttShell configuration with the console on UART1. Connect a 3.3 V
USB-to-serial adapter to J203:
========== ============ =====================
J203 pin Signal Adapter
========== ============ =====================
1 U1RX (RA8) TX
2 U1TX (RA9) RX
3 GND GND
========== ============ =====================
and open it at 115200 8N1, without flow control.
The SST26VF032B serial flash is registered as ``/dev/mtdblock0``.
.. code:: console
nsh> uname -a
NuttX 13.0.1-RC1 ec7277eeba Oct 3 2026 17:10:38 mips ev49n51a
nsh> ls -l /dev
/dev:
crw-rw-rw- 0 console
brw-rw-rw- 4194304 mtdblock0
crw-rw-rw- 0 null
crw-rw-rw- 0 ttyS0
crw-rw-rw- 0 zero
Boot trace
==========
``CONFIG_PIC32MZ_W1_BOOTTRACE=y`` prints one character on UART1 for each
PMU and clock bring-up step, before the PLLs are running. UART1 is clocked
from the internal FRC during this phase, so the baud rate is about
117647 instead of 115200; most terminals still read it. The normal console
takes over once the clocks are up.
Silicon tested: WFI32E01PE, revision B0 (DEVID 0x0A400000).
Limitations
===========
* No Ethernet or Wi-Fi driver.
* I2C1/I2C2 build but are not tested.
* SPI flash: only reads were tested (JEDEC ID and data), not writes or
erases.
* UART3 is not wired up.
* No button driver.
References
==========
* `PIC32MZ W1 and WFI32E01 Family Data Sheet (DS70005425)
<https://www.microchip.com/en-us/product/WFI32E01PE>`_
* `EV49N51A Ethernet to Wi-Fi Bridge
<https://www.microchip.com/en-us/development-tool/EV49N51A>`_

13
Documentation/platforms/mips/pic32mz/index.rst
View file

@ -60,6 +60,19 @@ This was a collaborative effort between Kristopher Tate, David Sidrane
and myself. The basic port is functional and a NuttShell (NSH)
configuration is available.
Microchip PIC32MZ-W1
--------------------
PIC32MZ-W1 family (MIPS32 M-Class core with 2.4 GHz Wi-Fi), including the
WFI32E01 module. A port is available for the Microchip EV49N51A (Ethernet
to Wi-Fi Bridge) board, based on the WFI32E01PE module
(PIC32MZ1025W104132).
The W1 special function register layout and clock tree differ from the
EC/EF families, and software must start the oscillator, the PLLs and the
power management unit at boot. Supported: UART, timers, GPIO and SPI
(tested), I2C (build only). Ethernet and Wi-Fi are not supported.
Supported Boards
================

14
boards/Kconfig
View file

@ -805,6 +805,16 @@ config ARCH_BOARD_CHIPKIT_WIFIRE
board is a chipKIT Arduino-compatible board. This board
features the Microchip PIC32MZ2048EFG100 MCU running at 200 MHz.
config ARCH_BOARD_EV49N51A
bool "Microchip EV49N51A Ethernet to Wi-Fi Bridge (WFI32E01PE)"
depends on ARCH_CHIP_WFI32E01
select ARCH_HAVE_LEDS
---help---
This option selects the Microchip EV49N51A Ethernet to Wi-Fi
Bridge board, built around the WFI32E01PE module (PIC32MZ-W1
family, MIPS32 M-Class core with integrated 802.11n Wi-Fi)
running at 200 MHz, with a LAN8720A Ethernet PHY.
config ARCH_BOARD_FLIPNCLICK_PIC32MZ
bool "Mikroe Flip&Click PIC32MZ"
depends on ARCH_CHIP_PIC32MZ2048EFH
@ -4047,6 +4057,7 @@ config ARCH_BOARD
default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO
default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32
default "chipkit-wifire" if ARCH_BOARD_CHIPKIT_WIFIRE
default "ev49n51a" if ARCH_BOARD_EV49N51A
default "flipnclick-pic32mz" if ARCH_BOARD_FLIPNCLICK_PIC32MZ
default "flipnclick-sam3x" if ARCH_BOARD_FLIPNCLICK_SAM3X
default "freedom-k28f" if ARCH_BOARD_FREEDOM_K28F
@ -5334,6 +5345,9 @@ endif
if ARCH_BOARD_CHIPKIT_WIFIRE
source "boards/mips/pic32mz/chipkit-wifire/Kconfig"
endif
if ARCH_BOARD_EV49N51A
source "boards/mips/pic32mz/ev49n51a/Kconfig"
endif
if ARCH_BOARD_FLIPNCLICK_PIC32MZ
source "boards/mips/pic32mz/flipnclick-pic32mz/Kconfig"
endif

8
boards/mips/pic32mz/ev49n51a/Kconfig Normal file
View file

@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_EV49N51A
endif # ARCH_BOARD_EV49N51A

43
boards/mips/pic32mz/ev49n51a/configs/nsh/defconfig Normal file
View file

@ -0,0 +1,43 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_RAMFUNCS is not set
CONFIG_ARCH="mips"
CONFIG_ARCH_BOARD="ev49n51a"
CONFIG_ARCH_BOARD_EV49N51A=y
CONFIG_ARCH_CHIP="pic32mz"
CONFIG_ARCH_CHIP_PIC32MZ=y
CONFIG_ARCH_CHIP_PIC32MZW1=y
CONFIG_ARCH_CHIP_WFI32E01=y
CONFIG_ARCH_MIPS=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=7245
CONFIG_BUILTIN=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_LINE_MAX=64
CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32=y
CONFIG_MTD=y
CONFIG_MTD_SST26=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_PIC32MZ_ICESEL_CH2=y
CONFIG_PIC32MZ_SPI1=y
CONFIG_PIC32MZ_UART1=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=262144
CONFIG_RAM_START=0xa0000000
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=2
CONFIG_START_MONTH=10
CONFIG_START_YEAR=2026
CONFIG_SYSTEM_NSH=y
CONFIG_UART1_SERIAL_CONSOLE=y

194
boards/mips/pic32mz/ev49n51a/include/board.h Normal file
View file

@ -0,0 +1,194 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/include/board.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_MIPS_PIC32MZ_EV49N51A_INCLUDE_BOARD_H
#define __BOARDS_MIPS_PIC32MZ_EV49N51A_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdbool.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************
*
* Unlike EC/EF, PIC32MZ-W1's system PLL is NOT configured from these
* BOARD_PLL_* macros by pic32mz_lowinit.c - it is configured directly by
* pic32mz_wfi32_pwrclk.c (a fixed, hardcoded SPLLCON value, matching
* Microchip's own reference firmware for this chip/board family). The
* macros below exist only so that:
*
* 1. pic32mz_lowinit.c's self-consistency sanity check
* (CALC_SYSCLOCK == BOARD_CPU_CLOCK) passes.
* 2. pic32mz_prefetch() picks the correct number of flash wait states
* for the real CPU clock.
*
* They were derived by decoding the actual SPLLCON value
* (WFI32_SPLLCON_VALUE in pic32mz_wfi32_pwrclk.c) field-by-field
* (SPLLREFDIV=5, SPLLFBDIV=150, SPLLPOSTDIV1=6), combined with the
* documented CPU_CLOCK_FREQUENCY=200000000 from Microchip's reference
* firmware (definitions.h) to solve for the crystal frequency - NOT
* taken from a schematic. If pic32mz_wfi32_pwrclk.c's SPLLCON value ever
* changes, these must be recomputed to match.
*/
#define BOARD_POSC_FREQ 40000000 /* Primary OSC XTAL frequency (derived, see above) */
#define BOARD_PLL_INPUT BOARD_POSC_FREQ
#define BOARD_PLL_IDIV 5 /* SPLLREFDIV */
#define BOARD_PLL_MULT 150 /* SPLLFBDIV */
#define BOARD_PLL_ODIV 6 /* SPLLPOSTDIV1 */
#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz, per Microchip's
* reference firmware for this chip */
/* Peripheral clocks.
*
* Only PBCLK4 is set explicitly by pic32mz_wfi32_pwrclk.c (to divide-by-10,
* i.e. 20MHz, the value used by Microchip's example firmware);
* pic32mz_pbclk() will then apply the same BOARD_PB4DIV value redundantly
* (harmless, see pic32mz_lowinit.c). PBCLK1-3/5 divisors below are this
* NuttX port's own choice, chosen conservatively; they can be tuned later
* once real peripherals are exercised. Peripheral to bus assignments are
* from DS70005425 Table 11-1.
*/
#define BOARD_PB1DIV 5 /* Divider = 5 */
#define BOARD_PBCLK1 40000000 /* PBCLK1 = 200MHz/5 = 40MHz (Timers, UART3) */
#define BOARD_PBCLK2_ENABLE 1
#define BOARD_PB2DIV 2 /* Divider = 2 */
#define BOARD_PBCLK2 100000000 /* PBCLK2 = 200MHz/2 = 100MHz (Ports, I2C1, ADC, CAN) */
#define BOARD_PBCLK3_ENABLE 1
#define BOARD_PB3DIV 4 /* Divider = 4 */
#define BOARD_PBCLK3 50000000 /* PBCLK3 = 200MHz/4 = 50MHz (UART1/2, SPI, I2C2, IC, OC) */
#define BOARD_PBCLK4_ENABLE 1
#define BOARD_PB4DIV 10 /* Divider = 10 (matches pic32mz_wfi32_pwrclk.c) */
#define BOARD_PBCLK4 20000000 /* PBCLK4 = 200MHz/10 = 20MHz (RTCC, DSCON) */
#define BOARD_PBCLK5_ENABLE 1
#define BOARD_PB5DIV 2 /* Divider = 2 */
#define BOARD_PBCLK5 100000000 /* PBCLK5 = 200MHz/2 = 100MHz (Flash, Crypto, SQI) */
#undef BOARD_PBCLK6_ENABLE
/* PIC32MZ-W1 has no PB7/PB8 bus - leave both undefined (see
* pic32mz_lowinit.c/hardware/pic32mz_osc.h for why these must stay
* undefined on this chip).
*/
#undef BOARD_PBCLK7_ENABLE
#undef BOARD_PBCLK8_ENABLE
/* Watchdog pre-scaler (not yet used - WDT is left disabled by the
* reference config; revisit if/when WDT support is added for this chip).
*/
#define BOARD_WD_PRESCALER 1048576
/* LED definitions **********************************************************
*
* Two user LEDs (EV49N51A schematic 02-01134 rev 2), both active high
* (anode on the pin, 330R to GND):
*
* D201 red - RK1 (module pad 34)
* D202 green - RK3 (module pad 35)
*
* When CONFIG_ARCH_LEDS is defined, they are used by the OS as follows:
*
* SYMBOL Meaning GREEN RED
* ----------------- ----------------------- ------- -------
* LED_STARTED NuttX has been started OFF OFF
* LED_HEAPALLOCATE Heap has been allocated OFF OFF
* LED_IRQSENABLED Interrupts enabled OFF OFF
* LED_STACKCREATED Idle stack created ON OFF
* LED_INIRQ In an interrupt N/C GLOW
* LED_SIGNAL In a signal handler N/C GLOW
* LED_ASSERTION An assertion failed N/C GLOW
* LED_PANIC The system has crashed N/C FLASH
*/
#define BOARD_LED_RED 0
#define BOARD_LED_GREEN 1
#define BOARD_NLEDS 2
#define BOARD_LED_RED_BIT (1 << BOARD_LED_RED)
#define BOARD_LED_GREEN_BIT (1 << BOARD_LED_GREEN)
#define LED_STARTED 0
#define LED_HEAPALLOCATE 1
#define LED_IRQSENABLED 2
#define LED_STACKCREATED 3
#define LED_INIRQ 4
#define LED_SIGNAL 4
#define LED_ASSERTION 4
#define LED_PANIC 4
/* UARTS ********************************************************************
*
* The console is UART1 on 3-pin header J203 (1=U1RX, 2=U1TX, 3=GND); an
* external 3.3V USB-UART adapter is required, there is no on-board
* debugger/USB-UART bridge. J203 is wired to module pads 29 (U1TX, RA9)
* and 30 (U1RX, RA8), which are UART1's dedicated, non-PPS pins (RA8/RA9
* have no RPn function). BOARD_U1RX_PPS/BOARD_U1TX_PPS are therefore
* intentionally left undefined so that no PPS routing is programmed.
*/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_MIPS_PIC32MZ_EV49N51A_INCLUDE_BOARD_H */

66
boards/mips/pic32mz/ev49n51a/scripts/Make.defs Normal file
View file

@ -0,0 +1,66 @@
############################################################################
# boards/mips/pic32mz/ev49n51a/scripts/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/pic32/Config.mk
include $(TOPDIR)/arch/mips/src/mips32/Toolchain.defs
# mips-debug.ld is plain GNU ld syntax and works with every supported
# toolchain (XC32, Pinguino, generic mips-elf), so override the
# per-toolchain default from Toolchain.defs.
LDSCRIPT = mips-debug.ld
# MPLAB XC32 (Linux). XC32 v6+ requires an explicit Device Family Pack
# (DFP) path via -mdfp - it no longer bundles device support. Point
# WFI32E01_DFP_DIR at an extracted Microchip PIC32MZ-W_DFP
# (packs.download.microchip.com) if it is not already at this default
# path.
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y)
MIPS_MPROCESSOR = WFI32E01
WFI32E01_DFP_DIR ?= $(HOME)/microchip/WFI32-W_DFP
ARCHCPUFLAGS += -mdfp=$(WFI32E01_DFP_DIR)
# -mprocessor=WFI32E01 lets XC32 emit DSP ASE instructions (e.g. lwx).
# They trap unless CP0 Status.MX is set, which NuttX's head.S does not
# do, and NuttX's MIPS context switch does not save the DSP state, so
# keep the compiler away from the DSP ASE (verified on hardware: the
# first lwx hung the boot).
ARCHCPUFLAGS += -mno-dsp -mno-dspr2
endif
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
# The linker is invoked directly, not through gcc, so it does not see the
# -EL from ARCHCPUFLAGS (see the note in mips-debug.ld).
LDFLAGS += -EL
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__

305
boards/mips/pic32mz/ev49n51a/scripts/mips-debug.ld Normal file
View file

@ -0,0 +1,305 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/scripts/mips-debug.ld
*
* Adapted from boards/mips/pic32mz/flipnclick-pic32mz/scripts/mips-debug.ld
* for the WFI32E01 (PIC32MZ-W1). Memory region addresses/sizes were
* cross-checked against Microchip's PIC32MZ-W_DFP (WFI32E01.atdf) and its
* reference linker script (xc32/WFI32E01/pWFI32E01.ld) - WFI32E01's
* program flash lives at a different physical base (0x10000000) than
* EC/EF (0x1d000000); do not assume EC/EF addresses apply.
*
* The MIPS32 microAptiv exception vector layout (reset/TLB-refill/cache
* error/general/interrupt/EJTAG offsets from EBase) is core-architecture
* defined, not PIC32-family specific, so that part is unchanged from
* EC/EF.
*
* The boot-flash configuration words (.devcfg at 0xbfc55f88, plus FCPN0
* and FSIGN0) are emitted by pic32mz_head.S; see
* hardware/pic32mzw1_features.h.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Memory Regions ***********************************************************/
MEMORY
{
/* WFI32E01 has 1024Kb (1MB) of program FLASH at physical address
* 0x10000000, always accessed at KSEG0 address 0x9000:0000.
*/
kseg0_progmem (rx) : ORIGIN = 0x90000000, LENGTH = 1024K
/* Exception vectors and startup trampoline, in boot flash
* (0xbfc00000, KSEG1). Offsets below the vectors are defined by the
* MIPS32 microAptiv core architecture (EBase-relative), same as on
* PIC32MZ-EC/EF:
*
* REGION PHYSICAL KSEG SIZE
* DESCRIPTION START ADDR (BYTES)
* ------------- ---------- ------ ----------------------
* Reset 0x1fc00000 KSEG1 512
* TLB Refill 0x1fc00200 KSEG1 256
* Cache Error 0x1fc00300 KSEG1 128
* Others 0x1fc00380 KSEG1 128
* Interrupt 0x1fc00400 KSEG1 128
* JTAG 0x1fc00480 KSEG1 16
*
* Exceptions assume STATUS:BEV=0/1,EXL=0; CAUSE:IV=1; multi-vector
* support disabled - same configuration pic32mz_head.S sets up for
* EC/EF.
*/
kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
/* Boot-flash configuration words (primary copy) */
kseg1_devcfg (r) : ORIGIN = 0xbfc55f88, LENGTH = 24
kseg1_devcp (r) : ORIGIN = 0xbfc55fbc, LENGTH = 4
kseg1_devsign (r) : ORIGIN = 0xbfc55fdc, LENGTH = 4
/* WFI32E01 has 256Kb of data memory at physical address 0x00000000,
* always accessed through KSEG1 (no data cache). 640 bytes are set
* aside at the start, matching the margin EC/EF boards reserve.
*/
kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 256K - 640
}
/* No OUTPUT_FORMAT: XC32 names its little-endian ELF target
* elf32-tradlittlemips while Pinguino's binutils only know
* elf32-littlemips. Make.defs passes -EL instead, so each linker
* picks its own little-endian format.
*/
OUTPUT_ARCH(mips)
ENTRY(__start)
SECTIONS
{
/* Boot FLASH sections */
.reset :
{
KEEP (*(.reset))
} > kseg1_reset
/* KSEG1 exception handler "trampolines" */
.gen_excpt :
{
KEEP (*(.gen_excpt))
} > kseg1_genexcpt
.ebase_excpt :
{
KEEP (*(.ebase_excpt))
} > kseg1_ebexcpt
.bev_excpt :
{
KEEP (*(.bev_excpt))
} > kseg1_bevexcpt
.int_excpt :
{
KEEP (*(.int_excpt))
} > kseg1_intexcpt
.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
.start :
{
/* KSEG0 Reset startup logic */
*(.start)
/* KSEG0 exception handlers */
*(.nmi_handler)
*(.bev_handler)
*(.int_handler)
} > kseg0_bootmem
.dbg_code = ORIGIN(kseg1_dbgcode);
.devcfg :
{
KEEP (*(.devcfg))
} > kseg1_devcfg
.devcfg_cp :
{
KEEP (*(.devcfg_cp))
} > kseg1_devcp
.devcfg_sign :
{
KEEP (*(.devcfg_sign))
} > kseg1_devsign
/* ABI flags note: not needed in the image; discard it so it is not
* placed as an orphan into the configuration regions above.
*/
/DISCARD/ : { *(.MIPS.abiflags) }
/* Program FLASH sections */
.text :
{
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.stub)
KEEP (*(.text.*personality*))
*(.gnu.linkonce.t.*)
*(.gnu.warning)
*(.mips16.fn.*)
*(.mips16.call.*)
/* Read-only data is included in the text section */
*(.rodata .rodata.*)
*(.rodata1)
*(.gnu.linkonce.r.*)
/* Small initialized constant global and static data */
*(.sdata2 .sdata2.*)
*(.gnu.linkonce.s2.*)
/* Uninitialized constant global and static data */
*(.sbss2 .sbss2.*)
*(.gnu.linkonce.sb2.*)
_etext = ABSOLUTE(.);
} > kseg0_progmem
/* Initialization data begins here in progmem */
_data_loaddr = LOADADDR(.data);
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
.data :
{
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
*(.data1)
} > kseg1_datamem AT > kseg0_progmem
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
_gp = ALIGN(16) + 0x7FF0 ;
.got :
{
*(.got.plt) *(.got)
} > kseg1_datamem AT > kseg0_progmem
.sdata :
{
*(.sdata .sdata.* .gnu.linkonce.s.*)
} > kseg1_datamem AT > kseg0_progmem
.lit8 :
{
*(.lit8)
} > kseg1_datamem AT > kseg0_progmem
.lit4 :
{
*(.lit4)
. = ALIGN(4);
_edata = ABSOLUTE(.);
} >kseg1_datamem AT>kseg0_progmem
.sbss :
{
. = ALIGN(16);
_sbss = ABSOLUTE(.);
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
} >kseg1_datamem
.bss :
{
*(.dynbss)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(16);
_ebss = ABSOLUTE(.);
} > kseg1_datamem
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/DISCARD/ : { *(.note.GNU-stack) }
}

35
boards/mips/pic32mz/ev49n51a/src/Makefile Normal file
View file

@ -0,0 +1,35 @@
############################################################################
# boards/mips/pic32mz/ev49n51a/src/Makefile
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = pic32mz_boot.c pic32mz_bringup.c
ifeq ($(CONFIG_PIC32MZ_SPI1),y)
CSRCS += pic32mz_spi.c
endif
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += pic32mz_autoleds.c
endif
include $(TOPDIR)/boards/Board.mk

95
boards/mips/pic32mz/ev49n51a/src/ev49n51a.h Normal file
View file

@ -0,0 +1,95 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/src/ev49n51a.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __BOARDS_MIPS_PIC32MZ_EV49N51A_SRC_EV49N51A_H
#define __BOARDS_MIPS_PIC32MZ_EV49N51A_SRC_EV49N51A_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "pic32mz_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LEDs: D201 red on RK1, D202 green on RK3, both active high (see
* include/board.h).
*/
#define GPIO_LED_RED (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTK | GPIO_PIN1)
#define GPIO_LED_GREEN (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTK | GPIO_PIN3)
/* SST26VF032B serial flash (U202) on SPI1: chip select on RA1, active low,
* initially deselected.
*/
#define GPIO_SST26_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTA | GPIO_PIN1)
/* SST26 MTD partition is exported as /dev/mtdblock<SST26_MTD_MINOR> */
#define SST26_MTD_MINOR 0
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: pic32mz_bringup
*
* Description:
* Bring up board features.
*
****************************************************************************/
int pic32mz_bringup(void);
/****************************************************************************
* Name: pic32mz_led_initialize
*
* Description:
* Configure on-board LED GPIO for output (CONFIG_ARCH_LEDS only).
*
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void pic32mz_led_initialize(void);
#endif
/****************************************************************************
* Name: pic32mz_spidev_initialize
*
* Description:
* Configure the SPI chip select GPIOs.
*
****************************************************************************/
#ifdef CONFIG_PIC32MZ_SPI1
void pic32mz_spidev_initialize(void);
#endif
#endif /* __BOARDS_MIPS_PIC32MZ_EV49N51A_SRC_EV49N51A_H */

88
boards/mips/pic32mz/ev49n51a/src/pic32mz_autoleds.c Normal file
View file

@ -0,0 +1,88 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/src/pic32mz_autoleds.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "mips_internal.h"
#include "pic32mz_gpio.h"
#include "ev49n51a.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pic32mz_led_initialize
****************************************************************************/
void pic32mz_led_initialize(void)
{
pic32mz_configgpio(GPIO_LED_RED);
pic32mz_configgpio(GPIO_LED_GREEN);
}
/****************************************************************************
* Name: board_autoled_on
****************************************************************************/
void board_autoled_on(int led)
{
switch (led)
{
case LED_STACKCREATED:
pic32mz_gpiowrite(GPIO_LED_GREEN, true);
break;
case LED_INIRQ:
pic32mz_gpiowrite(GPIO_LED_RED, true);
break;
default:
break;
}
}
/****************************************************************************
* Name: board_autoled_off
****************************************************************************/
void board_autoled_off(int led)
{
if (led == LED_INIRQ)
{
pic32mz_gpiowrite(GPIO_LED_RED, false);
}
}
#endif /* CONFIG_ARCH_LEDS */

81
boards/mips/pic32mz/ev49n51a/src/pic32mz_boot.c Normal file
View file

@ -0,0 +1,81 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/src/pic32mz_boot.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "ev49n51a.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pic32mz_boardinitialize
*
* Description:
* All PIC32MZ architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void pic32mz_boardinitialize(void)
{
#ifdef CONFIG_PIC32MZ_SPI1
pic32mz_spidev_initialize();
#endif
#ifdef CONFIG_ARCH_LEDS
pic32mz_led_initialize();
#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will
* be called immediately after up_initialize() is called and just before
* the initial application is started. This additional initialization
* phase may be used, for example, to initialize board-specific device
* drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board initialization */
pic32mz_bringup();
}
#endif /* CONFIG_BOARD_LATE_INITIALIZE */

99
boards/mips/pic32mz/ev49n51a/src/pic32mz_bringup.c Normal file
View file

@ -0,0 +1,99 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/src/pic32mz_bringup.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <syslog.h>
#include <nuttx/fs/fs.h>
#ifdef CONFIG_MTD_SST26
# include <nuttx/mtd/mtd.h>
# include "pic32mz_spi.h"
#endif
#include "ev49n51a.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pic32mz_bringup
*
* Description:
* Bring up board features
*
****************************************************************************/
int pic32mz_bringup(void)
{
int ret = OK;
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n",
ret);
}
#endif
#if defined(CONFIG_MTD_SST26) && defined(CONFIG_PIC32MZ_SPI1)
struct spi_dev_s *spi;
struct mtd_dev_s *mtd;
/* SST26VF032B serial flash on SPI1 */
spi = pic32mz_spibus_initialize(1);
if (spi == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to initialize SPI1\n");
}
else
{
mtd = sst26_initialize_spi(spi, 0);
if (mtd == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to bind SPI1 to the SST26\n");
}
else
{
ret = ftl_initialize(SST26_MTD_MINOR, mtd);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: ftl_initialize() failed: %d\n", ret);
}
}
}
#endif
UNUSED(ret);
return OK;
}

98
boards/mips/pic32mz/ev49n51a/src/pic32mz_spi.c Normal file
View file

@ -0,0 +1,98 @@
/****************************************************************************
* boards/mips/pic32mz/ev49n51a/src/pic32mz_spi.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/debug.h>
#include <nuttx/spi/spi.h>
#include "pic32mz_gpio.h"
#include "pic32mz_spi.h"
#include "ev49n51a.h"
#ifdef CONFIG_PIC32MZ_SPI1
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pic32mz_spidev_initialize
*
* Description:
* Configure the SPI chip select GPIOs. SPI1 itself uses its dedicated
* pins (SCK1 RC6, SDI1 RC7, SDO1 RC8), selected by DEVCFG1.HSSPIEN.
*
****************************************************************************/
void pic32mz_spidev_initialize(void)
{
pic32mz_configgpio(GPIO_SST26_CS);
}
/****************************************************************************
* Name: pic32mz_spi1select, pic32mz_spi1status and pic32mz_spi1cmddata
*
* Description:
* Board-specific select, status and cmddata methods of the SPI1
* interface (see include/nuttx/spi/spi.h). The only device on SPI1 is
* the SST26VF032B serial flash.
*
****************************************************************************/
void pic32mz_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %08" PRIx32 " CS: %s\n",
devid, selected ? "assert" : "de-assert");
if (devid == SPIDEV_FLASH(0))
{
/* CS is active low */
pic32mz_gpiowrite(GPIO_SST26_CS, !selected);
}
}
uint8_t pic32mz_spi1status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic32mz_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_PIC32MZ_SPI1 */