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arch/arm/stm32h5: map OTP, RO and EDATA flash non-cacheable.
The OTP, read-only (UID, flash size, package) and high-cycle data (EDATA) flash areas only accept 16/32-bit accesses and return a bus error otherwise (RM0481 Table 77). The manual requires the MPU to disable local cacheability for them (RM0481 7.3.2); with the ICACHE enabled and no such region, reading them raises a precise bus error. Until now this was worked around piecemeal: the driver disabled the ICACHE around stm32_get_uniqueid() and the OTP and EDATA word reads, and nucleo-h563zi mapped the 4 KB OTP/RO area non-cacheable in its board code. Other reads, for example stm32_otp_read() or an application reading the OTP on another board, still raised a precise bus error when the ICACHE was enabled. Map 0x08fff000-0x09017fff, which covers the three contiguous areas, as Normal non-cacheable and execute-never with a single MPU region before the ICACHE is enabled. STM32_ICACHE now selects ARM_MPU so that stm32_mpuinitialize() has reset and enabled the MPU by then. Remove the nucleo-h563zi OTP region in the same commit: the Armv8-M MPU faults on an address that matches more than one region, so keeping both would make OTP and UID reads fault on that board. Assisted-by: Claude:claude-sonnet-5-5 Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Ricardo Maurizio Paul <ricardopaul@geotab.com>
This commit is contained in:
Ricardo Maurizio Paul
Alan C. Assis
parent
6c3e9ad7b1
commit
3ff85acb4b
7 changed files with 34 additions and 67 deletions
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@ -324,6 +324,12 @@ config STM32_ICACHE
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bool "ICACHE"
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default n
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depends on STM32_HAVE_ICACHE
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select ARM_MPU
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---help---
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Enable the instruction cache (ICACHE) on the C-AHB bus. The OTP,
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read-only and high-cycle data flash areas cannot be cached
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(RM0481 7.3.2), so this option selects ARM_MPU and maps them
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non-cacheable.
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config STM32_DCACHE1
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depends on STM32_HAVE_DCACHE1
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@ -34,6 +34,7 @@
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#include <stdint.h>
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#include "arm_internal.h"
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#include "mpu.h"
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#include "stm32.h"
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/****************************************************************************
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@ -43,6 +44,15 @@
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#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32_ICACHE_INV_INT) ||\
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defined(CONFIG_STM32_ICACHE_ERR_INT))
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/* The OTP (0x08fff000), read-only (0x08fff800, UID) and EDATA
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* (0x09000000-0x09017fff) flash areas only accept 16/32-bit accesses
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* (RM0481 Table 77) and must be mapped non-cacheable (RM0481 7.3.2). They
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* are contiguous, so one MPU region covers them.
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*/
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#define STM32_ICACHE_NC_BASE 0x08fff000
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#define STM32_ICACHE_NC_END 0x09018000
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -238,12 +248,30 @@ static void stm32_icache_setup_region(struct stm32_icache_region region)
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}
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#endif
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static void stm32_icache_mpu_setup(void)
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{
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/* Non-cacheable, execute-never. stm32_mpuinitialize() enabled the MPU. */
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DEBUGASSERT((getreg32(MPU_CTRL) & MPU_CTRL_ENABLE) != 0);
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mpu_configure_region(STM32_ICACHE_NC_BASE,
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STM32_ICACHE_NC_END - STM32_ICACHE_NC_BASE,
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MPU_RBAR_XN | MPU_RBAR_AP_RWRW | MPU_RBAR_SH_NO,
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MPU_RLAR_NONCACHEABLE);
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}
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void stm32_icache_initialize(void)
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{
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#ifdef CONFIG_STM32_ICACHE_DIRECT
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uint32_t regval;
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#endif
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/* The flash areas that cannot be cached must be excluded before the
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* ICACHE is enabled.
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*/
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stm32_icache_mpu_setup();
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/* Set associativity */
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#ifdef CONFIG_STM32_ICACHE_DIRECT
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@ -52,10 +52,6 @@ if(CONFIG_STM32_USBFS_HOST)
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list(APPEND SRCS stm32_usb.c)
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endif()
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if(CONFIG_ARM_MPU)
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list(APPEND SRCS stm32_mpu.c)
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endif()
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target_sources(board PRIVATE ${SRCS})
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set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")
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@ -58,10 +58,6 @@ ifeq ($(CONFIG_STM32_USBFS_HOST),y)
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CSRCS += stm32_usb.c
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endif
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ifeq ($(CONFIG_ARM_MPU),y)
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CSRCS += stm32_mpu.c
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endif
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DEPPATH += --dep-path board
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VPATH += :board
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CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board
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@ -115,18 +115,6 @@
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int stm32_bringup(void);
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/****************************************************************************
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* Name: stm32_mpu_configure_otp
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*
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* Description:
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* Initialize MPU and configure the OTP flash region.
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*
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****************************************************************************/
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#if defined(CONFIG_ARM_MPU) && defined(CONFIG_STM32_ICACHE)
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void stm32_mpu_configure_otp(void);
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#endif
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#ifdef CONFIG_STM32_SPI
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/****************************************************************************
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* Name: stm32_spiregister
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@ -53,12 +53,6 @@
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void stm32_board_initialize(void)
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{
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#if defined(CONFIG_ARM_MPU) && defined(CONFIG_STM32_ICACHE)
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/* Configure OTP MPU region. */
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stm32_mpu_configure_otp();
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#endif
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#ifdef CONFIG_ARCH_LEDS
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/* Configure on-board LEDs if LED support has been selected. */
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@ -1,41 +0,0 @@
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/****************************************************************************
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* boards/arm/stm32h5/nucleo-h563zi/src/stm32_mpu.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/arch.h>
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#include "hardware/stm32_memorymap.h"
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#include "mpu.h"
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#include "stm32_mpuinit.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_mpu_configure_otp
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*
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* Description:
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* Configure the OTP flash region as non-cacheable, non-executable, non-
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* shareable, and read-only.
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*
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****************************************************************************/
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void stm32_mpu_configure_otp(void)
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{
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mpu_configure_region(STM32_OTP_BASE, 4096,
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MPU_RBAR_XN | MPU_RBAR_SH_NO | MPU_RBAR_AP_RORO,
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MPU_RLAR_NONCACHEABLE);
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}
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