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boards/mips/pic32mz/ev49n51a: add Ethernet support.
- Reset the LAN8720A PHY (nRST on RA14) at boot, after the RMII reference clock is running. - Define BOARD_EMAC_MIIM_DIV for a 2.5 MHz MDC. - Add the netnsh configuration: Ethernet, IPv4, TCP, UDP, ICMP, ping and telnetd, with the default static address of the network initialization and a locally administered MAC address (PIC32MZ-W1 has no factory MAC address). - Document the Ethernet interface, the RMII reference clock options and the netnsh configuration. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
This commit is contained in:
Daniel P. Carvalho
Xiang Xiao
parent
82f78ddaa0
commit
305c73f615
6 changed files with 145 additions and 8 deletions
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@ -45,7 +45,7 @@ Timers Yes System tick
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GPIO Yes
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SPI1 Yes SST26VF032B; reads tested only
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I2C1/I2C2 Build Not tested; no I2C device on board
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Ethernet No
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Ethernet Yes LAN8720A, RMII, 10/100 Mbps
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Wi-Fi No
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========================= ======= ====================================
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@ -69,11 +69,16 @@ RPC7 SPI1 SDI Dedicated SPI1 pin
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RPC8 SPI1 SDO Dedicated SPI1 pin
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RB4 / RB5 PGC2 / PGD2 ICSP (J204), debug channel 2
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RA4 / RA5 I2C1 GPIO header footprint (not fitted)
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RC12 ETH_CLK_OUT 50 MHz RMII reference clock to MAC and PHY
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RC13 ETXEN Dedicated Ethernet pin
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RC15 / RC14 ETXD0 / ETXD1 Dedicated Ethernet pins
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RC11 / RC10 ERXD0 / ERXD1 Dedicated Ethernet pins
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RK12 ECRSDV Dedicated Ethernet pin
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RC9 ERXERR Dedicated Ethernet pin
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RK14 / RK13 EMDC / EMDIO PHY management interface, PHY address 0
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RA14 PHY nRST GPIO, active low
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============== ================ =============================================
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The Ethernet PHY uses RPC9-RPC15, RPK6, RPK12-RPK14 and RPA14, but there
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is no Ethernet driver yet.
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Buttons and LEDs
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================
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@ -116,7 +121,9 @@ PLLs from the configuration words. At boot, ``pic32mz_wfi32_pwrclk.c``:
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MLDO mode.
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#. Starts the 40 MHz primary oscillator inside the module.
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#. Programs the system PLL (40 MHz / 5 * 150 / 6 = 200 MHz) and the
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Ethernet/Wi-Fi PLL, and switches SYSCLK to the system PLL.
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Ethernet/Wi-Fi PLL, and switches SYSCLK to the system PLL. When the
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Ethernet MAC is enabled, the Ethernet/Wi-Fi PLL also drives the 50 MHz
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RMII reference clock on ETH_CLK_OUT.
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The peripheral bus clocks are set in ``include/board.h``:
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@ -253,6 +260,49 @@ The SST26VF032B serial flash is registered as ``/dev/mtdblock0``.
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crw-rw-rw- 0 ttyS0
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crw-rw-rw- 0 zero
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netnsh
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------
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The ``nsh`` configuration with networking: Ethernet, IPv4, TCP, UDP and
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ICMP, the ``ping`` command and a Telnet server on port 23. The interface is
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brought up at boot with the default static address of the network
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initialization (``CONFIG_NETINIT_IPADDR``, 10.0.0.2/24 with 10.0.0.1 as
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the default router) and the MAC address 02:e0:de:ad:be:ef
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(``CONFIG_NETINIT_MACADDR_1/2``). Change these to match your network.
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The example below was taken with ``CONFIG_NETINIT_IPADDR`` set to
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192.168.100.2 and ``CONFIG_NETINIT_DRIPADDR`` to 192.168.100.1:
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.. code:: console
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nsh> ifconfig
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eth0 Link encap:Ethernet HWaddr 02:e0:de:ad:be:ef at RUNNING mtu 1500
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inet addr:192.168.100.2 DRaddr:192.168.100.1 Mask:255.255.255.0
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nsh> ping -c 3 192.168.100.1
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PING 192.168.100.1 56 bytes of data
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56 bytes from 192.168.100.1: icmp_seq=0 time=0.0 ms
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56 bytes from 192.168.100.1: icmp_seq=1 time=0.0 ms
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56 bytes from 192.168.100.1: icmp_seq=2 time=0.0 ms
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3 packets transmitted, 3 received, 0% packet loss, time 3030 ms
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rtt min/avg/max/mdev = 0.000/0.000/0.000/0.000 ms
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Ethernet
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========
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The LAN8720A PHY is connected to the MAC through RMII and is managed
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through MDIO at PHY address 0. The board code pulses the PHY reset (RA14)
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at boot, after the reference clock is running. The PHY interrupt output is
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not connected (R309 is not fitted), so the driver does not use it.
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The 50 MHz RMII reference clock comes from ETH_CLK_OUT (RC12) through R313.
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The board also has a footprint for a 50 MHz oscillator (X1, not fitted)
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that can clock the PHY through R314 (not fitted). If you fit X1 and R314,
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select ``CONFIG_PIC32MZ_W1_ETH_EXTREFCLK`` so that ETH_CLK_OUT is left
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disabled and the MAC uses the oscillator clock on the same pin.
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The PIC32MZ-W1 has no factory-programmed Ethernet MAC address. Assign one
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with ``CONFIG_NETINIT_NOMAC`` or with the ``SIOCSIFHWADDR`` ioctl before the
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interface is brought up.
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Boot trace
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==========
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@ -267,7 +317,7 @@ Silicon tested: WFI32E01PE, revision B0 (DEVID 0x0A400000).
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Limitations
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===========
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* No Ethernet or Wi-Fi driver.
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* No Wi-Fi driver.
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* I2C1/I2C2 build but are not tested.
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* SPI flash: only reads were tested (JEDEC ID and data), not writes or
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erases.
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@ -70,8 +70,8 @@ to Wi-Fi Bridge) board, based on the WFI32E01PE module
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The W1 special function register layout and clock tree differ from the
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EC/EF families, and software must start the oscillator, the PLLs and the
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power management unit at boot. Supported: UART, timers, GPIO and SPI
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(tested), I2C (build only). Ethernet and Wi-Fi are not supported.
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power management unit at boot. Supported: UART, timers, GPIO, SPI and
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Ethernet (tested), I2C (build only). Wi-Fi is not supported.
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Supported Boards
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================
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62
boards/mips/pic32mz/ev49n51a/configs/netnsh/defconfig
Normal file
62
boards/mips/pic32mz/ev49n51a/configs/netnsh/defconfig
Normal file
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@ -0,0 +1,62 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_ARCH_RAMFUNCS is not set
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CONFIG_ARCH="mips"
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CONFIG_ARCH_BOARD="ev49n51a"
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CONFIG_ARCH_BOARD_EV49N51A=y
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CONFIG_ARCH_CHIP="pic32mz"
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CONFIG_ARCH_CHIP_PIC32MZ=y
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CONFIG_ARCH_CHIP_PIC32MZW1=y
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CONFIG_ARCH_CHIP_WFI32E01=y
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CONFIG_ARCH_MIPS=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_BOARD_LOOPSPERMSEC=7245
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CONFIG_BUILTIN=y
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CONFIG_ETH0_PHY_LAN8720=y
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CONFIG_FS_PROCFS=y
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CONFIG_IDLETHREAD_STACKSIZE=2048
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LINE_MAX=64
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CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32=y
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CONFIG_MTD=y
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CONFIG_MTD_SST26=y
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CONFIG_NET=y
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CONFIG_NETDB_DNSCLIENT=y
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CONFIG_NETDEV_PHY_IOCTL=y
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CONFIG_NETINIT_MACADDR_2=0x02e0
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CONFIG_NETINIT_NOMAC=y
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CONFIG_NETINIT_THREAD=y
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CONFIG_NETUTILS_TELNETD=y
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CONFIG_NET_BROADCAST=y
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CONFIG_NET_ETH_PKTSIZE=1514
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CONFIG_NET_ICMP_SOCKET=y
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CONFIG_NET_STATISTICS=y
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CONFIG_NET_TCP=y
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CONFIG_NET_UDP=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_READLINE=y
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CONFIG_PIC32MZ_ETHERNET=y
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CONFIG_PIC32MZ_ICESEL_CH2=y
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CONFIG_PIC32MZ_SPI1=y
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CONFIG_PIC32MZ_UART1=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=262144
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CONFIG_RAM_START=0xa0000000
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_LPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SST26_SPIFREQUENCY=20000000
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CONFIG_START_DAY=2
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CONFIG_START_MONTH=10
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CONFIG_START_YEAR=2026
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_PING=y
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CONFIG_UART1_SERIAL_CONSOLE=y
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@ -115,6 +115,14 @@
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#define BOARD_WD_PRESCALER 1048576
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/* Ethernet MII management clock (MDC).
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*
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* The MIIM module is clocked at 100 MHz (PBCLK5), as on the other PIC32MZ
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* parts. The LAN8720A accepts MDC up to 2.5 MHz.
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*/
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#define BOARD_EMAC_MIIM_DIV 40 /* 100MHz/40 = 2.5MHz */
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/* LED definitions **********************************************************
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*
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* Two user LEDs (EV49N51A schematic 02-01134 rev 2), both active high
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@ -50,6 +50,12 @@
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#define GPIO_SST26_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTA | GPIO_PIN1)
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/* LAN8720A Ethernet PHY (U301) reset on RA14, active low. R304 pulls it
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* high, so the PHY also runs when the pin is left as an input.
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*/
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#define GPIO_PHY_NRST (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTA | GPIO_PIN14)
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/* SST26 MTD partition is exported as /dev/mtdblock<SST26_MTD_MINOR> */
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#define SST26_MTD_MINOR 0
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@ -48,6 +48,17 @@
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void pic32mz_boardinitialize(void)
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{
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#ifdef CONFIG_PIC32MZ_ETHERNET
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/* Reset the PHY now that its 50 MHz reference clock is running, so that
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* it starts from a known state. The LAN8720A needs nRST low for at
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* least 100 us.
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*/
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pic32mz_configgpio(GPIO_PHY_NRST);
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up_udelay(200);
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pic32mz_gpiowrite(GPIO_PHY_NRST, true);
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#endif
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#ifdef CONFIG_PIC32MZ_SPI1
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pic32mz_spidev_initialize();
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#endif
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