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arch/mips/pic32mz: add Ethernet support for PIC32MZ-W1.

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- PIC32MZ-W1 only has the RMII interface and no DEVCFG3, so hide the
  PIC32MZ_FMIIEN and PIC32MZ_FETHIO options and define
  CONFIG_PIC32MZ_FMIIEN as 0 (RMII), matching DEVCFG1.FMIIEN.  The
  default of 1 (MII) made the driver skip the RMII reset and speed
  setup, so the MAC ran its RMII logic at 10 Mbps.
- Enable ETH_CLK_OUT (EWPLLCON.ETHCLKOUTEN), the 50 MHz RMII reference
  clock for the MAC and the PHY, only when the Ethernet MAC is enabled.
- Add PIC32MZ_W1_ETH_EXTREFCLK for boards that clock the PHY and the
  MAC from an external 50 MHz oscillator; ETH_CLK_OUT is then left
  disabled.

Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
This commit is contained in:
Daniel P. Carvalho 2026-10-03 19:14:04 -03:00 • committed by Xiang Xiao
parent 447ebd7fd5
commit 82f78ddaa0
3 changed files with 29 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

14
arch/mips/src/pic32mz/Kconfig
View file

@ -121,6 +121,18 @@ config PIC32MZ_W1_FLASH_WAITSTATES
WFI32_Ethernet_Wi-Fi_Bridge_OOB example. The reset value, 7, is
the most conservative choice.
config PIC32MZ_W1_ETH_EXTREFCLK
bool "PIC32MZ-W1: RMII reference clock from an external oscillator"
default n
depends on ARCH_CHIP_PIC32MZW1 && PIC32MZ_ETHERNET
---help---
By default the Ethernet/Wi-Fi PLL drives the 50 MHz RMII reference
clock on ETH_CLK_OUT (RC12), which feeds both the MAC and the PHY.
Select this option if the board has a 50 MHz oscillator that
clocks the PHY and the MAC reference clock input (EREFCLK)
instead. ETH_CLK_OUT is then left disabled
(EWPLLCON.ETHCLKOUTEN = 0).
config PIC32MZ_W1_BOOTTRACE
bool "PIC32MZ-W1 early boot trace on UART1"
default n
@ -1263,6 +1275,7 @@ config PIC32MZ_FMIIEN
int "Ethernet MII"
default 1
range 0 1
depends on !ARCH_CHIP_PIC32MZW1
---help---
Ethernet MII enable selection
@ -1288,6 +1301,7 @@ config PIC32MZ_FETHIO
int "Ethernet I/O pins"
default 1
range 0 1
depends on !ARCH_CHIP_PIC32MZW1
---help---
Ethernet I/O pin selection

6
arch/mips/src/pic32mz/pic32mz_config.h
View file

@ -690,9 +690,13 @@
/* DEVCFG1. UART1 and SPI1 use their dedicated (non-PPS) pins unless the
* board routes them through PPS (BOARD_U1RX_PPS/BOARD_SDI1_PPS defined).
* Ethernet in RMII mode with the reference clock on ETH_CLK_OUT.
* Ethernet in RMII mode (FMIIEN = 0) with the reference clock on
* ETH_CLK_OUT (ETHEXEREF = 0). PIC32MZ-W1 only has the RMII interface
* [DS Tables 33-1, 33-2]; the Ethernet driver checks CONFIG_PIC32MZ_FMIIEN.
*/
#define CONFIG_PIC32MZ_FMIIEN 0
#ifdef CONFIG_PIC32MZ_DEBUGGER_ENABLE
# define W1CFG_DEBUG DEVCFG1_DEBUG_ENABLED
#else

12
arch/mips/src/pic32mz/pic32mz_wfi32_pwrclk.c
View file

@ -82,11 +82,19 @@
/* EWPLL: 40 MHz POSC / 4 * 160 = 1600 MHz VCO; / 32 = 50 MHz RMII
* reference on ETH_CLK_OUT, / 10 (CFGCON3.ETHPLLPOSTDIV2) = 160 MHz for
* Wi-Fi. Field layout [DS Reg 11-6]; the field values, and starting it
* with RST and PWDN set, are [EX].
* with RST and PWDN set, are [EX]. ETH_CLK_OUT is only enabled when the
* Ethernet MAC uses it as its RMII reference clock [DS Reg 11-6, 38-2].
*/
#if defined(CONFIG_PIC32MZ_ETHERNET) && \
!defined(CONFIG_PIC32MZ_W1_ETH_EXTREFCLK)
# define WFI32_EWPLL_CLKOUTEN PLLCON_CLKOUTEN
#else
# define WFI32_EWPLL_CLKOUTEN 0
#endif
#define WFI32_EWPLLCON \
(PLLCON_CLKOUTEN | PLLCON_REFDIV(4) | PLLCON_FBDIV(160) | \
(WFI32_EWPLL_CLKOUTEN | PLLCON_REFDIV(4) | PLLCON_FBDIV(160) | \
PLLCON_RST | PLLCON_POSTDIV1(32) | PLLCON_PWDN | PLLCON_BSWSEL(2))
#define WFI32_CFGCON3 CFGCON3_ETHPLLPOSTDIV2(10) /* [EX] */