diff --git a/Documentation/platforms/mips/pic32mz/boards/ev49n51a/index.rst b/Documentation/platforms/mips/pic32mz/boards/ev49n51a/index.rst index fb9510cf642..06a0417d8e1 100644 --- a/Documentation/platforms/mips/pic32mz/boards/ev49n51a/index.rst +++ b/Documentation/platforms/mips/pic32mz/boards/ev49n51a/index.rst @@ -45,7 +45,7 @@ Timers Yes System tick GPIO Yes SPI1 Yes SST26VF032B; reads tested only I2C1/I2C2 Build Not tested; no I2C device on board -Ethernet No +Ethernet Yes LAN8720A, RMII, 10/100 Mbps Wi-Fi No ========================= ======= ==================================== @@ -69,11 +69,16 @@ RPC7 SPI1 SDI Dedicated SPI1 pin RPC8 SPI1 SDO Dedicated SPI1 pin RB4 / RB5 PGC2 / PGD2 ICSP (J204), debug channel 2 RA4 / RA5 I2C1 GPIO header footprint (not fitted) +RC12 ETH_CLK_OUT 50 MHz RMII reference clock to MAC and PHY +RC13 ETXEN Dedicated Ethernet pin +RC15 / RC14 ETXD0 / ETXD1 Dedicated Ethernet pins +RC11 / RC10 ERXD0 / ERXD1 Dedicated Ethernet pins +RK12 ECRSDV Dedicated Ethernet pin +RC9 ERXERR Dedicated Ethernet pin +RK14 / RK13 EMDC / EMDIO PHY management interface, PHY address 0 +RA14 PHY nRST GPIO, active low ============== ================ ============================================= -The Ethernet PHY uses RPC9-RPC15, RPK6, RPK12-RPK14 and RPA14, but there -is no Ethernet driver yet. - Buttons and LEDs ================ @@ -116,7 +121,9 @@ PLLs from the configuration words. At boot, ``pic32mz_wfi32_pwrclk.c``: MLDO mode. #. Starts the 40 MHz primary oscillator inside the module. #. Programs the system PLL (40 MHz / 5 * 150 / 6 = 200 MHz) and the - Ethernet/Wi-Fi PLL, and switches SYSCLK to the system PLL. + Ethernet/Wi-Fi PLL, and switches SYSCLK to the system PLL. When the + Ethernet MAC is enabled, the Ethernet/Wi-Fi PLL also drives the 50 MHz + RMII reference clock on ETH_CLK_OUT. The peripheral bus clocks are set in ``include/board.h``: @@ -253,6 +260,49 @@ The SST26VF032B serial flash is registered as ``/dev/mtdblock0``. crw-rw-rw- 0 ttyS0 crw-rw-rw- 0 zero +netnsh +------ + +The ``nsh`` configuration with networking: Ethernet, IPv4, TCP, UDP and +ICMP, the ``ping`` command and a Telnet server on port 23. The interface is +brought up at boot with the default static address of the network +initialization (``CONFIG_NETINIT_IPADDR``, 10.0.0.2/24 with 10.0.0.1 as +the default router) and the MAC address 02:e0:de:ad:be:ef +(``CONFIG_NETINIT_MACADDR_1/2``). Change these to match your network. +The example below was taken with ``CONFIG_NETINIT_IPADDR`` set to +192.168.100.2 and ``CONFIG_NETINIT_DRIPADDR`` to 192.168.100.1: + +.. code:: console + + nsh> ifconfig + eth0 Link encap:Ethernet HWaddr 02:e0:de:ad:be:ef at RUNNING mtu 1500 + inet addr:192.168.100.2 DRaddr:192.168.100.1 Mask:255.255.255.0 + nsh> ping -c 3 192.168.100.1 + PING 192.168.100.1 56 bytes of data + 56 bytes from 192.168.100.1: icmp_seq=0 time=0.0 ms + 56 bytes from 192.168.100.1: icmp_seq=1 time=0.0 ms + 56 bytes from 192.168.100.1: icmp_seq=2 time=0.0 ms + 3 packets transmitted, 3 received, 0% packet loss, time 3030 ms + rtt min/avg/max/mdev = 0.000/0.000/0.000/0.000 ms + +Ethernet +======== + +The LAN8720A PHY is connected to the MAC through RMII and is managed +through MDIO at PHY address 0. The board code pulses the PHY reset (RA14) +at boot, after the reference clock is running. The PHY interrupt output is +not connected (R309 is not fitted), so the driver does not use it. + +The 50 MHz RMII reference clock comes from ETH_CLK_OUT (RC12) through R313. +The board also has a footprint for a 50 MHz oscillator (X1, not fitted) +that can clock the PHY through R314 (not fitted). If you fit X1 and R314, +select ``CONFIG_PIC32MZ_W1_ETH_EXTREFCLK`` so that ETH_CLK_OUT is left +disabled and the MAC uses the oscillator clock on the same pin. + +The PIC32MZ-W1 has no factory-programmed Ethernet MAC address. Assign one +with ``CONFIG_NETINIT_NOMAC`` or with the ``SIOCSIFHWADDR`` ioctl before the +interface is brought up. + Boot trace ========== @@ -267,7 +317,7 @@ Silicon tested: WFI32E01PE, revision B0 (DEVID 0x0A400000). Limitations =========== -* No Ethernet or Wi-Fi driver. +* No Wi-Fi driver. * I2C1/I2C2 build but are not tested. * SPI flash: only reads were tested (JEDEC ID and data), not writes or erases. diff --git a/Documentation/platforms/mips/pic32mz/index.rst b/Documentation/platforms/mips/pic32mz/index.rst index 9c48777b6fb..ab6c9094f98 100644 --- a/Documentation/platforms/mips/pic32mz/index.rst +++ b/Documentation/platforms/mips/pic32mz/index.rst @@ -70,8 +70,8 @@ to Wi-Fi Bridge) board, based on the WFI32E01PE module The W1 special function register layout and clock tree differ from the EC/EF families, and software must start the oscillator, the PLLs and the -power management unit at boot. Supported: UART, timers, GPIO and SPI -(tested), I2C (build only). Ethernet and Wi-Fi are not supported. +power management unit at boot. Supported: UART, timers, GPIO, SPI and +Ethernet (tested), I2C (build only). Wi-Fi is not supported. Supported Boards ================ diff --git a/boards/mips/pic32mz/ev49n51a/configs/netnsh/defconfig b/boards/mips/pic32mz/ev49n51a/configs/netnsh/defconfig new file mode 100644 index 00000000000..1162e285b4b --- /dev/null +++ b/boards/mips/pic32mz/ev49n51a/configs/netnsh/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_RAMFUNCS is not set +CONFIG_ARCH="mips" +CONFIG_ARCH_BOARD="ev49n51a" +CONFIG_ARCH_BOARD_EV49N51A=y +CONFIG_ARCH_CHIP="pic32mz" +CONFIG_ARCH_CHIP_PIC32MZ=y +CONFIG_ARCH_CHIP_PIC32MZW1=y +CONFIG_ARCH_CHIP_WFI32E01=y +CONFIG_ARCH_MIPS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=7245 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32=y +CONFIG_MTD=y +CONFIG_MTD_SST26=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETINIT_MACADDR_2=0x02e0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PIC32MZ_ETHERNET=y +CONFIG_PIC32MZ_ICESEL_CH2=y +CONFIG_PIC32MZ_SPI1=y +CONFIG_PIC32MZ_UART1=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0xa0000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SST26_SPIFREQUENCY=20000000 +CONFIG_START_DAY=2 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2026 +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_UART1_SERIAL_CONSOLE=y diff --git a/boards/mips/pic32mz/ev49n51a/include/board.h b/boards/mips/pic32mz/ev49n51a/include/board.h index d3333273292..6c382045545 100644 --- a/boards/mips/pic32mz/ev49n51a/include/board.h +++ b/boards/mips/pic32mz/ev49n51a/include/board.h @@ -115,6 +115,14 @@ #define BOARD_WD_PRESCALER 1048576 +/* Ethernet MII management clock (MDC). + * + * The MIIM module is clocked at 100 MHz (PBCLK5), as on the other PIC32MZ + * parts. The LAN8720A accepts MDC up to 2.5 MHz. + */ + +#define BOARD_EMAC_MIIM_DIV 40 /* 100MHz/40 = 2.5MHz */ + /* LED definitions ********************************************************** * * Two user LEDs (EV49N51A schematic 02-01134 rev 2), both active high diff --git a/boards/mips/pic32mz/ev49n51a/src/ev49n51a.h b/boards/mips/pic32mz/ev49n51a/src/ev49n51a.h index 2e2f0e1ddda..4fa0018b8b1 100644 --- a/boards/mips/pic32mz/ev49n51a/src/ev49n51a.h +++ b/boards/mips/pic32mz/ev49n51a/src/ev49n51a.h @@ -50,6 +50,12 @@ #define GPIO_SST26_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTA | GPIO_PIN1) +/* LAN8720A Ethernet PHY (U301) reset on RA14, active low. R304 pulls it + * high, so the PHY also runs when the pin is left as an input. + */ + +#define GPIO_PHY_NRST (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTA | GPIO_PIN14) + /* SST26 MTD partition is exported as /dev/mtdblock */ #define SST26_MTD_MINOR 0 diff --git a/boards/mips/pic32mz/ev49n51a/src/pic32mz_boot.c b/boards/mips/pic32mz/ev49n51a/src/pic32mz_boot.c index 3186911c1f5..e7a92e5584d 100644 --- a/boards/mips/pic32mz/ev49n51a/src/pic32mz_boot.c +++ b/boards/mips/pic32mz/ev49n51a/src/pic32mz_boot.c @@ -48,6 +48,17 @@ void pic32mz_boardinitialize(void) { +#ifdef CONFIG_PIC32MZ_ETHERNET + /* Reset the PHY now that its 50 MHz reference clock is running, so that + * it starts from a known state. The LAN8720A needs nRST low for at + * least 100 us. + */ + + pic32mz_configgpio(GPIO_PHY_NRST); + up_udelay(200); + pic32mz_gpiowrite(GPIO_PHY_NRST, true); +#endif + #ifdef CONFIG_PIC32MZ_SPI1 pic32mz_spidev_initialize(); #endif