Fixes bug where stm32_phyinit will succeed even when no PHY is connected. This is because there is no check that a PHY is actually communicating and returning data.
Update include/nuttx/net/mii.h
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
Due to interrupt latencies the i2c transfer done interrupt can get
deferred by a few hunder microseconds. This makes the i2c transfer timeout
way too early, even though the i2c IP block is already done.
Fix this by adding a significant amount of margin (1ms) to the timeout
value.
This removes several error conditions that can be present after a failed
i2c transaction. The most important of them is the priv->sem_isr semaphore
which can be signaled due to a race condition.
This also ensures the i2c device itself is in idle state before futzing
around with it.
Also, add a comment about the SI-flag in the I2C CTRL register; it has
a hidden dual meaning. Not only does it clear a pending interrupt, it
also moves the I2C IP state machine forward. This requires extra logic
in the driver to cope.
This selects ARM_THUMB for ARMV7R per ARM document:
https://developer.arm.com/documentation/dui0471
Thanks to hujun260 for spotting this, now ostest works.
Why it helps is still to be clarified, the `arm_signal_handler.S`
might require this THUMB option.
To keep ARM_THUMB as option, this only selects it for
PROTECTED as per anchao's suggestion.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This adds up_allocate_heap() support for PROTECTED mode so that
kernel and user heap sizes match memory.ld linker script.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes task start syscall in PROTECTED mode, following that
of armv7-m so that hello and getprime programs can run smoothly.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This adds MPU and userspace handling in QEMU chips so that to
boot PROTECTED target qemu-armv7r:pnsh.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This copies struct mpu_region_s from armv7-m to fix PROTECTED mode
build error: `invalid use of undefined type 'struct mpu_region_s'`
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes undefined 'ARCH_DATA_RESERVE' in arm_syscall.c:382 so
that to build qemu-armv7r:pnsh. Per nuttx/addrenv.h, that macro
is defined for BUILD_KERNEL, we need use BUILD_PROTECTED now.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes below issues when building for PROTECTED mode:
- `common/arm_fork.c:223 'struct xcpt_syscall_s' has no member 'cpsr'`
- `armv7-r/arm_syscall.c:454 'xcptcontext' has no member 'sigreturn'`
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
Espnow is a connectionless WiFi communication protocol that can be used
to exchange information between esp nodes.
A espnow pktradio driver is proposed that allows building a 6lowpan
network of nodes.
The driver has been evaluated using udpclient & server running on
different devices.
Solves #15347
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
The message RAM does not behave correctly if lower 16 bits of
buffer address overflow (upper 16 bits are set once in matrix driver
for the entire CAN driver). For example message RAM starting at
0x2040fc20 would not work for buffers that go beyond 0x20410000 and
MCAN would sent data located at 0x20400000 to the network. The same
issue would occur even if TX buffers would start directly at 0x20410000.
The upper 16 bits would still have 0x2040 value because of RX buffers
located in 0x2040ffff range.
This commit ensures the RAM is always located at the beginning of
the data section and thus the overflow mentioned above should never occur.
The alternative would be to use larger alignment, but the message RAM
can have up to 4352 words and this would cause a significant padding.
The RAM is also initialized to zero to ensure valid parity/ECC checksums.
The address issue is not described anywhere in the manual, so it is
possible this is caused by some incorrect configuration, but the context
of the registers looks valid.
This commit also fixes the compilation errors when the driver is run
without data cache.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The CPCSTOP has a negative effect on the periodic timer operation.
This causes the timer to stop when an overrun occurs.
Timer must be then restarted in the interrupt. However, as interrupts
are not infinitely fast, this prolongs the next timeout.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
This adds semihosting based poweroff to arm/common. It uses
semihosting operation SYS_EXIT (0x18) with parameter AppExit
(0x20026).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
1. Changes the phyadd to 0xC to speed up the training of phyadd.
2. Set RX DMA buffer size configureable.
3. Create netnsh configs as ethernet boot from QSPI FLASH.
4. Fix some typo in #15720 which is nonsynchronous with local code.
PIC(Position-Independent-Code) board could work on cmake:
cmake -B ap -DBOARD_CONFIG=mps3-an547:ap -GNinja
Signed-off-by: chao an <anchao.archer@bytedance.com>
Make sure the registers context size is aligned to 16bytes as required by armv8-a.
This issue has been reported earlier, thus make sense to make sure it won't happen in future.
Signed-off-by: Neo Xu <neo.xu1990@gmail.com>
zynq-mpsoc and zcu111 borad was broken by #15437, because #15437 changes
ARM64_CONTEXT_REGS from 36 to 37, resulting in the stack no longer being
16-byte aligned which appears to violate the ARMv8-A architecture's
requirement for 16-byte stack alignment. this commit changes ARM64_CONTEXT_REGS
to 38 to fix this issues.
Zynq MPSOC The processing system (PS) is equipped with four gigabit
Ethernet controllers.Each controller can be configured independently.
Each controller uses a reduced gigabit media independent interface (RGMII)
v2.0. This commit add support for ethernet of ZYNQ MPSOC.
Summary:
- Added `--print-memory-usage` to `LDFLAGS` in `Toolchain.defs` for both `lx6` and `lx7` architectures
- This flag enables memory usage reporting during the linking phase, providing better visibility into memory allocation
Impact:
- No functional changes - the flag only adds additional debug information during the build process
- Improves debugging and optimization capabilities by providing detailed memory usage statistics
- Maintains compatibility with existing build configurations and toolchains
Testing:
Test result on esp32s3:
```
Memory region Used Size Region Size %age Used
ROM: 556116 B 16777184 B 3.31%
iram0_0_seg: 23296 B 304 KB 7.48%
irom0_0_seg: 621652 B 16777184 B 3.71%
dram0_0_seg: 85780 B 288 KB 29.09%
drom0_0_seg: 157180 B 16777184 B 0.94%
rtc_iram_seg: 0 B 8168 B 0.00%
rtc_data_seg: 0 B 8168 B 0.00%
rtc_reserved_seg: 0 B 24 B 0.00%
rtc_slow_seg: 0 B 8 KB 0.00%
```
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
What's really need is a done signal sent from the secondary
cpu to the boot cpu, so let's simplify the logic by:
1.Change the spinlock to a bool flag
2.Set the flag to true in the secondary cpu
3.Wait the flag set in the boot cpu before continue booting
This also remove all bad usage of spinlock from the code base:
1.Lock spinlock in one thread, but unlock in a different thread
2.Lock spinlock twice in one thread, but unlock only once
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Also errors which currently return other than -EAGAIN, are typically
recoverable with retraining. So just re-try trainining 20 times on any
error, resetting the controller in between.
Only reset if it is not recovered in this time.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
So far only USART drivers could use TX/RX DMA. This commit adds the
support for UART drivers as well (with the exception of serial console).
UART peripheral does not have timeout interrupt, so external polling
is required to flush the RX data from DMA buffers even if the buffer
is not yet full. The board layer can do this by calling
sam_serial_dma_poll function.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
If scratchpad is being used, the cache way 0, which is automatically
enabled at boot, needs to be re-configured as part of scratchpad memory
Otherwise there is a possibility of random memory corruption in the
scratchpad
area due to cache eviction from way 0.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Summary:
- Unified the specification of LLVM architecture and ABI types across the CMake and Makefile configurations.
- Introduced `LLVM_ARCHTYPE` and `LLVM_CPUTYPE` variables in the CMake configuration to match the Makefile's approach.
- Standardized the ABI type (`LLVM_ABITYPE`) to `sysv` for both Linux and macOS host configurations.
Impact:
- Ensures consistent LLVM target definitions across build systems (CMake and Makefile).
- Simplifies future maintenance by avoiding divergence in LLVM-related configurations.
- No functional changes to the build output; only the internal representation of LLVM target information is aligned.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Progress in USB driver
Nothing is working yet. But just getting this in here so it is saved.
Minor changes with USB power enabled
Serial over USB is working now.
Removed stm32_usbdev.c, added stm32_usbfs.c. Still needs review before pull-request.
Rewrote VDDUSB valid check to use register definitions. Wait for USB33RDY before moving on. Also style updates.
Renamed stm32_usbdev files to stm32_usbfs. Renamed STM32H5 configuration options from STM32H5_USB to STM32H5_USBFS. Properly named REGDEBUG defines. Added STM32H5_USB_REGDEBUG to Kconfig and updated stm32_usbfs.c to use it. TRACE functionality still needs work.
Updated REGDEBUG for 32-bit register accesses.
More style updates.
Added usbnsh defconfig to nucleo-h563zi
Update to allow 16 buffers (max for 8 endpoints). Renamed lpinterrupt and lptransfer. Changed board.h to use SYNCSRC_USB only if USB is enabled.
Buffer size is still set to max packet size of 64 bytes, because we are using a full-speed peripheral. It is unclear to me whether having a buffer larger than the max packet size has any benefit. Double buffering is a way to increase throughput, though that still needs to be implemented.
Adapted USBFS Buffer table for 32-bit accesses.
Style updates
Build stm32_hsi48.c based on CONFIG_STM32H5_HAVE_HSI48.
Change LPMODE CNTR bit to SUSPRDY.
fix smp crash on sabre-6quad/smp, regression from:
|commit 1e49cb4828
|Author: hujun5 <hujun5@xiaomi.com>
|Date: Thu Dec 5 16:58:17 2024 +0800
|
| armv7-a/armv7-r/armv8-r: percpu reg store this_task
|
| This is continue work of https://github.com/apache/nuttx/pull/13726
|
| We can utilize percpu storage to hold information about the
| current running task. If we intend to implement this feature, we would
| need to define two macros that help us manage this percpu information
| effectively.
|
| up_this_task: This macro is designed to read the contents of the percpu
| register to retrieve information about the current
| running task.This allows us to quickly access
| task-specific data without having to disable interrupts,
| access global variables and obtain the current cpu index.
|
| up_update_task: This macro is responsible for updating the contents of
| the percpu register.It is typically called during
| initialization or when a context switch occurs to ensure
| that the percpu register reflects the information of the
| newly running task.
|
| Signed-off-by: hujun5 <hujun5@xiaomi.com>
Signed-off-by: chao an <anchao.archer@bytedance.com>
Summary:
- Added LLVM target definitions (`LLVM_ARCH`, `LLVM_CPU`, `LLVM_ABI`) to `arch/x86_64/src/cmake/Toolchain.cmake` and `arch/x86_64/src/common/Toolchain.defs`
- These definitions are necessary for compatibility with LLVM-based toolchains and ensure proper target architecture, CPU, and ABI settings
Impact:
- Enables support for LLVM-based toolchains when building for x86_64 architecture
- No functional changes for existing GNU-based toolchains
- Improves maintainability by centralizing LLVM-specific configurations in the toolchain files
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Added LLVM target definitions (`LLVM_ARCHTYPE`, `LLVM_CPUTYPE`, `LLVM_ABITYPE`) to the x86 toolchain configuration file
- These definitions are necessary for compatibility with LLVM-based toolchains
Impact:
- Enables support for LLVM toolchains when building for x86 targets
- No functional changes for existing GCC-based toolchains
- Improves cross-compilation flexibility by supporting additional toolchain options
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
