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Revert "Use small lock to protect resources related to i2c."

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This reverts commit 919ed2e3d4.
This commit is contained in:
Xiang Xiao 2025-02-06 23:00:23 +08:00 • committed by archer
parent 43a47f49dc
commit 61620affe6
26 changed files with 148 additions and 317 deletions
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18
arch/arm/src/at32/at32_i2c.c
View file

@ -151,7 +151,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include <nuttx/kmalloc.h>
@ -316,7 +316,6 @@ struct at32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -430,7 +429,6 @@ static struct at32_i2c_priv_s at32_i2c1_priv =
.config = &at32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -467,7 +465,6 @@ static struct at32_i2c_priv_s at32_i2c2_priv =
.config = &at32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -504,7 +501,6 @@ static struct at32_i2c_priv_s at32_i2c3_priv =
.config = &at32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -670,7 +666,7 @@ static inline int at32_i2c_sem_waitdone(struct at32_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -687,8 +683,6 @@ static inline int at32_i2c_sem_waitdone(struct at32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_AT32_I2C_DYNTIMEO
@ -707,8 +701,6 @@ static inline int at32_i2c_sem_waitdone(struct at32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -723,7 +715,7 @@ static inline int at32_i2c_sem_waitdone(struct at32_i2c_priv_s *priv)
at32_i2c_modifyreg32(priv, AT32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1624,7 +1616,7 @@ static int at32_i2c_isr_process(struct at32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1641,7 +1633,7 @@ static int at32_i2c_isr_process(struct at32_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

18
arch/arm/src/cxd56xx/cxd56_i2c.c
View file

@ -39,7 +39,7 @@
#include <nuttx/mutex.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -84,7 +84,6 @@ struct cxd56_i2cdev_s
uint32_t base_freq; /* branch frequency */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for transfer completion */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
@ -109,7 +108,6 @@ static struct cxd56_i2cdev_s g_i2c0dev =
.base = CXD56_SCU_I2C0_BASE,
.irqid = CXD56_IRQ_SCU_I2C0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -121,7 +119,6 @@ static struct cxd56_i2cdev_s g_i2c1dev =
.base = CXD56_SCU_I2C1_BASE,
.irqid = CXD56_IRQ_SCU_I2C1,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -133,7 +130,6 @@ static struct cxd56_i2cdev_s g_i2c2dev =
.base = CXD56_I2CM_BASE,
.irqid = CXD56_IRQ_I2CM,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -362,11 +358,11 @@ static void cxd56_i2c_setfrequency(struct cxd56_i2cdev_s *priv,
static void cxd56_i2c_timeout(wdparm_t arg)
{
struct cxd56_i2cdev_s *priv = (struct cxd56_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->error = -ENODEV;
nxsem_post(&priv->wait);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -525,7 +521,7 @@ static int cxd56_i2c_receive(struct cxd56_i2cdev_s *priv, int last)
i2c_reg_write(priv, CXD56_IC_DATA_CMD, CMD_READ);
}
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
cxd56_i2c_timeout, (wdparm_t)priv);
@ -534,7 +530,7 @@ static int cxd56_i2c_receive(struct cxd56_i2cdev_s *priv, int last)
i2c_reg_write(priv, CXD56_IC_DATA_CMD, CMD_READ | (en ? CMD_STOP : 0));
i2c_reg_rmw(priv, CXD56_IC_INTR_MASK, INTR_RX_FULL, INTR_RX_FULL);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
if (priv->error != OK)
@ -571,7 +567,7 @@ static int cxd56_i2c_send(struct cxd56_i2cdev_s *priv, int last)
while (!(i2c_reg_read(priv, CXD56_IC_STATUS) & STATUS_TFNF));
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
cxd56_i2c_timeout, (wdparm_t)priv);
i2c_reg_write(priv, CXD56_IC_DATA_CMD,
@ -580,7 +576,7 @@ static int cxd56_i2c_send(struct cxd56_i2cdev_s *priv, int last)
/* Enable TX_EMPTY interrupt for determine transfer done. */
i2c_reg_rmw(priv, CXD56_IC_INTR_MASK, INTR_TX_EMPTY, INTR_TX_EMPTY);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
return 0;

15
arch/arm/src/gd32f4/gd32f4xx_i2c.c
View file

@ -66,7 +66,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -243,7 +243,6 @@ struct gd32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -379,7 +378,6 @@ static struct gd32_i2c_priv_s gd32_i2c0_priv =
.config = &gd32_i2c0_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -415,7 +413,6 @@ static struct gd32_i2c_priv_s gd32_i2c1_priv =
.config = &gd32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -451,7 +448,6 @@ static struct gd32_i2c_priv_s gd32_i2c2_priv =
.config = &gd32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -695,7 +691,7 @@ static inline int gd32_i2c_sem_waitdone(struct gd32_i2c_priv_s *priv)
uint32_t regval;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -711,8 +707,6 @@ static inline int gd32_i2c_sem_waitdone(struct gd32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_GD32F4_I2C_DYNTIMEO
@ -731,8 +725,6 @@ static inline int gd32_i2c_sem_waitdone(struct gd32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -749,8 +741,7 @@ static inline int gd32_i2c_sem_waitdone(struct gd32_i2c_priv_s *priv)
regval &= ~I2C_CTL1_INTS_MASK;
gd32_i2c_putreg(priv, GD32_I2C_CTL1_OFFSET, regval);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else

11
arch/arm/src/kinetis/kinetis_i2c.c
View file

@ -41,7 +41,7 @@
#include <nuttx/semaphore.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -116,7 +116,6 @@ struct kinetis_i2cdev_s
volatile uint8_t state; /* State of state machine */
bool restart; /* Should next transfer restart or not */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for state machine completion */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
struct i2c_msg_s *msgs; /* Remaining transfers - first one is in
@ -194,7 +193,6 @@ static struct kinetis_i2cdev_s g_i2c0_dev =
.config = &kinetis_i2c0_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.state = STATE_OK,
.msgs = NULL,
@ -218,7 +216,6 @@ static struct kinetis_i2cdev_s g_i2c1_dev =
.config = &kinetis_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.state = STATE_OK,
.msgs = NULL,
@ -242,7 +239,6 @@ static struct kinetis_i2cdev_s g_i2c2_dev =
.config = &kinetis_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.state = STATE_OK,
.msgs = NULL,
@ -266,7 +262,6 @@ static struct kinetis_i2cdev_s g_i2c3_dev =
.config = &kinetis_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.state = STATE_OK,
.msgs = NULL,
@ -823,10 +818,10 @@ static void kinetis_i2c_timeout(wdparm_t arg)
DEBUGASSERT(priv != NULL);
i2cinfo("Timeout msg=%p\n", priv->msgs);
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->state = STATE_TIMEOUT;
kinetis_i2c_endwait(priv);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************

12
arch/arm/src/lc823450/lc823450_i2c.c
View file

@ -37,7 +37,7 @@
#include <stddef.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/clock.h>
#include <nuttx/signal.h>
@ -121,7 +121,6 @@ struct lc823450_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -210,7 +209,6 @@ static struct lc823450_i2c_priv_s lc823450_i2c0_priv =
.config = &lc823450_i2c0_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -241,7 +239,6 @@ static struct lc823450_i2c_priv_s lc823450_i2c1_priv =
.config = &lc823450_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -1008,7 +1005,7 @@ static int lc823450_i2c_transfer(struct i2c_master_s *dev,
if (lc823450_i2c_sem_waitdone(priv) < 0)
{
irqs = spin_lock_irqsave(&priv->spinlock);
irqs = enter_critical_section();
ret = -ETIMEDOUT;
@ -1020,7 +1017,7 @@ static int lc823450_i2c_transfer(struct i2c_master_s *dev,
priv->timedout = true;
spin_unlock_irqrestore(&priv->spinlock, irqs);
leave_critical_section(irqs);
/* Wait for irq handler completion. 10msec wait is probably enough
* to terminate i2c transaction, NACK and STOP contition for read
@ -1031,9 +1028,10 @@ static int lc823450_i2c_transfer(struct i2c_master_s *dev,
}
else
{
spin_unlock_irqrestore(&priv->spinlock, irqs);
i2cerr("No need of timeout handling. "
"It may be done in irq handler\n");
leave_critical_section(irqs);
}
#ifndef CONFIG_LC823450_IPL2

28
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View file

@ -60,7 +60,7 @@
#include <nuttx/semaphore.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -105,7 +105,6 @@ struct lpc17_40_i2cdev_s
uint16_t irqid; /* IRQ for this device */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
@ -145,25 +144,22 @@ static int lpc17_40_i2c_reset(struct i2c_master_s *dev);
#ifdef CONFIG_LPC17_40_I2C0
static struct lpc17_40_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC17_40_I2C1
static struct lpc17_40_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC17_40_I2C2
static struct lpc17_40_i2cdev_s g_i2c2dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
@ -292,10 +288,10 @@ static void lpc17_40_i2c_timeout(wdparm_t arg)
{
struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->state = 0xff;
nxsem_post(&priv->wait);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -531,7 +527,7 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
irqstate_t flags;
uint32_t regval;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
#ifdef CONFIG_LPC17_40_I2C0
if (port == 0)
@ -621,12 +617,12 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
else
#endif
{
spin_unlock_irqrestore(&priv->spinlock, flags);
i2cerr("ERROR: LPC I2C Only supports ports 0, 1 and 2\n");
leave_critical_section(flags);
return NULL;
}
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
putreg32(I2C_CONSET_I2EN, priv->base + LPC17_40_I2C_CONSET_OFFSET);

28
arch/arm/src/lpc2378/lpc23xx_i2c.c
View file

@ -62,7 +62,7 @@
#include <nuttx/semaphore.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -109,7 +109,6 @@ struct lpc2378_i2cdev_s
uint16_t irqid; /* IRQ for this device */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
@ -149,25 +148,22 @@ static int lpc2378_i2c_reset(struct i2c_master_s *dev);
#ifdef CONFIG_LPC2378_I2C0
static struct lpc2378_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC2378_I2C1
static struct lpc2378_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC2378_I2C2
static struct lpc2378_i2cdev_s g_i2c2dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
@ -269,10 +265,10 @@ static void lpc2378_i2c_timeout(wdparm_t arg)
{
struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->state = 0xff;
nxsem_post(&priv->wait);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -485,7 +481,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
irqstate_t flags;
uint32_t regval;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
#ifdef CONFIG_LPC2378_I2C0
if (port == 0)
@ -581,11 +577,11 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
else
#endif
{
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return NULL;
}
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET);

25
arch/arm/src/lpc31xx/lpc31_i2c.c
View file

@ -41,7 +41,7 @@
#include <nuttx/semaphore.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -74,7 +74,6 @@ struct lpc31_i2cdev_s
uint16_t irqid; /* IRQ for this device */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
struct wdog_s timeout; /* Watchdog to timeout when bus hung */
@ -97,14 +96,12 @@ struct lpc31_i2cdev_s
static struct lpc31_i2cdev_s i2cdevices[2] =
{
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
},
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
},
};
@ -426,7 +423,7 @@ static void i2c_timeout(wdparm_t arg)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
if (priv->state != I2C_STATE_DONE)
{
@ -452,7 +449,7 @@ static void i2c_timeout(wdparm_t arg)
nxsem_post(&priv->wait);
}
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -491,7 +488,7 @@ static int i2c_transfer(struct i2c_master_s *dev,
/* Get exclusive access to the I2C bus */
nxmutex_lock(&priv->lock);
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Set up for the transfer */
@ -519,17 +516,13 @@ static int i2c_transfer(struct i2c_master_s *dev,
while (priv->state != I2C_STATE_DONE)
{
spin_unlock_irqrestore(&priv->spinlock, flags);
nxsem_wait(&priv->wait);
flags = spin_lock_irqsave(&priv->spinlock);
}
wd_cancel(&priv->timeout);
ret = count - priv->nmsg;
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxmutex_unlock(&priv->lock);
return ret;
}

23
arch/arm/src/lpc43xx/lpc43_i2c.c
View file

@ -59,7 +59,7 @@
#include <nuttx/semaphore.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -97,7 +97,6 @@ struct lpc43_i2cdev_s
uint32_t base_freq; /* branch frequency */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for state machine completion */
volatile uint8_t state; /* State of state machine */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
@ -113,17 +112,15 @@ struct lpc43_i2cdev_s
#ifdef CONFIG_LPC43_I2C0
static struct lpc43_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC43_I2C1
static struct lpc43_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
@ -244,10 +241,10 @@ static void lpc43_i2c_timeout(wdparm_t arg)
{
struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->state = 0xff;
nxsem_post(&priv->wait);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -462,7 +459,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
irqstate_t flags;
uint32_t regval;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
#ifdef CONFIG_LPC43_I2C0
if (port == 0)
@ -523,11 +520,11 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
else
#endif
{
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return NULL;
}
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
putreg32(I2C_CONSET_I2EN, priv->base + LPC43_I2C_CONSET_OFFSET);

17
arch/arm/src/rp2040/rp2040_i2c.c
View file

@ -39,7 +39,7 @@
#include <nuttx/mutex.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -79,7 +79,6 @@ struct rp2040_i2cdev_s
uint32_t base_freq; /* branch frequency */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for transfer completion */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
@ -99,7 +98,6 @@ static struct rp2040_i2cdev_s g_i2c0dev =
.base = RP2040_I2C0_BASE,
.irqid = RP2040_I2C0_IRQ,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -111,7 +109,6 @@ static struct rp2040_i2cdev_s g_i2c1dev =
.base = RP2040_I2C1_BASE,
.irqid = RP2040_I2C1_IRQ,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -270,11 +267,11 @@ static void rp2040_i2c_setfrequency(struct rp2040_i2cdev_s *priv,
static void rp2040_i2c_timeout(wdparm_t arg)
{
struct rp2040_i2cdev_s *priv = (struct rp2040_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->error = -ENODEV;
nxsem_post(&priv->wait);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -437,7 +434,7 @@ static int rp2040_i2c_receive(struct rp2040_i2cdev_s *priv, int last)
RP2040_I2C_IC_DATA_CMD_CMD);
}
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
rp2040_i2c_timeout, (wdparm_t)priv);
@ -450,7 +447,7 @@ static int rp2040_i2c_receive(struct rp2040_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, RP2040_I2C_IC_INTR_MASK_OFFSET,
RP2040_I2C_IC_INTR_STAT_R_RX_FULL,
RP2040_I2C_IC_INTR_STAT_R_RX_FULL);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
if (priv->error != OK)
@ -492,7 +489,7 @@ static int rp2040_i2c_send(struct rp2040_i2cdev_s *priv, int last)
& RP2040_I2C_IC_STATUS_TFNF))
;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
rp2040_i2c_timeout, (wdparm_t)priv);
i2c_reg_write(priv, RP2040_I2C_IC_DATA_CMD_OFFSET,
@ -504,7 +501,7 @@ static int rp2040_i2c_send(struct rp2040_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, RP2040_I2C_IC_INTR_MASK_OFFSET,
RP2040_I2C_IC_INTR_STAT_R_TX_EMPTY,
RP2040_I2C_IC_INTR_STAT_R_TX_EMPTY);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
return 0;

17
arch/arm/src/rp23xx/rp23xx_i2c.c
View file

@ -39,7 +39,7 @@
#include <nuttx/mutex.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "chip.h"
@ -79,7 +79,6 @@ struct rp23xx_i2cdev_s
uint32_t base_freq; /* branch frequency */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
sem_t wait; /* Place to wait for transfer completion */
struct wdog_s timeout; /* watchdog to timeout when bus hung */
uint32_t frequency; /* Current I2C frequency */
@ -99,7 +98,6 @@ static struct rp23xx_i2cdev_s g_i2c0dev =
.base = RP23XX_I2C0_BASE,
.irqid = RP23XX_I2C0_IRQ,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -111,7 +109,6 @@ static struct rp23xx_i2cdev_s g_i2c1dev =
.base = RP23XX_I2C1_BASE,
.irqid = RP23XX_I2C1_IRQ,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.wait = SEM_INITIALIZER(0),
.refs = 0,
};
@ -270,11 +267,11 @@ static void rp23xx_i2c_setfrequency(struct rp23xx_i2cdev_s *priv,
static void rp23xx_i2c_timeout(wdparm_t arg)
{
struct rp23xx_i2cdev_s *priv = (struct rp23xx_i2cdev_s *)arg;
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
priv->error = -ENODEV;
nxsem_post(&priv->wait);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
}
/****************************************************************************
@ -437,7 +434,7 @@ static int rp23xx_i2c_receive(struct rp23xx_i2cdev_s *priv, int last)
RP23XX_I2C_IC_DATA_CMD_CMD);
}
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
rp23xx_i2c_timeout, (wdparm_t)priv);
@ -450,7 +447,7 @@ static int rp23xx_i2c_receive(struct rp23xx_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, RP23XX_I2C_IC_INTR_MASK_OFFSET,
RP23XX_I2C_IC_INTR_STAT_R_RX_FULL,
RP23XX_I2C_IC_INTR_STAT_R_RX_FULL);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
if (priv->error != OK)
@ -492,7 +489,7 @@ static int rp23xx_i2c_send(struct rp23xx_i2cdev_s *priv, int last)
& RP23XX_I2C_IC_STATUS_TFNF))
;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
wd_start(&priv->timeout, I2C_TIMEOUT,
rp23xx_i2c_timeout, (wdparm_t)priv);
i2c_reg_write(priv, RP23XX_I2C_IC_DATA_CMD_OFFSET,
@ -504,7 +501,7 @@ static int rp23xx_i2c_send(struct rp23xx_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, RP23XX_I2C_IC_INTR_MASK_OFFSET,
RP23XX_I2C_IC_INTR_STAT_R_TX_EMPTY,
RP23XX_I2C_IC_INTR_STAT_R_TX_EMPTY);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
nxsem_wait_uninterruptible(&priv->wait);
return 0;

18
arch/arm/src/stm32/stm32_i2c.c
View file

@ -66,7 +66,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -244,7 +244,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion lock */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -382,7 +381,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -416,7 +414,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -450,7 +447,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -556,7 +552,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
uint32_t regval;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -572,8 +568,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32_I2C_DYNTIMEO
@ -592,8 +586,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -610,7 +602,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
regval &= ~I2C_CR2_ALLINTS;
stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1215,7 +1207,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
#endif
/* Receive a byte */
@ -1231,7 +1223,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
}
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
#endif
}
else

14
arch/arm/src/stm32/stm32f40xxx_i2c.c
View file

@ -65,7 +65,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -274,7 +274,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -412,7 +411,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -455,7 +453,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
# ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
# endif
@ -496,7 +493,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
# ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
# endif
@ -609,7 +605,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
uint32_t regval;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -625,8 +621,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32_I2C_DYNTIMEO
@ -645,8 +639,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -663,7 +655,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
regval &= ~I2C_CR2_ALLINTS;
stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else

19
arch/arm/src/stm32f0l0g0/stm32_i2c.c
View file

@ -226,7 +226,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include <nuttx/kmalloc.h>
@ -396,7 +396,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -509,7 +508,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -545,7 +543,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -581,7 +578,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -617,7 +613,6 @@ static struct stm32_i2c_priv_s stm32_i2c4_priv =
.config = &stm32_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -784,7 +779,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -801,8 +796,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
@ -821,8 +814,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -837,7 +828,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1739,7 +1730,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1756,7 +1747,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

19
arch/arm/src/stm32f7/stm32_i2c.c
View file

@ -238,7 +238,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include <nuttx/kmalloc.h>
@ -438,7 +438,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -555,7 +554,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -593,7 +591,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -631,7 +628,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -669,7 +665,6 @@ static struct stm32_i2c_priv_s stm32_i2c4_priv =
.config = &stm32_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -825,7 +820,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -842,8 +837,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
@ -862,8 +855,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -878,7 +869,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1778,7 +1769,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1795,7 +1786,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

19
arch/arm/src/stm32h5/stm32_i2c.c
View file

@ -209,7 +209,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include <nuttx/kmalloc.h>
@ -391,7 +391,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -507,7 +506,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -546,7 +544,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -585,7 +582,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -624,7 +620,6 @@ static struct stm32_i2c_priv_s stm32_i2c4_priv =
.config = &stm32_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -790,7 +785,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -807,8 +802,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
@ -827,8 +820,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -843,7 +834,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1954,7 +1945,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1971,7 +1962,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

19
arch/arm/src/stm32h7/stm32_i2c.c
View file

@ -207,7 +207,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include <nuttx/kmalloc.h>
@ -394,7 +394,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -508,7 +507,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -545,7 +543,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -582,7 +579,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -619,7 +615,6 @@ static struct stm32_i2c_priv_s stm32_i2c4_priv =
.config = &stm32_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -785,7 +780,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -802,8 +797,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32H7_I2C_DYNTIMEO
@ -822,8 +815,6 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -838,7 +829,7 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1741,7 +1732,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1758,7 +1749,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

19
arch/arm/src/stm32l4/stm32l4_i2c.c
View file

@ -254,7 +254,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -415,7 +415,6 @@ struct stm32l4_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -537,7 +536,6 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv =
.config = &stm32l4_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -574,7 +572,6 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv =
.config = &stm32l4_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -611,7 +608,6 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv =
.config = &stm32l4_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -648,7 +644,6 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv =
.config = &stm32l4_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -819,7 +814,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -836,8 +831,6 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32L4_I2C_DYNTIMEO
@ -856,8 +849,6 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -872,7 +863,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1931,7 +1922,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1948,7 +1939,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

19
arch/arm/src/stm32u5/stm32_i2c.c
View file

@ -255,7 +255,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -416,7 +416,6 @@ struct stm32_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -538,7 +537,6 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
.config = &stm32_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -575,7 +573,6 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -612,7 +609,6 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -649,7 +645,6 @@ static struct stm32_i2c_priv_s stm32_i2c4_priv =
.config = &stm32_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -820,7 +815,7 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -837,8 +832,6 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32U5_I2C_DYNTIMEO
@ -857,8 +850,6 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -873,7 +864,7 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1981,7 +1972,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1998,7 +1989,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

17
arch/arm/src/stm32wb/stm32wb_i2c.c
View file

@ -172,7 +172,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -327,7 +327,6 @@ struct stm32wb_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -449,7 +448,6 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv =
.config = &stm32wb_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -486,7 +484,6 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv =
.config = &stm32wb_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -657,7 +654,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable I2C interrupts */
@ -674,8 +671,6 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv)
priv->intstate = INTSTATE_WAITING;
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32WB_I2C_DYNTIMEO
@ -694,8 +689,6 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -710,7 +703,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv)
stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else
@ -1604,7 +1597,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv)
*/
#ifdef CONFIG_I2C_POLLED
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
#endif
/* Receive a byte */
@ -1621,7 +1614,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv)
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
#endif
}
else

21
arch/arm/src/tiva/common/tiva_i2c.c
View file

@ -37,7 +37,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -198,7 +198,6 @@ struct tiva_i2c_priv_s
const struct tiva_i2c_config_s *config;
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t waitsem; /* Interrupt wait semaphore */
#endif
@ -324,7 +323,6 @@ static const struct tiva_i2c_config_s tiva_i2c0_config =
static struct tiva_i2c_priv_s tiva_i2c0_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -352,7 +350,6 @@ static const struct tiva_i2c_config_s tiva_i2c1_config =
static struct tiva_i2c_priv_s tiva_i2c1_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -380,7 +377,6 @@ static const struct tiva_i2c_config_s tiva_i2c2_config =
static struct tiva_i2c_priv_s tiva_i2c2_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -408,7 +404,6 @@ static const struct tiva_i2c_config_s tiva_i2c3_config =
static struct tiva_i2c_priv_s tiva_i2c3_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -436,7 +431,6 @@ static const struct tiva_i2c_config_s tiva_i2c4_config =
static struct tiva_i2c_priv_s tiva_i2c4_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -464,7 +458,6 @@ static const struct tiva_i2c_config_s tiva_i2c5_config =
static struct tiva_i2c_priv_s tiva_i2c5_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -492,7 +485,6 @@ static const struct tiva_i2c_config_s tiva_i2c6_config =
static struct tiva_i2c_priv_s tiva_i2c6_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -520,7 +512,6 @@ static const struct tiva_i2c_config_s tiva_i2c7_config =
static struct tiva_i2c_priv_s tiva_i2c7_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -548,7 +539,6 @@ static const struct tiva_i2c_config_s tiva_i2c8_config =
static struct tiva_i2c_priv_s tiva_i2c8_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -576,7 +566,6 @@ static const struct tiva_i2c_config_s tiva_i2c9_config =
static struct tiva_i2c_priv_s tiva_i2c9_priv =
{
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
#endif
@ -745,7 +734,7 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Enable the master interrupt. The I2C master module generates an
* interrupt when a transaction completes (either transmit or receive),
@ -761,8 +750,6 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv)
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_TIVA_I2C_DYNTIMEO
@ -783,8 +770,6 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv)
tiva_i2c_getreg(priv, TIVA_I2CM_RIS_OFFSET));
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -799,7 +784,7 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv)
tiva_i2c_putreg(priv, TIVA_I2CM_IMR_OFFSET, 0);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
#else

19
arch/arm/src/xmc4/xmc4_i2c.c
View file

@ -35,7 +35,7 @@
#include <arch/board/board.h>
#include <nuttx/mutex.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "chip.h"
@ -122,9 +122,8 @@ struct xmc4_i2cdev_s
uint32_t sda_gpio; /* GPIO config of SDA */
uint32_t scl_gpio; /* GPIO config of SCL */
mutex_t lock; /* Only one thread can access at a time */
spinlock_t spinlock; /* Spinlock */
int refs; /* Reference count */
mutex_t lock; /* Only one thread can access at a time */
int refs; /* Reference count */
};
/*****************************************************************************
@ -199,7 +198,6 @@ static struct xmc4_i2cdev_s g_i2c0 =
.scl_gpio = GPIO_I2C0_SCL, /* See i2c_set_input_source */
.frequency = (uint32_t)I2C_DEFAULT_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.refs = 0,
};
#endif
@ -216,7 +214,6 @@ static struct xmc4_i2cdev_s g_i2c1 =
.scl_gpio = GPIO_I2C1_SCL, /* See i2c_set_input_source */
.frequency = (uint32_t)I2C_DEFAULT_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.refs = 0,
};
#endif
@ -233,7 +230,6 @@ static struct xmc4_i2cdev_s g_i2c2 =
.scl_gpio = GPIO_I2C2_SCL, /* See i2c_set_input_source */
.frequency = (uint32_t)I2C_DEFAULT_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.refs = 0,
};
#endif
@ -250,7 +246,6 @@ static struct xmc4_i2cdev_s g_i2c3 =
.scl_gpio = GPIO_I2C3_SCL, /* See i2c_set_input_source */
.frequency = (uint32_t)I2C_DEFAULT_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.refs = 0,
};
#endif
@ -267,7 +262,6 @@ static struct xmc4_i2cdev_s g_i2c4 =
.scl_gpio = GPIO_I2C4_SCL, /* See i2c_set_input_source */
.frequency = (uint32_t)I2C_DEFAULT_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.refs = 0,
};
#endif
@ -284,7 +278,6 @@ static struct xmc4_i2cdev_s g_i2c5 =
.scl_gpio = GPIO_I2C5_SCL, /* See i2c_set_input_source */
.frequency = (uint32_t)I2C_DEFAULT_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
.refs = 0,
};
#endif
@ -824,7 +817,7 @@ static int i2c_transfer(struct i2c_master_s *dev,
/* Enter critical section to avoid interrupts during i2c transfert */
irqstate_t state = spin_lock_irqsave(&priv->spinlock);
irqstate_t state = enter_critical_section();
for (int i = 0; i < count; i++)
{
@ -844,8 +837,8 @@ static int i2c_transfer(struct i2c_master_s *dev,
}
else
{
spin_unlock_irqrestore(&priv->spinlock, state);
i2cerr("Can't update frequency between Start & Stop symbols\n");
leave_critical_section(state);
nxmutex_unlock(&priv->lock);
return -EINVAL;
}
@ -933,7 +926,7 @@ static int i2c_transfer(struct i2c_master_s *dev,
}
}
spin_unlock_irqrestore(&priv->spinlock, state);
leave_critical_section(state);
nxmutex_unlock(&priv->lock);
return ret;
}

24
arch/mips/src/pic32mz/pic32mz_i2c.c
View file

@ -36,7 +36,7 @@
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -189,7 +189,6 @@ struct pic32mz_i2c_priv_s
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
@ -338,7 +337,6 @@ static struct pic32mz_i2c_priv_s pic32mz_i2c1_priv =
.config = &pic32mz_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -371,7 +369,6 @@ static struct pic32mz_i2c_priv_s pic32mz_i2c2_priv =
.config = &pic32mz_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -404,7 +401,6 @@ static struct pic32mz_i2c_priv_s pic32mz_i2c3_priv =
.config = &pic32mz_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -437,7 +433,6 @@ static struct pic32mz_i2c_priv_s pic32mz_i2c4_priv =
.config = &pic32mz_i2c4_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -470,7 +465,6 @@ static struct pic32mz_i2c_priv_s pic32mz_i2c5_priv =
.config = &pic32mz_i2c5_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -688,7 +682,7 @@ pic32mz_i2c_sem_waitdone(struct pic32mz_i2c_priv_s *priv)
irqstate_t flags;
int ret;
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
/* Signal the interrupt handler that we are waiting */
@ -696,8 +690,6 @@ pic32mz_i2c_sem_waitdone(struct pic32mz_i2c_priv_s *priv)
do
{
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_PIC32MZ_I2C_DYNTIMEO
@ -716,8 +708,6 @@ pic32mz_i2c_sem_waitdone(struct pic32mz_i2c_priv_s *priv)
break;
}
flags = spin_lock_irqsave(&priv->spinlock);
}
/* Loop until the interrupt level transfer is complete. */
@ -733,7 +723,7 @@ pic32mz_i2c_sem_waitdone(struct pic32mz_i2c_priv_s *priv)
up_disable_irq(priv->config->ev_irq);
up_disable_irq(priv->config->er_irq);
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return ret;
}
@ -992,7 +982,7 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv)
if (priv->dcnt > 1)
{
#ifdef CONFIG_I2C_POLLED
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
#endif
*priv->ptr++ = pic32mz_i2c_receivebyte(priv);
@ -1009,7 +999,7 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv)
}
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
#endif
/* Go back and re-enable read mode to handle the rest of
* the data.
@ -1024,7 +1014,7 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv)
else
{
#ifdef CONFIG_I2C_POLLED
irqstate_t flags = spin_lock_irqsave(&priv->spinlock);
irqstate_t flags = enter_critical_section();
#endif
*priv->ptr++ = pic32mz_i2c_receivebyte(priv);
@ -1040,7 +1030,7 @@ static int pic32mz_i2c_isr_process(struct pic32mz_i2c_priv_s *priv)
}
#ifdef CONFIG_I2C_POLLED
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
#endif
priv->process_state = PROCESS_STATE_FETCH_NEXT;
}

9
arch/risc-v/src/common/espressif/esp_i2c.c
View file

@ -40,7 +40,7 @@
#include <sys/time.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -218,7 +218,6 @@ struct esp_i2c_priv_s
const struct esp_i2c_config_s *config;
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
@ -350,7 +349,6 @@ static struct esp_i2c_priv_s esp_i2c0_priv =
.config = &esp_i2c0_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -401,7 +399,6 @@ static struct esp_i2c_priv_s esp_i2c1_priv =
.config = &esp_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -1121,7 +1118,7 @@ static int esp_i2c_reset(struct i2c_master_s *dev)
DEBUGASSERT(priv->refs > 0);
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
esp_i2c_reset_fsmc(priv);
@ -1134,7 +1131,7 @@ static int esp_i2c_reset(struct i2c_master_s *dev)
priv->bytes = 0;
priv->ready_read = false;
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return OK;
}

8
arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c
View file

@ -40,7 +40,7 @@
#include <sys/time.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -223,7 +223,6 @@ struct esp32c3_i2c_priv_s
const struct esp32c3_i2c_config_s *config;
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
@ -334,7 +333,6 @@ static struct esp32c3_i2c_priv_s esp32c3_i2c0_priv =
.config = &esp32c3_i2c0_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -1100,7 +1098,7 @@ static int esp32c3_i2c_reset(struct i2c_master_s *dev)
DEBUGASSERT(priv->refs > 0);
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
esp32c3_i2c_reset_fsmc(priv);
@ -1113,7 +1111,7 @@ static int esp32c3_i2c_reset(struct i2c_master_s *dev)
priv->bytes = 0;
priv->ready_read = false;
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return OK;
}

9
arch/xtensa/src/esp32s2/esp32s2_i2c.c
View file

@ -39,7 +39,7 @@
#include <nuttx/arch.h>
#include <nuttx/clock.h>
#include <nuttx/spinlock.h>
#include <nuttx/irq.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
@ -212,7 +212,6 @@ struct esp32s2_i2c_priv_s
const struct esp32s2_i2c_config_s *config;
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
spinlock_t spinlock; /* Spinlock */
#ifndef CONFIG_I2C_POLLED
sem_t sem_isr; /* Interrupt wait semaphore */
@ -321,7 +320,6 @@ static struct esp32s2_i2c_priv_s g_esp32s2_i2c0_priv =
.config = &g_esp32s2_i2c0_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -358,7 +356,6 @@ static struct esp32s2_i2c_priv_s g_esp32s2_i2c1_priv =
.config = &g_esp32s2_i2c1_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
.spinlock = SP_UNLOCKED,
#ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
@ -1123,7 +1120,7 @@ static int i2c_reset(struct i2c_master_s *dev)
DEBUGASSERT(dev != NULL);
DEBUGASSERT(priv->refs > 0);
flags = spin_lock_irqsave(&priv->spinlock);
flags = enter_critical_section();
i2c_reset_fsmc(priv);
@ -1136,7 +1133,7 @@ static int i2c_reset(struct i2c_master_s *dev)
priv->bytes = 0;
priv->ready_read = false;
spin_unlock_irqrestore(&priv->spinlock, flags);
leave_critical_section(flags);
return OK;
}