reason:
We decouple semcount from business logic
by using an independent counting variable,
which allows us to remove critical sections in many cases.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
In kernel mode, sighand_test() may failed.
because nxsig_unmask_pendingsignal may change tcb->xcp.regs,and we should update return value(regs).
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In up_addrenv_kmap_pages, the MMU_MT_NORMAL_FLAGS are needed for the MMU
mappings in order for the memory & caches to function normally
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This moves ARM_HAVE_NEON from QEMU ARM family level down to the
processor level as not all processors have it (e.g. Cortex R5).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
It was dis overed during debug of the ethernet driver that the EMAC base was incorrect. After examination, it was determined that ICACHE and DCACHE also had incorrect base addresses. This commit fixes the base addresses according to the reference manual.
Summary:
This commit removes the riscv_mhartid function and replaces all its
usages with up_cpu_index. The functionality is consolidated into
up_cpu_index which provides a more consistent API for getting the
current CPU/hart ID across different execution modes (machine/supervisor).
Impact:
- Removes riscv_mhartid.S and its references from build systems
- Updates all arch-specific code to use up_cpu_index instead
- Adds more detailed documentation for up_cpu_index behavior
- Changes the implementation of up_cpu_index to use percpu scratch
register in supervisor mode
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Summary:
- Separated CPU index functionality from CPU ID mapping configuration
- Moved CPU ID mapping functions to new riscv_cpuidmap.c file
- Made up_cpu_index() implementation dependent on ARCH_USE_S_MODE
- Updated build system to handle new file organization
Impact:
- Improves code organization by separating concerns between basic CPU index
functionality and advanced CPU ID mapping features
- Makes CPU index functionality available independently of CPU ID mapping
- Reduces conditional compilation complexity in header files
- Better aligns with RISC-V architecture modes (M-mode vs S-mode)
Testing:
GitHub CI and local testing
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Sumamry:
Adjust VIRT_FLASH_PSECTION from 0x00000000-0x08000000 -> 0x00600000-0x08000000
The above changes avoid the problem of directly restarting when the process accesses/executes at address 0x0 without causing assert
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
It will be used to distinguish between hardware KASan and software KASan. Hardware KASan does not need to use plug-in
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
| commit c96b8cdfdd
| Author: hujun5 <hujun5@xiaomi.com>
| Date: Mon Dec 23 16:59:20 2024 +0800
|
| use small lock in following files:
Signed-off-by: chao an <anchao.archer@bytedance.com>
reason:
In AMP mode, we can also use SGI as an inter-core interrupt,
and ensure that arm_gic0_initialize is called only once.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When assembly code calls a C function, it needs to save the context. After enabling KASAN, the inserted __asan_load8_noabort function uses the rsi register, causing the value of rsi in the interrupt handler to be modified, which results in an incorrect interrupt number.
Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
This guards use of `-r` in LDELFFLAGS in risc-v common/Toolchain.defs so
that it is only used when BINFMT_ELF_RELOCATABLE is selected.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Added support for using timers with ADCs. Updated Kconfig to support TRGO2, although driver support for TRGO and TRGO2 not developed yet. Updated hardware/stm32_tim.h with missing CCER bits needed for compilation.
Changed the LLVM architecture type from thumbv7 to thumbv7a in
Toolchain.defs to better match the ARMv7-A architecture specification.
This change ensures proper code generation and optimization for
Cortex-A series processors when using the Thumb instruction set.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Added LLVM-specific configuration variables to ARM architecture CMake files:
- LLVM_ARCHTYPE for architecture variant (thumbv6m, thumbv7a, etc)
- LLVM_CPUTYPE for CPU target (cortex-m0, cortex-a5, etc)
- LLVM_ABITYPE for ABI (eabi/eabihf)
These changes enable LLVM/Clang toolchain support while maintaining
compatibility with existing GCC configurations. The LLVM variables
are set based on the same architecture/CPU/FPU configurations used
for GCC flags.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Reformatted the FPU options table to use a clearer markdown-style table format
with proper alignment and column headers. Added visual separators (~~~) to make
the table stand out from surrounding code. Improved consistency in column widths
and fixed line wrapping for better readability.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Used the STM32H7 as a reference.
Removed APB enabling from stm32h5xx_rcc.c. This is done in timer initialization, like STM32H7.
Also removed LPTIM. Will add later.
tim_lowerhalf: Timers 9, 10, and 11 removed. Timers 15,16, and 17 added.
Removed low-power timers from Kconfig. Not implemented yet.
Style Updates
Added stm32_tim_enable and stm32_tim_disable to Timer operations.
The method is the same as the method of saving the current DAIF state of the thread
It will pave the way for the future implementation of hwasan's memory management
Allows each thread to independently control the mte switch function
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
- Replace direct string comparisons with regex pattern matching for ARCHCPUEXTFLAGS
- Change from using LLVM_CPUFLAGS list to setting LLVM_CPUTYPE directly
- Simplify CPU type detection logic while maintaining same functionality
- Use more consistent string variable naming convention
This change makes the CPU type detection more flexible and maintainable
while keeping the same behavior for supported RISC-V configurations.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit cleans up redundant header file includes throughout the codebase.
The changes include:
- Removing duplicate #include directives that were present in the same file
- Consolidating includes that were split across multiple lines unnecessarily
- Removing unused includes that were no longer needed
- Fixing some formatting issues with includes
The changes improve code organization and maintainability by:
- Reducing unnecessary dependencies
- Making include dependencies more explicit
- Following consistent include patterns
- Removing dead code
No functional changes are made - this is purely a code cleanup commit.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Raise compilation error when I2C configuration is invalid.
It's better to catch invalid clock configuration during compilation instead of
producing binary that doesn't work as expected anyway.
Signed-off-by: raiden00pl <raiden00@railab.me>
Use findstring instead of direct equality checks for LLVM_CPUTYPE
conditions to better handle ARCHCPUEXTFLAGS that may contain additional
ISA extensions. This makes the CPU type detection more robust when
dealing with extended instruction sets while still ensuring the required
base ISA extensions are present.
For example, ARCHCPUEXTFLAGS="imc_zicsr_zifencei" will now correctly
match as sifive-e20 rather than failing the exact match check.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
