ADC peripheral can be configured also for PWM trigger, so the ifdef
should depend only on CONFIG_SAMV7_AFEC_SWTRIG. Also handle the
situation when ANIOC_TRIGGER is called and the peripheral is not
configured for SW trigger (but the other one may be, so config option
is set).
Trigger values saved to the private structure are also changed to
enums for better code clarity.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
reason:
In x86_64, tcb->xcp.regs is always valid, and we obtain the location
where the context is saved through irq_xcp_regs every time an interrupt occurs.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
reason:
1 Accelerated the implementation of sched_lock, remove enter_critical_section in sched_lock and
only enter_critical_section when task scheduling is required.
2 we add sched_lock_wo_note/sched_unlock_wo_note and it does not perform instrumentation logic
Signed-off-by: hujun5 <hujun5@xiaomi.com>
add sim_rpmsg_port_uart.c to verify the rpmsg port uart wrapper layer,
The physical transport layer could be:
1. SIM_RAM_UART(current)
2. SIM_UART(through "socat" virtual "/dev/pts/*", "socat" could monitor the bus data)
Signed-off-by: chao an <anchao.archer@bytedance.com>
This removes the need to call nxsched_self upon exception return. Later
with a bit of added logic, it is possible to use tp in kernel to store and
read the current tcb.
Note: setting tp in riscv_restorecontext is too late for this, as
this_task() points to the (next) ready-to-run task, thus tp should be
updated when the rtr list is updated (via up_update_task, which does not
exist for risc-v yet)
Set the LOCKED bit when the final ddr segmentatition is
in place. Otherwise the system is prone to potential
security issues if the config is altered later. Once the
LOCKED bit is set, the register may no longer be changed.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Corrections to CA training verify step. The original copied from HSS didn't
make sense in all aspects:
- The check is not per lane, so it should be out of the "for (lane_sel" loop.
- The check wasn't proper. The expected outcome is just a vector of increasing numbers
separated enough
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
After read training, check also that the eye is centered properly. Sometimes
after the training the width is long enough, but it is not centered.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Interrupts on MPFS platform are currently served on the hart, on
which the up_enable_irq was called.
Call to up_disable_irq may execute on different hart than on which
the up_enable_irq was executed. In this case the interrupt is not
disabled currently.
While there is nothing fancy (irq affinity control or such), an
easy way to fix this is to simply disable the irq on all harts.
This also changes the prototypes of mpfs_plic_get_iebase and
mpfs_plic_get_claimbase to get the hart id as an argument, in
order to accomplish this.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
common/espressif/esp_pcnt.c: In function 'esp_pcnt_isr_default':
common/espressif/esp_pcnt.c:396:41: warning: passing argument 1 of 'spin_lock_irqsave' makes pointer from integer without a cast [-Wint-conversion]
396 | flags = spin_lock_irqsave(unit->lock);
| ~~~~^~~~~~
| |
| spinlock_t {aka unsigned char}
In file included from common/espressif/esp_pcnt.c:44:
/home/hujun5/下载/vela_sim/nuttx/include/nuttx/spinlock.h:507:55: note: expected 'volatile spinlock_t *' {aka 'volatile unsigned char *'} but argument is of type 'spinlock_t' {aka 'unsigned char'}
507 | irqstate_t spin_lock_irqsave(FAR volatile spinlock_t *lock)
| ~~~~~~~~~~~~~~~~~~~~~^~~~
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This follows the formula in the "Startup Delay" section of the
datasheets, where `BOARD_XOSC_STARTUPDELAY` is the time in milliseconds,
which is then multiplied by the clock fequency in kHz, divided by 256
cycles, and rounded up.
This differs from `pico-sdk`, which just multiplied the value of the
expression it previously used by a `PICO_XOSC_STARTUP_DELAY_MULTIPLIER`.
This seems less correct, though it should be essentially the same except
rounding. (`BOARD_XOSC_STARTUPDELAY_MULTIPLIER` also wouldn't fit nicely
the way the `#define`s are aligned.)
This sets `BOARD_XOSC_STARTUPDELAY` to `1` for all boards, so this will
produce the same output and not change behavior.
Signed-off-by: Ian Douglas Scott <ian@iandouglasscott.com>
Previously this used a hard-coded value of 12 MHz, but this presumably
should use `BOARD_XOSC_FREQ`. Similarly to how it is done in pico-sdk.
It looks like all boards are currently defined to use 12 MHz XOSC
clocks, so this won't change behavior with any of them.
Signed-off-by: Ian Douglas Scott <ian@iandouglasscott.com>
No reason to keep asking for these over and over. Also fix bumping
the CPU booted counter when SBI is enabled.
Must also read g_hart_use_sbi before bumping the CPU booted counter.
This adds support for QEMU Cortex-R5 virtual processor on existing QEMU
Cortex-A7 code base with profile support in `armv7-r/` and `armv7-a/`.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This revise armv7-r/ header files needed to support QEMU cortex-r5
virtual process for armv7-r family.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This fixes compilation error:
```
/tmp/nuttx/arch/arm/src/armv7-r/gic.h:699:17: error:
'GIC_ICDSGIR_NSATT_GRP1' undeclared; did you mean 'GIC_ICDSGIR_NSATT'?
```
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
copied over files, not modified properly yet
Squashing lots of define errors to get ethernet.c working
quick path rename
Fix STM32_EMAC_BASE (and ICACHE/DCACHE Bases). Enable ETH, ETHTX, and ETHRX with CONFIG_STM32H5_ETHMAC (like H7 does).
Fixed stm32_get_uniqueid
Previously, an exception occurred as a result of calling this function. The problem turned out to be this line: uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i);. Dereferencing a 32-bit register as a 8-bit register seemed to be causing this issue. I think this function is better anyway, fewer register accesses and loop iterations.
Turn on SBS peripheral when using Ethernet
The SBS peripheral is required to be turned on because the ETH_SEL_PHY bits need to be set. Without turning this on, RMII mode is not possible. MII may not work either.
Style Updates
This moves ARM_HAVE_PSCI selection to virtual processor level as
armv7-r chips like Cortex-R5 doesn't have it.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
