Following the https://github.com/apache/nuttx/pull/14741, add the
`ARCH_HAVE_RAMFUNCS` config to ESP32-C6 and ESP32-H2 to suppress
the RWX memory region warning.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Add basic support for RA4M1.
The following perpheral are added:
* GPIO
* SCI (UART)
* Clock (Just internal clock - HOCO)
Signed-off-by: leocafonso <leocafonso@gmail.com>
Update the wireless symbols from ESP32_* to ESPRESSIF_* for using common layer.
Remove ESP32 specific WiFi files and edit build system to use common layer.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, switch the pin mode to I2C at the end of the i2c
initialization function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
During I2C communication between non-Spresense devices is performed,
the I2C bus may freeze after initialization of the Spresense I2C.
As a workaround, add clock gating process and disable GPIO input
to the I2C reset function.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
This commit disables optimization that alters ESP32C6 interrupt registers.
Without this optimization, the USB serial driver does not work properly.
This is a temporary workaround until a proper fix is found.
Signed-off-by: Felipe Moura de Oliveira <moura.fmo@gmail.com>
DTE (dead time enable) is the 17th bit in CMRx (channel mode) register.
Function pwm_set_polarity did however read and write this register as
16 bit large, therefore dead time generation was always disabled.
This fixes the issue, pwm_set_polarity now reads the register as 32
large.
Also set the initial value of CMRx correctly in pwm_setup().
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit implements re-enabling the cache before the exception
handler for ESP32-S3 and removes unnecessary checks (cache should
always be re-enabled during an exception handler and disabled again
after processed, except for ESP32-S3 that implements no recoverable
exceptions).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This adds configuration option for every fault input, that can be
latched (kept even after the input value is below the threshold) or
volatile (PWM is automatically enabled once the output polarity goes
back to the normal state).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- Move PLIC interrupt enable and disable functions into mpfs_plic.c
- When enabling interrupts, always clear pending interrupt
- Remove race conditions between irq enable/disable by adding spinlock
- An interrupt may trigger on one hart in the middle of enabling the interrupts - then the interrupt
handler might call up_disable_irq.
A pending interrupt would trigger immediately when enabling the interrupt source,
but this is not expected. The interrupt source is level sensitive, so it should
only trigger if the source is active at the time when it is enabled. Not if it
was active sometime in the past.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
If CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE is defined, the coremmc driver
uses SD card's dat0 line to detect whether the sd card is still busy.
This requires that the FPGA design using coremmc block wires dat0 line
to some fabric irq; and configures CONFIG_MPFS_COREMMC_WRCOMPLETE_IRQNUM
to point to that. Default for the irq number is 4. (MSS_INT_F2M_4)
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
This adds minimal support for NXP MCX-N236 CPU. Peripherals supported are:
- GPIO
- PINMUX
- CLOCK
- LPUART
An example board, FRDM-MCXN236 is also added, with a basic profile that
boots into nsh.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
From Polarfire SoC TRM:
6.5.8 Interrupt Completion
To signal the completion of executing an interrupt handler, the processor core writes the received interrupt ID to the
Claim/Complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that
target. If the completion ID does not match an interrupt source that is currently enabled for the target, the completion
is ignored.
The last paragraph clearly states that IRQ completion does not work for
sources that have been disabled -> must ACK the completion before disable.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
This commit allows placing .bss data into the external PSRAM.
Previously, the PSRAM was fully allocated to the heap memory only
and now part of it can be used to allocate .bss data freeing the
internal memory.
on ESP32, cpuint was allocated when register wdt handler, but not
deallocated when unregister, which cause debug assert when checking
`DEBUGASSERT((*freeints & bitmask) == 0)`, so set cpuint to initial value
after deallocate.
The same issue on ESP32s3 has been fixed by PR#15433
Update the wireless symbols from ESP32S3_* to ESPRESSIF_* for using common layer.
Remove ESP32S3 specific WiFi files and edit build system to use common layer.
Instead of enabling an interrupt on the calling hart, enable it on every
hart. This should balance the interrupt load some, especially in cases
where the interrupt source is enabled only once (which will almost
certainly happen on CPU 0 only).
Signed-off-by: Ville Juven <ville.juven@unikie.com>
When the l1entry first add to shm, mssing l1entry add.
shm mmu flags should use udata flags.
l1entry record in shm[] and should not use ~SECTION_MASK
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
chip/sam_1wire.c:921:7: warning: implicit declaration of function 'sam_usart0_enableclk' [-Wimplicit-function-declaration]
921 | sam_usart0_enableclk();
The same warning applied for other uart/usart peripherals configured
as 1 wire.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds support to TIOCGICOUNT for STM32, this way a
userspace application can collect information about UART errors.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
