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arch/risc-v: improve nested interrupt assertion on riscv_doirq

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Filipe Cavalcanti 2025-02-14 15:40:59 -03:00 • committed by Alan C. Assis
parent b417495284
commit becba7153f
1 changed files with 15 additions and 4 deletions
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19
arch/risc-v/src/common/riscv_doirq.c
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@ -88,13 +88,24 @@ uintreg_t *riscv_doirq(int irq, uintreg_t *regs)
(*running_task)->xcp.regs = regs;
}
/* Nested interrupts are not supported */
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
*
* Nested interrupts are not supported. But an exception may occur while
* processing an interrupt. In this case, current_regs will be non-NULL.
*/
DEBUGASSERT(!up_interrupt_context());
DEBUGASSERT(((irq > RISCV_MAX_EXCEPTION) && !up_interrupt_context()) ||
(irq <= RISCV_MAX_EXCEPTION));
/* Set irq flag */
/* Don't override current regs if it is already set (which is true if
* we were in a interrupt handler).
*/
up_set_interrupt_context(true);
if (!up_interrupt_context())
{
up_set_interrupt_context(true);
}
/* Deliver the IRQ */