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Fix memory map for EMAC, ICACHE, and DCACHE.

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It was dis overed during debug of the ethernet driver that the EMAC base was incorrect. After examination, it was determined that ICACHE and DCACHE also had incorrect base addresses. This commit fixes the base addresses according to the reference manual.
This commit is contained in:
Kyle Wilson 2025-01-14 08:13:57 -06:00 • committed by Xiang Xiao
parent d014867766
commit 9701b0f660
1 changed files with 3 additions and 3 deletions
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6
arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h
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@ -126,9 +126,9 @@
#define STM32_MPC_WM_BKPRAM_BASE 0x40036400
#define STM32_GTZC1_BASE 0x40032400
#define STM32_DCACHE_BASE 0x40030400
#define STM32_ICACHE_BASE 0x40031400
#define STM32_EMAC_BASE 0x40030400
#define STM32_DCACHE_BASE 0x40031400
#define STM32_ICACHE_BASE 0x40030400
#define STM32_EMAC_BASE 0x40028000
#define STM32_RAMCFG_BASE 0x40026000
#define STM32_FMAC_BASE 0x40023c00
#define STM32_CORDIC_BASE 0x40023800