Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8721F (amebagreen2). The driver is chip-agnostic and reads only
per-chip macros from ameba_rtc_chip.h; RTL8721F differs from amebadplus
only in the RTC interrupt vector (RTL8721F_IRQ_RTC, vector 41). The
APBPeriph_RTC masks and RTC_BASE_YEAR (1900) are identical across all
current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8721f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8720F. The driver is chip-agnostic and reads only per-chip macros
from ameba_rtc_chip.h; RTL8720F differs from amebadplus only in the RTC
interrupt vector (RTL8720F_IRQ_RTC, vector 33). The APBPeriph_RTC masks
and RTC_BASE_YEAR (1900) are identical across all current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8720f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Expose the Ameba on-chip RTC as a NuttX date/time RTC at /dev/rtc0
(rdtime/settime) with a single one-shot alarm (setalarm/rdalarm/
cancelalarm/setrelative) that fires the RTC interrupt and the upper-half
callback. The same hardware also backs the arch date/time RTC hooks
(up_rtc_initialize/getdatetime/settime, g_rtc_enabled) so the NuttX
system time is seeded from it.
The driver sits on the SDK fwlib RTC API (mirrored structures + local
externs, no vendor headers pulled into the NuttX include world). The
fwlib RTC API lives in the RAM source ameba_rtc.c, so it is added to the
board fwlib build under CONFIG_AMEBA_RTC. The hardware keeps a year plus
a day-of-year (no month/day register); the driver bridges that to the
NuttX month/day calendar with the libc UTC routines (timegm/gmtime_r),
which is exact and reversible.
The only per-chip fact -- the RTC interrupt vector -- lives in the
per-chip ameba_rtc_chip.h; the shared driver is never edited for a new
Ameba chip. A configs/rtc profile (examples/alarm) is added for
verification.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Replace the enumerated STM32U3/U5 chip conditions in the common M33
source lists and the RCC dispatch header with a single STM32_COMMON_M33
symbol, following the existing STM32_COMMON_* convention.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3 and U5 family-local Cortex-M33 RCC headers to
stm32_rcc_m33.h and dispatch to that private name for the two families
in the common RCC header.
This lets the shared M33 USART implementation use one include name
while RCC registers and clock definitions remain family-local. Extend
the stm32_ports.rst naming rules with the M33 header, source, and
Kconfig symbol conventions.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the shared U3/U5 heap allocator to stm32_allocateheap_m33_v1.c
and keep its direct family selection in Make and CMake.
Size the primary region from a now-mandatory STM32_PRIMARY_SRAM_SIZE,
provided by the U5 chip header as the SRAM1 size, and drop the
U5-specific SRAM bank descriptions so the allocator carries no family
conditionals.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the shared U3/U5 reset handler to stm32_start_m33_v1.c and keep
its direct family selection in Make and CMake.
Include stm32_userspace.h only under CONFIG_BUILD_PROTECTED and define
the SRAM2 span only when CONFIG_STM32_SRAM2_INIT requests the parity
initialization, so families without SRAM2 parity or userspace support
can use the file unchanged.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the shared U3/U5 USART sources to stm32_serial_m33_v3.c and
stm32_lowputc_usart_m33_v3.c and gate them with a new
STM32_HAVE_IP_USART_M33_V3 symbol selected by the U3 and U5 peripheral
options. Rename the USART hardware header to stm32_uart_m33_v3.h with
its register map unchanged.
Store each port's RCC enable register and bit in the serial
descriptor, provided by the family RCC headers as
STM32_<port>_FREQUENCY, _RCC_REG and _RCC_EN, so common clock control
needs no family-specific switch. Correct the LPUART1 RX DMA map name
to DMAMAP_LPUART1_RX.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3/U5 GPIO and EXTI sources to stm32_gpio_m33_v1.c and
stm32_exti_gpio_m33_v1.c and gate them with new
STM32_HAVE_IP_GPIO_M33_V1 and STM32_HAVE_IP_EXTI_M33_V1 symbols
selected by the U3 and U5 peripheral options.
Rename the GPIO and EXTI hardware headers to stm32_gpio_m33_v1.h and
stm32_exti_m33_v1.h with their register maps unchanged, dispatch to
them from the common GPIO and EXTI hardware headers by the new IP
symbols, and widen STM32_EXTI_EXTICR_PORT_MASK to the full 8-bit
EXTICR port-select field.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Remove the disabled CONFIG_STM32_SYSTICK_HCLKd8 reload path and the
non-functional clock-source write. SysTick always runs from HCLK on
these devices, so compute the reload value from STM32_HCLK_FREQUENCY
only.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Iterate the NVIC interrupt enable and priority registers from
STM32_IRQ_NEXTINTS instead of dumping a hardcoded U3/U5 register list,
so the helper works unchanged for any interrupt count.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3/U5 idle, NVIC, and SysTick sources to the Cortex-M33 v1
naming convention: stm32_idle_m33_v1.c, stm32_irq_m33_v1.c, and
stm32_timerisr_m33_v1.c, and move them into their own Make and CMake
block, still selected by the direct U3/U5 family condition.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Blank lines only; `git diff --ignore-blank-lines` against the parent is empty.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
MAXMB resets to 0x0f, so OR-ing the intended value into MCR can only ever
raise it. Every configuration with fewer than 16 mailboxes therefore runs with
MAXMB = 15 and FlexCAN arbitrates over mailboxes the driver never initialised:
with the classic payload layout MB14 and MB15 hold power-on contents, and with
a 64-byte CAN FD layout they are past the end of the mailbox RAM region
entirely.
s32k1xx_flexcan.c already does this; carry the same two lines over.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
imxrt_transmit() wrote the caller's deadline into txmb[] before testing
whether it had already passed, and the early return for an expired deadline
then left that deadline behind on a mailbox holding no frame. The next
watchdog expiry finds it, counts a transmit timeout that did not happen, and
writes CAN_TXMB_ABORT into a mailbox the allocator may have handed to a live
frame in the meantime.
Compute the timeout first and store the deadline after the early return.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
imxrt_txtimeout_work() had four defects that together let one expired frame
take the interface down permanently.
It aborted mailbox RXMBCOUNT + mbi while the deadline it consulted belongs to
RXMBCOUNT + 1 + mbi, so every abort landed one mailbox low and mbi == 0 wrote
CAN_TXMB_ABORT into the buffer reserved for the ERR005829 workaround, while
the highest TX mailbox was never aborted at all.
Its expiry test read `now.tv_sec > d.tv_sec || now.tv_usec > d.tv_usec`, which
declares any deadline that crosses a second boundary expired: in that case the
deadline's microsecond field is always the smaller of the two. The `now` it
compared against was a struct timespec cast to a struct timeval, so writing
tv_usec wrote over tv_nsec and tv_sec was whatever the cast happened to line
up with.
imxrt_txdone() cancelled the watchdog but left txmb[].deadline set, so a
retired mailbox looked expired forever and the next watchdog expiry on any
other mailbox aborted whatever frame had since been loaded there.
The walk ran to TXMBCOUNT, which counts the reserved mailbox as well, so its
last iteration addressed mailbox TOTALMBCOUNT - one past the ring, and
mb_address[] one past its end. Only txmb[] never being written that far kept
it in bounds. TXMBRINGSIZE now names the ring size that the rest of the driver
already assumes.
Aborting a frame that is already on the wire raises a bit error, so the
transmit error counter climbs and the node goes error passive. Since
imxrt_txmb_next() only hands out a mailbox above every pending one, a mailbox
left in DATAORREMOTE also pins the allocator at TOTALMBCOUNT and transmit
never recovers.
Measured on an ARK FMU-v6XRT with a DroneCAN GNSS node on the bus, offering
736 frames/s (9% of a 1 Mbit/s bus) from the PX4 uavcan driver: before, the
interface transmitted 0 frames/s with ECR[TXERRCNT] pinned at 128 and
ESR1[FLTCONF] error passive, and stayed dead across a reboot. After, 734
frames/s, 0.1% loss, TXERRCNT 0, error active.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The idle stack area started at _ebss + CONFIG_IDLETHREAD_STACKSIZE *
CONFIG_SMP_NCPUS, so the first CONFIG_SMP_NCPUS stack slots after .bss
were never used - 16MiB on a 4-CPU configuration with a 4MiB idle
stack. Start the area at _ebss and let the heap begin that much
earlier.
The -16 offset is kept: it is what places the AP initial RSP set up in
intel64_head.S below the xcp->regs block that up_cpu_idlestack()
reserves at the top of the same stack. Without it both land on the
same 64-byte slot and the first context save corrupts the AP stack.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
intel64 port explicitly enumerates five idle-stack
addresses and rejects configurations with more than five CPUs.
Store the CPU0 stack top and calculate every CPU stack address
from its index.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
The AP boot path masked RSP with ~XCPTCONTEXT_SIZE, which just clears
whichever bits happen to be set in the size (0x340 -> mask 0xfffffcbf).
That drops RSP by an arbitrary amount and only guarantees 16-byte
alignment, while the XSAVE area in the context needs 64.
Mask with ~(XCPTCONTEXT_ALIGN - 1) instead.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
nxstyle now checks case labels against their enclosing brace, and the
DWC2-derived OTG device drivers align every case label with the switch
brace itself, so any change that touches one of these files fails
checkpatch on hundreds of pre-existing lines.
Indent the switch bodies by two columns as the standard requires and
re-wrap the lines that this pushes past the width limit. Whitespace and
comment re-flow only; no code changes.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Every DWC2-derived USB device driver enables USBSUSP in GINTMSK but not
WKUP, and every one of them ANDs GINTSTS with GINTMSK before dispatch.
The resume handler is therefore unreachable: CLASS_SUSPEND is delivered
on suspend, CLASS_RESUME never is.
For CDC/ACM that is fatal. cdcacm_suspend() calls uart_connected(false),
after which serial.c refuses every open() and write() with -ENOTCONN,
and the cdcacm_resume() that would clear it never runs. On a Linux host
with the default USB autosuspend (power/control=auto, 2000 ms) simply
closing the tty is enough to trip it, and the port stays dead for the
rest of the boot while the device remains enumerated.
Verified on STM32H7 (ARK FMU v6X): before, one host suspend leaves the
CDC/ACM port permanently -ENOTCONN; after, ten forced suspend/resume
cycles all recover with the MAVLink stream intact. The remaining
drivers carry a line-for-line copy of the same initialisation.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Add LPTIM 1, 3, 4, 5 support. Based on STM32H7. setperiod and
setcompare have been made to wait for the auto-reload value to
be applied before returning.
6 is absent since generic stm32 configs for a 6th LPTIM are not
present yet. 2 is absent for no good reason besides maybe
that it's in a different RCC APB register. I am not adding
support last-minute without more testing. The build fails
noisily when LPTIM2 is enabled so the shortcoming is clear.
Corrected some RCC definitions. They are needed for selecting the LPTIMx
clock source. This is not done in the LPTIM driver. It is done
outside and the definitions should ideally be correct for that.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Co-authored-by: Farzan Farhangian <farzanfarhangian@geotab.com>
imxrt_transmit() handed out the lowest free TX mailbox. FlexCAN breaks an
arbitration tie between mailboxes holding equal CAN IDs by taking the lowest
mailbox number, so refilling a just-drained low mailbox while older frames
are still pending in higher ones puts the newer frame on the wire first.
imxrt_txdone_work() re-polls after each individual TX completion, which is
exactly the condition that triggers it.
Every frame of a multi-frame transport transfer carries the same CAN ID, so
this reorders transfers. On a DroneCAN bus the receiver sees a broken toggle
bit and discards the transfer: measured on the wire, a 6-frame message from
an i.MX RT1176 failed 82% of the time, while a node on the same bus running
a different controller was flawless over the same capture.
Hand out a mailbox above every pending one instead, and wrap back to the
bottom only once the ring has drained. Ordering then holds for any transfer
length; the cost is that the ring stalls at a wrap rather than refilling
immediately.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Correct the switch case label indentation in imxrt_netinitialize(), the brace
alignment in imxrt_ioctl(), and the indentation of the ERR005829 workaround
statements so imxrt_flexcan.c passes nxstyle. The last of these is only
reported since commit c81cc02e83.
These predate this series; CONTRIBUTING.md section 2.1 asks that modified
files be brought into compliance even where the contributor did not introduce
the problem.
Whitespace only, no functional change: `git diff -w` against the parent is
empty.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Select LIBC_ATOMIC_ARCH for TriCore when not using Tasking toolchain,
so that the tricore arch-atomic implementation is used instead of
the toolchain builtin.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
This patch get some fixes from ESP-IDF to fix a rolling issue
that happens on big resolution LCDs such as 800x480 LCDs.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Assisted-by: Claude Code
Wire the shared Ameba ADC driver into the RTL8721F build: add the
per-chip ameba_adc_chip.h (12 channels, CH0..CH7 external on
PA20,PA19,PA18,PA17,PA15,PA14,PA13,PA12, PINMUX function 5), the
board ADC table and registration, the adc board config, and build
glue for both cmake and make (including the fwlib RAM-layer
ameba_adc.c in ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba ADC driver into the RTL8720F build: add the
per-chip ameba_adc_chip.h (9 channels, CH0..CH5 external on
PA13..PA18, PINMUX function 5, APB clock on bit24), the board ADC
table and registration, the adc board config, and build glue for
both cmake and make (including the fwlib RAM-layer ameba_adc.c in
ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Add a NuttX ADC lower-half for the Ameba SoC family, wired for the
amebadplus/pke8721daf as /dev/adc0. The driver uses the fwlib ROM
API and drives on-demand polled conversions via ADC_ReceiveBuf with
the hardware auto channel-switch FIFO, because amebadplus disables the
ADC software-trigger path. Per-chip wiring (channel count, pinmux
function id, APB clock bits, optional aux clock) lives in a chip
header so a new IC only supplies its own values without touching the
shared driver.
Reports raw conversion codes per the NuttX convention (12-bit
effective, 0..~3876 for 0..3.3V), consistent with the STM32/i.MXRT/
Tiva ADC drivers.
Verified on hardware: 0V->121, 3.3V->3876 on CH0(PB19) while
CH1(PB18) held steady, confirming sampling, full-scale and
multi-channel switch-list isolation.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Rename atomic_fetch_add/sub/or/and/xor to atomic_add/sub/or/and/xor
to avoid conflicts with the C/C++ standard library naming. The
atomic_fetch_xxx naming is reserved by the standard; keeping it causes
function name conflicts when source files indirectly include both
<nuttx/atomic.h> and <atomic>/<stdatomic.h>.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Select LIBC_ATOMIC_IRQ at the architecture level (ARM7TDMI, ARM926EJS,
ARMv6M) for chips that do not support atomic operations natively. This
covers all ARM7TDMI, ARM926EJS, and Cortex-M0 based chips automatically.
Also select LIBC_ATOMIC_IRQ for specific non-ARM architectures (AVR,
RISC-V, SPARC, Xtensa) that lack atomic instruction support.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), and LIBC_ATOMIC_IRQ (interrupt disable). Rename
arch_atomic.c to arch_atomic_irq.c since it supports the IRQ backend.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
The receive path hands incoming packets to the stack and transmits
whatever reply comes back, without checking that a TX descriptor is
free, though the poll path checks exactly that. Under sustained
bidirectional load the reply lands on a descriptor the DMA still owns:
with assertions built in, a panic from the RX work queue
(DEBUGASSERT(des3 & RD_OWN), reproduced under a VNC pointer flood);
without them, corruption of a frame in flight.
A reply to received data is almost always an acknowledgement, and a
peer that misses one retransmits; overwriting a frame the DMA owns
recovers from nothing. Drop the reply when the ring is full, using the
same descriptor test the poll path already trusts.
Assisted-by: Claude:opus-5
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
On the linum-stm32h753bi, Ethernet throughput collapses in proportion to
what the display panel is showing. With the LTDC scanning a black screen
a 1.2 MiB TCP transfer to a wired peer takes 0.7 s; solid white takes 20
to 55 s and noise over 130 s, all at the same negotiated 100BASE-TX full
duplex, with the same bytes read from the same SDRAM. The display's
switching couples into the PHY hard enough to corrupt 100BASE-TX
signalling, and TCP grinds through the losses at whatever rate survives.
10BASE-T signals at 2.5 V with Manchester coding at a tenth of the
frequency, and does not care: black, white and noise all move at the
link rate. The same transfer that took five minutes with the display
rendering takes 5.6 seconds.
Restricting the ANAR advertisement is deliberately not the same as
disabling autonegotiation. A forced MCR leaves the partner to parallel
detection, which cannot sense duplex and picks half, a genuine
mismatch, verified here to stall bulk traffic completely. Advertising
only 10BASE-T full duplex keeps the negotiation and lands both ends on
the same mode.
Also fix the never-compiled !CONFIG_STM32_AUTONEG path, which still
called stm32_phywrite(); this driver has only ever had mdio_write().
And say what was negotiated at link-up: a duplex mismatch looks exactly
like a bad cable, and nothing else reports which of the two it is.
The vnc configuration of the linum board enables the new option, and its
packet pool sizing from a few commits ago stays: at any link speed, 24
buffers of 196 bytes was never going to stream a display.
Assisted-by: Claude:opus-5
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Add CRC header based on arch/arm/src/common/stm32/hardware/stm32_crc.h
and select STM32_HAVE_CRC in Kconfig
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Posix open() calls to /dev/adc# were hanging often due
to the ready loop check at the end of adc_enable() never
returning. According to ES0565 document, at least 4 ADC
clock cycles must pass between the time we waited for
calibration to end and before we can set ADEN. This will
depend on what clock is set for ADC. So to ensure enough
time passes, we are adding a short delay (so that even a
slow clock will work). Also, we are clearing the ADRDY
flag before hand to ensure we are detecting a fresh event.
The delay to wait for the voltage regulator is also
increased to account for extra time required in
non-ideal conditions.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The 20 selects that were repeated identically in every STM32_STM32H7*
helper are moved to STM32_H7_PERIPHERALS, leaving only the chip
specific ones in the per-family helpers.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add a driver for the STM32H7R/S XSPI controller. The driver implements
the NuttX QSPI interface and supports the memory-mapped mode used to
execute code from the external flash.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Move the STM32U5 startup, interrupt, GPIO, EXTI, serial, heap, idle, and
timer interrupt implementations into arch/arm/src/common/stm32.
This prepares the Cortex-M33 support for reuse by compatible STM32 families.
Assisted-by: OpenAI Codex:gpt-5
Signed-off-by: raiden00pl <raiden00@railab.me>
The STM32L073RZ provides a full speed USB device controller, but the
Nucleo-L073RZ board support did not enable it and no configuration
exercised it.
Add the pieces required to run USB device mode on this board:
- Add the USB device pin definitions to the STM32L0 pin map.
- Provide board level pull-up control using the embedded DP pull-up in
USB_BCDR, and register the CDC/ACM class at boot when it is selected.
- Add a usb-cdc configuration that presents an NSH console on USART2 and
a CDC/ACM serial device on USB.
The 48MHz clock for the controller is supplied by HSI48 trimmed from the
USB start of frame packet, which is the crystal-less USB configuration
already described by this board's board.h.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
