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arch/arm/stm32: Generalize Cortex-M33 heap support

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Rename the shared U3/U5 heap allocator to stm32_allocateheap_m33_v1.c
and keep its direct family selection in Make and CMake.

Size the primary region from a now-mandatory STM32_PRIMARY_SRAM_SIZE,
provided by the U5 chip header as the SRAM1 size, and drop the
U5-specific SRAM bank descriptions so the allocator carries no family
conditionals.

Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
This commit is contained in:
raiden00pl 2026-08-24 11:33:18 +02:00 • committed by Xiang Xiao
parent b269bb0c91
commit e20c4a76b6
4 changed files with 15 additions and 41 deletions
Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/include/stm32u5/chip.h
View file

@ -49,6 +49,8 @@
# error "Unsupported STM32U5 chip"
#endif
#define STM32_PRIMARY_SRAM_SIZE STM32_SRAM1_SIZE
#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX)
# define STM32_NFSMC 1 /* Have FSMC memory controller */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */

8
arch/arm/src/common/stm32/CMakeLists.txt
View file

@ -39,10 +39,6 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT AND (CONFIG_STM32_COMMON_LEGACY
list(APPEND SRCS stm32_pminitialize_default.c)
endif()
if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5)
list(APPEND SRCS stm32_allocateheap_m33_u3u5.c)
endif()
if(CONFIG_STM32_HAVE_IP_USART_M33_V3)
list(APPEND SRCS stm32_lowputc_usart_m33_v3.c stm32_serial_m33_v3.c)
endif()
@ -56,8 +52,8 @@ if(CONFIG_STM32_HAVE_IP_EXTI_M33_V1)
endif()
if(CONFIG_ARCH_CHIP_STM32U3 OR CONFIG_ARCH_CHIP_STM32U5)
list(APPEND SRCS stm32_irq_m33_v1.c stm32_start_m33_v1.c
stm32_timerisr_m33_v1.c)
list(APPEND SRCS stm32_allocateheap_m33_v1.c stm32_irq_m33_v1.c
stm32_start_m33_v1.c stm32_timerisr_m33_v1.c)
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
list(APPEND SRCS stm32_idle_m33_v1.c)

6
arch/arm/src/common/stm32/Make.defs
View file

@ -49,11 +49,6 @@ CHIP_CSRCS += stm32_pminitialize_default.c
endif
endif
ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \
$(CONFIG_ARCH_CHIP_STM32U5)),)
CHIP_CSRCS += stm32_allocateheap_m33_u3u5.c
endif
ifeq ($(CONFIG_STM32_HAVE_IP_USART_M33_V3),y)
CHIP_CSRCS += stm32_lowputc_usart_m33_v3.c
CHIP_CSRCS += stm32_serial_m33_v3.c
@ -69,6 +64,7 @@ endif
ifneq ($(filter y,$(CONFIG_ARCH_CHIP_STM32U3) \
$(CONFIG_ARCH_CHIP_STM32U5)),)
CHIP_CSRCS += stm32_allocateheap_m33_v1.c
CHIP_CSRCS += stm32_irq_m33_v1.c
CHIP_CSRCS += stm32_start_m33_v1.c
CHIP_CSRCS += stm32_timerisr_m33_v1.c

40
arch/arm/src/common/stm32/stm32_allocateheap_m33_u3u5.c → arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c
View file

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/common/stm32/stm32_allocateheap_m33_u3u5.c
* arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c
*
* SPDX-License-Identifier: Apache-2.0
*
@ -47,14 +47,17 @@
* Pre-processor Definitions
****************************************************************************/
/* Internal SRAM is available in all members of the STM32U3 and STM32U5
* families. The following definitions specify its family-specific size
* and location:
/* Each family using this implementation provides the following SRAM
* description:
*
* SRAM1_START STM32_SRAM1_BASE
* SRAM1_END
* SRAM1_END STM32_SRAM1_BASE + STM32_PRIMARY_SRAM_SIZE
* SRAM2_START STM32_SRAM2_BASE
* SRAM2_END
* SRAM2_END STM32_SRAM2_BASE + STM32_SRAM2_SIZE
*
* STM32_PRIMARY_SRAM_SIZE may span multiple contiguous SRAM banks. SRAM3
* and SRAM5 may be added as separate regions when their corresponding heap
* options are selected.
*
* In addition to internal SRAM, memory may also be available through the
* FSMC. In order to use FSMC SRAM, the following additional things need to
@ -75,33 +78,10 @@
# undef CONFIG_STM32_FSMC_SRAM
#endif
/* STM32U5[7,8]6xx have 128 KiB in two banks, both accessible to DMA:
*
* 1) 96 KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000
* 2) 32 KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000
*
* STM32U596xx have 320 KiB in two banks, both accessible to DMA:
*
* 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
*
* STM32U5Rxxx have 640 KiB in three banks:
*
* 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
* 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000
*
* In addition, external FSMC SRAM may be available.
*/
/* Set the range of system SRAM */
#define SRAM1_START STM32_SRAM1_BASE
#ifdef STM32_PRIMARY_SRAM_SIZE
# define SRAM1_END (SRAM1_START + STM32_PRIMARY_SRAM_SIZE)
#else
# define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE)
#endif
#define SRAM1_END (SRAM1_START + STM32_PRIMARY_SRAM_SIZE)
/* Set the range of SRAM2 as well, requires a second memory region */