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arch/arm/stm32: Generalize the Cortex-M33 NVIC dump helper

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Iterate the NVIC interrupt enable and priority registers from
STM32_IRQ_NEXTINTS instead of dumping a hardcoded U3/U5 register list,
so the helper works unchanged for any interrupt count.

Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
This commit is contained in:
raiden00pl 2026-08-25 14:59:06 +02:00 • committed by Xiang Xiao
parent 94b7968c89
commit d9eb2a7a55
1 changed files with 13 additions and 24 deletions
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37
arch/arm/src/common/stm32/stm32_irq_m33_v1.c
View file

@ -75,39 +75,28 @@
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
int i;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo(" IRQ ENABLE: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08" PRIx32 " %08" PRIx32
" %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08" PRIx32 " %08" PRIx32
" %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08" PRIx32 " %08" PRIx32
" %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08" PRIx32 " %08" PRIx32
" %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08" PRIx32 "\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
for (i = 0; i < STM32_IRQ_NEXTINTS; i += 32)
{
irqinfo(" IRQ ENABLE %3d-%3d: %08" PRIx32 "\n",
i, i + 31, getreg32(NVIC_IRQ_ENABLE(i)));
}
for (i = 0; i < STM32_IRQ_NEXTINTS; i += 4)
{
irqinfo(" IRQ PRIO %3d-%3d: %08" PRIx32 "\n",
i, i + 3, getreg32(NVIC_IRQ0_3_PRIORITY + i));
}
leave_critical_section(flags);
}