Treat PCI_ANY_ID in a configured UART slot as a wildcard while
still limiting probes to devices supported by the PCI 16550 driver.
This lets one console configuration select QEMU PCI serial or
the real PCI card at runtime.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Document the USART2 NSH console, USB FS pins, HSI48/CRS clock source and
the usb-cdc configuration that exposes a separate USB CDC/ACM serial
device.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The STM32L073RZ provides a full speed USB device controller, but the
Nucleo-L073RZ board support did not enable it and no configuration
exercised it.
Add the pieces required to run USB device mode on this board:
- Add the USB device pin definitions to the STM32L0 pin map.
- Provide board level pull-up control using the embedded DP pull-up in
USB_BCDR, and register the CDC/ACM class at boot when it is selected.
- Add a usb-cdc configuration that presents an NSH console on USART2 and
a CDC/ACM serial device on USB.
The 48MHz clock for the controller is supplied by HSI48 trimmed from the
USB start of frame packet, which is the crystal-less USB configuration
already described by this board's board.h.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Adds reference to the sdmmc_spi defconfig of esp32p4-tab5, with mounting
instructions for the SD Card.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Adds support for using SD Card on esp32p4-tab5 board.
Common source is added to esp32p4 common board directory which can be used
on different boards.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Return unsupported-format and mapping errors to board bring-up
instead of panicking, so a serial console can remain usable when
no suitable framebuffer exists.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
x86_64_uservaddr() depends on the address-environment layout and
is only consumed by the kernel address-environment path.
Guard it with CONFIG_ARCH_ADDRENV so MM_PGALLOC can also be
enabled in flat builds.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
read_line() removes a trailing newline and then checks g_line[len - 1]
for a line-continuation backslash. A blank line leaves len at zero, so
the continuation check reads before g_line.
Return the empty line to the caller before checking for a continuation.
kconfig_line() already skips empty lines, so parser behavior is
unchanged.
Signed-off-by: Old-Ding <ai.neo.ae86@gmail.com>
Python warns about return statements inside finally blocks because they
can suppress pending exceptions. Move the returns after the try/finally
and try/except bodies so normal return values stay the same while
unexpected exceptions are no longer swallowed.
Signed-off-by: Old-Ding <ai.neo.ae86@gmail.com>
Python 3.14 warns about invalid escape sequences in a few tooling strings. Escape those backslashes at the Python literal layer; the licensing regex AST stays unchanged, and the IDE exporter change only corrects the docstring path example.
Run black on tools/licensing/check.py so the licensing helper matches the project formatting check.
Signed-off-by: Old-Ding <ai.neo.ae86@gmail.com>
status() reads one reset line at a time, and only for a caller that
already knows the id. Nothing else in the interface says how many lines
a controller has or what any of them resets, so the lines a board is
holding cannot be surveyed.
Adds an optional get_line method describing one line as a structure: its
name, and a text member for controller specific fields the structure
does not cover. The asserted state stays with status(), which already
reports it, so a controller does not supply the same fact twice.
Returning -ENODEV reports an id that names no line, which is how
controllers with gaps in their numbering are handled.
reset_controller_dev gains the line count that bounds the ids.
CONFIG_RESET_PROCFS adds /proc/reset, one key:value line per reset line,
every line the same tokens in the same order so the file is machine
parseable. A controller without get_line is listed by name and a note.
The controller list already existed for reset_control_get() to search,
so the renderer only walks what was there. /proc/reset is claimed when
the first controller registers; procfs_register() requires that procfs
is not yet mounted, which holds because controllers register during
board or architecture start up, and it appends without checking for
duplicates, so the entry is claimed once for the lifetime of the system.
Documents the framework, which had a page with nothing on it: the
consumer interface and what shared and exclusive handles mean, the
controller interface, the new method, and /proc/reset.
Off by default and costs nothing when off. No in-tree configuration
enables RESET, so this builds only when a board turns it on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The pinctrl interface is write only: every operation sets a property,
and nothing reports what a pin currently holds.
Adds an optional get_pad method describing one pad as a structure: the
settable fields, each with a validity bit because a pad need not have
them all, and a text member for the controller specific fields the
structure does not cover. The structure embeds its strings rather than
pointing at them, so the same shape serves both callers.
The first caller is /proc/pinctrl, which renders one key:value line per
pad, every line the same tokens in the same order with - for a field the
pad does not have, so the file is machine parseable. The framework owns
the format; controllers only supply data.
The second is a new PINCTRLC_GETPAD ioctl, which gives userspace the
read-back that text cannot: reading a pad back after setting it.
PINCTRL_PADNAME() and two lookup helpers let a controller declare its
pad and function-select names in one table instead of inventing its own.
Registration keeps a list, which the renderer iterates; pinctrl_dev_s
gains the pad count. /proc/pinctrl is claimed when the first controller
appears; procfs_register() requires that procfs is not yet mounted,
which holds because controllers register during board or architecture
start up.
Documents the method, the validity bits and the optional naming, and
records that /proc/pinctrl exists.
Off by default and costs nothing when off. No in-tree configuration
enables PINCTRL, so this builds only when a board turns it on.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
The stm32h5 SPI driver had some issues when both
non-DMA and DMA instances were present at the same time.
Modify the driver to allow them to correctly coexist.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The stm32h5 SPI driver is based on stm32h7's.
It does not build when DMA is enabled. Port
stm32h5 DMA to the stm32h5 SPI driver using the
H5-specific DMA API. Use equivalents.
Use correct cache line definition.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Add board spi1 initialization and generic spi
chardev registration for nucleo-h563zi.
Specify the SPI1 clock source and frequency on
this board for the spi driver.
Define the SPI pins for this board. The SPI_A
CN7 header pins were used.
Include stm32_spi.h in stm32h5/stm32.h.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The standard requires braces after 'if', 'else', 'while', 'for' and 'do'
even when the body is a single statement. Nothing checked this.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Decode the saved setup request fields after processing the optional OUT data phase. This ensures the fields are initialized when the EP0 handler is entered again to complete an OUT control transfer.
This also fixes Clang builds that treat the resulting maybe-uninitialized diagnostics as errors.
Assisted-by: Codex:GPT-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Add the correct pin map definitions for MCO1 and MCO2, and add the clock
division option to stm32_mco{1,2}config with a macro. This matches the
STM32H7 implementation.
Signed-off-by: Darryl Ring <darryl@bluerobotics.com>
Update the MIPS Creator CI20 board documentation to include a detailed
peripherals support table. This replaces the basic bulleted list with
comprehensive status details for CPU cores, RAM, Display, Ethernet,
GPIO, TRNG, Timers, UART0, USB Host, and Watchdog.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
romfs_seek() clamps the computed position to the file size when it
exceeds rf_size, but never checks for a negative result. lseek(fd,
offset, SEEK_SET/SEEK_CUR/SEEK_END) with an offset that produces a
negative position (e.g. a negative SEEK_SET offset, or a SEEK_CUR/
SEEK_END offset more negative than the current position/file size)
is written straight into filep->f_pos.
The subsequent romfs_read() computes
`rf->rf_startoffset + filep->f_pos` into a uint32_t, so a negative
f_pos wraps around to a huge unsigned offset, and romfs_hwread()'s
XIP path memcpy()s from rm_xipbase plus that offset -- an
out-of-bounds read far past the mapped flash region.
Add the same "if (position < 0) return -EINVAL" guard already used
by fs/fat/fs_fat32.c's seek function, before the existing
end-of-file clamp.
Signed-off-by: yi chen <94xhn1@gmail.com>
Assisted-by: Claude:claude-sonnet-5
Fix NULL pointer dereference and memory corruption by using
file_put() instead of file_close() + kmm_free().
Add peer NULL check to local_freectl().
Signed-off-by: Bogdan <Bogdan4ik0759@gmail.com>
Document the usb-cdc-uart configuration, which keeps NSH on the USART2
ST-LINK virtual COM port and exposes a separate USB CDC/ACM serial
device on the STM32 USB FS connector.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The STM32F072RB provides a full speed USB device controller, but the
Nucleo-F072RB board support did not enable it and no configuration
exercised it.
Add the pieces required to run USB device mode on this board:
- Select HSI48 as the 48MHz source and use the USB start of frame packet
as the CRS synchronisation event, which is the intended crystal-less
USB configuration for this part.
- Add the USB device pin definitions to the STM32F07x pin map.
- Provide board level pull-up control and register the CDC/ACM class at
boot when it is selected.
- Add a usb-cdc-uart configuration that presents an NSH console on
USART2 and a CDC/ACM serial device on USB.
- Enable the USB device pins in the nsh configuration so the two
configurations stay consistent.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
clock_gettime(CLOCK_MONOTONIC) reads g_system_ticks, which is only
refreshed when a timer expiration is processed. On SCHED_TICKLESS an
idle system has no timeout armed, so the clock returns 0 before the
first expiration and a frozen value afterwards.
This regressed in commit c7b6442974, which switched CLOCK_MONOTONIC to
the sched tick counter to exclude suspended time. Excluding suspend time
needs explicit accounting maintained by PM code, the tick counter cannot
provide it on tickless.
Restore the live read. On non-tickless builds clock_systime_timespec()
falls back to the same tick counter, so behavior there is unchanged.
Verified on qemu-intel64, nrf52840-dk and rv-virt.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
vrefint_enable() sets SYSCFG_CFGR3_ENBUFVREFINTHSI48 in its local copy
of the register value but never writes that value back to the hardware.
The VREFINT reference for the HSI48 scaler is therefore never enabled.
Only the earlier ENVREFINT update reaches the register, so VREFINT
itself is enabled while the HSI48 reference is not. HSI48 then runs
without its voltage reference and the 48MHz clock is not accurate enough
to be used by the USB device controller.
Write the register after applying the HSI48 reference bit.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
STM32_HSI48_SYNCSRC was SYNCSRC_NONE, which makes stm32_enable_hsi48()
return before configuring the CRS at all. HSI48 then free runs at its
untrimmed factory frequency, which is not accurate enough for USB full
speed operation.
The board has no CRS_SYNC pin wired and does not fit an LSE crystal for
this purpose, so the USB start of frame packet is the available
synchronisation source. This is the intended configuration for
crystal-less USB on this part.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
stm32_enable_hsi48() set CRS_CR_AUTOTRIMEN but left CRS_CR_CEN clear.
AUTOTRIMEN only instructs the hardware to apply corrections derived from
the frequency error counter; the counter itself is enabled by CEN. With
CEN clear no error measurement is ever produced and the HSI48 TRIM value
stays at its reset default, so the oscillator is never disciplined to the
synchronisation source.
Set both bits, matching the value the STM32 ROM bootloader programs when
it runs its own crystal-less USB stack (CRS_CR = 0x1a60, i.e.
CEN | AUTOTRIMEN with a trimmed TRIM field).
This file is shared by the M0 STM32 parts (F0, G0, C0, L0); all of them
require CEN for automatic trimming to function.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The SYSCFG peripheral clock was gated on CONFIG_STM32_SYSCFG, but that
symbol is not defined by the STM32L0 Kconfig (only stm32h7 declares it),
so RCC_APB2ENR_SYSCFGEN was never set on this chip.
With SYSCFG unclocked every write performed by vrefint_enable() is
discarded and SYSCFG_CFGR3 reads back as 0x00000000. VREFINT and, in
particular, the ENBUFVREFINTHSI48 reference for the HSI48 oscillator are
therefore never enabled. HSI48 still reports HSI48RDY, but it runs
without its voltage reference and the 48MHz clock supplied to the USB
device controller is unusable: the controller cannot sample the bus,
never latches a reset condition in USB_ISTR, and never raises its
interrupt. The result is a USB device that is configured correctly in
every visible register yet never enumerates.
VREFINT is configured exclusively through SYSCFG_CFGR3, so enable the
SYSCFG clock whenever CONFIG_STM32_VREFINT is selected.
Observed on NUCLEO-L073RZ (STM32L073RZ):
before: SYSCFG_CFGR3 = 0x00000000, no enumeration
after: SYSCFG_CFGR3 non-zero, device enumerates as CDC/ACM
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The clock recovery system peripheral clock was enabled only when
CONFIG_STM32_CRS was selected. The CRS is required by any board that
uses HSI48 as the 48MHz clock source, because HSI48 must be trimmed from
an external synchronisation event to stay within the tolerance demanded
by USB full speed operation.
STM32_USE_HSI48 is the condition under which the remaining HSI48 and CRS
setup is compiled in, see stm32_enable_hsi48(), so accept that condition
here as well. Without the peripheral clock the CRS registers are
inaccessible and automatic trimming silently does nothing.
CONFIG_STM32_CRS is retained so that boards selecting the CRS directly
are unaffected.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The code that claimed to "enable clocking to the USB peripheral" cleared
RCC_APB1ENR_USBEN inside RCC_APB1RSTR. That is both the wrong register
and the wrong bit: USBEN belongs to RCC_APB1ENR, while APB1RSTR holds
RCC_APB1RSTR_USBRST. The peripheral clock is enabled by the RCC setup
performed at boot, so the write had no useful effect and merely cleared
an unrelated reset bit.
Issue a proper reset pulse on RCC_APB1RSTR_USBRST instead, so the
controller starts from a known state.
On STM32L0 the D+/D- lines are connected to the USB transceiver
automatically once the peripheral is enabled and there is no alternate
function to select, so skip the GPIO configuration on that chip. The
board GPIO_USB_DM/GPIO_USB_DP definitions do not exist there.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The initial interrupt mask enabled only reset, suspend and correct
transfer. Error conditions reported by the controller, USB_ISTR_ERR and
USB_ISTR_PMAOVRN, were neither enabled nor acknowledged.
Because the status bits are never cleared, an error condition latched in
USB_ISTR remains set and is re-evaluated on every subsequent interrupt,
which makes the reported status misleading when debugging transfer
problems.
Add ERRM and PMAOVRN to the initial mask and clear the corresponding
status bits when they are seen.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The correct transfer loop in stm32_usb_interrupt() dispatched every
completion to stm32_epdone(), including those for endpoint 0.
stm32_epdone() implements the generic bulk/interrupt endpoint completion
path. It does not decode the SETUP stage, does not maintain the EP0
state machine, and does not apply the EP0 specific RX/TX status rules.
Control transfers therefore never completed correctly and the device
could not be enumerated.
Dispatch endpoint 0 to stm32_ep0done(), which is the control endpoint
handler and is already used for the same purpose by the low priority
transfer path in stm32_lptransfer().
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
The packet memory area (PMA) accessors in the M0 USB device driver were
carried over from the STM32F1 implementation, where the PMA is seen by
the CPU as 16-bit values placed on 32-bit boundaries. On the STM32F0,
STM32L0 and other M0 parts the PMA is a linear 16-bit memory, so the
F1 scaling is wrong:
- STM32_USB_BTABLE_RADDR() shifted the computed buffer descriptor offset
left by one, addressing every second descriptor entry.
- The buffer descriptor accessors declared the descriptor entries as
uint32_t and accessed them 32 bits at a time, so each write clobbered
the adjacent entry.
- stm32_copytopma() and stm32_copyfrompma() scaled the PMA offset by two
when computing the packet buffer address.
The result is that endpoint buffer descriptors and packet data are
written to the wrong offsets in packet memory, and no transfer completes
correctly.
Drop the F1 scaling and use 16-bit accesses throughout. Note that the
sibling stm32_usbfs.h defines STM32_USB_BTABLE_RADDR() without the shift
already, so this brings the M0 header in line with it.
Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
CONFIG_STM32_GPIOIRQ has never had a Kconfig definition, and the guarded
stm32_gpioirqinitialize function has no declaration or implementation.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
CONFIG_STM32_GPIO_IRQ has no Kconfig definition, and the guarded stm32_gpioirq
functions have no declarations or implementations.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Remove the dependency on the iLLD SFR headers (IfxCpu_bf.h and
IfxCbs_reg.h) and the iLLD intrinsics (__mfcr/__mtcr) from the
hardware debug monitor implementation.
The debug CSFR numbers, trigger-event register (TR0..TR7) addresses,
TREVT bit-field offsets and the CBS_OEC register address are now
defined locally with a TC_ prefix, so the file no longer leaks the
iLLD CPU_* namespace (which is still pulled in transitively through
arch/irq.h). Register accesses use the tricore_mfcr/tricore_mtcr
macros, and the DBGTCR/DBGCFG/DBGACT bit-field unions are replaced
with explicit shifts.
This is a pure de-iLLD refactor with no behavior change, verified on
a TC4x7 EVB: the board boots to NuttShell and breakpoints trigger
identically before and after the change.
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
add an MTD driver for the Macronix MX25UW25645G Octal SPI NOR flash.
Extend the QSPI transfer descriptors with octal and DTR flags so
controller lower halves can issue OPI transactions.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
Add initial Apache NuttX support for the Allwinner D1 / T-Head C906
running in supervisor mode under OpenSBI.
Add support for:
- RV64 D1 architecture definitions
- Lichee RV 86 Panel board configuration
- UART0 console at 115200 baud
- D1 PLIC interrupt controller
- native D1 Timer1 scheduler tick
- early inherited-watchdog disable
- FLAT S-mode NSH configuration
The port has been tested on physical Sipeed Lichee RV / 86 Panel
hardware and boots to an interactive NuttShell.
The scheduler tick uses OSC24M Timer1 at 1000 Hz. The Timer1 interval
register is programmed with 23999 to produce exactly 24000 input clocks
per tick on the physical D1.
Assisted-by: OpenAI Codex:gpt-5.6-sol
Signed-off-by: Lance Harvie <lanceharvie@gmail.com>
The memory order '__ATOMIC_xxx' is not a name specified by the standard.
To achieve uniformity, if it is not defined, it will be defined one by
one in the order of 0 to 5.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add a fallback macro in compiler.h that defines __has_include(x) as 0
when the compiler does not natively support it. This allows simplifying
the guards in atomic.h by removing the defined(__has_include) check
and the __has_include(<stdatomic.h>) check, since __has_include is now
always defined and __STDC_NO_ATOMICS__ is sufficient to determine
atomic support.
The NEED_ATOMIC_MACROS logic is kept unchanged to preserve the C++
conflict fix from commit cd8ba3377c.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Launder each register value through a register with an empty asm, on
loads and stores both, so the access is the width the source specifies.
Same fix as usbhost_xhci_pci.c commit 4b702058f6.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
