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stm32l0: Enable SYSCFG clock when VREFINT is enabled.

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The SYSCFG peripheral clock was gated on CONFIG_STM32_SYSCFG, but that
symbol is not defined by the STM32L0 Kconfig (only stm32h7 declares it),
so RCC_APB2ENR_SYSCFGEN was never set on this chip.

With SYSCFG unclocked every write performed by vrefint_enable() is
discarded and SYSCFG_CFGR3 reads back as 0x00000000.  VREFINT and, in
particular, the ENBUFVREFINTHSI48 reference for the HSI48 oscillator are
therefore never enabled.  HSI48 still reports HSI48RDY, but it runs
without its voltage reference and the 48MHz clock supplied to the USB
device controller is unusable: the controller cannot sample the bus,
never latches a reset condition in USB_ISTR, and never raises its
interrupt.  The result is a USB device that is configured correctly in
every visible register yet never enumerates.

VREFINT is configured exclusively through SYSCFG_CFGR3, so enable the
SYSCFG clock whenever CONFIG_STM32_VREFINT is selected.

Observed on NUCLEO-L073RZ (STM32L073RZ):

  before: SYSCFG_CFGR3 = 0x00000000, no enumeration
  after:  SYSCFG_CFGR3 non-zero, device enumerates as CDC/ACM

Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
This commit is contained in:
jsanchez-2g 2026-08-18 14:34:15 -05:00 • committed by Xiang Xiao
parent 561da42812
commit 16e3c8c6de
1 changed files with 3 additions and 1 deletions
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4
arch/arm/src/stm32l0/stm32l0_rcc.c
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@ -319,7 +319,9 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32_SYSCFG
/* VREFINT is configured through SYSCFG_CFGR3, so its clock is required */
#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_VREFINT)
/* SYSCFG clock */
regval |= RCC_APB2ENR_SYSCFGEN;