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stm32f0/l0: Gate the CRS clock on STM32_USE_HSI48.

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The clock recovery system peripheral clock was enabled only when
CONFIG_STM32_CRS was selected.  The CRS is required by any board that
uses HSI48 as the 48MHz clock source, because HSI48 must be trimmed from
an external synchronisation event to stay within the tolerance demanded
by USB full speed operation.

STM32_USE_HSI48 is the condition under which the remaining HSI48 and CRS
setup is compiled in, see stm32_enable_hsi48(), so accept that condition
here as well.  Without the peripheral clock the CRS registers are
inaccessible and automatic trimming silently does nothing.

CONFIG_STM32_CRS is retained so that boards selecting the CRS directly
are unaffected.

Assisted-by: GitHub Copilot:claude-opus-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
This commit is contained in:
jsanchez-2g 2026-08-18 16:13:40 -05:00 • committed by Xiang Xiao
parent d70725e4e0
commit 561da42812
2 changed files with 2 additions and 2 deletions
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2
arch/arm/src/stm32f0/stm32f0_rcc.c
View file

@ -248,7 +248,7 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_CAN1EN;
#endif
#ifdef CONFIG_STM32_CRS
#if defined(CONFIG_STM32_CRS) || defined(STM32_USE_HSI48)
/* Clock recovery system clock enable */
regval |= RCC_APB1ENR_CRSEN;

2
arch/arm/src/stm32l0/stm32l0_rcc.c
View file

@ -268,7 +268,7 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_USBEN;
#endif
#ifdef CONFIG_STM32_CRS
#if defined(CONFIG_STM32_CRS) || defined(STM32_USE_HSI48)
/* Clock recovery system clock enable */
regval |= RCC_APB1ENR_CRSEN;