From 561da42812a31f11f8ab983b7ff0f5da4ff124de Mon Sep 17 00:00:00 2001 From: jsanchez-2g Date: Tue, 18 Aug 2026 16:13:40 -0500 Subject: [PATCH] stm32f0/l0: Gate the CRS clock on STM32_USE_HSI48. The clock recovery system peripheral clock was enabled only when CONFIG_STM32_CRS was selected. The CRS is required by any board that uses HSI48 as the 48MHz clock source, because HSI48 must be trimmed from an external synchronisation event to stay within the tolerance demanded by USB full speed operation. STM32_USE_HSI48 is the condition under which the remaining HSI48 and CRS setup is compiled in, see stm32_enable_hsi48(), so accept that condition here as well. Without the peripheral clock the CRS registers are inaccessible and automatic trimming silently does nothing. CONFIG_STM32_CRS is retained so that boards selecting the CRS directly are unaffected. Assisted-by: GitHub Copilot:claude-opus-5 Signed-off-by: jsanchez-2g --- arch/arm/src/stm32f0/stm32f0_rcc.c | 2 +- arch/arm/src/stm32l0/stm32l0_rcc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f0/stm32f0_rcc.c b/arch/arm/src/stm32f0/stm32f0_rcc.c index b5106208ca9..525529decb1 100644 --- a/arch/arm/src/stm32f0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0/stm32f0_rcc.c @@ -248,7 +248,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32_CRS +#if defined(CONFIG_STM32_CRS) || defined(STM32_USE_HSI48) /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; diff --git a/arch/arm/src/stm32l0/stm32l0_rcc.c b/arch/arm/src/stm32l0/stm32l0_rcc.c index 79359bb30bf..10f32d300bb 100644 --- a/arch/arm/src/stm32l0/stm32l0_rcc.c +++ b/arch/arm/src/stm32l0/stm32l0_rcc.c @@ -268,7 +268,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32_CRS +#if defined(CONFIG_STM32_CRS) || defined(STM32_USE_HSI48) /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN;