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arch/tricore: drop iLLD dependency in hwdebug
Remove the dependency on the iLLD SFR headers (IfxCpu_bf.h and IfxCbs_reg.h) and the iLLD intrinsics (__mfcr/__mtcr) from the hardware debug monitor implementation. The debug CSFR numbers, trigger-event register (TR0..TR7) addresses, TREVT bit-field offsets and the CBS_OEC register address are now defined locally with a TC_ prefix, so the file no longer leaks the iLLD CPU_* namespace (which is still pulled in transitively through arch/irq.h). Register accesses use the tricore_mfcr/tricore_mtcr macros, and the DBGTCR/DBGCFG/DBGACT bit-field unions are replaced with explicit shifts. This is a pure de-iLLD refactor with no behavior change, verified on a TC4x7 EVB: the board boots to NuttShell and breakpoints trigger identically before and after the change. Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
This commit is contained in:
zhangyuan29
Xiang Xiao
parent
0a2f484e12
commit
6ccb459e1a
1 changed files with 101 additions and 42 deletions
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@ -27,10 +27,6 @@
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <IfxCpu_bf.h>
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#include <IfxCbs_reg.h>
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#include "tricore_internal.h"
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@ -38,40 +34,93 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Core Special Function Register (CSFR) numbers used below. These were
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* previously pulled in from the iLLD SFR headers; define them locally so
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* this file no longer depends on iLLD.
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*/
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#define TC_DBGSR 0xfd00 /* Debug Status Register */
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#define TC_DBGACT 0xfd14 /* Debug Action Register */
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#define TC_DMS 0xfd40 /* Debug Monitor Start Addr */
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#define TC_DCX 0xfd44 /* Debug Context Save Addr */
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#define TC_DBGTCR 0xfd48 /* Debug Trap Control Register */
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#define TC_DBGCFG 0xfd4c /* Debug Configuration Register */
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/* Trigger event registers TR0..TR7: EVT at 0xf000 + n * 8, ADR at + 4 */
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#define TC_TR0_EVT 0xf000
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#define TC_TR1_EVT 0xf008
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#define TC_TR2_EVT 0xf010
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#define TC_TR3_EVT 0xf018
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#define TC_TR4_EVT 0xf020
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#define TC_TR5_EVT 0xf028
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#define TC_TR6_EVT 0xf030
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#define TC_TR7_EVT 0xf038
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#define TC_TR0_ADR 0xf004
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#define TC_TR1_ADR 0xf00c
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#define TC_TR2_ADR 0xf014
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#define TC_TR3_ADR 0xf01c
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#define TC_TR4_ADR 0xf024
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#define TC_TR5_ADR 0xf02c
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#define TC_TR6_ADR 0xf034
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#define TC_TR7_ADR 0xf03c
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/* CBS_OEC (OCDS Enable Control) memory-mapped register address */
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#ifdef CONFIG_ARCH_TC1V6
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# define CBS_OEC_ADDR 0xf0000478
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#elif defined(CONFIG_ARCH_TC1V8)
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# define CBS_OEC_ADDR 0xfa180068
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#endif
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/* Trigger event register (TREVT) bit field offsets/masks. The address
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* match/type bits share the same layout on TC1V6 and TC1V8; only the
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* enable field differs (see TREVT_CFG_REG_EN_* below).
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*/
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#define TREVT_BBM_OFF 3 /* Break Before Make */
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#define TREVT_TYP_OFF 12 /* 0: watchpoint 1: breakpoint */
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#define TREVT_AST_OFF 27 /* Address store trigger */
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#define TREVT_ALD_OFF 28 /* Address load trigger */
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/* Debug Status Register (DBGSR) event source field */
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#define DBGSR_EVTSRC_OFF 8
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#define DBGSR_EVTSRC_MSK 0x1f
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/* Debug Configuration Register (DBGCFG) - TC1V8 only */
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#define DBGCFG_EN_OFF 15 /* Debug enable */
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/* Watchpoint and breakpoint share a set of trigger events */
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#define TREVT_DEBUG_NUM 8
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#define TREVT_DEBUG_REGS 4
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#define TREVT_DEBUG_MATCH_TRAPMODE 0x03
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#define TREVT_DEBUG_EVTSRC_BASE 0x10
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#ifdef CONFIG_ARCH_TC1V8
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# define IFX_CPU_TR_EVT_BBM_OFF IFX_CPU_TREVT_BBM_OFF
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# define IFX_CPU_TR_EVT_TYP_OFF IFX_CPU_TREVT_TYP_OFF
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# define IFX_CPU_TR_EVT_AST_OFF IFX_CPU_TREVT_AST_OFF
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# define IFX_CPU_TR_EVT_ALD_OFF IFX_CPU_TREVT_ALD_OFF
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#endif
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#define TREVT_DEBUG_BBM (1 << IFX_CPU_TR_EVT_BBM_OFF)
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#define TREVT_DEBUG_WP (0 << IFX_CPU_TR_EVT_TYP_OFF)
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#define TREVT_DEBUG_BP (1 << IFX_CPU_TR_EVT_TYP_OFF)
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#define TREVT_DEBUG_WP_AST (1 << IFX_CPU_TR_EVT_AST_OFF)
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#define TREVT_DEBUG_WP_ALD (1 << IFX_CPU_TR_EVT_ALD_OFF)
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#define TREVT_DEBUG_BBM (1 << TREVT_BBM_OFF)
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#define TREVT_DEBUG_WP (0 << TREVT_TYP_OFF)
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#define TREVT_DEBUG_BP (1 << TREVT_TYP_OFF)
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#define TREVT_DEBUG_WP_AST (1 << TREVT_AST_OFF)
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#define TREVT_DEBUG_WP_ALD (1 << TREVT_ALD_OFF)
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#define TREVT_DEBUG_WP_ASTLD (TREVT_DEBUG_WP_AST | TREVT_DEBUG_WP_ALD)
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/* Register TREVT[2:0] have difference between tc3xx and tc4xx */
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#ifdef CONFIG_ARCH_TC1V6
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# define TREVT_CFG_REG_EN_MASK IFX_CPU_TR_EVT_EVTA_MSK
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# define TREVT_CFG_REG_EN_MASK 0x7 /* EVTA field mask */
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# define TREVT_CFG_REG_EN_VALUE TREVT_DEBUG_MATCH_TRAPMODE
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#elif defined(CONFIG_ARCH_TC1V8)
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# define TREVT_CFG_REG_EN_MASK IFX_CPU_TREVT_EN_MSK
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# define TREVT_CFG_REG_EN_MASK 0x1 /* EN bit mask */
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# define TREVT_CFG_REG_EN_VALUE 0x01
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#endif
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#define TREVT_SET_CASE(reg, n, val) \
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case n: __mtcr(CPU_TR##n##_##reg, val); break;
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case n: tricore_mtcr(TC_TR##n##_##reg, val); break;
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#define TREVT_GET_CASE(reg, n, val) \
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case n: val = __mfcr(CPU_TR##n##_##reg); break;
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case n: val = tricore_mfcr(TC_TR##n##_##reg); break;
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#define TREVT_GET_CFG_REG(n) TREVT_GET(EVT, n)
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#define TREVT_SET_CFG_REG(n, val) TREVT_SET(EVT, n, val)
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@ -123,9 +172,17 @@ struct tricore_debugpoint_s
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void *arg;
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};
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/* The debug context save area pointed to by DCX must be aligned to a full
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* context (upper + lower CSA = 32 registers). This matches the value that
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* arch/irq.h exports as XCPTCONTEXT_SIZE, defined locally to avoid pulling
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* in the iLLD-tainted header.
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*/
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#define TRICORE_DBG_CTX_SIZE (sizeof(uintptr_t) * 32)
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struct tricore_debug_s
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{
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uintptr_t aligned_data(XCPTCONTEXT_SIZE) dcx[TREVT_DEBUG_REGS];
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uintptr_t aligned_data(TRICORE_DBG_CTX_SIZE) dcx[TREVT_DEBUG_REGS];
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struct tricore_debugpoint_s dp[TREVT_DEBUG_NUM];
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};
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@ -259,8 +316,8 @@ void tricore_trevt_match(void)
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dp = g_trevt_debug.dp;
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evtsrc = ((__mfcr(CPU_DBGSR) >> IFX_CPU_DBGSR_EVTSRC_OFF) &
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IFX_CPU_DBGSR_EVTSRC_MSK) - TREVT_DEBUG_EVTSRC_BASE;
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evtsrc = ((tricore_mfcr(TC_DBGSR) >> DBGSR_EVTSRC_OFF) &
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DBGSR_EVTSRC_MSK) - TREVT_DEBUG_EVTSRC_BASE;
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dp[evtsrc].callback(dp[evtsrc].type, dp[evtsrc].addr,
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dp[evtsrc].size, dp[evtsrc].arg);
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@ -276,47 +333,49 @@ void tricore_trevt_match(void)
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int tricore_init_dbgmonitor(void)
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{
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Ifx_CPU_DBGTCR dbgtcr;
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/* DBGTCR: DTA (bit 0) = 0, all other fields cleared */
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dbgtcr.B.DTA = 0;
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uint32_t dbgtcr = 0;
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#ifdef CONFIG_ARCH_TC1V8
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/* DBGCFG: EN (bit 15) = 1, TC (bit 0) = 0, TCP (bit 1) = 0.
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* DBGACT: EVTA (bits 2:0) = trap mode.
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*/
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if (!(__mfcr(CPU_DBGSR) & 0x1))
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uint32_t dbgcfg = 1 << DBGCFG_EN_OFF;
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uint32_t dbgact = TREVT_DEBUG_MATCH_TRAPMODE;
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#endif
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if (!(tricore_mfcr(TC_DBGSR) & 0x1))
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{
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CBS_OEC.U = 0xa1;
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CBS_OEC.U = 0x5e;
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CBS_OEC.U = 0xa1;
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CBS_OEC.U = 0x5e;
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/* Unlock sequence for the OCDS Enable Control register */
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putreg32(0xa1, CBS_OEC_ADDR);
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putreg32(0x5e, CBS_OEC_ADDR);
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putreg32(0xa1, CBS_OEC_ADDR);
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putreg32(0x5e, CBS_OEC_ADDR);
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}
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#ifdef CONFIG_ARCH_TC1V8
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Ifx_CPU_DBGCFG dbgcfg;
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Ifx_CPU_DBGACT dbgact;
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dbgcfg.B.EN = 1;
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dbgcfg.B.TC = 0;
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dbgcfg.B.TCP = 0;
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dbgact.B.EVTA = TREVT_DEBUG_MATCH_TRAPMODE;
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/* Set debug configuration register */
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__mtcr(CPU_DBGCFG, dbgcfg.U);
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tricore_mtcr(TC_DBGCFG, dbgcfg);
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/* Set debug action configuration register */
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__mtcr(CPU_DBGACT, dbgact.U);
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tricore_mtcr(TC_DBGACT, dbgact);
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#endif
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/* Set debug trap control register */
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__mtcr(CPU_DBGTCR, dbgtcr.U);
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tricore_mtcr(TC_DBGTCR, dbgtcr);
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/* Set trevt trap handler */
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__mtcr(CPU_DMS, (uintptr_t)tricore_dbgmonitor);
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tricore_mtcr(TC_DMS, (uintptr_t)tricore_dbgmonitor);
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/* Set dcx register */
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__mtcr(CPU_DCX, (uintptr_t)g_trevt_debug.dcx);
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tricore_mtcr(TC_DCX, (uintptr_t)g_trevt_debug.dcx);
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return OK;
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}
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