The PHY was polled with nxsched_usleep(100) in a loop of 0x1998
iterations, so the time the link had to come up depended on the period
of the system tick. With the usual 10 ms tick that is about 65 s, but
with CONFIG_SCHED_TICKLESS and a 100 us tick it is about 0.65 s, shorter
than the auto-negotiation of the PHY (about 1.7 s on the board tested),
and the interface could not be brought up.
Poll every 10 ms and give the PHY up to 5 s, both for the link and for
the auto-negotiation to complete, whatever the tick.
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Assisted-by: Claude:claude-sonnet-5
The comment of stm32_eth_ptp_convert_rxtime() said that it converts to
CLOCK_REALTIME. Since the timestamp is delivered as the value of the
PTP counter of the MAC, which is the time base of /dev/ptp0, say
that.
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Assisted-by: Claude:claude-sonnet-5
Implement lower-half PTP hardware clock operations (struct ptp_lowerhalf_s
and struct ptp_ops_s) in the STM32 Ethernet driver and register it with the
generic PTP clock framework (drivers/timers/ptp_clock.c) to expose /dev/ptp0.
Supported operations:
- adjfine: adjust PTP clock frequency in parts per billion (ppb)
- adjphase: adjust PTP clock phase via hardware TSSTU
- adjtime: shift PTP clock time by signed delta in nanoseconds
- gettime: atomic double-read of hardware timestamp registers
- settime: initialize hardware timestamp counter via TSSTI
- getres: return 1 ns clock resolution
Also fix a sign bug in stm32_eth_ptp_adjust() where uint64_t addend
promoted negative ppb adjustments to unsigned, corrupting frequency trim
for crystals running faster than nominal.
Follow-up to #20148 per review recommendation to use the standard POSIX
/dev/ptp0 character driver instead of custom socket ioctls.
Assisted-by: Gemini:gemini-3.8-pro
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
The MAC hardware counter is the PTP clock reference. Delivering its
raw timestamp directly (instead of synthesizing one against
CLOCK_REALTIME, which starts at an arbitrary boot-time phase) lets the
PTP daemon close the feedback loop and phase-lock the MAC counter -
and therefore the physical PPS output - to the master.
Assisted-by: Gemini:gemini-3.8-flash-medium
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Set ETH_MACCR_ROD unconditionally when configuring the MAC. In
half-duplex mode the MAC otherwise reflects every frame it transmits
back to its own receiver, flooding the receive path with our own
traffic right as a genuine reply arrives. The bit has no effect in
full-duplex (confirmed on our hardware: fduplex=1), so setting it
unconditionally is safe and changes nothing observable for boards
already running full-duplex.
The sibling stm32f7 driver has the same gap (ETH_MACCR_ROD cleared
but never set) and stm32h7's equivalent ETH_MACCR_DO bit has the same
issue; both are left out of scope here since only m3m4_v1 hardware
was available to validate against.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
(cherry picked from commit 41536cb8c9f5ff448864d2eb490b35aea7cdafcf)
stm32_receive() called pkt_input() before
stm32_eth_ptp_convert_rxtime(), so every packet handed to a packet
socket carried the previous frame's RX timestamp instead of its own
in dev->d_rxtime. Reorder so the timestamp is converted first.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
(cherry picked from commit 9bfa20da28da79a567e3b38cb127767cf9e03042)
In comp_ioctl(), propagate the return code of comp_enable() to caller so
failures (such as when the comparator CSR register is locked) return -EPERM.
Also call comp_lock_set() if the comparator was configured with locking,
handling cases where initialization was delayed.
Assisted-by: Gemini:gemini-3.8-pro
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Implement ao_ioctl in stm32_comp_m3m4_v2.c to handle ANIOC_COMP_ENABLE and
ANIOC_COMP_DISABLE commands. Also add CONFIG_STM32_COMP_INIT_DISABLED to
allow keeping the comparator disabled after driver initialization until
explicitly enabled.
Update nucleo-g431kb:comp defconfig to enable CONFIG_EXAMPLES_COMP and
set default DAC path for comparator ramp verification.
Assisted-by: Gemini:gemini-2.5-pro
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Add a function which can be called from M33 core on imx118x to start
executing on M7 core.
The function:
- Configures the M7 clock root
- Releases M7 from reset
- Asks the secure element to release the M7 (ENABLE_APC)
- Enables the M7 clock
The function is compiled in when a configuration flag
CONFIG_IMXRT_CM7_BOOT=y
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Add driver supporting the DMA3 and DMA4 in iMXRT118x chips. The driver is first copied
from imx93, and then changed just the relevant parts (function names, clocking and
irq handling) to match the imx118x configuration.
- Add the DMA channel numbering in hardware/rt118x/imxrt118x_dmamux.h from RM
by claude.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add a few !defined(CONFIG_ARCH_FAMILY_IMXRT118x) gates similar to 1176 to
buid the common drivers also for 118x variants.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Move/make sure that ep0buf is in usb dma capable memory. Especially if
.data/.bss are in TCM, the buffers need to be placed in another section.
If the section .dmamemory doesn't exist, they will end up in .data like before
- change "#ifdef CONFIG_ARCH_FAMILY_IMXRT117x" into
"#if defined(CONFIG_ARCH_FAMILY_IMXRT117x) || defined(CONFIG_ARCH_FAMILY_IMXRT118x)"
- In imxrt_epcomplete dtd->buffer0 must NOT be used to compute the data buffer's
cache-maintenance address range. The hardware advances buffer0 (and its
"current offset" low-order bits) as the transfer progresses, so by completion
time it points *past* the start of the buffer (at start + xfer_len), not at
the buffer itself. Instead, use the original privreq->req.buf when the transfer
is complete.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Small additions to existing drivers to support more UARTs
- Properly invalidate the cache over DMA RX buffer initially
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Add imxrt118x compatible IOMUX definitions, named as IOMUX_VER3. This is the
same IP as what is used for example for IMX9. Instead of directly copying the support
from imx9, pack the padconfig into the same 32-bit value used for GPIO for easy use.
- Add imxrt118x compatible rgpio driver. This is the same GPIO block as what has been used
in imx9. Instead of directly copying the support from IMX9, add pin muxing directly
into GPIO driver as well, to keep the usage compatible with existing IMXRT boards.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Initialize the internal secure element, if configured
- Initialize the TRDC, if configured
- Disable the TCM enabling code when compiling for other than Cortex-M7 chip.
This needs to be skipped for M33 core on imx118x
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
iMXRT118x uses the same security element as the imx93. Just add iMXRT specific
register definitions and port over the driver code.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The trdc driver has been copied from arm64/imx93, and modified to fit imxrt118x.
The relevant register definitions have been generated by AI from the RM.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add IMXRT AONMIX register addresses and bit definitions in a separate header file
"imxrt118x_blkctrl.h".
The header is generated using AI from imxrt118x reference manual.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Support reading the OCOTP via the shadow register on imxrt chips with integrated
ELE. On these chips, writing is done via ELE, this is not yet implemented.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add register definitions for IMXRT118x Analog-Digital top level block.
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Port the ccm / clock configuration from iMX93 to iMXRT118x.
Register definitions are generated from RM using AI
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add interrupt numbering for imxrt118x in imxrt118x_irq.h, and support
for more interrupts in imxrt_irq.c and imxrt_clrpend.c.
The interrupt numbers are generated from the Reference Manual by AI
Assisted-by: Claude Code:claude-opus-4-7
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Add imxrt118x memorymaps as hardware/rt118x/imxrt118x_memorymap.h
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
- Only submit and account for a wrapped second TX segment when scatter/gather descriptors
are available. Without in-memory TCDs, submitting the second segment overwrites the
active hardware descriptor and incorrectly advances the serial buffer past unsent data.
- Invalidate DMA RX buffer initially
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Support USART waking from low power modes, allow keeping
HSI running in STOP mode, allow specifying clock source
for USARTs, add some missing register and field definitions.
stm32 common Kconfigs:
Add common STM32 UART config options USARTx_WAKE_FROM_LOW_POWER and USARTx_WUS
for USART to cause wake up from low power modes.
stm32h5 board configs:
Allow board.h to choose the clock source of each USART.
Allow board.h to express that HSI should continue running
in low power modes.
stm32h5 RCC:
Set the clock source for each USART if specified in the
board configs (STM32_RCC_CCIPR1_USARTxSEL).
Keep HSI on in STOP mode if specified in the board configs
(STM32_BOARD_HSIKERON_ENABLE).
stm32h5 serial driver:
Use the new USARTx_WAKE_FROM_LOW_POWER and USARTx_WUS in
stm32h5 serial driver to wake from low power modes.
Use the USART clock source specified by board configs.
Enable FIFOs.
Clear UE bit before initialization.
Co-authored-by: Javier Casas <javiercasas@geotab.com>
Co-authored-by: daniellizewski <daniellizewski@geotab.com>
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Replace compile-time CONFIG_ARCH_HAVE_NETDEV_TIMESTAMP with
a runtime NETDEV_RX_STAMP bit in net_driver_s.d_features.
Drivers providing hardware RX timestamps set the flag at
probe time; the stack checks it at runtime.
Signed-off-by: OceanfromXiaomi <zhaohaiyang1@xiaomi.com>
Add board-level configuration and driver support for differential input
channels and auto-calibration on STM32 ADC IPv2 and IPv2G4 (STM32F3,
STM32G4), following the STM32H5 architecture pattern requested in review:
- In hardware headers (stm32_adc_v2.h and stm32_adc_v2g4.h), fix register
comments and define ADC_DIFSEL register shift and masks.
- In stm32_adc_m3m4_v1v2.c:
- Add difsel field to struct stm32_dev_s initialized from
BOARD_ADCx_DIFSEL if defined, falling back to ADC_DIFSEL_DEFAULT (0).
- Configure DIFSEL before enabling the ADC in adc_configure().
- Fix and enable adc_calibrate() for HAVE_IP_ADC_V2, supporting both
single-ended calibration (ADCALDIF=0) and differential calibration
(ADCALDIF=1) based on the channel selection.
Verified on Nucleo-G431KB (single-ended and differential channel 1).
Assisted-by: Gemini:gemini-2.5-pro
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Add an API for OTP (one-time programmable) memory on stm32h5.
There are OTP APIs for non-STM32 platforms.
There is no other API for STM32 so far with these names.
Implement it in stm32h563xx_flash.c since the progmem abstraction
also lives there.
int stm32_otp_write(const uint16_t *data, uint16_t len, uint32_t offset);
int stm32_otp_read(uint16_t *data, uint16_t len, uint32_t offset);
The API allows cross-block reads/writes that don't necessarily
start/end at block boundaries.
The type of `data` is uint16_t * to express to the caller that the
pointer should be 2-aligned. The natural size of OTP words is 16 bits.
`len` is uint16_t for no strong reason. Preserve author's work.
uint32_t stm32_otp_getlockstatus(void);
Get a mask of blocks that are locked. A block being locked
is considered as being one-time programmed.
Co-authored-by: Mykhailo Sopiha <mykhailosopiha@geotab.com>
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Record the eCAP1 and eCAP2 APWM outputs in the board's Peripheral
Support list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds a PWM lower-half using the eCAP modules in APWM mode as single-channel
generators rather than capture units.
start() reprograms the time base only when the frequency changes, so a
duty-only update does not stop or zero a live counter.
t3-gem-o1 registers /dev/ecap1 and /dev/ecap2; output pad selection is left to
the board, as the candidates collide with I2C0.
Verified on t3-gem-o1: examples/pwm runs a 1 kHz, 50% duty train on both
instances and accepts a duty-only change (25% then 75%). The output pins have
not been measured on copper, as no pad is assigned to them on this board.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
This patch addresses two issues in the single-timer capture/compare
tickless OS drivers for STM32 families (common m3m4 v1 for F1/F2/F3/F4/G4,
F7, H7, and WB):
1. Zero-period handling: when up_timer_start() is called with a zero or
negative duration (or period converts to 0 ticks), the driver now
enables the compare match interrupt and immediately fires an event
via EGR (CCxG), avoiding missed events or unexpected counter behavior.
2. Compare-match race condition: after programming CCR and enabling the
compare interrupt, a post-check validates whether the free-running
counter already reached or passed count + period during register
configuration. If elapsed, the interrupt is forced immediately via EGR,
preventing the counter from missing the match and hanging until a full
32-bit rollover (approx. 71 minutes at 1 MHz).
Verified on real hardware:
- STM32H743ZI (IED R550): validated with ping, sleep, and usleep.
- STM32G431KB (Nucleo-G431KB): validated with uptime, sleep, and usleep.
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
Moves EPWM initialization from am67_bringup.c to am67_pwm.c. Initialization
now requires only a function call in bringup.c.
Nxstyle checked, builds same.
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds a PWM lower-half for EPWM0 and EPWM1, covering both output channels of
each. The CTRL_MMR EPWM clock enables are unlocked once during board bring-up.
t3-gem-o1 registers /dev/pwm0 and /dev/pwm1 with PWM_NCHANNELS=2.
Verified on t3-gem-o1: all four outputs (EPWM0 A+B, EPWM1 A+B) drive physical
pins, jumpered into a Linux GPIO input -- 50% and 20% duty read back at the
expected sample ratios, and gpiomon timed a 50 Hz half-period at 9.998-10.002
ms. examples/pwm starts and stops a 1 kHz train cleanly.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Record the WKUP_I2C0 master in the board's Peripheral Support list.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Adds an I2C master driver for the AM67 I2C instances, completing transfers on
ARDY as the K3 controller signals.
Bring-up is deferred to the first transfer, because the Linux Device Manager
enables the I2C clocks late and touching the bus during early board init is not
safe here. The last reference drop clears the flag so the next transfer
re-initialises the hardware.
t3-gem-o1 registers WKUP_I2C0 as /dev/i2c2.
Verified on t3-gem-o1: i2c dev finds 0x30, 0x40, 0x51 and 0x68, the RTC at
0x68 reads a ticking BCD seconds register, repeated reads are consistent, and
NACK recovery returns the bus to a usable state.
Assisted-by: Claude Code:claude-fable-5
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
Fix a potential deadlock in the DMA driver. DMA completion callbacks
may immediately submit another transfer, for example:
imx9_dmaterminate()
-> imx9_dma_txcallback()
-> imx9_dma_txavailable()
-> uart_xmitchars_dma()
-> imx9_dma_send()
-> imx9_dmach_stop()
-> imx9_dmaterminate()
Resulting dmaterminate to take the same spinlock again. Fix this by moving
the spin_unlock_irqrestore_nopreempt before calling the callback. It is not
necessary to keep dma channel locked during the callback; the channel is
already free at this point.
This doesn't directly affect arch/arm/imx9 (the cortex-m version) because
it is not SMP (the spinlock is reduced to blocking irqs), but it is worth
fixing at the same to keep drivers in sync.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The compilation of stm32_mpuinit.c is guarded by CMakeLists.txt and
Make.defs, so this is unneccessary.
Signed-off-by: Darryl Ring <darryl@bluerobotics.com>
If CONFIG_ARM_MPU and CONFIG_STM32_ICACHE are set, this will configure an
MPU region marking the OTP flash as non-cacheable. This prevents hard faults
when accessing the 4K OTP region from software.
Signed-off-by: Darryl Ring <darryl@bluerobotics.ca>
This adds MPU initialization code based on the STM32U5. Unlike the
STM32U5 code, though, this allows the MPU to be used outside of
PROTECTED build mode.
PROTECTED build mode is still not yet supported.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Darryl Ring <darryl@bluerobotics.com>
Add a Peripheral Support section to the board page listing the GPIO and
MCU_MCSPI0 drivers, and replace the "UART console only" warning on both
the chip and board pages -- it no longer describes the port. The
replacement states what actually constrains the port: NuttX runs on the
R5F under RemoteProc and depends on the bootloader or Linux Device
Manager having powered and clocked the peripherals, because there is no
TISCI client yet.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Ulaş Sertan Kemeç <sertan.usk@gmail.com>
