The commits that follow teach the ELF loader to load an FDPIC object. This
puts the option they hang off and the definitions they share in one place
first, so each of them builds on its own.
CONFIG_FDPIC depends on ARCH_HAVE_ELF_FDPIC, which an architecture selects
when it has a PIC base register and the FDPIC relocations. Only armv7-m
and armv8-m select it today, and it defaults off, so nothing changes for
anyone who does not ask for it.
include/nuttx/fdpic.h holds what both sides of the loader need: the two
word function descriptor an FDPIC module passes instead of a code address,
the test for whether the caller is such a module, and the call sequence
that enters one with its own data base. All of it is behind CONFIG_FDPIC,
thus the header is empty without it and a file may include it
unconditionally.
The call sequence itself is architecture specific, so arch/arm/include/arch.h
supplies it as up_fdpic_invoke(), beside the other PIC base register macros.
up_setpicbase() cannot serve here: the register has to hold the module's
base for exactly one call and then go back, and nothing in C tells the
compiler the register is live across that call, so the save, the install,
the branch and the restore have to be one sequence.
Built for mps3-an547:bl and mps3-an547:picostest, with CONFIG_FDPIC off,
which is every configuration in the tree.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Remove the per-arch testset implementation from the spinlock layer.
The testset abstraction predates the unified spinlock.h API and is no
longer used now that all arches provide spin_lock_irqsave()/
spin_unlock_irqrestore() directly. Drop the per-arch *_testset.{c,S}
implementations and spinlock.h files for arm, sim, sparc, tricore,
x86_64, and xtensa, along with the CXD56_TESTSET,
CXD56_TESTSET_WITH_HWSEM, and CXD56_ATOMIC_WITH_HWSEM Kconfig options
in arch/arm/src/cxd56xx, and simplify the CXD56 semaphore pool loop
in cxd56_sph.c to a single unconditional range.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Implement atomic_lock/atomic_unlock using hwspinlock when
CONFIG_LIBC_ATOMIC_HWSPINLOCK is selected, and using up_irq_save/
up_irq_restore when CONFIG_LIBC_ATOMIC_IRQ is selected. Rename
arch_atomic_irq.c to arch_atomic.c.
The 64-bit atomic operations use spinlock (spin_lock_irqsave)
regardless of the selected backend, ensuring multi-core safety.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Select LIBC_ATOMIC_IRQ at the architecture level (ARM7TDMI, ARM926EJS,
ARMv6M) for chips that do not support atomic operations natively. This
covers all ARM7TDMI, ARM926EJS, and Cortex-M0 based chips automatically.
Also select LIBC_ATOMIC_IRQ for specific non-ARM architectures (AVR,
RISC-V, SPARC, Xtensa) that lack atomic instruction support.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), and LIBC_ATOMIC_IRQ (interrupt disable). Rename
arch_atomic.c to arch_atomic_irq.c since it supports the IRQ backend.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add a P0 skeleton port for the Realtek RTL8721F (SDK codename Green2 /
amebagreen2). Structurally the RTL8721F is a twin of the RTL8720F -- the
AP/host core is km4tz (ARMv8-M.main, TrustZone secure) and the WiFi MAC/PHY
runs on the km4ns network-processor core -- so this port is modelled on the
RTL8720F one and shares the IC-agnostic ameba glue in
arch/arm/src/common/ameba.
This is the "configures and links" skeleton (rtl8721f_evb:nsh builds an
image end to end). Four differences from the RTL8720F template were needed
to make the empty shell link against amebagreen2:
* km4tz has no FPU (cmsis_cpu.h defines __FPU_PRESENT 0), so the chip does
not select ARCH_HAVE_FPU and the image is built soft-float.
* ameba_app_start.c matches amebagreen2's ram_km4tz silicon init: the
nocache MPU map, the non-secure ROM BSS clear, OSC4M (not OSC2M)
calibration gated on EFUSE cut >= B and CHIP_TYPE_ASIC_POSTSIM.
* amebagreen2 ships no lib_rom.a, so the ROM archive whole-archive link is
dropped; the WiFi/OS/non-secure ROM symbols come from the SDK
ameba_rom_symbol_acut{,_wifi,_os}.ld maps appended to the image2 linker
script, exactly as green2's own image2 link does.
* the AP WiFi security lib is lib_wifi_common.a (was lib_wifi_com_sec.a).
The per-chip IRQ vector table (irq.h) and the RAM_START/RAM_SIZE layout
still carry RTL8720F values and are refined in the follow-up bring-up work.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Two device-controller defects that break standard host error recovery,
found while root-causing why macOS never mounts a NuttX mass-storage
function (full analysis and host traces in apache/nuttx#19435):
1. epsubmit() aborted (-EBUSY) any IN request submitted while the
endpoint was halted. The mass storage class halts bulk-IN for a
failed device-to-host command (BOT-legal) and then submits the CSW;
the CSW was dropped on the floor, so after the host's Clear-Halt the
endpoint NAKed forever and the host timed out (macOS: 30 s, then a
Bulk-Only-reset/device-reset spiral until it disables the port).
This is exactly the race documented for years in the usbmsc_scsi.c
header (David Hewson's analysis); the USBMSC_STALL_RACEWAR sleep
workaround only survives hosts that clear the halt within 100 ms --
Linux does, macOS does not, which is why Linux testing never saw it.
Implement the stall-queueing contract instead: requests submitted
while an endpoint is halted are queued without arming the hardware
(arming rewrites the buffer control word and would silently clear
the STALL bit); a halt terminates any in-flight IN transfer (its
hardware buffer is disarmed by the STALL write and would never
complete); clearing the halt resets the data toggle and re-arms the
head of the queue; stale buffer completions latched for transfers
aborted by a halt are ignored. RP2040/RP23XX now select
ARCH_USBDEV_STALLQUEUE, which also retires the RACEWAR's two 100 ms
sleeps per failed command.
2. The USB_REQ_GETSTATUS handler in ep0setup() validated the request
but never queued the two-byte response, for all three recipients
(device/interface/endpoint), so EP0 NAKed the host's data stage
forever and every GET STATUS timed out. macOS issues GetPipeStatus
= GET STATUS(endpoint) on a halted pipe before running Bulk-Only
reset recovery and hit this on every probe; lsusb -v's device-status
query hangs on it as well. Send the response: endpoint recipient
reports the halt bit, device recipient reports self-powered,
interface reports zeros; the status stage is armed by handle_zlp()
exactly as for class-dispatched IN transfers.
Validated on RP2350 silicon (Raspberry Pi Pico 2 W, composite
CDC-ACM + CDC-NCM + USBMSC): pre-fix, a raw-usbfs replay of macOS's
sequence and timing reproduced both defects deterministically (CSW read
ETIMEDOUT after a delayed clear-halt; all GET STATUS variants
ETIMEDOUT). Post-fix: the CSW survives the halt and is delivered after
Clear-Halt with correct tag/status/residue across a post-stall delay
sweep of 0-1000 ms; all GET STATUS variants answer immediately with
correct halt reporting; no regressions in the exact-length SCSI suite,
Bulk-Only reset, FAT mount and full reads, CDC-NCM/ACM, or warm
reboots; and macOS now mounts the volume (together with the companion
usbmsc fixes). The rp2040 driver shares the code and receives the
identical fix (build-tested).
Assisted-by: Claude (Anthropic Claude Code)
Signed-off-by: Ricard Rosson <ricard@groundbits.com>
The port could only run with a periodic ARM SysTick tick. Add an alarm/
oneshot lower-half backed by an RP2350 system timer block so the scheduler
can run tickless, waking the CPU only when a timer actually expires.
rp23xx_oneshot.c implements the ONESHOT_COUNT lower-half (mirroring the
RISC-V mtimer driver). A timer block is a free-running 64-bit microsecond
counter (clocked by the TICKS block, independent of the SysTick), which serves
directly as the monotonic time base returned by current(), so timekeeping is
exact to 1 us. The one adaptation versus a full 64-bit compare timer is that
the RP2350 ALARM registers match only the low 32 bits of the counter:
max_delay() is therefore capped below 2^32 counts (~71.5 minutes) so the
scheduler never asks for a longer interval, and any deadline that is already
due -- or that the counter reaches while the alarm is being armed -- is
raised immediately through the INTF force register instead of waiting a full
32-bit wrap for the compare to match again.
Enabled with CONFIG_RP23XX_SYSTIMER_TICKLESS (mutually exclusive with
RP23XX_SYSTIMER_SYSTICK), which selects ONESHOT, ONESHOT_COUNT and
ALARM_ARCH; up_timer_initialize() then hands the oneshot to
up_alarm_set_lowerhalf(). ARCH_CHIP_RP23XX now selects ARCH_HAVE_TICKLESS.
The block is selectable with CONFIG_RP23XX_SYSTIMER_TICKLESS_TIMER0 (default)
or _TIMER1; the chosen block is claimed exclusively by the scheduler and is
excluded from the /dev/timer driver (CONFIG_RP23XX_TIMER) in Kconfig, so the
tickless clock and a /dev/timer device can coexist on different blocks.
Tested on Pimoroni Pico Plus 2 (RP2350B) hardware with CONFIG_SCHED_TICKLESS
and CONFIG_SCHED_TICKLESS_ALARM: the image boots to nsh and keeps accurate
time -- "uptime" advances at real-time rate (17 s over a measured 17.4 s) and
"sleep 4" blocks for 4.25 s of wall time -- confirming the oneshot both drives
the scheduler and provides a correct 1 MHz monotonic clock.
Assisted-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Move the stm32l1 sources, headers and boards into arch/arm/src/stm32l1,
arch/arm/include/stm32l1 and boards/arm/stm32l1, then finalize the split:
source each split family directly in arch/arm/Kconfig and boards/Kconfig and
remove the now-empty combined arch/arm/src/stm32 and boards/arm/stm32 trees.
BREAKING CHANGE: The legacy STM32 architecture and board paths were split into
stm32f1, stm32l1, stm32f2, stm32f3, stm32f4, and stm32g4 directories.
Out-of-tree boards must move from stm32 to the matching split family.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32N6 Kconfig symbols were renamed from CONFIG_STM32N6_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32WL5 Kconfig symbols were renamed from CONFIG_STM32WL5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32WB Kconfig symbols were renamed from CONFIG_STM32WB_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32U5 Kconfig symbols were renamed from CONFIG_STM32U5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32L5 Kconfig symbols were renamed from CONFIG_STM32L5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32L4 Kconfig symbols were renamed from CONFIG_STM32L4_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32H7 Kconfig symbols were renamed from CONFIG_STM32H7_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_STM32H7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32H5 Kconfig symbols were renamed from CONFIG_STM32H5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32F7 Kconfig symbols were renamed from CONFIG_STM32F7_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_STM32F7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32F0/L0/G0/C0 Kconfig symbols were renamed from
CONFIG_STM32F0L0G0_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs
and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the
family-to-common pattern:
CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.
Signed-off-by: raiden00pl <raiden00@railab.me>
Add the shared STM32 Kconfig include and introduce the hidden
common ARCH_CHIP_STM32 selector used by concrete STM32 families.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: Convert the legacy STM32 F1/F2/F3/F4/G4/L1 port to the concrete
family selectors while keeping the shared STM32 selector hidden.
Legacy STM32 family selector Kconfig symbols were split by
concrete STM32 sub-family. Out-of-tree defconfigs and code must update
CONFIG_ARCH_CHIP_* selections to the new family-specific selectors.
Signed-off-by: raiden00pl <raiden00@railab.me>
This commit introduces basic support for running NuttX on
main domain R5F core of TI AM67 chips, including irq, mpu, pinmux,
timer, and serial configurations. Currently only UART console is
supported. NuttX can be loaded into R5F core from U-Boot or Linux
via RemoteProc.
Co-authored-by: Emre Cecanpunar <emreleno@gmail.com>
Co-authored-by: Abdullah Türkmen <abdullahturkmen@protonmail.com>
Co-authored-by: Muhammet Onur Bayraktar <mobayraktar@t3gemstone.org>
Co-authored-by: Bayram Akay <bakay@t3gemstone.org>
Signed-off-by: Erkan Vatan <evatan@t3gemstone.org>
Introduce minimal chip support for the STMicro STM32N6 family
(Cortex-M55, ARMv8.1-M with TrustZone and FPU), sufficient to bring
up an NSH console over USART1.
Scope (deliberately minimal first drop):
- Chip selector ARCH_CHIP_STM32N6 wired into arch/arm/Kconfig and
chip-name mapping ("stm32n6").
- Sub-Kconfig under arch/arm/src/stm32n6 with the STM32N657X0 chip
selector and a single user-selectable USART (USART1).
- Boot path: stm32_start with a naked dispatcher that clears the
boot-ROM MSPLIM/PSPLIM stack limits before any compiler-emitted
prologue, then runs vector relocation and SRAM-only heap init.
The chip runs entirely in the Secure state; SAU is left in its
reset configuration.
- PLL1-based clock tree fed from HSI64 targeting 200 MHz CPU, with
USART1 kernel-clock routed to HSI for a predictable BRR that is
independent of any later clock change.
- Low-level USART driver with full serial framework support.
stm32_serial.c is adapted from arch/arm/src/stm32h5/stm32_serial.c
(sibling ARMv8-M Mainline port with the same USART IP), stripped
of DMA-RX, LPUART, the per-USART2..5 plumbing, RS-485 driver-enable,
TIOCSINVERT/SWAP and HALFDUPLEX paths.
- SysTick system timer.
- GPIO, PWR and RCC helpers.
TrustZone, MPU, I/D-cache and Helium (MVE) are left disabled to
minimise bring-up surface; these will be added in follow-up patches
alongside the drivers that need them.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
BREAKING CHANGE: remove PWM_MULTICHAN option
PWM_MULTICHAN option is redundant, we can just set CONFIG_PWM_NCHANNELS > 1.
At default CONFIG_PWM_NCHANNELS is set to 1, so the default behavior is preserved.
Access to single channel API is now `info->channels[0].XXX` instead of `info->XXX`
This is the first step to simplify PWM implementation and make it more portable.
Signed-off-by: raiden00pl <raiden00@railab.me>
Add initial HT32F491x3 support with startup, IRQ handling,
serial console, GPIO helpers, custom vectors, and CMake build files.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
This change enables performance monitoring unit (PMU) access from userspace
on ARMv7-R architecture by adding CONFIG_ARCH_HAVE_PERF_EVENTS_USER_ACCESS
support and building PMU code for userspace when needed.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
On a system with multiple CPU cores, when the system is powered on,
multiple cores may start running simultaneously. In this case, software
is required to handle the startup logic for multi-core synchronization.
One approach is to use global variables.
however, the global variable region may not have been initialized yet.
In such scenarios, we can use a busywait flag to
implement the synchronization strategy.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In the toolchain, ARCH_TOOLCHAIN_XXX is used to select the compiler to be used. If clang is selected here, subsequent errors will occur
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Support hardware debugging of ARM architecture, and support smp mode.We can use "up_debugpoint_add" or "up_debugpoint_remove" to add breakpoints, and the hardware will jump into the interrupt after detecting it.
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
Add basic support for RA4M1.
The following perpheral are added:
* GPIO
* SCI (UART)
* Clock (Just internal clock - HOCO)
Signed-off-by: leocafonso <leocafonso@gmail.com>
This adds minimal support for NXP MCX-N236 CPU. Peripherals supported are:
- GPIO
- PINMUX
- CLOCK
- LPUART
An example board, FRDM-MCXN236 is also added, with a basic profile that
boots into nsh.
Signed-off-by: Ville Juven <ville.juven@unikie.com>
This selects ARM_THUMB for ARMV7R per ARM document:
https://developer.arm.com/documentation/dui0471
Thanks to hujun260 for spotting this, now ostest works.
Why it helps is still to be clarified, the `arm_signal_handler.S`
might require this THUMB option.
To keep ARM_THUMB as option, this only selects it for
PROTECTED as per anchao's suggestion.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This adds semihosting based poweroff to arm/common. It uses
semihosting operation SYS_EXIT (0x18) with parameter AppExit
(0x20026).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This moves ARM_HAVE_PSCI selection to virtual processor level as
armv7-r chips like Cortex-R5 doesn't have it.
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
This moves ARM_HAVE_NEON from QEMU ARM family level down to the
processor level as not all processors have it (e.g. Cortex R5).
Signed-off-by: Yanfeng Liu <p-liuyanfeng9@xiaomi.com>
