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!arch/stm32f0l0g0: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32F0/L0/G0/C0 Kconfig symbols were renamed from
CONFIG_STM32F0L0G0_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs
and Kconfig references to the new CONFIG_STM32_* names.

The custom clock option is a special breaking case that does not follow the
family-to-common pattern:

CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-18 18:02:30 +02:00 • committed by Alan C. Assis
parent c22a3d67d6
commit f08267ce4c
136 changed files with 2775 additions and 3084 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/Kconfig
View file

@ -593,18 +593,21 @@ config ARCH_CHIP_STM32L1
config ARCH_CHIP_STM32F0
bool "STMicro STM32 F0"
select ARCH_CHIP_STM32
select ARCH_CORTEXM0
---help---
STMicro STM32F0 architectures (ARM Cortex-M0).
config ARCH_CHIP_STM32L0
bool "STMicro STM32 L0"
select ARCH_CHIP_STM32
select ARCH_CORTEXM0
---help---
STMicro STM32L0 architectures (ARM Cortex-M0+).
config ARCH_CHIP_STM32G0
bool "STMicro STM32 G0"
select ARCH_CHIP_STM32
select ARCH_CORTEXM0
select ARCH_HAVE_PROGMEM
---help---
@ -612,6 +615,7 @@ config ARCH_CHIP_STM32G0
config ARCH_CHIP_STM32C0
bool "STMicro STM32 C0"
select ARCH_CHIP_STM32
select ARCH_CORTEXM0
---help---
STMicro STM32C0 architectures (ARM Cortex-M0+).

4
arch/arm/include/stm32f0l0g0/stm32g0_irq.h
View file

@ -80,8 +80,8 @@
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */
#if defined(CONFIG_STM32F0L0G0_STM32G0BX) || \
defined(CONFIG_STM32F0L0G0_STM32G0C1)
#if defined(CONFIG_STM32_STM32G0BX) || \
defined(CONFIG_STM32_STM32G0C1)
# define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */
# define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */
# define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */

40
arch/arm/src/stm32f0l0g0/CMakeLists.txt
View file

@ -35,15 +35,15 @@ list(
stm32_rcc.c
stm32_uid.c)
if(CONFIG_STM32F0L0G0_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK)
if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK)
list(APPEND SRCS stm32_lse.c)
endif()
if(CONFIG_STM32F0L0G0_DMA)
if(CONFIG_STM32_DMA)
list(APPEND SRCS stm32_dma.c)
endif()
if(CONFIG_STM32F0L0G0_PWR)
if(CONFIG_STM32_PWR)
list(APPEND SRCS stm32_pwr.c)
endif()
@ -59,11 +59,11 @@ if(CONFIG_BUILD_PROTECTED)
list(APPEND SRCS stm32_userspace.c)
endif()
if(CONFIG_STM32F0L0G0_PROGMEM)
if(CONFIG_STM32_PROGMEM)
list(APPEND SRCS stm32_flash.c)
endif()
if(CONFIG_STM32F0L0G0_GPIOIRQ)
if(CONFIG_STM32_GPIOIRQ)
list(APPEND SRCS stm32_gpioint.c)
endif()
@ -71,59 +71,59 @@ if(CONFIG_ARCH_IRQPRIO)
list(APPEND SRCS stm32_irqprio.c)
endif()
if(CONFIG_STM32F0L0G0_HAVE_HSI48)
if(CONFIG_STM32_HAVE_HSI48)
list(APPEND SRCS stm32_hsi48.c)
endif()
if(CONFIG_STM32F0L0G0_USB)
if(CONFIG_STM32_USB)
list(APPEND SRCS stm32_usbdev.c)
endif()
if(CONFIG_STM32F0L0G0_I2C)
if(CONFIG_STM32_I2C)
list(APPEND SRCS stm32_i2c.c)
endif()
if(CONFIG_STM32F0L0G0_SPI)
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi.c)
endif()
if(CONFIG_STM32F0L0G0_PWM)
if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
if(CONFIG_PULSECOUNT AND CONFIG_STM32F0L0G0_TIM1_PULSECOUNT)
if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
if(CONFIG_STM32F0L0G0_ADC)
if(CONFIG_STM32_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_STM32F0L0G0_AES)
if(CONFIG_STM32_AES)
list(APPEND SRCS stm32_aes.c)
endif()
if(CONFIG_STM32F0L0G0_RNG)
if(CONFIG_STM32_RNG)
list(APPEND SRCS stm32_rng.c)
endif()
if(CONFIG_STM32F0L0G0_TIM)
if(CONFIG_STM32_TIM)
list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c)
endif()
if(CONFIG_STM32F0L0G0_IWDG)
if(CONFIG_STM32_IWDG)
list(APPEND SRCS stm32_iwdg.c)
endif()
if(CONFIG_STM32F0L0G0_WWDG)
if(CONFIG_STM32_WWDG)
list(APPEND SRCS stm32_wwdg.c)
endif()
if(CONFIG_STM32F0L0G0_FDCAN)
if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER)
if(CONFIG_STM32_FDCAN)
if(CONFIG_STM32_FDCAN_CHARDRIVER)
list(APPEND SRCS stm32_fdcan.c)
endif()
if(CONFIG_STM32F0L0G0_FDCAN_SOCKET)
if(CONFIG_STM32_FDCAN_SOCKET)
list(APPEND SRCS stm32_fdcan_sock.c)
endif()
endif()

2545
arch/arm/src/stm32f0l0g0/Kconfig
View file

File diff suppressed because it is too large Load diff

40
arch/arm/src/stm32f0l0g0/Make.defs
View file

@ -25,15 +25,15 @@ include armv6-m/Make.defs
CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c
ifneq ($(CONFIG_STM32F0L0G0_RTC_LSECLOCK)$(CONFIG_STM32F0L0G0_LCD_LSECLOCK),)
ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),)
CHIP_CSRCS += stm32_lse.c
endif
ifeq ($(CONFIG_STM32F0L0G0_DMA),y)
ifeq ($(CONFIG_STM32_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
ifeq ($(CONFIG_STM32F0L0G0_PWR),y)
ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_pwr.c
endif
@ -49,69 +49,69 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace.c
endif
ifeq ($(CONFIG_STM32F0L0G0_PROGMEM),y)
ifeq ($(CONFIG_STM32_PROGMEM),y)
CHIP_CSRCS += stm32_flash.c
endif
ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y)
ifeq ($(CONFIG_STM32_GPIOIRQ),y)
CHIP_CSRCS += stm32_gpioint.c
endif
ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y)
ifeq ($(CONFIG_STM32_HAVE_HSI48),y)
CHIP_CSRCS += stm32_hsi48.c
endif
ifeq ($(CONFIG_STM32F0L0G0_USB),y)
ifeq ($(CONFIG_STM32_USB),y)
CHIP_CSRCS += stm32_usbdev.c
endif
ifeq ($(CONFIG_STM32F0L0G0_I2C),y)
ifeq ($(CONFIG_STM32_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
ifeq ($(CONFIG_STM32_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32F0L0G0_PWM),y)
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_PULSECOUNT),y)
ifeq ($(CONFIG_STM32F0L0G0_TIM1_PULSECOUNT),y)
ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
endif
ifeq ($(CONFIG_STM32F0L0G0_ADC),y)
ifeq ($(CONFIG_STM32_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32F0L0G0_AES),y)
ifeq ($(CONFIG_STM32_AES),y)
CHIP_CSRCS += stm32_aes.c
endif
ifeq ($(CONFIG_STM32F0L0G0_RNG),y)
ifeq ($(CONFIG_STM32_RNG),y)
CHIP_CSRCS += stm32_rng.c
endif
ifeq ($(CONFIG_STM32F0L0G0_TIM),y)
ifeq ($(CONFIG_STM32_TIM),y)
CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c
endif
ifeq ($(CONFIG_STM32F0L0G0_IWDG),y)
ifeq ($(CONFIG_STM32_IWDG),y)
CHIP_CSRCS += stm32_iwdg.c
endif
ifeq ($(CONFIG_STM32F0L0G0_WWDG),y)
ifeq ($(CONFIG_STM32_WWDG),y)
CHIP_CSRCS += stm32_wwdg.c
endif
ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y)
ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y)
ifeq ($(CONFIG_STM32_FDCAN),y)
ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
CHIP_CSRCS += stm32_fdcan.c
endif
ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y)
ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y)
CHIP_CSRCS += stm32_fdcan_sock.c
endif
endif

6
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
View file

@ -49,7 +49,7 @@
/* Support for ADC clock prescaler */
#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0)
#if defined(CONFIG_STM32_STM32L0) || defined(CONFIG_STM32_STM32G0)
# define HAVE_ADC_PRE
#else
# undef HAVE_ADC_PRE
@ -57,7 +57,7 @@
/* Support for LCD voltage */
#ifdef CONFIG_STM32F0L0G0_HAVE_LCD
#ifdef CONFIG_STM32_HAVE_LCD
# define HAVE_ADC_VLCD
#else
# undef HAVE_ADC_VLCD
@ -65,7 +65,7 @@
/* Support for Low frequency mode */
#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
#ifdef CONFIG_STM32_ENERGYLITE
# define HAVE_ADC_LFM
#else
# undef HAVE_ADC_LFM

4
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
View file

@ -151,9 +151,9 @@
/* Import DMAMUX map */
#if defined(CONFIG_STM32F0L0G0_STM32G0)
#if defined(CONFIG_STM32_STM32G0)
# include "hardware/stm32g0_dmamux.h"
#elif defined(CONFIG_STM32F0L0G0_STM32C0)
#elif defined(CONFIG_STM32_STM32C0)
# include "hardware/stm32c0_dmamux.h"
#else
# error "Unsupported STM32 M0 sub family"

8
arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0G0_STM32F03X)
#if defined(CONFIG_STM32_STM32F03X)
# include "hardware/stm32f03x_memorymap.h"
#elif defined(CONFIG_STM32F0L0G0_STM32F05X) || \
defined(CONFIG_STM32F0L0G0_STM32F07X) || \
defined(CONFIG_STM32F0L0G0_STM32F09X)
#elif defined(CONFIG_STM32_STM32F05X) || \
defined(CONFIG_STM32_STM32F07X) || \
defined(CONFIG_STM32_STM32F09X)
# include "hardware/stm32f05xf07xf09x_memorymap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include "hardware/stm32l0_memorymap.h"

8
arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
View file

@ -30,13 +30,13 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0G0_STM32F03X)
#if defined(CONFIG_STM32_STM32F03X)
# include "hardware/stm32f03x_pinmap.h"
#elif defined(CONFIG_STM32F0L0G0_STM32F05X)
#elif defined(CONFIG_STM32_STM32F05X)
# include "hardware/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0L0G0_STM32F07X)
#elif defined(CONFIG_STM32_STM32F07X)
# include "hardware/stm32f07x_pinmap.h"
#elif defined(CONFIG_STM32F0L0G0_STM32F09X)
#elif defined(CONFIG_STM32_STM32F09X)
# include "hardware/stm32f09x_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32L0)
# include "hardware/stm32l0_pinmap.h"

8
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
View file

@ -32,11 +32,11 @@
/* Select STM32 SPI IP core */
#if defined(CONFIG_STM32F0L0G0_STM32F0) || \
defined(CONFIG_STM32F0L0G0_STM32G0) || \
defined(CONFIG_STM32F0L0G0_STM32C0)
#if defined(CONFIG_STM32_STM32F0) || \
defined(CONFIG_STM32_STM32G0) || \
defined(CONFIG_STM32_STM32C0)
# define HAVE_IP_SPI_V2
#elif defined(CONFIG_STM32F0L0G0_STM32L0)
#elif defined(CONFIG_STM32_STM32L0)
# define HAVE_IP_SPI_V1
#else
# error Unsupported family

2
arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
View file

@ -41,7 +41,7 @@
#if defined(CONFIG_ARCH_CHIP_STM32L0)
# define HAVE_TIM2_16BIT 1
# undef HAVE_TIM2_32BIT
#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32F09X)
#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32_STM32F09X)
# define HAVE_TIM2_32BIT 1
# undef HAVE_TIM2_16BIT
#else

4
arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
View file

@ -30,9 +30,9 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "hardware/stm32_uart_v1.h"
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "hardware/stm32_uart_v2.h"
#else
# error "Unsupported STM32 M0 USART"

4
arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include <chip.h>
#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV
#ifdef CONFIG_STM32_HAVE_USBDEV
/****************************************************************************
* Pre-processor Definitions
@ -251,5 +251,5 @@
#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */
#endif /* CONFIG_STM32_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */

116
arch/arm/src/stm32f0l0g0/stm32_adc.c
View file

@ -54,13 +54,13 @@
/* STM32 ADC "lower-half" support must be enabled */
#ifdef CONFIG_STM32F0L0G0_ADC
#ifdef CONFIG_STM32_ADC
/* Some ADC peripheral must be enabled */
#if defined(CONFIG_STM32F0L0G0_ADC1)
#if defined(CONFIG_STM32_ADC1)
#if defined(CONFIG_STM32F0L0G0_STM32F0)
#if defined(CONFIG_STM32_STM32F0)
# error Not tested
#endif
@ -90,11 +90,11 @@
/* C0 and G0 support additional sample time selection 2 */
#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0)
#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0)
# define ADC_HAVE_SMPR_SMP2
#endif
#if defined(ADC_HAVE_DMA) || (CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES == 1)
#if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1)
# if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0)
# define ADC_SMP1_DEFAULT ADC_SMPR_12p5
# define ADC_SMP2_DEFAULT ADC_SMPR_12p5
@ -121,10 +121,10 @@
* (ST manual)
*/
#if defined(CONFIG_STM32F0L0G0_STM32F0) || \
defined(CONFIG_STM32F0L0G0_STM32L0) || \
defined(CONFIG_STM32F0L0G0_STM32C0) || \
defined(CONFIG_STM32F0L0G0_STM32G0)
#if defined(CONFIG_STM32_STM32F0) || \
defined(CONFIG_STM32_STM32L0) || \
defined(CONFIG_STM32_STM32C0) || \
defined(CONFIG_STM32_STM32G0)
# define ADC_CHANNELS_NUMBER 19
#else
# error "Not supported"
@ -155,7 +155,7 @@
#define ADC_HAVE_DMACFG 1
#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32L0)
#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32L0)
# ifndef ANIOC_SET_OVERSAMPLE
# define ANIOC_SET_OVERSAMPLE _ANIOC(0x0f)
# endif
@ -181,10 +181,10 @@ struct adccmn_data_s
struct stm32_dev_s
{
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */
#endif
#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA)
#if !defined(CONFIG_STM32_ADC_NOIRQ) | defined(ADC_HAVE_DMA)
const struct adc_callback_s *cb;
uint8_t irq; /* Interrupt generated by this ADC block */
#endif
@ -206,7 +206,7 @@ struct stm32_dev_s
bool hasdma; /* True: This channel supports DMA */
uint16_t dmabatch; /* Number of conversions for DMA batch */
#endif
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Sample time selection. These bits must be written only when ADON=0. */
# ifdef ADC_HAVE_SMPR_SMP2
@ -242,7 +242,7 @@ struct stm32_dev_s
/* List of selected ADC channels to sample */
uint8_t r_chanlist[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES];
uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES];
};
/****************************************************************************
@ -280,10 +280,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
static int adc_interrupt(struct adc_dev_s *dev);
static int adc1_interrupt(int irq, void *context, void *arg);
#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
/* ADC Driver Methods */
@ -334,7 +334,7 @@ static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg);
static void adc_dumpregs(struct stm32_dev_s *priv);
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
static void adc_llops_intack(struct stm32_adc_dev_s *dev,
uint32_t source);
static void adc_llops_inten(struct stm32_adc_dev_s *dev,
@ -349,7 +349,7 @@ static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev,
static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev,
uint16_t *buffer, uint8_t len);
# endif
# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
static void adc_sampletime_set(struct stm32_adc_dev_s *dev,
struct adc_sample_time_s *time_samples);
static void adc_sampletime_write(struct stm32_adc_dev_s *dev);
@ -375,7 +375,7 @@ static const struct adc_ops_s g_adcops =
/* Publicly visible ADC lower-half operations */
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
static const struct stm32_adc_ops_s g_adc_llops =
{
.int_ack = adc_llops_intack,
@ -387,7 +387,7 @@ static const struct stm32_adc_ops_s g_adc_llops =
# ifdef ADC_HAVE_DMA
.regbuf_reg = adc_llops_regbufregister,
# endif
# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
.stime_set = adc_sampletime_set,
.stime_write = adc_sampletime_write,
# endif
@ -397,47 +397,47 @@ static const struct stm32_adc_ops_s g_adc_llops =
/* ADC1 state */
#ifdef CONFIG_STM32F0L0G0_ADC1
#ifdef CONFIG_STM32_ADC1
#ifdef ADC1_HAVE_DMA
static uint16_t g_adc1_dmabuffer[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES *
CONFIG_STM32F0L0G0_ADC1_DMA_BATCH];
static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC1_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv1 =
{
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
.llops = &g_adc_llops,
#endif
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
.irq = STM32_IRQ_ADC,
.isr = adc1_interrupt,
#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
#ifdef HAVE_ADC_CMN_DATA
.cmn = &ADC1CMN_DATA,
#endif
.intf = 1,
#ifdef HAVE_ADC_RESOLUTION
.resolution = CONFIG_STM32F0L0G0_ADC1_RESOLUTION,
.resolution = CONFIG_STM32_ADC1_RESOLUTION,
#endif
.base = STM32_ADC1_BASE,
#ifdef ADC1_HAVE_EXTCFG
.extcfg = ADC1_EXTCFG_VALUE,
#endif
#ifdef ADC1_HAVE_TIMER
.trigger = CONFIG_STM32F0L0G0_ADC1_TIMTRIG,
.trigger = CONFIG_STM32_ADC1_TIMTRIG,
.tbase = ADC1_TIMER_BASE,
.pclck = ADC1_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
#endif
#ifdef ADC1_HAVE_DMA
.dmachan = ADC1_DMA_CHAN,
# ifdef ADC_HAVE_DMACFG
.dmacfg = CONFIG_STM32F0L0G0_ADC1_DMA_CFG,
.dmacfg = CONFIG_STM32_ADC1_DMA_CFG,
# endif
.hasdma = true,
.r_dmabuffer = g_adc1_dmabuffer,
.dmabatch = CONFIG_STM32F0L0G0_ADC1_DMA_BATCH
.dmabatch = CONFIG_STM32_ADC1_DMA_BATCH
#endif
};
@ -1178,7 +1178,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset)
switch (priv->intf)
{
#if defined(CONFIG_STM32F0L0G0_ADC1)
#if defined(CONFIG_STM32_ADC1)
case 1:
{
adcbit = RCC_RSTR_ADC1RST;
@ -1322,7 +1322,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
static int adc_bind(struct adc_dev_s *dev,
const struct adc_callback_s *callback)
{
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv;
DEBUGASSERT(priv != NULL);
@ -1399,7 +1399,7 @@ static void adc_mode_cfg(struct stm32_dev_s *priv)
clrbits |= ADC_CFGR1_EXTEN_MASK;
setbits |= ADC_CFGR1_EXTEN_NONE;
#ifdef CONFIG_STM32F0L0G0_ADC1_CONTINUOUS
#ifdef CONFIG_STM32_ADC1_CONTINUOUS
setbits |= ADC_CFGR1_CONT;
#endif
@ -1432,7 +1432,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev)
/* Initialize the same sample time for each ADC.
* During sample cycles channel selection bits must remain unchanged.
*/
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
struct adc_sample_time_s time_samples = {
# ifdef STM32_ADC1_SMPR_SMP1
.smp1 = STM32_ADC1_SMPR_SMP1,
@ -1682,7 +1682,7 @@ static void adc_configure(struct adc_dev_s *dev)
adc_dumpregs(priv);
}
#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE
#ifdef CONFIG_STM32_ADC_OVERSAMPLE
/****************************************************************************
* Name: adc_oversample
@ -1696,10 +1696,10 @@ static void adc_oversample(struct adc_dev_s *dev)
ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK;
uint32_t setbits = ADC_CFGR2_OVSE |
(CONFIG_STM32F0L0G0_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) |
(CONFIG_STM32F0L0G0_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT);
(CONFIG_STM32_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) |
(CONFIG_STM32_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT);
# ifdef CONFIG_STM32F0L0G0_ADC_TOVS
# ifdef CONFIG_STM32_ADC_TOVS
setbits |= ADC_CFGR2_TOVS;
# endif
@ -1779,15 +1779,15 @@ static void adc_reset(struct adc_dev_s *dev)
static int adc_setup(struct adc_dev_s *dev)
{
#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \
defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV)
#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \
defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV)
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv;
#endif
int ret = OK;
/* Attach the ADC interrupt */
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
ret = irq_attach(priv->irq, priv->isr, NULL);
if (ret < 0)
{
@ -1804,7 +1804,7 @@ static int adc_setup(struct adc_dev_s *dev)
adc_configure(dev);
#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE
#ifdef CONFIG_STM32_ADC_OVERSAMPLE
adc_oversample(dev);
#endif
@ -1829,7 +1829,7 @@ static int adc_setup(struct adc_dev_s *dev)
* or later with ANIOC_TRIGGER ioctl call.
*/
#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV
/* Start regular conversion */
adc_reg_startconv(priv, true);
@ -1838,7 +1838,7 @@ static int adc_setup(struct adc_dev_s *dev)
/* Enable the ADC interrupt */
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
up_enable_irq(priv->irq);
#endif
@ -1880,7 +1880,7 @@ static void adc_shutdown(struct adc_dev_s *dev)
adc_enable(priv, false);
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
/* Disable ADC interrupts and detach the ADC interrupt handler */
up_disable_irq(priv->irq);
@ -2274,7 +2274,7 @@ static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg)
return ret;
}
#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE
#ifdef CONFIG_STM32_ADC_OVERSAMPLE
/****************************************************************************
* Name: adc_ioc_set_oversample
@ -2494,7 +2494,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
break;
}
#if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE)
#if defined(CONFIG_STM32_ADC_OVERSAMPLE)
case ANIOC_SET_OVERSAMPLE:
{
ret = adc_ioc_set_oversample(dev, arg);
@ -2513,7 +2513,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
return ret;
}
#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
/****************************************************************************
* Name: adc_interrupt
@ -2620,9 +2620,9 @@ static int adc1_interrupt(int irq, void *context, void *arg)
return OK;
}
#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
/****************************************************************************
* Name: adc_llops_intack
@ -2736,7 +2736,7 @@ static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev,
}
#endif /* ADC_HAVE_DMA */
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/****************************************************************************
* Name: adc_sampletime_write
*
@ -2796,7 +2796,7 @@ static void adc_sampletime_set(struct stm32_adc_dev_s *dev,
priv->smpsel = time_samples->smpsel;
#endif
}
#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */
#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */
/****************************************************************************
* Name: adc_llops_dumpregs
@ -2809,7 +2809,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev)
adc_dumpregs(priv);
}
#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */
#endif /* CONFIG_STM32_ADC_LL_OPS */
/****************************************************************************
* Public Functions
@ -2841,7 +2841,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
switch (intf)
{
#ifdef CONFIG_STM32F0L0G0_ADC1
#ifdef CONFIG_STM32_ADC1
case 1:
{
ainfo("ADC1 selected\n");
@ -2862,7 +2862,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
priv = (struct stm32_dev_s *)dev->ad_priv;
priv->cb = NULL;
DEBUGASSERT(channels <= CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES);
DEBUGASSERT(channels <= CONFIG_STM32_ADC_MAX_SAMPLES);
priv->cr_channels = channels;
memcpy(priv->r_chanlist, chanlist, channels);
@ -2878,5 +2878,5 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
return dev;
}
#endif /* CONFIG_STM32F0L0G0_ADC1 */
#endif /* CONFIG_STM32F0L0G0_ADC */
#endif /* CONFIG_STM32_ADC1 */
#endif /* CONFIG_STM32_ADC */

118
arch/arm/src/stm32f0l0g0/stm32_adc.h
View file

@ -43,45 +43,45 @@
/* Configuration ************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* to control periodic ADC sampling. If CONFIG_STM32F0L0G0_TIMn is defined
* then CONFIG_STM32F0L0G0_TIMn_ADC must also be defined to indicate that
* to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined
* then CONFIG_STM32_TIMn_ADC must also be defined to indicate that
* timer "n" is intended to be used for that purpose. Timers 1-6 and 8 may
* be used.
*/
#ifndef CONFIG_STM32F0L0G0_TIM1
# undef CONFIG_STM32F0L0G0_TIM1_ADC
# undef CONFIG_STM32F0L0G0_TIM1_ADC1
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_ADC
# undef CONFIG_STM32_TIM1_ADC1
#endif
#ifndef CONFIG_STM32F0L0G0_TIM2
# undef CONFIG_STM32F0L0G0_TIM2_ADC
# undef CONFIG_STM32F0L0G0_TIM2_ADC1
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_ADC
# undef CONFIG_STM32_TIM2_ADC1
#endif
#ifndef CONFIG_STM32F0L0G0_TIM3
# undef CONFIG_STM32F0L0G0_TIM3_ADC
# undef CONFIG_STM32F0L0G0_TIM3_ADC1
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_ADC
# undef CONFIG_STM32_TIM3_ADC1
#endif
#ifndef CONFIG_STM32F0L0G0_TIM15
# undef CONFIG_STM32F0L0G0_TIM15_ADC
# undef CONFIG_STM32F0L0G0_TIM15_ADC1
#ifndef CONFIG_STM32_TIM15
# undef CONFIG_STM32_TIM15_ADC
# undef CONFIG_STM32_TIM15_ADC1
#endif
/* Up to 1 ADC interfaces are supported */
#if STM32_NADC < 1
# undef CONFIG_STM32F0L0G0_ADC1
# undef CONFIG_STM32_ADC1
#endif
#if defined(CONFIG_STM32F0L0G0_ADC1)
#if defined(CONFIG_STM32_ADC1)
/* DMA support */
#undef ADC_HAVE_DMA
#if defined(CONFIG_STM32F0L0G0_ADC1_DMA)
#if defined(CONFIG_STM32_ADC1_DMA)
# define ADC_HAVE_DMA 1
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1_DMA
#ifdef CONFIG_STM32_ADC1_DMA
# define ADC1_HAVE_DMA 1
#else
# undef ADC1_HAVE_DMA
@ -91,19 +91,19 @@
* information about the timer.
*/
#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1)
#if defined(CONFIG_STM32_TIM1_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM1_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1)
#elif defined(CONFIG_STM32_TIM2_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM2_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1)
#elif defined(CONFIG_STM32_TIM3_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM3_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1)
#elif defined(CONFIG_STM32_TIM15_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM15_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN
@ -112,11 +112,11 @@
#endif
#ifdef ADC1_HAVE_TIMER
# ifndef CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY not defined"
# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32F0L0G0_ADC1_TIMTRIG
# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG not defined"
# ifndef CONFIG_STM32_ADC1_TIMTRIG
# error "CONFIG_STM32_ADC1_TIMTRIG not defined"
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2"
# endif
#endif
@ -129,7 +129,7 @@
/* EXTSEL */
#if defined(CONFIG_STM32F0L0G0_STM32F0)
#if defined(CONFIG_STM32_STM32F0)
# define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -139,7 +139,7 @@
* TRG6 reserved
* TRG7 reserved
*/
#elif defined(CONFIG_STM32F0L0G0_STM32L0)
#elif defined(CONFIG_STM32_STM32L0)
/* TRG0 reserved */
# define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -148,7 +148,7 @@
# define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5
/* TRG6 reserved */
# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7
#elif defined(CONFIG_STM32F0L0G0_STM32G0)
#elif defined(CONFIG_STM32_STM32G0)
# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -156,7 +156,7 @@
# define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4
/* TRG5 and TRG6 reserved */
# define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7
#elif defined(CONFIG_STM32F0L0G0_STM32C0)
#elif defined(CONFIG_STM32_STM32C0)
# define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0
# define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1
# define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2
@ -171,49 +171,49 @@
/* EXTSEL configuration *****************************************************/
/* NOTE:
* this configuration if used only if CONFIG_STM32F0L0G0_TIMx_ADCy is
* this configuration if used only if CONFIG_STM32_TIMx_ADCy is
* selected.
* You can still connect the ADC with a timer trigger using the
* CONFIG_STM32F0L0G0_ADCx_EXTSEL option.
* CONFIG_STM32_ADCx_EXTSEL option.
*/
#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1)
# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3
#if defined(CONFIG_STM32_TIM1_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 5
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
# else
# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1)
# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3
#elif defined(CONFIG_STM32_TIM2_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4
# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
# else
# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1)
# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM3_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
# else
# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1)
# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM15_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO
# else
# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F0L0G0_TIM21_ADC1)
# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 1
#elif defined(CONFIG_STM32_TIM21_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21CC2
# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21TRGO
# else
# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#endif
@ -222,7 +222,7 @@
#ifdef ADC1_EXTSEL_VALUE
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32F0L0G0_ADC1_EXTSEL)
#elif defined(CONFIG_STM32_ADC1_EXTSEL)
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE 0
#else
@ -322,9 +322,9 @@ enum stm32_adc_resoluton_e
ADC_RESOLUTION_6BIT = 3 /* 6 bit */
};
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
struct adc_sample_time_s
{
@ -332,7 +332,7 @@ struct adc_sample_time_s
uint8_t smp2; /* Sample time for channels with SMPSEL bit = 1 */
uint32_t smpsel; /* Bitmask for selecting which channels use SMP2 */
};
#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */
#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */
/* This structure provides the publicly visible representation of the
* "lower-half" ADC driver structure.
@ -380,7 +380,7 @@ struct stm32_adc_ops_s
void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state);
#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Set ADC sample time */
void (*stime_set)(struct stm32_adc_dev_s *dev,
@ -394,7 +394,7 @@ struct stm32_adc_ops_s
void (*dump_regs)(struct stm32_adc_dev_s *dev);
};
#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */
#endif /* CONFIG_STM32_ADC_LL_OPS */
/****************************************************************************
* Public Function Prototypes
@ -433,7 +433,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
* Name: stm32_adc_llops_get
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
const struct stm32_adc_ops_s
*stm32_adc_llops_get(struct adc_dev_s *dev);
#endif
@ -444,5 +444,5 @@ const struct stm32_adc_ops_s
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F0L0G0_ADC1 */
#endif /* CONFIG_STM32_ADC1 */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */

2
arch/arm/src/stm32f0l0g0/stm32_dma.c
View file

@ -28,7 +28,7 @@
#include "chip.h"
#if defined(CONFIG_STM32F0L0G0_HAVE_DMAMUX)
#if defined(CONFIG_STM32_HAVE_DMAMUX)
# include "stm32_dma_v1mux.c"
#else
# include "stm32_dma_v1.c"

4
arch/arm/src/stm32f0l0g0/stm32_dma.h
View file

@ -32,7 +32,7 @@
#include "hardware/stm32_dma_v1.h"
#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX
#ifdef CONFIG_STM32_HAVE_DMAMUX
# include "hardware/stm32_dmamux.h"
#endif
@ -238,7 +238,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
#else
# define stm32_dmacapable(maddr, count, ccr) (true)

4
arch/arm/src/stm32f0l0g0/stm32_dma_v1.c
View file

@ -51,7 +51,7 @@
* the DMA requests for each channel.
*/
#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX
#ifdef CONFIG_STM32_HAVE_DMAMUX
# error DMAMUX not supported here. Look at stm32_dma_v1mux.c
#endif
@ -628,7 +628,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr)
{
uint32_t transfer_size;

60
arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c
View file

@ -50,20 +50,20 @@
#define DMAMUX_NUM 1
#define DMA_CONTROLLERS 2
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
# if defined(CONFIG_ARCH_CHIP_STM32C0) || \
defined(CONFIG_STM32F0L0G0_STM32G03X) || \
defined(CONFIG_STM32F0L0G0_STM32G041)
defined(CONFIG_STM32_STM32G03X) || \
defined(CONFIG_STM32_STM32G041)
# define DMA1_NCHAN 5
# define DMA2_NCHAN 0
# elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \
defined(CONFIG_STM32F0L0G0_STM32G061) || \
defined(CONFIG_STM32F0L0G0_STM32G07X) || \
defined(CONFIG_STM32F0L0G0_STM32G081)
# elif defined(CONFIG_STM32_STM32G05X) || \
defined(CONFIG_STM32_STM32G061) || \
defined(CONFIG_STM32_STM32G07X) || \
defined(CONFIG_STM32_STM32G081)
# define DMA1_NCHAN 7
# define DMA2_NCHAN 0
# elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \
defined(CONFIG_STM32F0L0G0_STM32G0C1)
# elif defined(CONFIG_STM32_STM32G0BX) || \
defined(CONFIG_STM32_STM32G0C1)
# define DMA1_NCHAN 7
# define DMA2_NCHAN 5
# else
@ -86,16 +86,16 @@
/* DMAMUX channels */
#if defined(CONFIG_ARCH_CHIP_STM32C0) || \
defined(CONFIG_STM32F0L0G0_STM32G03X) || \
defined(CONFIG_STM32F0L0G0_STM32G041)
defined(CONFIG_STM32_STM32G03X) || \
defined(CONFIG_STM32_STM32G041)
# define DMAMUX_NCHANNELS 5
#elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \
defined(CONFIG_STM32F0L0G0_STM32G061) || \
defined(CONFIG_STM32F0L0G0_STM32G07X) || \
defined(CONFIG_STM32F0L0G0_STM32G081)
#elif defined(CONFIG_STM32_STM32G05X) || \
defined(CONFIG_STM32_STM32G061) || \
defined(CONFIG_STM32_STM32G07X) || \
defined(CONFIG_STM32_STM32G081)
# define DMAMUX_NCHANNELS 7
#elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \
defined(CONFIG_STM32F0L0G0_STM32G0C1)
#elif defined(CONFIG_STM32_STM32G0BX) || \
defined(CONFIG_STM32_STM32G0C1)
# define DMAMUX_NCHANNELS 12
#else
# error "Unknown chip for DMAMUX channel count"
@ -191,7 +191,7 @@ struct stm32_dma_ops_s
* Private Functions
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2)
#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
static void stm32_dma12_disable(DMA_CHANNEL dmachan);
static int stm32_dma12_interrupt(int irq, void *context, void *arg);
static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr,
@ -237,7 +237,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first,
static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
{
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* 0 - DMA1 */
{
@ -257,7 +257,7 @@ static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
},
#endif
#ifdef CONFIG_STM32F0L0G0_DMA2
#ifdef CONFIG_STM32_DMA2
/* 1 - DMA2 */
{
@ -293,7 +293,7 @@ static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] =
static const struct stm32_dma_s g_dma[DMA_NCHANNELS] =
{
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* 0 - DMA1 */
{
@ -305,7 +305,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] =
},
#endif
#ifdef CONFIG_STM32F0L0G0_DMA2
#ifdef CONFIG_STM32_DMA2
/* 1 - DMA2 */
{
@ -322,7 +322,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] =
static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] =
{
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA1 */
{
@ -396,7 +396,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] =
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA2 */
{
@ -628,7 +628,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first,
* DMA controller functions
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2)
#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
/****************************************************************************
* Name: stm32_dma12_disable
@ -680,14 +680,14 @@ static int stm32_dma12_interrupt(int irq, void *context, void *arg)
if (0)
{
}
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
{
channel = irq - STM32_IRQ_DMA1CH1;
controller = DMA1;
}
#endif
#ifdef CONFIG_STM32F0L0G0_DMA2
#ifdef CONFIG_STM32_DMA2
else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
{
channel = irq - STM32_IRQ_DMA2CH1;
@ -753,7 +753,7 @@ static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr,
" ntransfers: %zd ccr: %08" PRIx32 "\n",
paddr, maddr, ntransfers, ccr);
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr));
#endif
@ -942,7 +942,7 @@ static void stm32_dma12_dump(DMA_HANDLE handle,
}
#endif
#endif /* CONFIG_STM32F0L0G0_DMA1 || CONFIG_STM32F0L0G0_DMA2 */
#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */
/****************************************************************************
* Name: stm32_dmamux_sample
@ -1334,7 +1334,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
{
unsigned int msize_shift;

6
arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
View file

@ -44,7 +44,7 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
#if defined(CONFIG_STM32_HAVE_IP_EXTI_V2)
# define STM32_EXTI_FTSR STM32_EXTI_FTSR1
# define STM32_EXTI_RTSR STM32_EXTI_RTSR1
# define STM32_EXTI_IMR STM32_EXTI_IMR1
@ -77,7 +77,7 @@ static struct gpio_callback_s g_gpio_callbacks[16];
* Interrupt Service Routines - Dispatchers
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1)
static int stm32_exti_multiisr(int irq, void *context, void *arg,
int first, int last)
{
@ -121,7 +121,7 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg,
return ret;
}
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2)
static int stm32_exti_multiisr(int irq, void *context, void *arg,
int first, int last)
{

64
arch/arm/src/stm32f0l0g0/stm32_fdcan.c
View file

@ -72,7 +72,7 @@
# define FDCAN_MSGRAM_WORDS (212)
# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000)
# ifdef CONFIG_STM32F0L0G0_FDCAN1
# ifdef CONFIG_STM32_FDCAN1
# define FDCAN1_STDFILTER_SIZE (28)
# define FDCAN1_EXTFILTER_SIZE (8)
# define FDCAN1_RXFIFO0_SIZE (3)
@ -93,16 +93,16 @@
/* FDCAN1 Configuration *****************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Bit timing */
# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1)
# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1)
# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1)
# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1)
# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \
((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \
CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1)
# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1)
CONFIG_STM32_FDCAN1_BITRATE)) - 1)
# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1)
# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX
# error Invalid FDCAN1 NTSEG1
@ -117,19 +117,19 @@
# error Invalid FDCAN1 NBRP
# endif
# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS
# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1)
# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1)
# ifdef CONFIG_STM32_FDCAN1_FD_BRS
# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1)
# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1)
# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \
((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \
CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1)
# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1)
CONFIG_STM32_FDCAN1_DBITRATE)) - 1)
# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1)
# else
# define FDCAN1_DTSEG1 1
# define FDCAN1_DTSEG2 1
# define FDCAN1_DBRP 1
# define FDCAN1_DSJW 1
# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */
# endif /* CONFIG_STM32_FDCAN1_FD_BRS */
# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX
# error Invalid FDCAN1 DTSEG1
@ -156,12 +156,12 @@
# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS)
# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS)
#endif /* CONFIG_STM32F0L0G0_FDCAN1 */
#endif /* CONFIG_STM32_FDCAN1 */
/* Loopback mode */
#undef STM32_FDCAN_LOOPBACK
#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK)
#if defined(CONFIG_STM32_FDCAN1_LOOPBACK)
# define STM32_FDCAN_LOOPBACK 1
#endif
@ -243,7 +243,7 @@
/* Debug configurations that may be enabled just for testing FDCAN */
#ifndef CONFIG_DEBUG_CAN_INFO
# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
# undef CONFIG_STM32_FDCAN_REGDEBUG
#endif
/****************************************************************************
@ -348,7 +348,7 @@ struct stm32_fdcan_s
#endif
uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
uintptr_t regaddr; /* Last register address read */
uint32_t regval; /* Last value read from the register */
unsigned int count; /* Number of times that the value was read */
@ -364,7 +364,7 @@ struct stm32_fdcan_s
static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset);
static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
uint32_t regval);
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
const char *msg);
static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
@ -441,7 +441,7 @@ static const struct can_ops_s g_fdcanops =
.co_txempty = fdcan_txempty,
};
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Message RAM allocation */
/* Constant configuration */
@ -451,7 +451,7 @@ static const struct stm32_config_s g_fdcan1const =
.rxpinset = GPIO_FDCAN1_RX,
.txpinset = GPIO_FDCAN1_TX,
.base = STM32_FDCAN1_BASE,
.baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE,
.baud = CONFIG_STM32_FDCAN1_BITRATE,
.nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) |
FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) |
FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) |
@ -463,14 +463,14 @@ static const struct stm32_config_s g_fdcan1const =
.port = 1,
.irq0 = STM32_IRQ_FDCAN1_0,
.irq1 = STM32_IRQ_FDCAN1_1,
#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC)
#if defined(CONFIG_STM32_FDCAN1_CLASSIC)
.mode = FDCAN_CLASSIC_MODE,
#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD)
#elif defined(CONFIG_STM32_FDCAN1_FD)
.mode = FDCAN_FD_MODE,
#else
.mode = FDCAN_FD_BRS_MODE,
#endif
#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT)
#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT)
.format = FDCAN_NONISO_BOSCH_V1_FORMAT,
#else
.format = FDCAN_ISO11898_1_FORMAT,
@ -486,7 +486,7 @@ static const struct stm32_config_s g_fdcan1const =
.txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE),
.txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE),
#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK
#ifdef CONFIG_STM32_FDCAN1_LOOPBACK
.loopback = true,
#endif
@ -508,7 +508,7 @@ static const struct stm32_config_s g_fdcan1const =
static struct stm32_fdcan_s g_fdcan1priv;
static struct can_dev_s g_fdcan1dev;
#endif /* CONFIG_STM32F0L0G0_FDCAN1 */
#endif /* CONFIG_STM32_FDCAN1 */
/****************************************************************************
* Private Functions
@ -528,7 +528,7 @@ static struct can_dev_s g_fdcan1dev;
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset)
{
const struct stm32_config_s *config = priv->config;
@ -608,7 +608,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
uint32_t regval)
{
@ -648,7 +648,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -694,7 +694,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -737,7 +737,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumptxregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -786,7 +786,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv)
{
const struct stm32_config_s *config = priv->config;
@ -3096,7 +3096,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv)
/* Enable FIFO/Queue mode */
regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET);
#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE
#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE
regval |= FDCAN_TXBC_TFQM;
#else
regval &= ~FDCAN_TXBC_TFQM;
@ -3185,7 +3185,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port)
/* Select FDCAN peripheral to be initialized */
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
if (port == FDCAN1)
{
/* Select the FDCAN1 device structure */

4
arch/arm/src/stm32f0l0g0/stm32_fdcan.h
View file

@ -65,7 +65,7 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER
#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
/****************************************************************************
* Name: stm32_fdcaninitialize
@ -84,7 +84,7 @@ extern "C"
struct can_dev_s *stm32_fdcaninitialize(int port);
#endif
#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET
#ifdef CONFIG_STM32_FDCAN_SOCKET
/****************************************************************************
* Name: stm32_fdcansockinitialize

66
arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c
View file

@ -93,7 +93,7 @@
# define FDCAN_MSGRAM_WORDS (212)
# define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000)
# ifdef CONFIG_STM32F0L0G0_FDCAN1
# ifdef CONFIG_STM32_FDCAN1
# define FDCAN1_STDFILTER_SIZE (28)
# define FDCAN1_EXTFILTER_SIZE (8)
# define FDCAN1_RXFIFO0_SIZE (3)
@ -114,16 +114,16 @@
/* FDCAN1 Configuration *****************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Bit timing */
# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1)
# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1)
# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1)
# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1)
# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \
((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \
CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1)
# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1)
CONFIG_STM32_FDCAN1_BITRATE)) - 1)
# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1)
# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX
# error Invalid FDCAN1 NTSEG1
@ -138,19 +138,19 @@
# error Invalid FDCAN1 NBRP
# endif
# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS
# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1)
# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1)
# ifdef CONFIG_STM32_FDCAN1_FD_BRS
# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1)
# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1)
# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \
((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \
CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1)
# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1)
CONFIG_STM32_FDCAN1_DBITRATE)) - 1)
# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1)
# else
# define FDCAN1_DTSEG1 1
# define FDCAN1_DTSEG2 1
# define FDCAN1_DBRP 1
# define FDCAN1_DSJW 1
# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */
# endif /* CONFIG_STM32_FDCAN1_FD_BRS */
# if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX
# error Invalid FDCAN1 DTSEG1
@ -177,12 +177,12 @@
# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS)
# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS)
#endif /* CONFIG_STM32F0L0G0_FDCAN1 */
#endif /* CONFIG_STM32_FDCAN1 */
/* Loopback mode */
#undef STM32_FDCAN_LOOPBACK
#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK)
#if defined(CONFIG_STM32_FDCAN1_LOOPBACK)
# define STM32_FDCAN_LOOPBACK 1
#endif
@ -259,7 +259,7 @@
/* Debug configurations that may be enabled just for testing FDCAN */
#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
# undef CONFIG_STM32_FDCAN_REGDEBUG
#endif
/****************************************************************************
@ -362,7 +362,7 @@ struct stm32_fdcan_s
#endif
uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
uintptr_t regaddr; /* Last register address read */
uint32_t regval; /* Last value read from the register */
unsigned int count; /* Number of times that the value was read */
@ -399,7 +399,7 @@ struct stm32_fdcan_s
static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset);
static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
uint32_t regval);
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
const char *msg);
static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
@ -489,7 +489,7 @@ static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Message RAM allocation */
/* Constant configuration */
@ -499,7 +499,7 @@ static const struct stm32_config_s g_fdcan1const =
.rxpinset = GPIO_FDCAN1_RX,
.txpinset = GPIO_FDCAN1_TX,
.base = STM32_FDCAN1_BASE,
.baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE,
.baud = CONFIG_STM32_FDCAN1_BITRATE,
.nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) |
FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) |
FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) |
@ -511,14 +511,14 @@ static const struct stm32_config_s g_fdcan1const =
.port = 1,
.irq0 = STM32_IRQ_FDCAN1_0,
.irq1 = STM32_IRQ_FDCAN1_1,
#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC)
#if defined(CONFIG_STM32_FDCAN1_CLASSIC)
.mode = FDCAN_CLASSIC_MODE,
#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD)
#elif defined(CONFIG_STM32_FDCAN1_FD)
.mode = FDCAN_FD_MODE,
#else
.mode = FDCAN_FD_BRS_MODE,
#endif
#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT)
#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT)
.format = FDCAN_NONISO_BOSCH_V1_FORMAT,
#else
.format = FDCAN_ISO11898_1_FORMAT,
@ -534,7 +534,7 @@ static const struct stm32_config_s g_fdcan1const =
.txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE),
.txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE),
#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK
#ifdef CONFIG_STM32_FDCAN1_LOOPBACK
.loopback = true,
#endif
@ -555,7 +555,7 @@ static const struct stm32_config_s g_fdcan1const =
static struct stm32_fdcan_s g_fdcan1priv;
#endif /* CONFIG_STM32F0L0G0_FDCAN1 */
#endif /* CONFIG_STM32_FDCAN1 */
/****************************************************************************
* Private Functions
@ -575,7 +575,7 @@ static struct stm32_fdcan_s g_fdcan1priv;
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset)
{
const struct stm32_config_s *config = priv->config;
@ -655,7 +655,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
uint32_t regval)
{
@ -695,7 +695,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -741,7 +741,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -784,7 +784,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumptxregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -833,7 +833,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv)
{
const struct stm32_config_s *config = priv->config;
@ -2567,7 +2567,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv)
/* Enable FIFO/Queue mode */
regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET);
#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE
#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE
regval |= FDCAN_TXBC_TFQM;
#else
regval &= ~FDCAN_TXBC_TFQM;
@ -2916,7 +2916,7 @@ int stm32_fdcansockinitialize(int port)
/* Select FDCAN peripheral to be initialized */
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
if (port == FDCAN1)
{
/* Select the FDCAN1 device structure */
@ -2984,7 +2984,7 @@ errout:
#if !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void)
{
#ifdef CONFIG_STM32F0L0G0_CAN1
#ifdef CONFIG_STM32_CAN1
stm32_fdcansockinitialize(FDCAN1);
#endif
}

2
arch/arm/src/stm32f0l0g0/stm32_flash.c
View file

@ -26,7 +26,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0)
#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0)
# include "stm32g0c0_flash.c"
#else
# error "Flash driver unsupported on selected chip."

8
arch/arm/src/stm32f0l0g0/stm32_gpio.c
View file

@ -40,9 +40,9 @@
#include "chip.h"
#include "stm32_gpio.h"
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1)
# include "hardware/stm32_syscfg.h"
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2)
# include "hardware/stm32_exti.h"
#endif
@ -317,7 +317,7 @@ int stm32_configgpio(uint32_t cfgset)
uint32_t regaddr;
int shift;
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1)
/* Set the bits in the SYSCFG EXTICR register */
regaddr = STM32_SYSCFG_EXTICR(pin);
@ -327,7 +327,7 @@ int stm32_configgpio(uint32_t cfgset)
regval |= (((uint32_t)port) << shift);
putreg32(regval, regaddr);
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2)
/* Set the bits in the EXTI EXTICR register */
regaddr = STM32_EXTI_EXTICR(pin);

2
arch/arm/src/stm32f0l0g0/stm32_gpio.h
View file

@ -188,7 +188,7 @@
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
#if defined (CONFIG_STM32F0L0G0_STM32F03X)
#if defined (CONFIG_STM32_STM32F03X)
# define GPIO_PORTF (4 << GPIO_PORT_SHIFT) /* GPIOF */
#else
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */

4
arch/arm/src/stm32f0l0g0/stm32_hsi48.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48
#ifdef CONFIG_STM32_HAVE_HSI48
/****************************************************************************
* Public Types
@ -92,5 +92,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc);
void stm32_disable_hsi48(void);
#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */
#endif /* CONFIG_STM32_HAVE_HSI48 */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */

92
arch/arm/src/stm32f0l0g0/stm32_i2c.c
View file

@ -153,24 +153,24 @@
*
* To use this driver, enable the following configuration variable:
*
* CONFIG_STM32F0L0G0_I2C1
* CONFIG_STM32F0L0G0_I2C2
* CONFIG_STM32F0L0G0_I2C3
* CONFIG_STM32F0L0G0_I2C4
* CONFIG_STM32_I2C1
* CONFIG_STM32_I2C2
* CONFIG_STM32_I2C3
* CONFIG_STM32_I2C4
*
* To configure the ISR timeout using fixed values
* (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n):
* (CONFIG_STM32_I2C_DYNTIMEO=n):
*
* CONFIG_STM32F0L0G0_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32F0L0G0_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks)
* CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks)
*
* To configure the ISR timeout using dynamic values
* (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y):
* (CONFIG_STM32_I2C_DYNTIMEO=y):
*
* CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE
* CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE
* (Timeout in microseconds per byte)
* CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP
* CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
* (Timeout for start/stop in milliseconds)
*
* Debugging output enabled with:
@ -243,8 +243,8 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \
defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4)
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4)
/****************************************************************************
* Pre-processor Definitions
@ -260,25 +260,25 @@
/* Interrupt wait timeout in seconds and milliseconds */
#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS)
# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0
# define CONFIG_STM32F0L0G0_I2CTIMEOMS 500 /* Default is 500 milliseconds */
#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOSEC 0
# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */
# warning "Using Default 500 Ms Timeout"
#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC)
# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS)
# define CONFIG_STM32F0L0G0_I2CTIMEOMS 0 /* User provided seconds */
#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */
#endif
/* Interrupt wait time timeout in system timer ticks */
#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS
# define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS))
#ifndef CONFIG_STM32_I2CTIMEOTICKS
# define CONFIG_STM32_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
#endif
#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS)
#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
#endif
/* Macros to convert a I2C pin to a GPIO output */
@ -448,9 +448,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv,
static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */
#endif /* CONFIG_STM32_I2C_DYNTIMEO */
static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv);
#ifdef CONFIG_I2C_TRACE
@ -490,7 +490,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
static const struct stm32_i2c_config_s stm32_i2c1_config =
{
.base = STM32_I2C1_BASE,
@ -525,7 +525,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
#ifdef CONFIG_STM32_I2C2
static const struct stm32_i2c_config_s stm32_i2c2_config =
{
.base = STM32_I2C2_BASE,
@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_I2C3
#ifdef CONFIG_STM32_I2C3
static const struct stm32_i2c_config_s stm32_i2c3_config =
{
.base = STM32_I2C3_BASE,
@ -595,7 +595,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_I2C4
#ifdef CONFIG_STM32_I2C4
static const struct stm32_i2c_config_s stm32_i2c4_config =
{
.base = STM32_I2C4_BASE,
@ -724,7 +724,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
{
size_t bytecount = 0;
@ -741,7 +741,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
* factor.
*/
return USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount);
return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
}
#endif
@ -798,12 +798,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
{
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
stm32_i2c_toticks(priv->msgc, priv->msgv));
#else
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
CONFIG_STM32F0L0G0_I2CTIMEOTICKS);
CONFIG_STM32_I2CTIMEOTICKS);
#endif
if (ret < 0)
{
@ -841,10 +841,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
/* Get the timeout value */
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = stm32_i2c_toticks(priv->msgc, priv->msgv);
#else
timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv)
/* Select a timeout */
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP);
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
#else
timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Wait as stop might still be in progress */
@ -2708,22 +2708,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port)
switch (port)
{
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
case 1:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
#ifdef CONFIG_STM32_I2C2
case 2:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C3
#ifdef CONFIG_STM32_I2C3
case 3:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C4
#ifdef CONFIG_STM32_I2C4
case 4:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
break;
@ -2810,5 +2810,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \
* CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \
* CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */

8
arch/arm/src/stm32f0l0g0/stm32_i2c.h
View file

@ -41,10 +41,10 @@
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
# if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32_I2C_DYNTIMEO
# endif
#endif

2
arch/arm/src/stm32f0l0g0/stm32_idle.c
View file

@ -83,7 +83,7 @@ void up_idle(void)
* disabled in order to save power."
*/
#ifdef CONFIG_STM32F0L0G0_GPDMA
#ifdef CONFIG_STM32_GPDMA
if (g_dma_inprogress == 0)
#endif
{

2
arch/arm/src/stm32f0l0g0/stm32_irq.c
View file

@ -217,7 +217,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
#ifdef CONFIG_STM32F0L0G0_GPIOIRQ
#ifdef CONFIG_STM32_GPIOIRQ
stm32_gpioirqinitialize();
#endif

4
arch/arm/src/stm32f0l0g0/stm32_lowputc.c
View file

@ -27,9 +27,9 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "stm32_lowputc_v1.c"
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "stm32_lowputc_v2.c"
#else
# error "Unsupported STM32 M0 serial"

10
arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
View file

@ -268,7 +268,7 @@ void stm32_lowsetup(void)
/* Setup clocking and GPIO pins for all configured USARTs */
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
/* Enable USART APB2 clock */
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
@ -284,7 +284,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
@ -300,7 +300,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
@ -316,7 +316,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
@ -332,7 +332,7 @@ void stm32_lowsetup(void)
#endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
/* Enable USART APB1 clock */
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);

22
arch/arm/src/stm32f0l0g0/stm32_pulsecount.c
View file

@ -45,7 +45,7 @@
/* This module only supports pulse count on advanced timers. */
#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
/****************************************************************************
* Pre-processor Definitions
@ -68,13 +68,13 @@
# define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN
#endif
#if CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 1
#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1
# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT
#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 2
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2
# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH2OUT
#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 3
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3
# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH3OUT
#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 4
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4
# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH4OUT
#else
# error Unsupported TIM1 pulse count channel
@ -180,14 +180,14 @@ static const struct pulsecount_ops_s g_pulsecountops =
.ioctl = stm32pulsecount_ioctl,
};
#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static struct stm32_pulsecounttimer_s g_pulsecount1dev =
{
.ops = &g_pulsecountops,
.timid = 1,
.channel =
{
.channel = CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL,
.channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL,
.pincfg = PULSECOUNT_TIM1_CHCFG,
},
.timtype = TIMTYPE_TIM1,
@ -958,7 +958,7 @@ static void stm32pulsecount_setapbclock(
switch (priv->timid)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM1EN;
@ -1166,7 +1166,7 @@ static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev)
switch (priv->timid)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM1RST;
@ -1255,7 +1255,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer)
switch (timer)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
lower = &g_pulsecount1dev;
@ -1274,4 +1274,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer)
return (struct pulsecount_lowerhalf_s *)lower;
}
#endif /* CONFIG_STM32F0L0G0_TIMx_PULSECOUNT */
#endif /* CONFIG_STM32_TIMx_PULSECOUNT */

178
arch/arm/src/stm32f0l0g0/stm32_pwm.c
View file

@ -64,10 +64,10 @@
* intended for use with the PWM upper half driver.
*/
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM17_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
/****************************************************************************
* Pre-processor Definitions
@ -98,15 +98,15 @@
/* Advanced timer */
#if defined (CONFIG_STM32F0L0G0_TIM1_PWM)
#if defined (CONFIG_STM32_TIM1_PWM)
# define HAVE_IP_TIMERS_V2 1
#endif
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM8_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM15_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM17_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || \
defined(CONFIG_STM32_TIM8_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || \
defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
# define HAVE_ADVTIM
#else
# undef HAVE_ADVTIM
@ -114,8 +114,8 @@
/* CCMR2 */
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM3_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || \
defined(CONFIG_STM32_TIM3_PWM)
# define HAVE_CCMR2
#else
# undef HAVE_CCMR2
@ -237,159 +237,159 @@ static const struct pwm_ops_s g_pwmops =
.ioctl = stm32pwm_ioctl,
};
#ifdef CONFIG_STM32F0L0G0_TIM1_PWM
#ifdef CONFIG_STM32_TIM1_PWM
static struct stm32_pwmtimer_s g_pwm1dev =
{
.ops = &g_pwmops,
.timid = 1,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1
#ifdef CONFIG_STM32_TIM1_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM1_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM1_CH1MODE,
.mode = CONFIG_STM32_TIM1_CH1MODE,
.npincfg = PWM_TIM1_CH1NCFG,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2
#ifdef CONFIG_STM32_TIM1_CHANNEL2
{
.channel = 2,
.pincfg = PWM_TIM1_CH2CFG,
.mode = CONFIG_STM32F0L0G0_TIM1_CH2MODE,
.mode = CONFIG_STM32_TIM1_CH2MODE,
.npincfg = PWM_TIM1_CH2NCFG,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3
#ifdef CONFIG_STM32_TIM1_CHANNEL3
{
.channel = 3,
.pincfg = PWM_TIM1_CH3CFG,
.mode = CONFIG_STM32F0L0G0_TIM1_CH3MODE,
.mode = CONFIG_STM32_TIM1_CH3MODE,
.npincfg = PWM_TIM1_CH3NCFG,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4
#ifdef CONFIG_STM32_TIM1_CHANNEL4
{
.channel = 4,
.pincfg = PWM_TIM1_CH4CFG,
.mode = CONFIG_STM32F0L0G0_TIM1_CH4MODE,
.mode = CONFIG_STM32_TIM1_CH4MODE,
.npincfg = 0,
},
#endif
},
.timtype = TIMTYPE_TIM1,
.mode = CONFIG_STM32F0L0G0_TIM1_MODE,
.mode = CONFIG_STM32_TIM1_MODE,
.base = STM32_TIM1_BASE,
.pclk = STM32_APB2_TIM1_CLKIN,
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_PWM
#ifdef CONFIG_STM32_TIM2_PWM
static struct stm32_pwmtimer_s g_pwm2dev =
{
.ops = &g_pwmops,
.timid = 2,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1
#ifdef CONFIG_STM32_TIM2_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM2_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM2_CH1MODE,
.mode = CONFIG_STM32_TIM2_CH1MODE,
.npincfg = 0,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2
#ifdef CONFIG_STM32_TIM2_CHANNEL2
{
.channel = 2,
.pincfg = PWM_TIM2_CH2CFG,
.mode = CONFIG_STM32F0L0G0_TIM2_CH2MODE,
.mode = CONFIG_STM32_TIM2_CH2MODE,
.npincfg = 0,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3
#ifdef CONFIG_STM32_TIM2_CHANNEL3
{
.channel = 3,
.pincfg = PWM_TIM2_CH3CFG,
.mode = CONFIG_STM32F0L0G0_TIM2_CH3MODE,
.mode = CONFIG_STM32_TIM2_CH3MODE,
.npincfg = 0,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4
#ifdef CONFIG_STM32_TIM2_CHANNEL4
{
.channel = 4,
.pincfg = PWM_TIM2_CH4CFG,
.mode = CONFIG_STM32F0L0G0_TIM2_CH4MODE,
.mode = CONFIG_STM32_TIM2_CH4MODE,
.npincfg = 0,
},
#endif
},
.timtype = TIMTYPE_TIM2,
.mode = CONFIG_STM32F0L0G0_TIM2_MODE,
.mode = CONFIG_STM32_TIM2_MODE,
.base = STM32_TIM2_BASE,
.pclk = STM32_APB1_TIM2_CLKIN,
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_PWM
#ifdef CONFIG_STM32_TIM3_PWM
static struct stm32_pwmtimer_s g_pwm3dev =
{
.ops = &g_pwmops,
.timid = 3,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1
#ifdef CONFIG_STM32_TIM3_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM3_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM3_CH1MODE,
.mode = CONFIG_STM32_TIM3_CH1MODE,
.npincfg = 0,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2
#ifdef CONFIG_STM32_TIM3_CHANNEL2
{
.channel = 2,
.pincfg = PWM_TIM3_CH2CFG,
.mode = CONFIG_STM32F0L0G0_TIM3_CH2MODE,
.mode = CONFIG_STM32_TIM3_CH2MODE,
.npincfg = 0,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3
#ifdef CONFIG_STM32_TIM3_CHANNEL3
{
.channel = 3,
.pincfg = PWM_TIM3_CH3CFG,
.mode = CONFIG_STM32F0L0G0_TIM3_CH3MODE,
.mode = CONFIG_STM32_TIM3_CH3MODE,
.npincfg = 0,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4
#ifdef CONFIG_STM32_TIM3_CHANNEL4
{
.channel = 4,
.pincfg = PWM_TIM3_CH4CFG,
.mode = CONFIG_STM32F0L0G0_TIM3_CH4MODE,
.mode = CONFIG_STM32_TIM3_CH4MODE,
.npincfg = 0,
},
#endif
},
.timtype = TIMTYPE_TIM3,
.mode = CONFIG_STM32F0L0G0_TIM3_MODE,
.mode = CONFIG_STM32_TIM3_MODE,
.base = STM32_TIM3_BASE,
.pclk = STM32_APB1_TIM3_CLKIN,
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14_PWM
#ifdef CONFIG_STM32_TIM14_PWM
static struct stm32_pwmtimer_s g_pwm14dev =
{
.ops = &g_pwmops,
.timid = 14,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1
#ifdef CONFIG_STM32_TIM14_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM14_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM14_CH1MODE,
.mode = CONFIG_STM32_TIM14_CH1MODE,
.npincfg = PWM_TIM14_CH1NCFG,
},
#endif
@ -401,26 +401,26 @@ static struct stm32_pwmtimer_s g_pwm14dev =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_PWM
#ifdef CONFIG_STM32_TIM15_PWM
static struct stm32_pwmtimer_s g_pwm15dev =
{
.ops = &g_pwmops,
.timid = 15,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1
#ifdef CONFIG_STM32_TIM15_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM15_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM15_CH1MODE,
.mode = CONFIG_STM32_TIM15_CH1MODE,
.npincfg = PWM_TIM15_CH1NCFG,
},
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2
#ifdef CONFIG_STM32_TIM15_CHANNEL2
{
.channel = 2,
.pincfg = PWM_TIM15_CH2CFG,
.mode = CONFIG_STM32F0L0G0_TIM15_CH2MODE,
.mode = CONFIG_STM32_TIM15_CH2MODE,
.npincfg = 0,
},
#endif
@ -432,18 +432,18 @@ static struct stm32_pwmtimer_s g_pwm15dev =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16_PWM
#ifdef CONFIG_STM32_TIM16_PWM
static struct stm32_pwmtimer_s g_pwm16dev =
{
.ops = &g_pwmops,
.timid = 16,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1
#ifdef CONFIG_STM32_TIM16_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM16_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM16_CH1MODE,
.mode = CONFIG_STM32_TIM16_CH1MODE,
.npincfg = PWM_TIM16_CH1NCFG,
},
#endif
@ -455,18 +455,18 @@ static struct stm32_pwmtimer_s g_pwm16dev =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17_PWM
#ifdef CONFIG_STM32_TIM17_PWM
static struct stm32_pwmtimer_s g_pwm17dev =
{
.ops = &g_pwmops,
.timid = 17,
.channels =
{
#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1
#ifdef CONFIG_STM32_TIM17_CHANNEL1
{
.channel = 1,
.pincfg = PWM_TIM17_CH1CFG,
.mode = CONFIG_STM32F0L0G0_TIM17_CH1MODE,
.mode = CONFIG_STM32_TIM17_CH1MODE,
.npincfg = PWM_TIM17_CH1NCFG,
},
#endif
@ -689,7 +689,7 @@ static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv,
stm32pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
stm32pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
stm32pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET));
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
@ -939,9 +939,9 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
* and TIMTYPE_BASIC
*/
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \
defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM)
if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16 &&
priv->timtype != TIMTYPE_COUNTUP16_N)
@ -1001,7 +1001,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv,
/* Set the advanced timer's repetition counter */
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
if (priv->timtype == TIMTYPE_ADVANCED)
{
/* If a non-zero repetition count has been selected, then set the
@ -1394,43 +1394,43 @@ static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on)
switch (priv->timid)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_PWM
#ifdef CONFIG_STM32_TIM1_PWM
case 1:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_PWM
#ifdef CONFIG_STM32_TIM2_PWM
case 2:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_PWM
#ifdef CONFIG_STM32_TIM3_PWM
case 3:
regaddr = STM32_RCC_APB1ENR;
en_bit = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14_PWM
#ifdef CONFIG_STM32_TIM14_PWM
case 14:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM14EN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_PWM
#ifdef CONFIG_STM32_TIM15_PWM
case 15:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM15EN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16_PWM
#ifdef CONFIG_STM32_TIM16_PWM
case 16:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM16EN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17_PWM
#ifdef CONFIG_STM32_TIM17_PWM
case 17:
regaddr = STM32_RCC_APB2ENR;
en_bit = RCC_APB2ENR_TIM17EN;
@ -1683,70 +1683,70 @@ static int stm32pwm_stop(struct pwm_lowerhalf_s *dev)
switch (priv->timid)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_PWM
#ifdef CONFIG_STM32_TIM1_PWM
case 1:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM1RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_PWM
#ifdef CONFIG_STM32_TIM2_PWM
case 2:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM2RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_PWM
#ifdef CONFIG_STM32_TIM3_PWM
case 3:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM3RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4_PWM
#ifdef CONFIG_STM32_TIM4_PWM
case 4:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM4RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5_PWM
#ifdef CONFIG_STM32_TIM5_PWM
case 5:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM5RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8_PWM
#ifdef CONFIG_STM32_TIM8_PWM
case 8:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM8RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14_PWM
#ifdef CONFIG_STM32_TIM14_PWM
case 14:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM14RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_PWM
#ifdef CONFIG_STM32_TIM15_PWM
case 15:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM15RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16_PWM
#ifdef CONFIG_STM32_TIM16_PWM
case 16:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM16RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17_PWM
#ifdef CONFIG_STM32_TIM17_PWM
case 17:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM17RST;
@ -1834,7 +1834,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
switch (timer)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_PWM
#ifdef CONFIG_STM32_TIM1_PWM
case 1:
lower = &g_pwm1dev;
@ -1843,31 +1843,31 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_PWM
#ifdef CONFIG_STM32_TIM2_PWM
case 2:
lower = &g_pwm2dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_PWM
#ifdef CONFIG_STM32_TIM3_PWM
case 3:
lower = &g_pwm3dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4_PWM
#ifdef CONFIG_STM32_TIM4_PWM
case 4:
lower = &g_pwm4dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5_PWM
#ifdef CONFIG_STM32_TIM5_PWM
case 5:
lower = &g_pwm5dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8_PWM
#ifdef CONFIG_STM32_TIM8_PWM
case 8:
lower = &g_pwm8dev;
@ -1876,25 +1876,25 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14_PWM
#ifdef CONFIG_STM32_TIM14_PWM
case 14:
lower = &g_pwm14dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_PWM
#ifdef CONFIG_STM32_TIM15_PWM
case 15:
lower = &g_pwm15dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16_PWM
#ifdef CONFIG_STM32_TIM16_PWM
case 16:
lower = &g_pwm16dev;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17_PWM
#ifdef CONFIG_STM32_TIM17_PWM
case 17:
lower = &g_pwm17dev;
break;
@ -1908,4 +1908,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
return (struct pwm_lowerhalf_s *)lower;
}
#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */
#endif /* CONFIG_STM32_TIMx_PWM */

372
arch/arm/src/stm32f0l0g0/stm32_pwm.h
View file

@ -64,56 +64,56 @@
/* Timer devices may be used for different purposes. One special purpose is
* to generate modulated outputs for such things as motor control. If
* CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM
* CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM
* must also be defined to indicate that timer "n" is intended to be used for
* pulsed output signal generation.
*/
#ifndef CONFIG_STM32F0L0G0_TIM1
# undef CONFIG_STM32F0L0G0_TIM1_PWM
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_PWM
#endif
#ifndef CONFIG_STM32F0L0G0_TIM2
# undef CONFIG_STM32F0L0G0_TIM2_PWM
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_PWM
#endif
#ifndef CONFIG_STM32F0L0G0_TIM3
# undef CONFIG_STM32F0L0G0_TIM3_PWM
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_PWM
#endif
#ifndef CONFIG_STM32F0L0G0_TIM14
# undef CONFIG_STM32F0L0G0_TIM14_PWM
#ifndef CONFIG_STM32_TIM14
# undef CONFIG_STM32_TIM14_PWM
#endif
#ifndef CONFIG_STM32F0L0G0_TIM15
# undef CONFIG_STM32F0L0G0_TIM15_PWM
#ifndef CONFIG_STM32_TIM15
# undef CONFIG_STM32_TIM15_PWM
#endif
#ifndef CONFIG_STM32F0L0G0_TIM16
# undef CONFIG_STM32F0L0G0_TIM16_PWM
#ifndef CONFIG_STM32_TIM16
# undef CONFIG_STM32_TIM16_PWM
#endif
#ifndef CONFIG_STM32F0L0G0_TIM17
# undef CONFIG_STM32F0L0G0_TIM17_PWM
#ifndef CONFIG_STM32_TIM17
# undef CONFIG_STM32_TIM17_PWM
#endif
/* The basic timers (timer 6 and 7)
* are not capable of generating output pulses
*/
#undef CONFIG_STM32F0L0G0_TIM6_PWM
#undef CONFIG_STM32F0L0G0_TIM7_PWM
#undef CONFIG_STM32_TIM6_PWM
#undef CONFIG_STM32_TIM7_PWM
/* Check if PWM support for any channel is enabled. */
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \
defined(CONFIG_STM32F0L0G0_TIM17_PWM)
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
#ifdef CONFIG_STM32F0L0G0_PWM_MULTICHAN
#ifdef CONFIG_STM32_PWM_MULTICHAN
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM1_CH1OUT
#ifdef CONFIG_STM32_TIM1_CHANNEL1
# ifdef CONFIG_STM32_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# else
# define PWM_TIM1_CH1CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM1_CH1NOUT
# ifdef CONFIG_STM32_TIM1_CH1NOUT
# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT
# else
# define PWM_TIM1_CH1NCFG 0
@ -122,13 +122,13 @@
#else
# define PWM_TIM1_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2
# ifdef CONFIG_STM32F0L0G0_TIM1_CH2OUT
#ifdef CONFIG_STM32_TIM1_CHANNEL2
# ifdef CONFIG_STM32_TIM1_CH2OUT
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# else
# define PWM_TIM1_CH2CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM1_CH2NOUT
# ifdef CONFIG_STM32_TIM1_CH2NOUT
# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT
# else
# define PWM_TIM1_CH2NCFG 0
@ -137,13 +137,13 @@
#else
# define PWM_TIM1_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3
# ifdef CONFIG_STM32F0L0G0_TIM1_CH3OUT
#ifdef CONFIG_STM32_TIM1_CHANNEL3
# ifdef CONFIG_STM32_TIM1_CH3OUT
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# else
# define PWM_TIM1_CH3CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM1_CH3NOUT
# ifdef CONFIG_STM32_TIM1_CH3NOUT
# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT
# else
# define PWM_TIM1_CH3NCFG 0
@ -152,8 +152,8 @@
#else
# define PWM_TIM1_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4
# ifdef CONFIG_STM32F0L0G0_TIM1_CH4OUT
#ifdef CONFIG_STM32_TIM1_CHANNEL4
# ifdef CONFIG_STM32_TIM1_CH4OUT
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# define PWM_TIM1_CH4CFG 0
@ -165,8 +165,8 @@
#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM2_CH1OUT
#ifdef CONFIG_STM32_TIM2_CHANNEL1
# ifdef CONFIG_STM32_TIM2_CH1OUT
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# else
# define PWM_TIM2_CH1CFG 0
@ -175,8 +175,8 @@
#else
# define PWM_TIM2_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2
# ifdef CONFIG_STM32F0L0G0_TIM2_CH2OUT
#ifdef CONFIG_STM32_TIM2_CHANNEL2
# ifdef CONFIG_STM32_TIM2_CH2OUT
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# else
# define PWM_TIM2_CH2CFG 0
@ -185,8 +185,8 @@
#else
# define PWM_TIM2_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3
# ifdef CONFIG_STM32F0L0G0_TIM2_CH3OUT
#ifdef CONFIG_STM32_TIM2_CHANNEL3
# ifdef CONFIG_STM32_TIM2_CH3OUT
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# else
# define PWM_TIM2_CH3CFG 0
@ -195,8 +195,8 @@
#else
# define PWM_TIM2_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4
# ifdef CONFIG_STM32F0L0G0_TIM2_CH4OUT
#ifdef CONFIG_STM32_TIM2_CHANNEL4
# ifdef CONFIG_STM32_TIM2_CH4OUT
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# define PWM_TIM2_CH4CFG 0
@ -208,8 +208,8 @@
#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM3_CH1OUT
#ifdef CONFIG_STM32_TIM3_CHANNEL1
# ifdef CONFIG_STM32_TIM3_CH1OUT
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# else
# define PWM_TIM3_CH1CFG 0
@ -218,8 +218,8 @@
#else
# define PWM_TIM3_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2
# ifdef CONFIG_STM32F0L0G0_TIM3_CH2OUT
#ifdef CONFIG_STM32_TIM3_CHANNEL2
# ifdef CONFIG_STM32_TIM3_CH2OUT
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# else
# define PWM_TIM3_CH2CFG 0
@ -228,8 +228,8 @@
#else
# define PWM_TIM3_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3
# ifdef CONFIG_STM32F0L0G0_TIM3_CH3OUT
#ifdef CONFIG_STM32_TIM3_CHANNEL3
# ifdef CONFIG_STM32_TIM3_CH3OUT
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# else
# define PWM_TIM3_CH3CFG 0
@ -238,8 +238,8 @@
#else
# define PWM_TIM3_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4
# ifdef CONFIG_STM32F0L0G0_TIM3_CH4OUT
#ifdef CONFIG_STM32_TIM3_CHANNEL4
# ifdef CONFIG_STM32_TIM3_CH4OUT
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# define PWM_TIM3_CH4CFG 0
@ -251,13 +251,13 @@
#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM14_CH1OUT
#ifdef CONFIG_STM32_TIM14_CHANNEL1
# ifdef CONFIG_STM32_TIM14_CH1OUT
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# else
# define PWM_TIM14_CH1CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM14_CH1NOUT
# ifdef CONFIG_STM32_TIM14_CH1NOUT
# define PWM_TIM14_CH1NCFG GPIO_TIM14_CH1NOUT
# else
# define PWM_TIM14_CH1NCFG 0
@ -268,13 +268,13 @@
#endif
#define PWM_TIM14_NCHANNELS PWM_TIM14_CHANNEL1
#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM15_CH1OUT
#ifdef CONFIG_STM32_TIM15_CHANNEL1
# ifdef CONFIG_STM32_TIM15_CH1OUT
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# else
# define PWM_TIM15_CH1CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM15_CH1NOUT
# ifdef CONFIG_STM32_TIM15_CH1NOUT
# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT
# else
# define PWM_TIM15_CH1NCFG 0
@ -283,8 +283,8 @@
#else
# define PWM_TIM15_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2
# ifdef CONFIG_STM32F0L0G0_TIM15_CH2OUT
#ifdef CONFIG_STM32_TIM15_CHANNEL2
# ifdef CONFIG_STM32_TIM15_CH2OUT
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# define PWM_TIM15_CH2CFG 0
@ -295,13 +295,13 @@
#endif
#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM16_CH1OUT
#ifdef CONFIG_STM32_TIM16_CHANNEL1
# ifdef CONFIG_STM32_TIM16_CH1OUT
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# define PWM_TIM16_CH1CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM16_CH1NOUT
# ifdef CONFIG_STM32_TIM16_CH1NOUT
# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT
# else
# define PWM_TIM16_CH1NCFG 0
@ -312,13 +312,13 @@
#endif
#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1
# ifdef CONFIG_STM32F0L0G0_TIM17_CH1OUT
#ifdef CONFIG_STM32_TIM17_CHANNEL1
# ifdef CONFIG_STM32_TIM17_CH1OUT
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# define PWM_TIM17_CH1CFG 0
# endif
# ifdef CONFIG_STM32F0L0G0_TIM17_CH1NOUT
# ifdef CONFIG_STM32_TIM17_CH1NOUT
# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT
# else
# define PWM_TIM17_CH1NCFG 0
@ -337,178 +337,170 @@
MAX(PWM_TIM16_NCHANNELS, \
PWM_TIM17_NCHANNELS))))))
#else /* !CONFIG_STM32F0L0G0_PWM_MULTICHAN */
#else /* !CONFIG_STM32_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
*
* CONFIG_STM32F0L0G0_TIMx_CHANNEL - Specifies the timer output channel
* {1,..,4}
* PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h.
* In the case where there are multiple pin selections, the correct
* setting must be provided in the arch/board/board.h file.
* CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel
* {1,..,4} PWM_TIMx_CHn - One of the values defined in
* chip/stm32*_pinmap.h. In the case where there are multiple pin
* selections, the correct setting must be provided in the arch/board/board.h
* file.
*
* NOTE:
* The STM32 timers are each capable of generating different signals on
* each of the four channels with different duty cycles. That capability
* is not supported by this driver: Only one output channel per timer.
* NOTE: The STM32 timers are each capable of generating different signals on
* each of the four channels with different duty cycles. That capability is
* not supported by this driver: Only one output channel per timer.
*/
#ifdef CONFIG_STM32F0L0G0_TIM1_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM1_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM1_CH1MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# define PWM_TIM1_CH1NCFG 0
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM1_CH2MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# define PWM_TIM1_CH2NCFG 0
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 3
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL3 1
# define CONFIG_STM32F0L0G0_TIM1_CH3MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# define PWM_TIM1_CH3NCFG 0
# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 4
# define CONFIG_STM32F0L0G0_TIM1_CHANNEL4 1
# define CONFIG_STM32F0L0G0_TIM1_CH4MODE CONFIG_STM32F0L0G0_TIM1_CHMODE
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
#ifdef CONFIG_STM32_TIM1_PWM
# if !defined(CONFIG_STM32_TIM1_CHANNEL)
# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32_TIM1_CHANNEL == 1
# define CONFIG_STM32_TIM1_CHANNEL1 1
# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# define PWM_TIM1_CH1NCFG 0
# elif CONFIG_STM32_TIM1_CHANNEL == 2
# define CONFIG_STM32_TIM1_CHANNEL2 1
# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# define PWM_TIM1_CH2NCFG 0
# elif CONFIG_STM32_TIM1_CHANNEL == 3
# define CONFIG_STM32_TIM1_CHANNEL3 1
# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# define PWM_TIM1_CH3NCFG 0
# elif CONFIG_STM32_TIM1_CHANNEL == 4
# define CONFIG_STM32_TIM1_CHANNEL4 1
# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM1_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
# endif
# define PWM_TIM1_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM2_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM2_CH1MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM2_CH2MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 3
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL3 1
# define CONFIG_STM32F0L0G0_TIM2_CH3MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 4
# define CONFIG_STM32F0L0G0_TIM2_CHANNEL4 1
# define CONFIG_STM32F0L0G0_TIM2_CH4MODE CONFIG_STM32F0L0G0_TIM2_CHMODE
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
#ifdef CONFIG_STM32_TIM2_PWM
# if !defined(CONFIG_STM32_TIM2_CHANNEL)
# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32_TIM2_CHANNEL == 1
# define CONFIG_STM32_TIM2_CHANNEL1 1
# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 2
# define CONFIG_STM32_TIM2_CHANNEL2 1
# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 3
# define CONFIG_STM32_TIM2_CHANNEL3 1
# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 4
# define CONFIG_STM32_TIM2_CHANNEL4 1
# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM2_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
# endif
# define PWM_TIM2_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM3_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM3_CH1MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM3_CH2MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 3
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL3 1
# define CONFIG_STM32F0L0G0_TIM3_CH3MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 4
# define CONFIG_STM32F0L0G0_TIM3_CHANNEL4 1
# define CONFIG_STM32F0L0G0_TIM3_CH4MODE CONFIG_STM32F0L0G0_TIM3_CHMODE
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
#ifdef CONFIG_STM32_TIM3_PWM
# if !defined(CONFIG_STM32_TIM3_CHANNEL)
# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32_TIM3_CHANNEL == 1
# define CONFIG_STM32_TIM3_CHANNEL1 1
# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 2
# define CONFIG_STM32_TIM3_CHANNEL2 1
# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 3
# define CONFIG_STM32_TIM3_CHANNEL3 1
# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 4
# define CONFIG_STM32_TIM3_CHANNEL4 1
# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM3_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
# endif
# define PWM_TIM3_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM14_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM14_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM14_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM14_CH1MODE CONFIG_STM32F0L0G0_TIM14_CHMODE
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# define PWM_TIM14_CH1NCFG 0
#ifdef CONFIG_STM32_TIM14_PWM
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32_TIM14_CHANNEL == 1
# define CONFIG_STM32_TIM14_CHANNEL1 1
# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# define PWM_TIM14_CH1NCFG 0
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM14_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
# endif
# define PWM_TIM14_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM15_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM15_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM15_CH1MODE CONFIG_STM32F0L0G0_TIM15_CHMODE
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# define PWM_TIM15_CH1NCFG 0
# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 2
# define CONFIG_STM32F0L0G0_TIM15_CHANNEL2 1
# define CONFIG_STM32F0L0G0_TIM15_CH2MODE CONFIG_STM32F0L0G0_TIM15_CHMODE
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
#ifdef CONFIG_STM32_TIM15_PWM
# if !defined(CONFIG_STM32_TIM15_CHANNEL)
# error "CONFIG_STM32_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32_TIM15_CHANNEL == 1
# define CONFIG_STM32_TIM15_CHANNEL1 1
# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# define PWM_TIM15_CH1NCFG 0
# elif CONFIG_STM32_TIM15_CHANNEL == 2
# define CONFIG_STM32_TIM15_CHANNEL2 1
# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM15_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL"
# endif
# define PWM_TIM15_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM16_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM16_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM16_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM16_CH1MODE CONFIG_STM32F0L0G0_TIM16_CHMODE
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# define PWM_TIM16_CH1NCFG 0
#ifdef CONFIG_STM32_TIM16_PWM
# if !defined(CONFIG_STM32_TIM16_CHANNEL)
# error "CONFIG_STM32_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32_TIM16_CHANNEL == 1
# define CONFIG_STM32_TIM16_CHANNEL1 1
# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# define PWM_TIM16_CH1NCFG 0
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM16_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL"
# endif
# define PWM_TIM16_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17_PWM
# if !defined(CONFIG_STM32F0L0G0_TIM17_CHANNEL)
# error "CONFIG_STM32F0L0G0_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32F0L0G0_TIM17_CHANNEL == 1
# define CONFIG_STM32F0L0G0_TIM17_CHANNEL1 1
# define CONFIG_STM32F0L0G0_TIM17_CH1MODE CONFIG_STM32F0L0G0_TIM17_CHMODE
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# define PWM_TIM17_CH1NCFG 0
#ifdef CONFIG_STM32_TIM17_PWM
# if !defined(CONFIG_STM32_TIM17_CHANNEL)
# error "CONFIG_STM32_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32_TIM17_CHANNEL == 1
# define CONFIG_STM32_TIM17_CHANNEL1 1
# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# define PWM_TIM17_CH1NCFG 0
# else
# error "Unsupported value of CONFIG_STM32F0L0G0_TIM17_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL"
# endif
# define PWM_TIM17_NCHANNELS 1
#endif
#define PWM_NCHANNELS 1
#endif /* CONFIG_STM32F0L0G0_PWM_MULTICHAN */
#endif
/* Complementary outputs support */
#if defined(CONFIG_STM32F0L0G0_TIM1_CH1NOUT) || defined(CONFIG_STM32F0L0G0_TIM1_CH2NOUT) || \
defined(CONFIG_STM32F0L0G0_TIM1_CH3NOUT)
#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \
defined(CONFIG_STM32_TIM1_CH3NOUT)
# define HAVE_TIM1_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32F0L0G0_TIM15_CH1NOUT)
#if defined(CONFIG_STM32_TIM15_CH1NOUT)
# define HAVE_TIM15_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32F0L0G0_TIM16_CH1NOUT)
#if defined(CONFIG_STM32_TIM16_CH1NOUT)
# define HAVE_TIM16_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32F0L0G0_TIM17_CH1NOUT)
#if defined(CONFIG_STM32_TIM17_CH1NOUT)
# define HAVE_TIM17_COMPLEMENTARY
#endif
#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \
@ -566,6 +558,6 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */
#endif /* CONFIG_STM32_TIMx_PWM */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */

4
arch/arm/src/stm32f0l0g0/stm32_pwr.c
View file

@ -31,9 +31,9 @@
* according to the selected MCU family.
*/
#if defined(CONFIG_STM32F0L0G0_STM32G0)
#if defined(CONFIG_STM32_STM32G0)
# include "stm32g0_pwr.c"
#elif defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0)
#elif defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0)
# include "stm32f0l0_pwr.c"
#endif

12
arch/arm/src/stm32f0l0g0/stm32_pwr.h
View file

@ -34,7 +34,7 @@
#include "chip.h"
#include "hardware/stm32_pwr.h"
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
/****************************************************************************
* Pre-processor Definitions
@ -172,9 +172,9 @@ bool stm32_pwr_getwuf(void);
*
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) || defined(CONFIG_STM32F0L0G0_STM32G0)
#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0)
void stm32_pwr_setvos(uint16_t vos);
#endif /* CONFIG_STM32F0L0G0_ENERGYLITE || CONFIG_STM32F0L0G0_STM32G0 */
#endif /* CONFIG_STM32_ENERGYLITE || CONFIG_STM32_STM32G0 */
/****************************************************************************
* Name: stm32_pwr_setpvd
@ -193,7 +193,7 @@ void stm32_pwr_setvos(uint16_t vos);
*
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_ENERGYLITE)
#if defined(CONFIG_STM32_ENERGYLITE)
void stm32_pwr_setpvd(uint16_t pls);
/****************************************************************************
@ -216,7 +216,7 @@ void stm32_pwr_enablepvd(void);
void stm32_pwr_disablepvd(void);
#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
#endif /* CONFIG_STM32_ENERGYLITE */
#undef EXTERN
#if defined(__cplusplus)
@ -224,5 +224,5 @@ void stm32_pwr_disablepvd(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F0L0G0_PWR */
#endif /* CONFIG_STM32_PWR */
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */

170
arch/arm/src/stm32f0l0g0/stm32_qencoder.c
View file

@ -51,13 +51,13 @@
/* Timers *******************************************************************/
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
# undef HAVE_32BIT_TIMERS
# undef HAVE_16BIT_TIMERS
/* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */
# if defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_32BIT)
# if defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_32BIT)
# define HAVE_32BIT_TIMERS 1
# endif
@ -65,9 +65,9 @@
* 16-bit timers
*/
# if defined(CONFIG_STM32F0L0G0_TIM1_QE) || defined(CONFIG_STM32F0L0G0_TIM3_QE) || \
defined(CONFIG_STM32F0L0G0_TIM4_QE) || \
(defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_16BIT))
# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \
defined(CONFIG_STM32_TIM4_QE) || \
(defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_16BIT))
# define HAVE_16BIT_TIMERS 1
# endif
@ -92,65 +92,65 @@
/* Input filter *************************************************************/
#ifdef CONFIG_STM32F0L0G0_QENCODER_FILTER
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_1)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
#ifdef CONFIG_STM32_QENCODER_FILTER
# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
# endif
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_CKINT)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_2)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_4)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8
# endif
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_2)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28
# endif
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_4)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48
# endif
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_8)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88
# endif
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_16)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168
# endif
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_32)
# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326
# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8)
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328
# endif
# endif
# ifndef STM32F0L0G0_QENCODER_ICF
# ifndef STM32_QENCODER_ICF
# warning "Invalid encoder filter combination, filter disabled"
# endif
#endif
#ifndef STM32F0L0G0_QENCODER_ICF
# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
#ifndef STM32_QENCODER_ICF
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
#endif
#define STM32F0L0G0_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
/* Debug ********************************************************************/
@ -207,13 +207,13 @@ struct stm32_lowerhalf_s
bool inuse; /* True: The lower-half driver is in-use */
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
uint32_t index_pin; /* Index pin GPIO */
bool index_use; /* True: Index pin is configured */
int32_t index_offset; /* Index pin offset */
#endif
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
volatile int32_t position; /* The current position offset */
#endif
spinlock_t lock; /* Spinlock */
@ -243,11 +243,11 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim);
/* Interrupt handling */
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
static int stm32_qe_index_irq(int irq, void *context, void *arg);
#endif
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
static int stm32_interrupt(int irq, void *context, void *arg);
#endif
@ -281,7 +281,7 @@ static const struct qe_ops_s g_qecallbacks =
/* Per-timer state structures */
#ifdef CONFIG_STM32F0L0G0_TIM1_QE
#ifdef CONFIG_STM32_TIM1_QE
static const struct stm32_qeconfig_s g_tim1config =
{
.timid = 1,
@ -290,7 +290,7 @@ static const struct stm32_qeconfig_s g_tim1config =
.width = TIM1_BITWIDTH,
#endif
.base = STM32_TIM1_BASE,
.psc = CONFIG_STM32F0L0G0_TIM1_QEPSC,
.psc = CONFIG_STM32_TIM1_QEPSC,
.ti1cfg = GPIO_TIM1_CH1IN,
.ti2cfg = GPIO_TIM1_CH2IN,
};
@ -305,7 +305,7 @@ static struct stm32_lowerhalf_s g_tim1lower =
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_QE
#ifdef CONFIG_STM32_TIM2_QE
static const struct stm32_qeconfig_s g_tim2config =
{
.timid = 2,
@ -314,7 +314,7 @@ static const struct stm32_qeconfig_s g_tim2config =
.width = TIM2_BITWIDTH,
#endif
.base = STM32_TIM2_BASE,
.psc = CONFIG_STM32F0L0G0_TIM2_QEPSC,
.psc = CONFIG_STM32_TIM2_QEPSC,
.ti1cfg = GPIO_TIM2_CH1IN,
.ti2cfg = GPIO_TIM2_CH2IN,
};
@ -329,7 +329,7 @@ static struct stm32_lowerhalf_s g_tim2lower =
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_QE
#ifdef CONFIG_STM32_TIM3_QE
static const struct stm32_qeconfig_s g_tim3config =
{
.timid = 3,
@ -338,7 +338,7 @@ static const struct stm32_qeconfig_s g_tim3config =
.width = TIM3_BITWIDTH,
#endif
.base = STM32_TIM3_BASE,
.psc = CONFIG_STM32F0L0G0_TIM3_QEPSC,
.psc = CONFIG_STM32_TIM3_QEPSC,
.ti1cfg = GPIO_TIM3_CH1IN,
.ti2cfg = GPIO_TIM3_CH2IN,
};
@ -353,7 +353,7 @@ static struct stm32_lowerhalf_s g_tim3lower =
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4_QE
#ifdef CONFIG_STM32_TIM4_QE
static const struct stm32_qeconfig_s g_tim4config =
{
.timid = 4,
@ -362,7 +362,7 @@ static const struct stm32_qeconfig_s g_tim4config =
.width = TIM4_BITWIDTH,
#endif
.base = STM32_TIM4_BASE,
.psc = CONFIG_STM32F0L0G0_TIM4_QEPSC,
.psc = CONFIG_STM32_TIM4_QEPSC,
.ti1cfg = GPIO_TIM4_CH1IN,
.ti2cfg = GPIO_TIM4_CH2IN,
};
@ -511,7 +511,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv,
sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n",
stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET),
stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET));
#if defined(CONFIG_STM32F0L0G0_TIM1_QE)
#if defined(CONFIG_STM32_TIM1_QE)
if (priv->config->timid == 1)
{
sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
@ -542,19 +542,19 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim)
{
switch (tim)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_QE
#ifdef CONFIG_STM32_TIM1_QE
case 1:
return &g_tim1lower;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_QE
#ifdef CONFIG_STM32_TIM2_QE
case 2:
return &g_tim2lower;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_QE
#ifdef CONFIG_STM32_TIM3_QE
case 3:
return &g_tim3lower;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4_QE
#ifdef CONFIG_STM32_TIM4_QE
case 4:
return &g_tim4lower;
#endif
@ -571,7 +571,7 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
static int stm32_qe_index_irq(int irq, void *context, void *arg)
{
struct stm32_lowerhalf_s *priv;
@ -601,7 +601,7 @@ static int stm32_qe_index_irq(int irq, void *context, void *arg)
*
****************************************************************************/
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
static int stm32_interrupt(int irq, void *context, void *arg)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg;
@ -656,7 +656,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
uint32_t ccmr1;
uint16_t ccer;
uint16_t cr1;
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
uint16_t regval;
int ret;
#endif
@ -699,7 +699,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
stm32_putreg16(priv,
STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc);
#if defined(CONFIG_STM32F0L0G0_TIM1_QE)
#if defined(CONFIG_STM32_TIM1_QE)
if (priv->config->timid == 1)
{
/* Clear the Repetition Counter value */
@ -741,7 +741,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK);
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT;
ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT;
ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT;
/* Select the Polarity=rising and set the CC1E Bit */
@ -777,7 +777,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK);
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT;
ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT;
ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT;
/* Select the Polarity=rising and set the CC2E Bit */
@ -806,7 +806,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
/* There is no need for interrupts with 32-bit timers */
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
#ifdef HAVE_MIXEDWIDTH_TIMERS
if (priv->config->width != 32)
#endif
@ -839,7 +839,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
/* There is no need for interrupts with 32-bit timers */
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
#ifdef HAVE_MIXEDWIDTH_TIMERS
if (priv->config->width != 32)
#endif
@ -857,7 +857,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
}
#endif
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
priv->index_offset = 0;
#endif
@ -913,25 +913,25 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower)
switch (priv->config->timid)
{
#ifdef CONFIG_STM32F0L0G0_TIM1_QE
#ifdef CONFIG_STM32_TIM1_QE
case 1:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM1RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2_QE
#ifdef CONFIG_STM32_TIM2_QE
case 2:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM2RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3_QE
#ifdef CONFIG_STM32_TIM3_QE
case 3:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM3RST;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4_QE
#ifdef CONFIG_STM32_TIM4_QE
case 4:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM4RST;
@ -961,14 +961,14 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower)
/* Put the TI1 GPIO pin back to its default state */
pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT;
pincfg |= STM32_GPIO_INPUT_FLOAT;
stm32_configgpio(pincfg);
/* Put the TI2 GPIO pin back to its default state */
pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT;
pincfg |= STM32_GPIO_INPUT_FLOAT;
stm32_configgpio(pincfg);
return OK;
@ -985,7 +985,7 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower)
static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
irqstate_t flags;
int32_t position;
int32_t verify;
@ -1027,7 +1027,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos)
static int stm32_reset(struct qe_lowerhalf_s *lower)
{
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS
#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS
irqstate_t flags;
sninfo("Resetting position to zero\n");
@ -1094,7 +1094,7 @@ static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos)
static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos)
{
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower;
int ret = OK;
@ -1201,7 +1201,7 @@ int stm32_qeinitialize(const char *devpath, int tim)
return OK;
}
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
/****************************************************************************
* Name: stm32_qe_index_init
*

34
arch/arm/src/stm32f0l0g0/stm32_qencoder.h
View file

@ -38,23 +38,23 @@
****************************************************************************/
/* Timer devices may be used for different purposes. One special purpose is
* as a quadrature encoder input device. If CONFIG_STM32F0L0G0_TIMn is
* defined then the CONFIG_STM32F0L0G0_TIMn_QE must also be defined to
* as a quadrature encoder input device. If CONFIG_STM32_TIMn is
* defined then the CONFIG_STM32_TIMn_QE must also be defined to
* indicate that timer "n" is intended to be used for as a quadrature
* encoder.
*/
#ifndef CONFIG_STM32F0L0G0_TIM1
# undef CONFIG_STM32F0L0G0_TIM1_QE
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_QE
#endif
#ifndef CONFIG_STM32F0L0G0_TIM2
# undef CONFIG_STM32F0L0G0_TIM2_QE
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_QE
#endif
#ifndef CONFIG_STM32F0L0G0_TIM3
# undef CONFIG_STM32F0L0G0_TIM3_QE
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_QE
#endif
#ifndef CONFIG_STM32F0L0G0_TIM4
# undef CONFIG_STM32F0L0G0_TIM4_QE
#ifndef CONFIG_STM32_TIM4
# undef CONFIG_STM32_TIM4_QE
#endif
/* Only timers 1-4 can be used as a quadrature encoder (timers with
@ -63,12 +63,12 @@
* capability.
*/
#undef CONFIG_STM32F0L0G0_TIM6_QE
#undef CONFIG_STM32F0L0G0_TIM7_QE
#undef CONFIG_STM32F0L0G0_TIM14_QE
#undef CONFIG_STM32F0L0G0_TIM15_QE
#undef CONFIG_STM32F0L0G0_TIM16_QE
#undef CONFIG_STM32F0L0G0_TIM17_QE
#undef CONFIG_STM32_TIM6_QE
#undef CONFIG_STM32_TIM7_QE
#undef CONFIG_STM32_TIM14_QE
#undef CONFIG_STM32_TIM15_QE
#undef CONFIG_STM32_TIM16_QE
#undef CONFIG_STM32_TIM17_QE
/****************************************************************************
* Public Function Prototypes
@ -93,7 +93,7 @@
int stm32_qeinitialize(const char *devpath, int tim);
#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN
#ifdef CONFIG_STM32_QENCODER_INDEX_PIN
/****************************************************************************
* Name: stm32_qe_index_init
*

14
arch/arm/src/stm32f0l0g0/stm32_rcc.c
View file

@ -42,13 +42,13 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_RNG
#ifdef CONFIG_STM32_RNG
# ifndef STM32_USE_CLK48
# error RNG requires CLK48 enabled
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
# ifndef STM32_USE_CLK48
# error USB requires CLK48 enabled
# endif
@ -103,7 +103,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
*
****************************************************************************/
#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR)
#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR)
static inline void rcc_resetbkp(void)
{
uint32_t regval;
@ -144,7 +144,7 @@ static inline void rcc_resetbkp(void)
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -166,7 +166,7 @@ void stm32_clockconfig(void)
rcc_resetbkp();
#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();
@ -198,7 +198,7 @@ void stm32_clockconfig(void)
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -213,7 +213,7 @@ void stm32_clockconfig(void)
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();

4
arch/arm/src/stm32f0l0g0/stm32_rng.c
View file

@ -41,7 +41,7 @@
#include "hardware/stm32_rng.h"
#include "arm_internal.h"
#if defined(CONFIG_STM32F0L0G0_RNG)
#if defined(CONFIG_STM32_RNG)
#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
/****************************************************************************
@ -311,4 +311,4 @@ void devurandom_register(void)
#endif
#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
#endif /* CONFIG_STM32F0L0G0_RNG */
#endif /* CONFIG_STM32_RNG */

4
arch/arm/src/stm32f0l0g0/stm32_serial.c
View file

@ -33,9 +33,9 @@
* - STM32 UART IP version 2 - G0
*/
#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
#if defined(CONFIG_STM32_HAVE_IP_USART_V1)
# include "stm32_serial_v1.c"
#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
#elif defined(CONFIG_STM32_HAVE_IP_USART_V2)
# include "stm32_serial_v2.c"
#else
# error "Unsupported STM32 M0 serial"

76
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
View file

@ -84,14 +84,14 @@
*/
# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA)
# ifndef CONFIG_STM32F0L0G0_DMA1
# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1
# ifndef CONFIG_STM32_DMA1
# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32_DMA1
# endif
# endif
# if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA)
# ifndef CONFIG_STM32F0L0G0_DMA2
# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2
# ifndef CONFIG_STM32_DMA2
# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32_DMA2
# endif
# endif
@ -160,8 +160,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
/* Keep track if a Break was set
@ -175,7 +175,7 @@
* See stm32serial_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -348,7 +348,7 @@ static const struct uart_ops_s g_uart_dma_ops =
/* I/O buffers */
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_USART1_RXDMA
@ -356,7 +356,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_USART2_RXDMA
@ -364,7 +364,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
# ifdef CONFIG_USART3_RXDMA
@ -372,7 +372,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
# ifdef CONFIG_USART4_RXDMA
@ -380,7 +380,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
# ifdef CONFIG_USART5_RXDMA
@ -390,7 +390,7 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
static struct stm32_serial_s g_usart1priv =
{
.dev =
@ -452,7 +452,7 @@ static struct stm32_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
static struct stm32_serial_s g_usart2priv =
{
.dev =
@ -514,7 +514,7 @@ static struct stm32_serial_s g_usart2priv =
/* This describes the state of the STM32 USART3 port. */
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
static struct stm32_serial_s g_usart3priv =
{
.dev =
@ -576,7 +576,7 @@ static struct stm32_serial_s g_usart3priv =
/* This describes the state of the STM32 USART4 port. */
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
static struct stm32_serial_s g_usart4priv =
{
.dev =
@ -642,7 +642,7 @@ static struct stm32_serial_s g_usart4priv =
/* This describes the state of the STM32 USART5 port. */
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
static struct stm32_serial_s g_usart5priv =
{
.dev =
@ -710,19 +710,19 @@ static struct stm32_serial_s g_usart5priv =
static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] =
{
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
[0] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
[1] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
[2] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
[3] = &g_usart4priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
[4] = &g_usart5priv,
#endif
};
@ -1005,7 +1005,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev)
regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -1047,31 +1047,31 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR_USART2EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR_USART3EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
case STM32_USART4_BASE:
rcc_en = RCC_APB1ENR_USART4EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
case STM32_USART5_BASE:
rcc_en = RCC_APB1ENR_USART5EN;
regaddr = STM32_RCC_APB1ENR;
@ -1132,7 +1132,7 @@ static int stm32serial_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -1464,8 +1464,8 @@ static int up_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -1609,7 +1609,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE
#ifdef CONFIG_STM32_USART_SINGLEWIRE
#warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN
case TIOCSSINGLEWIRE:
{
@ -1747,8 +1747,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32F0L0G0_USART_BREAKS
# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -1967,7 +1967,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev,
struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -2218,7 +2218,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable)
}
# endif
# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{
leave_critical_section(flags);
@ -2471,7 +2471,7 @@ void arm_serialinit(void)
#if CONSOLE_USART > 0
uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev);
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console USART to ttyS0 and exclude
* it from initializing it further down
*/
@ -2500,7 +2500,7 @@ void arm_serialinit(void)
continue;
}
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

70
arch/arm/src/stm32f0l0g0/stm32_serial_v2.c
View file

@ -68,8 +68,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
/* Keep track if a Break was set
@ -83,7 +83,7 @@
* See up_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -93,9 +93,9 @@
/* Warnings for potentially unsafe configuration combinations. */
#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \
#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \
!defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS)
# error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \
# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \
CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled."
#endif
@ -216,29 +216,29 @@ static const struct uart_ops_s g_uart_ops =
/* Receive/Transmit buffers */
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
#endif
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
static struct up_dev_s g_usart1priv =
{
.dev =
@ -293,7 +293,7 @@ static struct up_dev_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
static struct up_dev_s g_usart2priv =
{
.dev =
@ -348,7 +348,7 @@ static struct up_dev_s g_usart2priv =
/* This describes the state of the STM32 USART3 port. */
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
static struct up_dev_s g_usart3priv =
{
.dev =
@ -403,7 +403,7 @@ static struct up_dev_s g_usart3priv =
/* This describes the state of the STM32 USART4 port. */
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
static struct up_dev_s g_usart4priv =
{
.dev =
@ -460,16 +460,16 @@ static struct up_dev_s g_usart4priv =
static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] =
{
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
[0] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
[1] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
[2] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
[3] = &g_usart4priv
#endif
};
@ -738,7 +738,7 @@ static void up_set_format(struct uart_dev_s *dev)
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \
!defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
!defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -782,25 +782,25 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR_USART2EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR_USART3EN;
regaddr = STM32_RCC_APB1ENR;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
case STM32_USART4_BASE:
rcc_en = RCC_APB1ENR_USART4EN;
regaddr = STM32_RCC_APB1ENR;
@ -865,7 +865,7 @@ static int up_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -1093,8 +1093,8 @@ static int up_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -1207,14 +1207,14 @@ static int up_interrupt(int irq, void *context, void *arg)
static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
|| defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \
|| defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT)
|| defined(CONFIG_STM32_USART_SINGLEWIRE) \
|| defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT)
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
#endif
#if defined(CONFIG_SERIAL_TERMIOS) \
|| defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \
|| defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT)
|| defined(CONFIG_STM32_USART_SINGLEWIRE) \
|| defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT)
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#endif
int ret = OK;
@ -1237,7 +1237,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
break;
#endif
#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE
#ifdef CONFIG_STM32_USART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
uint32_t cr1;
@ -1390,8 +1390,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32F0L0G0_USART_BREAKS
# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -1590,7 +1590,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -1966,7 +1966,7 @@ void arm_serialinit(void)
#if CONSOLE_USART > 0
uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev);
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
* it from initializing it further down
*/
@ -1990,7 +1990,7 @@ void arm_serialinit(void)
continue;
}
#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

86
arch/arm/src/stm32f0l0g0/stm32_spi.c
View file

@ -80,7 +80,7 @@
#include <arch/board/board.h>
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/****************************************************************************
* Pre-processor Definitions
@ -90,19 +90,19 @@
/* SPI interrupts */
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
# error "Interrupt driven SPI not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA)
#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
@ -129,10 +129,10 @@
/* SPI clocks */
#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0)
#if defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0)
# define SPI1_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
#elif defined(CONFIG_STM32F0L0G0_STM32G0)
#elif defined(CONFIG_STM32_STM32G0)
# define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
@ -157,10 +157,10 @@ struct stm32_spidev_s
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
uint32_t spibase; /* SPIn base address */
uint32_t spiclock; /* Clocking for the SPI module */
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
uint8_t spiirq; /* SPI IRQ number */
#endif
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the RX DMA */
#ifdef CONFIG_SPI_TRIGGER
@ -211,7 +211,7 @@ static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv,
/* DMA support */
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv);
static int spi_dmatxwait(struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv);
@ -247,7 +247,7 @@ static void spi_exchange(struct spi_dev_s *dev,
const void *txbuffer, void *rxbuffer,
size_t nwords);
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_exchange_nodma(struct spi_dev_s *dev,
const void *txbuffer, void *rxbuffer,
size_t nwords);
@ -278,7 +278,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
static const struct spi_ops_s g_spi1ops =
{
.lock = spi_lock,
@ -318,10 +318,10 @@ static struct stm32_spidev_s g_spi1dev =
},
.spibase = STM32_SPI1_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI1,
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1_DMA
#ifdef CONFIG_STM32_SPI1_DMA
/* lines must be configured in board.h */
.rxch = DMACHAN_SPI1_RX,
@ -333,11 +333,11 @@ static struct stm32_spidev_s g_spi1dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
.config = CONFIG_STM32F0L0G0_SPI1_COMMTYPE,
.config = CONFIG_STM32_SPI1_COMMTYPE,
};
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
static const struct spi_ops_s g_spi2ops =
{
.lock = spi_lock,
@ -377,10 +377,10 @@ static struct stm32_spidev_s g_spi2dev =
},
.spibase = STM32_SPI2_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI2,
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2_DMA
#ifdef CONFIG_STM32_SPI2_DMA
.rxch = DMACHAN_SPI2_RX,
.txch = DMACHAN_SPI2_TX,
.rxsem = SEM_INITIALIZER(0),
@ -390,11 +390,11 @@ static struct stm32_spidev_s g_spi2dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
.config = CONFIG_STM32F0L0G0_SPI2_COMMTYPE,
.config = CONFIG_STM32_SPI2_COMMTYPE,
};
#endif
#ifdef CONFIG_STM32F0L0G0_SPI3
#ifdef CONFIG_STM32_SPI3
static const struct spi_ops_s g_spi3ops =
{
.lock = spi_lock,
@ -434,10 +434,10 @@ static struct stm32_spidev_s g_spi3dev =
},
.spibase = STM32_SPI3_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI3,
#endif
#ifdef CONFIG_STM32F0L0G0_SPI3_DMA
#ifdef CONFIG_STM32_SPI3_DMA
.rxch = DMACHAN_SPI3_RX,
.txch = DMACHAN_SPI3_TX,
.rxsem = SEM_INITIALIZER(0),
@ -447,7 +447,7 @@ static struct stm32_spidev_s g_spi3dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
.config = CONFIG_STM32F0L0G0_SPI3_COMMTYPE,
.config = CONFIG_STM32_SPI3_COMMTYPE,
};
#endif
@ -754,7 +754,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -787,7 +787,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmatxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -820,7 +820,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->rxsem);
@ -835,7 +835,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->txsem);
@ -850,7 +850,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -870,7 +870,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -890,7 +890,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer, void *rxdummy,
size_t nwords)
@ -941,7 +941,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer, const void *txdummy,
size_t nwords)
@ -992,7 +992,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
{
priv->rxresult = 0;
@ -1008,7 +1008,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmatxstart(struct stm32_spidev_s *priv)
{
priv->txresult = 0;
@ -1495,7 +1495,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
*
****************************************************************************/
#if !defined(CONFIG_STM32F0L0G0_SPI_DMA)
#if !defined(CONFIG_STM32_SPI_DMA)
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
#else
@ -1604,7 +1604,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
@ -1622,7 +1622,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
return;
}
#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
if ((txbuffer &&
!stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) ||
(rxbuffer &&
@ -1684,7 +1684,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#endif
}
}
#endif /* CONFIG_STM32F0L0G0_SPI_DMA */
#endif /* CONFIG_STM32_SPI_DMA */
/****************************************************************************
* Name: spi_trigger
@ -1705,7 +1705,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#ifdef CONFIG_SPI_TRIGGER
static int spi_trigger(struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
@ -1969,7 +1969,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7);
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
if (priv->rxch && priv->txch)
{
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the
@ -2032,7 +2032,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
irqstate_t flags = enter_critical_section();
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
if (bus == 1)
{
/* Select SPI1 */
@ -2056,7 +2056,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
if (bus == 2)
{
/* Select SPI2 */
@ -2080,7 +2080,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32F0L0G0_SPI3
#ifdef CONFIG_STM32_SPI3
if (bus == 3)
{
/* Select SPI3 */
@ -2110,7 +2110,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
goto errout;
}
#ifdef CONFIG_STM32F0L0G0_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
/* SPI DMA supported only for full-duplex mode */
if (priv->rxch && priv->txch && priv->config != FULL_DUPLEX)
@ -2131,4 +2131,4 @@ errout:
return (struct spi_dev_s *)priv;
}
#endif /* CONFIG_STM32F0L0G0_SPI */
#endif /* CONFIG_STM32_SPI */

12
arch/arm/src/stm32f0l0g0/stm32_spi.h
View file

@ -104,21 +104,21 @@ struct spi_dev_s *stm32_spibus_initialize(int bus);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32F0L0G0_SPI3
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid);
@ -146,17 +146,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32F0L0G0_SPI3
#ifdef CONFIG_STM32_SPI3
int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif

300
arch/arm/src/stm32f0l0g0/stm32_tim.c
View file

@ -68,96 +68,96 @@
* include:
*
* - To generate modulated outputs for such things as motor control. If
* CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM
* CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM
* may also be defined to indicate that the timer is intended to be used
* for pulsed output modulation.
*
* - To control periodic ADC input sampling. If CONFIG_STM32F0L0G0_TIMn is
* defined then CONFIG_STM32F0L0G0_TIMn_ADC may also be defined to indicate
* - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is
* defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate
* that timer "n" is intended to be used for that purpose.
*
* - To control periodic DAC outputs. If CONFIG_STM32F0L0G0_TIMn is defined
* then CONFIG_STM32F0L0G0_TIMn_DAC may also be defined to indicate that
* - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined
* then CONFIG_STM32_TIMn_DAC may also be defined to indicate that
* timer "n" is intended to be used for that purpose.
*
* - To use a Quadrature Encoder. If CONFIG_STM32F0L0G0_TIMn is defined then
* CONFIG_STM32F0L0G0_TIMn_QE may also be defined to indicate that timer
* - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then
* CONFIG_STM32_TIMn_QE may also be defined to indicate that timer
* "n" is intended to be used for that purpose.
*
* In any of these cases, the timer will not be used by this timer module.
*/
#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM1_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM1_DAC) || defined(CONFIG_STM32F0L0G0_TIM1_QE)
# undef CONFIG_STM32F0L0G0_TIM1
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM1_ADC) || \
defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE)
# undef CONFIG_STM32_TIM1
#endif
#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM2_DAC) || defined(CONFIG_STM32F0L0G0_TIM2_QE)
# undef CONFIG_STM32F0L0G0_TIM2
#if defined(CONFIG_STM32_TIM2_PWM) || defined(CONFIG_STM32_TIM2_ADC) || \
defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE)
# undef CONFIG_STM32_TIM2
#endif
#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM3_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM3_DAC) || defined(CONFIG_STM32F0L0G0_TIM3_QE)
# undef CONFIG_STM32F0L0G0_TIM3
#if defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM3_ADC) || \
defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE)
# undef CONFIG_STM32_TIM3
#endif
#if defined(CONFIG_STM32F0L0G0_TIM4_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM4_DAC) || defined(CONFIG_STM32F0L0G0_TIM4_QE)
# undef CONFIG_STM32F0L0G0_TIM4
#if defined(CONFIG_STM32_TIM4_PWM) || defined(CONFIG_STM32_TIM4_ADC) || \
defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE)
# undef CONFIG_STM32_TIM4
#endif
#if defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM5_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM5_DAC) || defined(CONFIG_STM32F0L0G0_TIM5_QE)
# undef CONFIG_STM32F0L0G0_TIM5
#if defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM5_ADC) || \
defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE)
# undef CONFIG_STM32_TIM5
#endif
#if defined(CONFIG_STM32F0L0G0_TIM6_PWM) || defined(CONFIG_STM32F0L0G0_TIM6_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM6_DAC) || defined(CONFIG_STM32F0L0G0_TIM6_QE)
# undef CONFIG_STM32F0L0G0_TIM6
#if defined(CONFIG_STM32_TIM6_PWM) || defined(CONFIG_STM32_TIM6_ADC) || \
defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE)
# undef CONFIG_STM32_TIM6
#endif
#if defined(CONFIG_STM32F0L0G0_TIM7_PWM) || defined(CONFIG_STM32F0L0G0_TIM7_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM7_DAC) || defined(CONFIG_STM32F0L0G0_TIM7_QE)
# undef CONFIG_STM32F0L0G0_TIM7
#if defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM7_ADC) || \
defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE)
# undef CONFIG_STM32_TIM7
#endif
#if defined(CONFIG_STM32F0L0G0_TIM8_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM8_DAC) || defined(CONFIG_STM32F0L0G0_TIM8_QE)
# undef CONFIG_STM32F0L0G0_TIM8
#if defined(CONFIG_STM32_TIM8_PWM) || defined(CONFIG_STM32_TIM8_ADC) || \
defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE)
# undef CONFIG_STM32_TIM8
#endif
#if defined(CONFIG_STM32F0L0G0_TIM12_PWM) || defined(CONFIG_STM32F0L0G0_TIM12_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM12_DAC) || defined(CONFIG_STM32F0L0G0_TIM12_QE)
# undef CONFIG_STM32F0L0G0_TIM12
#if defined(CONFIG_STM32_TIM12_PWM) || defined(CONFIG_STM32_TIM12_ADC) || \
defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE)
# undef CONFIG_STM32_TIM12
#endif
#if defined(CONFIG_STM32F0L0G0_TIM13_PWM) || defined(CONFIG_STM32F0L0G0_TIM13_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM13_DAC) || defined(CONFIG_STM32F0L0G0_TIM13_QE)
# undef CONFIG_STM32F0L0G0_TIM13
#if defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM13_ADC) || \
defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE)
# undef CONFIG_STM32_TIM13
#endif
#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM14_DAC) || defined(CONFIG_STM32F0L0G0_TIM14_QE)
# undef CONFIG_STM32F0L0G0_TIM14
#if defined(CONFIG_STM32_TIM14_PWM) || defined(CONFIG_STM32_TIM14_ADC) || \
defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE)
# undef CONFIG_STM32_TIM14
#endif
#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM15_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM15_DAC) || defined(CONFIG_STM32F0L0G0_TIM15_QE)
# undef CONFIG_STM32F0L0G0_TIM15
#if defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM15_ADC) || \
defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE)
# undef CONFIG_STM32_TIM15
#endif
#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM16_DAC) || defined(CONFIG_STM32F0L0G0_TIM16_QE)
# undef CONFIG_STM32F0L0G0_TIM16
#if defined(CONFIG_STM32_TIM16_PWM) || defined(CONFIG_STM32_TIM16_ADC) || \
defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE)
# undef CONFIG_STM32_TIM16
#endif
#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) || defined(CONFIG_STM32F0L0G0_TIM17_ADC) || \
defined(CONFIG_STM32F0L0G0_TIM17_DAC) || defined(CONFIG_STM32F0L0G0_TIM17_QE)
# undef CONFIG_STM32F0L0G0_TIM17
#if defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_TIM17_ADC) || \
defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE)
# undef CONFIG_STM32_TIM17
#endif
#if defined(CONFIG_STM32F0L0G0_TIM1)
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \
defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \
defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT)
@ -165,35 +165,35 @@
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM2)
#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \
defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM3)
#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \
defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM4)
#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \
defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM5)
#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \
defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM8)
#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \
defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \
defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT)
@ -201,37 +201,37 @@
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM12)
#if defined(CONFIG_STM32_TIM12)
# if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT)
# define HAVE_TIM12_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM13)
#if defined(CONFIG_STM32_TIM13)
# if defined(GPIO_TIM13_CH1OUT)
# define HAVE_TIM13_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM14)
#if defined(CONFIG_STM32_TIM14)
# if defined(GPIO_TIM14_CH1OUT)
# define HAVE_TIM14_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM15)
#if defined(CONFIG_STM32_TIM15)
# if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT)
# define HAVE_TIM15_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM16)
#if defined(CONFIG_STM32_TIM16)
# if defined(GPIO_TIM16_CH1OUT)
# define HAVE_TIM16_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_TIM17)
#if defined(CONFIG_STM32_TIM17)
# if defined(GPIO_TIM17_CH1OUT)
# define HAVE_TIM17_GPIOCONFIG 1
# endif
@ -241,13 +241,13 @@
* intended for some other purpose.
*/
#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \
defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \
defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \
defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \
defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \
defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \
defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17)
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \
defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \
defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)
/****************************************************************************
* Private Types
@ -324,7 +324,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops =
.ackint = &stm32_tim_ackint
};
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
struct stm32_tim_priv_s stm32_tim1_priv =
{
.ops = &stm32_tim_ops,
@ -332,7 +332,7 @@ struct stm32_tim_priv_s stm32_tim1_priv =
.base = STM32_TIM1_BASE,
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
.ops = &stm32_tim_ops,
@ -341,7 +341,7 @@ struct stm32_tim_priv_s stm32_tim2_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv =
{
.ops = &stm32_tim_ops,
@ -350,7 +350,7 @@ struct stm32_tim_priv_s stm32_tim3_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
#ifdef CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv =
{
.ops = &stm32_tim_ops,
@ -359,7 +359,7 @@ struct stm32_tim_priv_s stm32_tim4_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5
#ifdef CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv =
{
.ops = &stm32_tim_ops,
@ -368,7 +368,7 @@ struct stm32_tim_priv_s stm32_tim5_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
.ops = &stm32_tim_ops,
@ -377,7 +377,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
.ops = &stm32_tim_ops,
@ -386,7 +386,7 @@ struct stm32_tim_priv_s stm32_tim7_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8
#ifdef CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv =
{
.ops = &stm32_tim_ops,
@ -395,7 +395,7 @@ struct stm32_tim_priv_s stm32_tim8_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM12
#ifdef CONFIG_STM32_TIM12
struct stm32_tim_priv_s stm32_tim12_priv =
{
.ops = &stm32_tim_ops,
@ -404,7 +404,7 @@ struct stm32_tim_priv_s stm32_tim12_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
struct stm32_tim_priv_s stm32_tim13_priv =
{
.ops = &stm32_tim_ops,
@ -413,7 +413,7 @@ struct stm32_tim_priv_s stm32_tim13_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
struct stm32_tim_priv_s stm32_tim14_priv =
{
.ops = &stm32_tim_ops,
@ -422,7 +422,7 @@ struct stm32_tim_priv_s stm32_tim14_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
struct stm32_tim_priv_s stm32_tim15_priv =
{
.ops = &stm32_tim_ops,
@ -431,7 +431,7 @@ struct stm32_tim_priv_s stm32_tim15_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
struct stm32_tim_priv_s stm32_tim16_priv =
{
.ops = &stm32_tim_ops,
@ -440,7 +440,7 @@ struct stm32_tim_priv_s stm32_tim16_priv =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
struct stm32_tim_priv_s stm32_tim17_priv =
{
.ops = &stm32_tim_ops,
@ -582,47 +582,47 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = STM32_APB2_TIM1_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = STM32_APB1_TIM2_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = STM32_APB1_TIM3_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = STM32_APB1_TIM6_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = STM32_APB1_TIM7_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
freqin = STM32_APB2_TIM14_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = STM32_APB2_TIM15_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = STM32_APB2_TIM16_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = STM32_APB2_TIM17_CLKIN;
break;
@ -680,47 +680,47 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = STM32_APB2_TIM1_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = STM32_APB1_TIM2_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = STM32_APB1_TIM3_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = STM32_APB1_TIM6_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = STM32_APB1_TIM7_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
freqin = STM32_APB2_TIM14_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = STM32_APB2_TIM15_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = STM32_APB2_TIM16_CLKIN;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = STM32_APB2_TIM17_CLKIN;
break;
@ -789,52 +789,52 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1_BRK;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
vectorno = STM32_IRQ_TIM13;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
vectorno = STM32_IRQ_TIM14;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
vectorno = STM32_IRQ_TIM15;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
vectorno = STM32_IRQ_TIM16;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
vectorno = STM32_IRQ_TIM17;
break;
@ -960,16 +960,16 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev,
stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val);
/* Advanced registers require Main Output Enable */
#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM8)
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM8)
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE
# if defined(CONFIG_STM32F0L0G0_TIM8)
# if defined(CONFIG_STM32_TIM8)
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE
# endif
)
{
stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
}
#endif /* CONFIG_STM32F0L0G0_TIM1 || CONFIG_STM32F0L0G0_TIM8 */
#endif /* CONFIG_STM32_TIM1 || CONFIG_STM32_TIM8 */
return OK;
}
@ -1065,7 +1065,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
@ -1099,7 +1099,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
@ -1159,7 +1159,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
switch (channel)
{
@ -1174,7 +1174,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
switch (channel)
{
@ -1189,7 +1189,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
switch (channel)
{
@ -1209,7 +1209,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
switch (channel)
{
@ -1224,7 +1224,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
switch (channel)
{
@ -1308,85 +1308,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM12
#ifdef CONFIG_STM32_TIM12
case 12:
dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
case 13:
dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case 14:
dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
@ -1418,72 +1418,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM12
#ifdef CONFIG_STM32_TIM12
case STM32_TIM12_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
break;
@ -1499,4 +1499,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev)
return OK;
}
#endif /* defined(CONFIG_STM32F0L0G0_TIM1 || ... || TIM17) */
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */

70
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c
View file

@ -61,13 +61,13 @@
#include "stm32_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \
defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \
defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \
defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \
defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \
defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \
defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17))
(defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \
defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \
defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17))
/****************************************************************************
* Pre-processor Definitions
@ -143,7 +143,7 @@ static const struct timer_ops_s g_timer_ops =
.ioctl = NULL,
};
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
#ifdef CONFIG_STM32_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5
#ifdef CONFIG_STM32_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8
#ifdef CONFIG_STM32_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM12
#ifdef CONFIG_STM32_TIM12
static struct stm32_lowerhalf_s g_tim12_lowerhalf =
{
.ops = &g_timer_ops,
@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
static struct stm32_lowerhalf_s g_tim13_lowerhalf =
{
.ops = &g_timer_ops,
@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
static struct stm32_lowerhalf_s g_tim14_lowerhalf =
{
.ops = &g_timer_ops,
@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
@ -247,7 +247,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf =
};
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
@ -559,72 +559,72 @@ int stm32_timer_initialize(const char *devpath, int timer)
switch (timer)
{
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM12
#ifdef CONFIG_STM32_TIM12
case 12:
lower = &g_tim12_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM13
#ifdef CONFIG_STM32_TIM13
case 13:
lower = &g_tim13_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
case 14:
lower = &g_tim14_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;

6
arch/arm/src/stm32f0l0g0/stm32_timerisr.c
View file

@ -47,9 +47,9 @@
* (when CLKSOURCE = 0). ..."
*/
#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK)
#if defined(CONFIG_STM32_SYSTICK_CORECLK)
# define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */
#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16)
#elif defined(CONFIG_STM32_SYSTICK_CORECLK_DIV16)
# define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */
#endif
@ -137,7 +137,7 @@ void up_timer_initialize(void)
* a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
*/
#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK
#ifdef CONFIG_STM32_SYSTICK_CORECLK
putreg32((SYSTICK_CSR_CLKSOURCE |
SYSTICK_CSR_TICKINT |
SYSTICK_CSR_ENABLE),

236
arch/arm/src/stm32f0l0g0/stm32_uart.h
View file

@ -41,29 +41,29 @@
* device.
*/
#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8)
# undef CONFIG_STM32F0L0G0_USART8
#if STM32_NUSART < 8 || !defined(CONFIG_STM32_HAVE_USART8)
# undef CONFIG_STM32_USART8
#endif
#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7)
# undef CONFIG_STM32F0L0G0_USART7
#if STM32_NUSART < 7 || !defined(CONFIG_STM32_HAVE_USART7)
# undef CONFIG_STM32_USART7
#endif
#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6)
# undef CONFIG_STM32F0L0G0_USART6
#if STM32_NUSART < 6 || !defined(CONFIG_STM32_HAVE_USART6)
# undef CONFIG_STM32_USART6
#endif
#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5)
# undef CONFIG_STM32F0L0G0_USART5
#if STM32_NUSART < 5 || !defined(CONFIG_STM32_HAVE_USART5)
# undef CONFIG_STM32_USART5
#endif
#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4)
# undef CONFIG_STM32F0L0G0_USART4
#if STM32_NUSART < 4 || !defined(CONFIG_STM32_HAVE_USART4)
# undef CONFIG_STM32_USART4
#endif
#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3)
# undef CONFIG_STM32F0L0G0_USART3
#if STM32_NUSART < 3 || !defined(CONFIG_STM32_HAVE_USART3)
# undef CONFIG_STM32_USART3
#endif
#if STM32_NUSART < 2
# undef CONFIG_STM32F0L0G0_USART2
# undef CONFIG_STM32_USART2
#endif
#if STM32_NUSART < 1
# undef CONFIG_STM32F0L0G0_USART1
# undef CONFIG_STM32_USART1
#endif
/* USART 3-8 are multiplexed to the same interrupt. Current interrupt
@ -72,128 +72,128 @@
* issue in the future.
*/
#if defined(CONFIG_STM32F0L0G0_USART3)
# undef CONFIG_STM32F0L0G0_USART4
# undef CONFIG_STM32F0L0G0_USART5
# undef CONFIG_STM32F0L0G0_USART6
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART4)
# undef CONFIG_STM32F0L0G0_USART5
# undef CONFIG_STM32F0L0G0_USART6
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART5)
# undef CONFIG_STM32F0L0G0_USART6
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART6)
# undef CONFIG_STM32F0L0G0_USART7
# undef CONFIG_STM32F0L0G0_USART8
#elif defined(CONFIG_STM32F0L0G0_USART7)
# undef CONFIG_STM32F0L0G0_USART8
#if defined(CONFIG_STM32_USART3)
# undef CONFIG_STM32_USART4
# undef CONFIG_STM32_USART5
# undef CONFIG_STM32_USART6
# undef CONFIG_STM32_USART7
# undef CONFIG_STM32_USART8
#elif defined(CONFIG_STM32_USART4)
# undef CONFIG_STM32_USART5
# undef CONFIG_STM32_USART6
# undef CONFIG_STM32_USART7
# undef CONFIG_STM32_USART8
#elif defined(CONFIG_STM32_USART5)
# undef CONFIG_STM32_USART6
# undef CONFIG_STM32_USART7
# undef CONFIG_STM32_USART8
#elif defined(CONFIG_STM32_USART6)
# undef CONFIG_STM32_USART7
# undef CONFIG_STM32_USART8
#elif defined(CONFIG_STM32_USART7)
# undef CONFIG_STM32_USART8
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \
defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \
defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \
defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8)
#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \
defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART4) || \
defined(CONFIG_STM32_USART5) || defined(CONFIG_STM32_USART6) || \
defined(CONFIG_STM32_USART7) || defined(CONFIG_STM32_USART8)
# define HAVE_USART 1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32F0L0G0_USART1)
# undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32_USART1)
# undef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART2)
# undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32_USART2)
# undef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART3)
# undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER
#if !defined(CONFIG_STM32_USART3)
# undef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_STM32_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART4)
# undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER
#if !defined(CONFIG_STM32_USART4)
# undef CONFIG_STM32_USART4_SERIALDRIVER
# undef CONFIG_STM32_USART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART5)
# undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER
#if !defined(CONFIG_STM32_USART5)
# undef CONFIG_STM32_USART5_SERIALDRIVER
# undef CONFIG_STM32_USART5_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART6)
# undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER
#if !defined(CONFIG_STM32_USART6)
# undef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_STM32_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART7)
# undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER
#if !defined(CONFIG_STM32_USART7)
# undef CONFIG_STM32_USART7_SERIALDRIVER
# undef CONFIG_STM32_USART7_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32F0L0G0_USART8)
# undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER
# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER
#if !defined(CONFIG_STM32_USART8)
# undef CONFIG_STM32_USART8_SERIALDRIVER
# undef CONFIG_STM32_USART8_1WIREDRIVER
#endif
/* Check 1-Wire and U(S)ART conflicts */
#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER
#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER
#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER
#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined
# undef CONFIG_STM32_USART3_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER
#if defined(CONFIG_STM32_USART4_1WIREDRIVER) && defined(CONFIG_STM32_USART4_SERIALDRIVER)
# error Both CONFIG_STM32_USART4_1WIREDRIVER and CONFIG_STM32_USART4_SERIALDRIVER defined
# undef CONFIG_STM32_USART4_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER
#if defined(CONFIG_STM32_USART5_1WIREDRIVER) && defined(CONFIG_STM32_USART5_SERIALDRIVER)
# error Both CONFIG_STM32_USART5_1WIREDRIVER and CONFIG_STM32_USART5_SERIALDRIVER defined
# undef CONFIG_STM32_USART5_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER
#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER)
# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined
# undef CONFIG_STM32_USART6_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER
#if defined(CONFIG_STM32_USART7_1WIREDRIVER) && defined(CONFIG_STM32_USART7_SERIALDRIVER)
# error Both CONFIG_STM32_USART7_1WIREDRIVER and CONFIG_STM32_USART7_SERIALDRIVER defined
# undef CONFIG_STM32_USART7_1WIREDRIVER
#endif
#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
# error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined
# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER
#if defined(CONFIG_STM32_USART8_1WIREDRIVER) && defined(CONFIG_STM32_USART8_SERIALDRIVER)
# error Both CONFIG_STM32_USART8_1WIREDRIVER and CONFIG_STM32_USART8_SERIALDRIVER defined
# undef CONFIG_STM32_USART8_1WIREDRIVER
#endif
/* Is the serial driver enabled? */
#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \
defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_USART4_SERIALDRIVER) || \
defined(CONFIG_STM32_USART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \
defined(CONFIG_STM32_USART7_SERIALDRIVER) || defined(CONFIG_STM32_USART8_SERIALDRIVER)
# define HAVE_SERIALDRIVER 1
#endif
/* Is the 1-Wire driver? */
#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \
defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER)
#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \
defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_USART4_1WIREDRIVER) || \
defined(CONFIG_STM32_USART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \
defined(CONFIG_STM32_USART7_1WIREDRIVER) || defined(CONFIG_STM32_USART8_1WIREDRIVER)
# define HAVE_1WIREDRIVER 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER)
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -203,7 +203,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -213,7 +213,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART4_SERIAL_CONSOLE
@ -223,7 +223,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)
#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -233,7 +233,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)
#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -243,7 +243,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER)
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -253,7 +253,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)
#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART7_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -264,7 +264,7 @@
# undef CONFIG_USART8_SERIAL_CONSOLE
# define CONSOLE_USART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART8_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -304,35 +304,35 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER
#ifndef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER
#ifndef CONFIG_STM32_USART4_SERIALDRIVER
# undef CONFIG_USART4_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER
#ifndef CONFIG_STM32_USART5_SERIALDRIVER
# undef CONFIG_USART5_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER
#ifndef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER
#ifndef CONFIG_STM32_USART7_SERIALDRIVER
# undef CONFIG_USART7_RXDMA
#endif
#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER
#ifndef CONFIG_STM32_USART8_SERIALDRIVER
# undef CONFIG_USART8_RXDMA
#endif
@ -370,21 +370,21 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#if defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
#elif defined(CONFIG_STM32_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
#elif defined(CONFIG_STM32_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
#elif defined(CONFIG_STM32_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
#elif defined(CONFIG_STM32_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif

14
arch/arm/src/stm32f0l0g0/stm32_usbdev.c
View file

@ -55,7 +55,7 @@
#include "stm32_gpio.h"
#include "stm32_usbdev.h"
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB)
#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB)
/****************************************************************************
* Pre-processor Definitions
@ -76,7 +76,7 @@
*/
#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
# undef CONFIG_STM32_USBDEV_REGDEBUG
#endif
/* Initial interrupt mask: Reset + Suspend + Correct Transfer */
@ -350,7 +350,7 @@ struct stm32_usbdev_s
/* Register operations ******************************************************/
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint16_t val, uint32_t addr);
static void stm32_dumpep(int epno);
@ -598,7 +598,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
* Name: stm32_getreg
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static uint16_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -656,7 +656,7 @@ static uint16_t stm32_getreg(uint32_t addr)
* Name: stm32_putreg
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_putreg(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
@ -673,7 +673,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
* Name: stm32_dumpep
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
#ifdef CONFIG_STM32_USBDEV_REGDEBUG
static void stm32_dumpep(int epno)
{
uint32_t addr;
@ -3885,4 +3885,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
return OK;
}
#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */
#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */

4
arch/arm/src/stm32f0l0g0/stm32_wdg.h
View file

@ -69,7 +69,7 @@ extern "C"
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_IWDG
#ifdef CONFIG_STM32_IWDG
void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq);
#endif
@ -90,7 +90,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_WWDG
#ifdef CONFIG_STM32_WWDG
void stm32_wwdginitialize(const char *devpath);
#endif

54
arch/arm/src/stm32f0l0g0/stm32c0_rcc.c
View file

@ -114,31 +114,31 @@ static inline void rcc_enableahb(void)
regval = getreg32(STM32_RCC_AHBENR);
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_MIF
#ifdef CONFIG_STM32_MIF
/* Memory interface clock enable */
regval |= RCC_AHBENR_MIFEN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHBENR_CRCEN;
#endif
#ifdef CONFIG_STM32F0L0G0_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHBENR_RNGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_AES
#ifdef CONFIG_STM32_AES
/* AES modules clock enable */
regval |= RCC_AHBENR_AESEN;
@ -165,67 +165,67 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
/* Timer 2 clock enable */
regval |= RCC_APB1ENR_TIM2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
/* Timer 3 clock enable */
regval |= RCC_APB1ENR_TIM3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* FDCAN1 clock enable */
regval |= RCC_APB1ENR_FDCANEN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI 2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
/* USB clock enable */
regval |= RCC_APB1ENR_USBEN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_APB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
/* USART 3 clock enable */
regval |= RCC_APB1ENR_USART3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
/* USART 4 clock enable */
regval |= RCC_APB1ENR_USART4EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C 1 clock enable */
regval |= RCC_APB1ENR_I2C1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
/* Power interface clock enable */
regval |= RCC_APB1ENR_PWREN;
@ -252,55 +252,55 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32F0L0G0_SYSCFG
#ifdef CONFIG_STM32_SYSCFG
/* SYSCFG clock */
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
/* TIM1 Timer clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI 1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
/* TIM14 Timer clock enable */
regval |= RCC_APB2ENR_TIM14EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
/* TIM5 Timer clock enable */
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
/* TIM16 Timer clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
/* TIM17 Timer clock enable */
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
#ifdef CONFIG_STM32_ADC1
/* ADC 1 clock enable */
regval |= RCC_APB2ENR_ADC1EN;
@ -364,7 +364,7 @@ static inline bool stm32_rcc_enablehse(void)
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
static void stm32_stdclockconfig(void)
{
uint32_t regval;
@ -457,7 +457,7 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#ifdef CONFIG_STM32F0L0G0_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Configure FDCAN1 clock source */
regval = getreg32(STM32_RCC_CCIPR1);

74
arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
View file

@ -44,7 +44,7 @@
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48)
#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48
# define STM32_USE_HSI48
# endif
@ -107,25 +107,25 @@ static inline void rcc_enableahb(void)
regval = getreg32(STM32_RCC_AHBENR);
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHBENR_DMA2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHBENR_CRCEN;
#endif
#ifdef CONFIG_STM32F0L0G0_TSC
#ifdef CONFIG_STM32_TSC
/* TSC clock enable */
regval |= RCC_AHBENR_TSCEN;
@ -152,121 +152,121 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
/* Timer 2 clock enable */
regval |= RCC_APB1ENR_TIM2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
/* Timer 3 clock enable */
regval |= RCC_APB1ENR_TIM3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM4
#ifdef CONFIG_STM32_TIM4
/* Timer 4 clock enable */
regval |= RCC_APB1ENR_TIM4EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
/* Timer 6 clock enable */
regval |= RCC_APB1ENR_TIM6EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
/* Timer 7 clock enable */
regval |= RCC_APB1ENR_TIM7EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
/* Timer 14 clock enable */
regval |= RCC_APB1ENR_TIM14EN;
#endif
#ifdef CONFIG_STM32F0L0G0_WWDG
#ifdef CONFIG_STM32_WWDG
/* Window Watchdog clock enable */
regval |= RCC_APB1ENR_WWDGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI 2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
/* USART 3 clock enable */
regval |= RCC_APB1ENR_USART3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
/* USART 4 clock enable */
regval |= RCC_APB1ENR_USART4EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
/* USART 5 clock enable */
regval |= RCC_APB1ENR_USART5EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C 1 clock enable */
regval |= RCC_APB1ENR_I2C1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C 2 clock enable */
regval |= RCC_APB1ENR_I2C2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
/* USB clock enable */
regval |= RCC_APB1ENR_USBEN;
#endif
#ifdef CONFIG_STM32F0L0G0_CAN1
#ifdef CONFIG_STM32_CAN1
/* CAN1 clock enable */
regval |= RCC_APB1ENR_CAN1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRS
#ifdef CONFIG_STM32_CRS
/* Clock recovery system clock enable */
regval |= RCC_APB1ENR_CRSEN;
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
/* Power interface clock enable */
regval |= RCC_APB1ENR_PWREN;
#endif
#ifdef CONFIG_STM32F0L0G0_DAC1
#ifdef CONFIG_STM32_DAC1
/* DAC 1 interface clock enable */
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_CEC
#ifdef CONFIG_STM32_CEC
/* CEC interface clock enable */
regval |= RCC_APB1ENR_CECEN;
@ -293,67 +293,67 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32F0L0G0_SYSCFG
#ifdef CONFIG_STM32_SYSCFG
/* SYSCFG clock */
regval |= RCC_APB2ENR_SYSCFGCOMPEN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART6
#ifdef CONFIG_STM32_USART6
/* USART 6 clock enable */
regval |= RCC_APB2ENR_USART6EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART7
#ifdef CONFIG_STM32_USART7
/* USART 7 clock enable */
regval |= RCC_APB2ENR_USART7EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART8
#ifdef CONFIG_STM32_USART8
/* USART 8 clock enable */
regval |= RCC_APB2ENR_USART8EN;
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
#ifdef CONFIG_STM32_ADC1
/* ADC 1 clock enable */
regval |= RCC_APB2ENR_ADC1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
/* Timer 1 clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI 1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
/* Timer 15 clock enable */
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
/* Timer 16 clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
/* Timer 17 clock enable */
regval |= RCC_APB2ENR_TIM17EN;
@ -379,7 +379,7 @@ static inline void rcc_enableapb2(void)
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
static void stm32_stdclockconfig(void)
{
uint32_t regval;

8
arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
View file

@ -37,7 +37,7 @@
#include "arm_internal.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32F0L0G0_PWR)
#if defined(CONFIG_STM32_PWR)
/****************************************************************************
* Private Data
@ -299,7 +299,7 @@ bool stm32_pwr_getwuf(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
#ifdef CONFIG_STM32_ENERGYLITE
void stm32_pwr_setvos(uint16_t vos)
{
uint16_t regval;
@ -391,6 +391,6 @@ void stm32_pwr_disablepvd(void)
stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0);
}
#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
#endif /* CONFIG_STM32_ENERGYLITE */
#endif /* CONFIG_STM32F0L0G0_PWR */
#endif /* CONFIG_STM32_PWR */

4
arch/arm/src/stm32f0l0g0/stm32g0_pwr.c
View file

@ -36,7 +36,7 @@
#include "arm_internal.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32F0L0G0_PWR)
#if defined(CONFIG_STM32_PWR)
/****************************************************************************
* Private Functions
@ -93,4 +93,4 @@ void stm32_pwr_setvos(uint16_t vos)
/* TODO Other stm32_pwr_* functions need to be implemented */
#endif /* CONFIG_STM32F0L0G0_PWR */
#endif /* CONFIG_STM32_PWR */

80
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
View file

@ -124,37 +124,37 @@ static inline void rcc_enableahb(void)
regval = getreg32(STM32_RCC_AHBENR);
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_MIF
#ifdef CONFIG_STM32_MIF
/* Memory interface clock enable */
regval |= RCC_AHBENR_MIFEN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHBENR_CRCEN;
#endif
#ifdef CONFIG_STM32F0L0G0_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHBENR_RNGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_AES
#ifdef CONFIG_STM32_AES
/* AES modules clock enable */
regval |= RCC_AHBENR_AESEN;
@ -181,91 +181,91 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
/* Timer 2 clock enable */
regval |= RCC_APB1ENR_TIM2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
/* Timer 3 clock enable */
regval |= RCC_APB1ENR_TIM3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
/* Timer 6 clock enable */
regval |= RCC_APB1ENR_TIM6EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
/* Timer 7 clock enable */
regval |= RCC_APB1ENR_TIM7EN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI 2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
/* USART 3 clock enable */
regval |= RCC_APB1ENR_USART3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
/* USART 4 clock enable */
regval |= RCC_APB1ENR_USART4EN;
#endif
#ifdef CONFIG_STM32F0L0G0_LPUSART1
#ifdef CONFIG_STM32_LPUSART1
/* USART 5 clock enable */
regval |= RCC_APB1ENR_LPUSART1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C 1 clock enable */
regval |= RCC_APB1ENR_I2C1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C 2 clock enable */
regval |= RCC_APB1ENR_I2C2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
/* Power interface clock enable */
regval |= RCC_APB1ENR_PWREN;
#endif
#ifdef CONFIG_STM32F0L0G0_DAC1
#ifdef CONFIG_STM32_DAC1
/* DAC 1 interface clock enable */
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_LPTIM1
#ifdef CONFIG_STM32_LPTIM1
/* LPTIM1 clock enable */
regval |= RCC_APB1ENR_LPTIM1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_LPTIM2
#ifdef CONFIG_STM32_LPTIM2
/* LPTIM2 clock enable */
regval |= RCC_APB1ENR_LPTIM2EN;
@ -292,55 +292,55 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32F0L0G0_SYSCFG
#ifdef CONFIG_STM32_SYSCFG
/* SYSCFG clock */
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM1
#ifdef CONFIG_STM32_TIM1
/* TIM1 Timer clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI 1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM14
#ifdef CONFIG_STM32_TIM14
/* TIM14 Timer clock enable */
regval |= RCC_APB2ENR_TIM14EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM15
#ifdef CONFIG_STM32_TIM15
/* TIM5 Timer clock enable */
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM16
#ifdef CONFIG_STM32_TIM16
/* TIM16 Timer clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM17
#ifdef CONFIG_STM32_TIM17
/* TIM17 Timer clock enable */
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
#ifdef CONFIG_STM32_ADC1
/* ADC 1 clock enable */
regval |= RCC_APB2ENR_ADC1EN;
@ -407,14 +407,14 @@ static inline bool stm32_rcc_enablehse(void)
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
static void stm32_stdclockconfig(void)
{
uint32_t regval;
#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
uint16_t pwrcr;
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
uint32_t pwr_vos;
#endif
uint32_t flash_ws;
@ -451,7 +451,7 @@ static void stm32_stdclockconfig(void)
if (STM32_SYSCLK_FREQUENCY > 16000000)
{
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
pwr_vos = PWR_CR1_VOS_RANGE1;
#endif
@ -470,7 +470,7 @@ static void stm32_stdclockconfig(void)
}
else
{
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
pwr_vos = PWR_CR1_VOS_RANGE2;
#endif
@ -484,11 +484,11 @@ static void stm32_stdclockconfig(void)
}
}
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
stm32_pwr_setvos(pwr_vos);
#endif
#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
/* If RTC / LCD selects HSE as clock source, the RTC prescaler
* needs to be set before HSEON bit is set.
*/
@ -626,8 +626,8 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32F0L0G0_IWDG) || \
defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
#if defined(CONFIG_STM32_IWDG) || \
defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
@ -638,7 +638,7 @@ static void stm32_stdclockconfig(void)
#endif
#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to

68
arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c
View file

@ -63,55 +63,55 @@
#define FLASH_BLOCK_SIZE _K(2)
#define FLASH_PAGE_SIZE 8
#if !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) && \
!defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) && \
!defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) && \
!defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE)
#if !defined(CONFIG_STM32_FLASH_CONFIG_4) && \
!defined(CONFIG_STM32_FLASH_CONFIG_6) && \
!defined(CONFIG_STM32_FLASH_CONFIG_8) && \
!defined(CONFIG_STM32_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE)
# error "No valid flash configuration was defined."
#endif
#ifdef CONFIG_STM32F0L0G0_FLASH_OVERRIDE
# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_4
# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_6
# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_8
# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_B
# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_C
# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_E
# if defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_4)
# define CONFIG_STM32F0L0G0_FLASH_CONFIG_4
# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_6)
# define CONFIG_STM32F0L0G0_FLASH_CONFIG_6
# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_8)
# define CONFIG_STM32F0L0G0_FLASH_CONFIG_8
# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_B)
# define CONFIG_STM32F0L0G0_FLASH_CONFIG_B
# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_C)
# define CONFIG_STM32F0L0G0_FLASH_CONFIG_C
# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_E)
# define CONFIG_STM32F0L0G0_FLASH_CONFIG_E
#ifdef CONFIG_STM32_FLASH_OVERRIDE
# undef CONFIG_STM32_FLASH_CONFIG_4
# undef CONFIG_STM32_FLASH_CONFIG_6
# undef CONFIG_STM32_FLASH_CONFIG_8
# undef CONFIG_STM32_FLASH_CONFIG_B
# undef CONFIG_STM32_FLASH_CONFIG_C
# undef CONFIG_STM32_FLASH_CONFIG_E
# if defined(CONFIG_STM32_FLASH_OVERRIDE_4)
# define CONFIG_STM32_FLASH_CONFIG_4
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_6)
# define CONFIG_STM32_FLASH_CONFIG_6
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_8)
# define CONFIG_STM32_FLASH_CONFIG_8
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B)
# define CONFIG_STM32_FLASH_CONFIG_B
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C)
# define CONFIG_STM32_FLASH_CONFIG_C
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32_FLASH_CONFIG_E
# else
# error "Invalid flash configuration override provided"
# endif
#endif
#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4)
#if defined(CONFIG_STM32_FLASH_CONFIG_4)
# define FLASH_NBLOCKS 8
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6)
#elif defined(CONFIG_STM32_FLASH_CONFIG_6)
# define FLASH_NBLOCKS 16
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8)
#elif defined(CONFIG_STM32_FLASH_CONFIG_8)
# define FLASH_NBLOCKS 32
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B)
#elif defined(CONFIG_STM32_FLASH_CONFIG_B)
# define FLASH_NBLOCKS 64
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C)
#elif defined(CONFIG_STM32_FLASH_CONFIG_C)
# define FLASH_NBLOCKS 128
# ifdef CONFIG_ARCH_CHIP_STM32G0
# define FLASH_DUAL_BANK 1
# define FLASH_BANK2_BASE 0x08020000
# endif
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E)
#elif defined(CONFIG_STM32_FLASH_CONFIG_E)
# define FLASH_NBLOCKS 256
# ifdef CONFIG_ARCH_CHIP_STM32G0
# define FLASH_DUAL_BANK 1
@ -421,12 +421,12 @@ static void flash_lock_opt(void)
static int flash_verify_blocknum(size_t block)
{
#ifdef FLASH_DUAL_BANK
#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C)
#if defined(CONFIG_STM32_FLASH_CONFIG_C)
if ((block < 0 || block > 63) && (block < 256 || block > 319))
{
return -EFAULT;
}
#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E)
#elif defined(CONFIG_STM32_FLASH_CONFIG_E)
if ((block < 0 || block > 127) && (block < 256 || block > 383))
{
return -EFAULT;

80
arch/arm/src/stm32f0l0g0/stm32l0_rcc.c
View file

@ -51,10 +51,10 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48)
#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
# define STM32_USE_HSI48
# ifndef CONFIG_STM32F0L0G0_VREFINT
# ifndef CONFIG_STM32_VREFINT
# error VREFINT must be enabled if HSI48 used
# endif
# endif
@ -133,31 +133,31 @@ static inline void rcc_enableahb(void)
regval = getreg32(STM32_RCC_AHBENR);
#ifdef CONFIG_STM32F0L0G0_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_MIF
#ifdef CONFIG_STM32_MIF
/* Memory interface clock enable */
regval |= RCC_AHBENR_MIFEN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHBENR_CRCEN;
#endif
#ifdef CONFIG_STM32F0L0G0_TSC
#ifdef CONFIG_STM32_TSC
/* TSC clock enable */
regval |= RCC_AHBENR_TSCEN;
#endif
#ifdef CONFIG_STM32F0L0G0_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHBENR_RNGEN;
@ -184,115 +184,115 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#ifdef CONFIG_STM32F0L0G0_TIM2
#ifdef CONFIG_STM32_TIM2
/* Timer 2 clock enable */
regval |= RCC_APB1ENR_TIM2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM3
#ifdef CONFIG_STM32_TIM3
/* Timer 3 clock enable */
regval |= RCC_APB1ENR_TIM3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM6
#ifdef CONFIG_STM32_TIM6
/* Timer 6 clock enable */
regval |= RCC_APB1ENR_TIM6EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM7
#ifdef CONFIG_STM32_TIM7
/* Timer 7 clock enable */
regval |= RCC_APB1ENR_TIM7EN;
#endif
#ifdef CONFIG_STM32F0L0G0_LCD
#ifdef CONFIG_STM32_LCD
/* LCD clock enable */
regval |= RCC_APB1ENR_LCDEN;
#endif
#ifdef CONFIG_STM32F0L0G0_WWDG
#ifdef CONFIG_STM32_WWDG
/* Window Watchdog clock enable */
regval |= RCC_APB1ENR_WWDGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI 2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART3
#ifdef CONFIG_STM32_USART3
/* USART 3 clock enable */
regval |= RCC_APB1ENR_USART3EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART4
#ifdef CONFIG_STM32_USART4
/* USART 4 clock enable */
regval |= RCC_APB1ENR_USART4EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART5
#ifdef CONFIG_STM32_USART5
/* USART 5 clock enable */
regval |= RCC_APB1ENR_USART5EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C 1 clock enable */
regval |= RCC_APB1ENR_I2C1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C 2 clock enable */
regval |= RCC_APB1ENR_I2C2EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
/* USB clock enable */
regval |= RCC_APB1ENR_USBEN;
#endif
#ifdef CONFIG_STM32F0L0G0_CRS
#ifdef CONFIG_STM32_CRS
/* Clock recovery system clock enable */
regval |= RCC_APB1ENR_CRSEN;
#endif
#ifdef CONFIG_STM32F0L0G0_PWR
#ifdef CONFIG_STM32_PWR
/* Power interface clock enable */
regval |= RCC_APB1ENR_PWREN;
#endif
#ifdef CONFIG_STM32F0L0G0_DAC1
#ifdef CONFIG_STM32_DAC1
/* DAC 1 interface clock enable */
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_I2C3
#ifdef CONFIG_STM32_I2C3
/* I2C 3 clock enable */
regval |= RCC_APB1ENR_I2C4EN;
#endif
#ifdef CONFIG_STM32F0L0G0_LPTIM1
#ifdef CONFIG_STM32_LPTIM1
/* LPTIM1 clock enable */
regval |= RCC_APB1ENR_LPTIM1EN;
@ -319,37 +319,37 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32F0L0G0_SYSCFG
#ifdef CONFIG_STM32_SYSCFG
/* SYSCFG clock */
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM21
#ifdef CONFIG_STM32_TIM21
/* TIM21 Timer clock enable */
regval |= RCC_APB2ENR_TIM21EN;
#endif
#ifdef CONFIG_STM32F0L0G0_TIM22
#ifdef CONFIG_STM32_TIM22
/* TIM22 Timer clock enable */
regval |= RCC_APB2ENR_TIM10EN;
#endif
#ifdef CONFIG_STM32F0L0G0_ADC1
#ifdef CONFIG_STM32_ADC1
/* ADC 1 clock enable */
regval |= RCC_APB2ENR_ADC1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI 1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32F0L0G0_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
@ -448,11 +448,11 @@ static inline bool stm32_rcc_enablehse(void)
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
static void stm32_stdclockconfig(void)
{
uint32_t regval;
#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
uint16_t pwrcr;
#endif
uint32_t pwr_vos;
@ -504,7 +504,7 @@ static void stm32_stdclockconfig(void)
stm32_pwr_setvos(pwr_vos);
#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
/* If RTC / LCD selects HSE as clock source, the RTC prescaler
* needs to be set before HSEON bit is set.
*/
@ -683,8 +683,8 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32F0L0G0_IWDG) || \
defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
#if defined(CONFIG_STM32_IWDG) || \
defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
@ -695,7 +695,7 @@ static void stm32_stdclockconfig(void)
#endif
#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
@ -722,7 +722,7 @@ static void stm32_stdclockconfig(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_VREFINT
#ifdef CONFIG_STM32_VREFINT
static void vrefint_enable(void)
{
uint32_t regval = 0;
@ -759,7 +759,7 @@ static inline void rcc_enableperipherals(void)
rcc_enableahb();
rcc_enableapb2();
rcc_enableapb1();
#ifdef CONFIG_STM32F0L0G0_VREFINT
#ifdef CONFIG_STM32_VREFINT
vrefint_enable();
#endif

10
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig
View file

@ -48,11 +48,11 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_ADC1=y
CONFIG_STM32F0L0G0_ADC1_DMA=y
CONFIG_STM32F0L0G0_DMA1=y
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_ADC1=y
CONFIG_STM32_ADC1_DMA=y
CONFIG_STM32_DMA1=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

4
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig
View file

@ -44,8 +44,8 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

6
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig
View file

@ -55,9 +55,9 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_I2C1=y
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_I2C1=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_STACKSIZE=1024
CONFIG_TASK_NAME_SIZE=0

6
boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig
View file

@ -53,9 +53,9 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_SPI1=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_PWR=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

2
boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h
View file

@ -87,7 +87,7 @@
/* 48MHz clock configuration */
#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG)
#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG)
# define STM32_USE_CLK48 1
# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
# define STM32_HSI48_SYNCSRC SYNCSRC_NONE

2
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt
View file

@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS)
list(APPEND SRCS stm32_buttons.c)
endif()
if(CONFIG_STM32F0L0G0_SPI)
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi.c)
endif()

2
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs
View file

@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
ifeq ($(CONFIG_STM32_SPI),y)
CSRCS += stm32_spi.c
endif

2
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h
View file

@ -137,7 +137,7 @@ int stm32_bringup(void);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
void stm32_spidev_initialize(void);
#endif

4
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c
View file

@ -36,7 +36,7 @@
#include "stm32.h"
#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1)
#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1)
/****************************************************************************
* Pre-processor Definitions
@ -130,4 +130,4 @@ int stm32_adc_setup(void)
return OK;
}
#endif /* CONFIG_ADC && CONFIG_STM32F0L0G0_ADC1 */
#endif /* CONFIG_ADC && CONFIG_STM32_ADC1 */

2
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c
View file

@ -70,7 +70,7 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/* Configure SPI chip selects */
stm32_spidev_initialize();

6
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c
View file

@ -97,13 +97,13 @@ static void stm32_i2c_register(int bus)
#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
static void stm32_i2ctool(void)
{
#ifdef CONFIG_STM32F0L0G0_I2C1
#ifdef CONFIG_STM32_I2C1
stm32_i2c_register(1);
#endif
#ifdef CONFIG_STM32F0L0G0_I2C2
#ifdef CONFIG_STM32_I2C2
stm32_i2c_register(2);
#endif
#ifdef CONFIG_STM32F0L0G0_I2C3
#ifdef CONFIG_STM32_I2C3
stm32_i2c_register(3);
#endif
}

14
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c
View file

@ -41,7 +41,7 @@
#include "b-l072z-lrwan1.h"
#include <arch/board/board.h>
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/****************************************************************************
* Pre-processor Definitions
@ -79,7 +79,7 @@ void stm32_spidev_initialize(void)
* architecture.
*/
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
# ifdef CONFIG_LPWAN_SX127X
/* Configure the SPI-based SX127X chip select GPIO */
@ -117,7 +117,7 @@ void stm32_spidev_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@ -168,9 +168,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
return status;
}
#endif /* CONFIG_STM32F0L0G0_SPI1 */
#endif /* CONFIG_STM32_SPI1 */
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@ -182,6 +182,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif /* CONFIG_STM32F0L0G0_SPI2 */
#endif /* CONFIG_STM32_SPI2 */
#endif /* CONFIG_STM32F0L0G0_SPI */
#endif /* CONFIG_STM32_SPI */

20
boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig
View file

@ -46,16 +46,16 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STM32F0L0G0_ADC1=y
CONFIG_STM32F0L0G0_ADC1_DMA=y
CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1
CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY=10
CONFIG_STM32F0L0G0_ADC1_TIMTRIG=3
CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6
CONFIG_STM32F0L0G0_DMA1=y
CONFIG_STM32F0L0G0_TIM1=y
CONFIG_STM32F0L0G0_TIM1_ADC=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_ADC1=y
CONFIG_STM32_ADC1_DMA=y
CONFIG_STM32_ADC1_DMA_CFG=1
CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=10
CONFIG_STM32_ADC1_TIMTRIG=3
CONFIG_STM32_ADC_MAX_SAMPLES=6
CONFIG_STM32_DMA1=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM1_ADC=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_ADCSCOPE=y
CONFIG_SYSTEM_ADCSCOPE_FETCH_INTERVAL=0
CONFIG_SYSTEM_ADCSCOPE_SERIAL_PATH="/dev/ttyS0"

28
boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig
View file

@ -72,20 +72,20 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_ADC1=y
CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6
CONFIG_STM32F0L0G0_DMA1=y
CONFIG_STM32F0L0G0_IWDG=y
CONFIG_STM32F0L0G0_PWM_MULTICHAN=y
CONFIG_STM32F0L0G0_TIM14=y
CONFIG_STM32F0L0G0_TIM14_CH1OUT=y
CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM14_PWM=y
CONFIG_STM32F0L0G0_TIM3=y
CONFIG_STM32F0L0G0_TIM3_QE=y
CONFIG_STM32F0L0G0_USART1=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32F0L0G0_WWDG=y
CONFIG_STM32_ADC1=y
CONFIG_STM32_ADC_MAX_SAMPLES=6
CONFIG_STM32_DMA1=y
CONFIG_STM32_IWDG=y
CONFIG_STM32_PWM_MULTICHAN=y
CONFIG_STM32_TIM14=y
CONFIG_STM32_TIM14_CH1OUT=y
CONFIG_STM32_TIM14_CHANNEL1=y
CONFIG_STM32_TIM14_PWM=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM3_QE=y
CONFIG_STM32_USART1=y
CONFIG_STM32_USART2=y
CONFIG_STM32_WWDG=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NXMBCLIENT=y
CONFIG_TASK_NAME_SIZE=0

2
boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig
View file

@ -38,7 +38,7 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

2
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c
View file

@ -54,7 +54,7 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/* Configure SPI chip selects */
stm32_spidev_initialize();

4
boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c
View file

@ -38,7 +38,7 @@
# include <nuttx/leds/userled.h>
#endif
#ifdef CONFIG_STM32F0L0G0_IWDG
#ifdef CONFIG_STM32_IWDG
# include <stm32_wdg.h>
#endif
@ -77,7 +77,7 @@ int stm32_bringup(void)
{
int ret;
#ifdef CONFIG_STM32F0L0G0_IWDG
#ifdef CONFIG_STM32_IWDG
/* Initialize the watchdog timer */
stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY);

10
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig
View file

@ -42,10 +42,10 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_FDCAN1=y
CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000
CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143
CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_FDCAN1=y
CONFIG_STM32_FDCAN1_BITRATE=250000
CONFIG_STM32_FDCAN1_NTSEG1=143
CONFIG_STM32_FDCAN1_NTSEG2=48
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_USART2_SERIAL_CONSOLE=y

12
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig
View file

@ -47,11 +47,11 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=10
CONFIG_START_YEAR=2014
CONFIG_STM32F0L0G0_FDCAN1=y
CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000
CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143
CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48
CONFIG_STM32F0L0G0_FDCAN_SOCKET=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_FDCAN1=y
CONFIG_STM32_FDCAN1_BITRATE=250000
CONFIG_STM32_FDCAN1_NTSEG1=143
CONFIG_STM32_FDCAN1_NTSEG2=48
CONFIG_STM32_FDCAN_SOCKET=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_USART2_SERIAL_CONSOLE=y

30
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig
View file

@ -69,21 +69,21 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_ADC1=y
CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=2
CONFIG_STM32F0L0G0_DMA1=y
CONFIG_STM32F0L0G0_IWDG=y
CONFIG_STM32F0L0G0_PWM_MULTICHAN=y
CONFIG_STM32F0L0G0_TIM14=y
CONFIG_STM32F0L0G0_TIM14_CH1OUT=y
CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM14_PWM=y
CONFIG_STM32F0L0G0_TIM1=y
CONFIG_STM32F0L0G0_TIM1_PULSECOUNT=y
CONFIG_STM32F0L0G0_TIM3=y
CONFIG_STM32F0L0G0_TIM3_QE=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32F0L0G0_WWDG=y
CONFIG_STM32_ADC1=y
CONFIG_STM32_ADC_MAX_SAMPLES=2
CONFIG_STM32_DMA1=y
CONFIG_STM32_IWDG=y
CONFIG_STM32_PWM_MULTICHAN=y
CONFIG_STM32_TIM14=y
CONFIG_STM32_TIM14_CH1OUT=y
CONFIG_STM32_TIM14_CHANNEL1=y
CONFIG_STM32_TIM14_PWM=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM1_PULSECOUNT=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM3_QE=y
CONFIG_STM32_USART2=y
CONFIG_STM32_WWDG=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

2
boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig
View file

@ -38,7 +38,7 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

6
boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt
View file

@ -36,11 +36,11 @@ if(CONFIG_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_STM32F0L0G0_FDCAN)
if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER)
if(CONFIG_STM32_FDCAN)
if(CONFIG_STM32_FDCAN_CHARDRIVER)
list(APPEND SRCS stm32_can.c)
endif()
if(CONFIG_STM32F0L0G0_FDCAN_SOCKET)
if(CONFIG_STM32_FDCAN_SOCKET)
list(APPEND SRCS stm32_cansock.c)
endif()
endif()

6
boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs
View file

@ -38,11 +38,11 @@ ifeq ($(CONFIG_ADC),y)
CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y)
ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y)
ifeq ($(CONFIG_STM32_FDCAN),y)
ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
CSRCS += stm32_can.c
endif
ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y)
ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y)
CSRCS += stm32_cansock.c
endif
endif

4
boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h
View file

@ -116,7 +116,7 @@ int stm32_adc_setup(void);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER
#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
int stm32_can_setup(void);
#endif
@ -128,7 +128,7 @@ int stm32_can_setup(void);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET
#ifdef CONFIG_STM32_FDCAN_SOCKET
int stm32_cansock_setup(void);
#endif

2
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c
View file

@ -54,7 +54,7 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/* Configure SPI chip selects */
stm32_spidev_initialize();

8
boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c
View file

@ -39,7 +39,7 @@
# include <nuttx/leds/userled.h>
#endif
#ifdef CONFIG_STM32F0L0G0_IWDG
#ifdef CONFIG_STM32_IWDG
# include <stm32_wdg.h>
#endif
@ -85,7 +85,7 @@ int stm32_bringup(void)
#endif
int ret;
#ifdef CONFIG_STM32F0L0G0_IWDG
#ifdef CONFIG_STM32_IWDG
/* Initialize the watchdog timer */
stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY);
@ -150,7 +150,7 @@ int stm32_bringup(void)
}
#endif
#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER
#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
/* Initialize CAN and register the CAN driver. */
ret = stm32_can_setup();
@ -160,7 +160,7 @@ int stm32_bringup(void)
}
#endif
#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET
#ifdef CONFIG_STM32_FDCAN_SOCKET
/* Initialize CAN socket interface */
ret = stm32_cansock_setup();

4
boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig
View file

@ -50,8 +50,8 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_RXBUFSIZE=32

4
boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h
View file

@ -101,7 +101,7 @@
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
@ -117,7 +117,7 @@
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */

12
boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h
View file

@ -42,14 +42,14 @@
/* How many SPI modules does this chip support? */
#if STM32_NSPI < 1
# undef CONFIG_STM32F0L0G0_SPI1
# undef CONFIG_STM32F0L0G0_SPI2
# undef CONFIG_STM32F0L0G0_SPI3
# undef CONFIG_STM32_SPI1
# undef CONFIG_STM32_SPI2
# undef CONFIG_STM32_SPI3
#elif STM32_NSPI < 2
# undef CONFIG_STM32F0L0G0_SPI2
# undef CONFIG_STM32F0L0G0_SPI3
# undef CONFIG_STM32_SPI2
# undef CONFIG_STM32_SPI3
#elif STM32_NSPI < 3
# undef CONFIG_STM32F0L0G0_SPI3
# undef CONFIG_STM32_SPI3
#endif
/* Nucleo-F072RB GPIOs ******************************************************/

2
boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c
View file

@ -40,7 +40,7 @@
****************************************************************************/
#undef HAVE_I2C_DRIVER
#if defined(CONFIG_STM32F0L0G0_I2C1) && defined(CONFIG_I2C_DRIVER)
#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER)
# define HAVE_I2C_DRIVER 1
#endif

4
boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig
View file

@ -52,8 +52,8 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

6
boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig
View file

@ -53,9 +53,9 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_SPI1=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_PWR=y
CONFIG_STM32_SPI1=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_SERIAL_CONSOLE=y

4
boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h
View file

@ -101,7 +101,7 @@
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */
#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
# undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */
# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
@ -117,7 +117,7 @@
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
#ifdef CONFIG_STM32F0L0G0_USB
#ifdef CONFIG_STM32_USB
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
#else
# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */

2
boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt
View file

@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS)
list(APPEND SRCS stm32_buttons.c)
endif()
if(CONFIG_STM32F0L0G0_SPI)
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi.c)
endif()

2
boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs
View file

@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
ifeq ($(CONFIG_STM32_SPI),y)
CSRCS += stm32_spi.c
endif

14
boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h
View file

@ -42,14 +42,14 @@
/* How many SPI modules does this chip support? */
#if STM32_NSPI < 1
# undef CONFIG_STM32F0L0G0_SPI1
# undef CONFIG_STM32F0L0G0_SPI2
# undef CONFIG_STM32F0L0G0_SPI3
# undef CONFIG_STM32_SPI1
# undef CONFIG_STM32_SPI2
# undef CONFIG_STM32_SPI3
#elif STM32_NSPI < 2
# undef CONFIG_STM32F0L0G0_SPI2
# undef CONFIG_STM32F0L0G0_SPI3
# undef CONFIG_STM32_SPI2
# undef CONFIG_STM32_SPI3
#elif STM32_NSPI < 3
# undef CONFIG_STM32F0L0G0_SPI3
# undef CONFIG_STM32_SPI3
#endif
/* Nucleo-F091RC GPIOs ******************************************************/
@ -126,7 +126,7 @@ int stm32_bringup(void);
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
void stm32_spidev_initialize(void);
#endif

2
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c
View file

@ -57,7 +57,7 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/* Configure SPI chip selects */
stm32_spidev_initialize();

14
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c
View file

@ -41,7 +41,7 @@
#include "nucleo-f091rc.h"
#include <arch/board/board.h>
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/****************************************************************************
* Pre-processor Definitions
@ -79,7 +79,7 @@ void stm32_spidev_initialize(void)
* architecture.
*/
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
# ifdef CONFIG_LPWAN_SX127X
/* Configure the SPI-based SX127X chip select GPIO */
@ -90,7 +90,7 @@ void stm32_spidev_initialize(void)
stm32_gpiowrite(GPIO_SX127X_CS, true);
# endif
#endif /* CONFIG_STM32F0L0G0_SPI1 */
#endif /* CONFIG_STM32_SPI1 */
}
/****************************************************************************
@ -119,7 +119,7 @@ void stm32_spidev_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F0L0G0_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev,
uint32_t devid, bool selected)
{
@ -170,9 +170,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid)
return status;
}
#endif /* CONFIG_STM32F0L0G0_SPI1 */
#endif /* CONFIG_STM32_SPI1 */
#ifdef CONFIG_STM32F0L0G0_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
@ -184,6 +184,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif /* CONFIG_STM32F0L0G0_SPI2 */
#endif /* CONFIG_STM32_SPI2 */
#endif

82
boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig
View file

@ -58,47 +58,47 @@ CONFIG_START_DAY=19
CONFIG_START_MONTH=5
CONFIG_START_YEAR=2013
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_STM32F0L0G0_I2C1=y
CONFIG_STM32F0L0G0_PWM_MULTICHAN=y
CONFIG_STM32F0L0G0_PWR=y
CONFIG_STM32F0L0G0_TIM14=y
CONFIG_STM32F0L0G0_TIM14_CH1OUT=y
CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM14_PWM=y
CONFIG_STM32F0L0G0_TIM15=y
CONFIG_STM32F0L0G0_TIM15_CH1OUT=y
CONFIG_STM32F0L0G0_TIM15_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM15_PWM=y
CONFIG_STM32F0L0G0_TIM16=y
CONFIG_STM32F0L0G0_TIM16_CH1OUT=y
CONFIG_STM32F0L0G0_TIM16_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM16_PWM=y
CONFIG_STM32F0L0G0_TIM17=y
CONFIG_STM32F0L0G0_TIM17_CH1OUT=y
CONFIG_STM32F0L0G0_TIM17_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM17_PWM=y
CONFIG_STM32F0L0G0_TIM1=y
CONFIG_STM32F0L0G0_TIM1_CH1OUT=y
CONFIG_STM32F0L0G0_TIM1_CH2OUT=y
CONFIG_STM32F0L0G0_TIM1_CH3OUT=y
CONFIG_STM32F0L0G0_TIM1_CH4OUT=y
CONFIG_STM32F0L0G0_TIM1_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM1_CHANNEL2=y
CONFIG_STM32F0L0G0_TIM1_CHANNEL3=y
CONFIG_STM32F0L0G0_TIM1_CHANNEL4=y
CONFIG_STM32F0L0G0_TIM1_PWM=y
CONFIG_STM32F0L0G0_TIM3=y
CONFIG_STM32F0L0G0_TIM3_CH1OUT=y
CONFIG_STM32F0L0G0_TIM3_CH2OUT=y
CONFIG_STM32F0L0G0_TIM3_CH3OUT=y
CONFIG_STM32F0L0G0_TIM3_CH4OUT=y
CONFIG_STM32F0L0G0_TIM3_CHANNEL1=y
CONFIG_STM32F0L0G0_TIM3_CHANNEL2=y
CONFIG_STM32F0L0G0_TIM3_CHANNEL3=y
CONFIG_STM32F0L0G0_TIM3_CHANNEL4=y
CONFIG_STM32F0L0G0_TIM3_PWM=y
CONFIG_STM32F0L0G0_TIM6=y
CONFIG_STM32F0L0G0_USART2=y
CONFIG_STM32_I2C1=y
CONFIG_STM32_PWM_MULTICHAN=y
CONFIG_STM32_PWR=y
CONFIG_STM32_TIM14=y
CONFIG_STM32_TIM14_CH1OUT=y
CONFIG_STM32_TIM14_CHANNEL1=y
CONFIG_STM32_TIM14_PWM=y
CONFIG_STM32_TIM15=y
CONFIG_STM32_TIM15_CH1OUT=y
CONFIG_STM32_TIM15_CHANNEL1=y
CONFIG_STM32_TIM15_PWM=y
CONFIG_STM32_TIM16=y
CONFIG_STM32_TIM16_CH1OUT=y
CONFIG_STM32_TIM16_CHANNEL1=y
CONFIG_STM32_TIM16_PWM=y
CONFIG_STM32_TIM17=y
CONFIG_STM32_TIM17_CH1OUT=y
CONFIG_STM32_TIM17_CHANNEL1=y
CONFIG_STM32_TIM17_PWM=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM1_CH1OUT=y
CONFIG_STM32_TIM1_CH2OUT=y
CONFIG_STM32_TIM1_CH3OUT=y
CONFIG_STM32_TIM1_CH4OUT=y
CONFIG_STM32_TIM1_CHANNEL1=y
CONFIG_STM32_TIM1_CHANNEL2=y
CONFIG_STM32_TIM1_CHANNEL3=y
CONFIG_STM32_TIM1_CHANNEL4=y
CONFIG_STM32_TIM1_PWM=y
CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM3_CH1OUT=y
CONFIG_STM32_TIM3_CH2OUT=y
CONFIG_STM32_TIM3_CH3OUT=y
CONFIG_STM32_TIM3_CH4OUT=y
CONFIG_STM32_TIM3_CHANNEL1=y
CONFIG_STM32_TIM3_CHANNEL2=y
CONFIG_STM32_TIM3_CHANNEL3=y
CONFIG_STM32_TIM3_CHANNEL4=y
CONFIG_STM32_TIM3_PWM=y
CONFIG_STM32_TIM6=y
CONFIG_STM32_USART2=y
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0

2
boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c
View file

@ -54,7 +54,7 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_STM32F0L0G0_SPI
#ifdef CONFIG_STM32_SPI
/* Configure SPI chip selects */
stm32_spidev_initialize();

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