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!arch/stm32l5: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32L5 Kconfig symbols were renamed from CONFIG_STM32L5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-28 14:28:41 +02:00 • committed by Alan C. Assis
parent 0d4a9cf1c8
commit 4033c54742
37 changed files with 469 additions and 3629 deletions
Download patch file Download diff file Expand all files Collapse all files

4
Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst
View file

@ -104,7 +104,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
Use make menuconfig to configure USART3 as the console::
CONFIG_STM32L5_USART3=y
CONFIG_STM32_USART3=y
CONFIG_USART3_SERIALDRIVER=y
CONFIG_USART3_SERIAL_CONSOLE=y
CONFIG_USART3_RXBUFSIZE=256
@ -126,7 +126,7 @@ Solder Bridges (active by default on Nucleo-L552ZE-Q)::
Use make menuconfig to configure LPUART1 as the console::
CONFIG_STM32L5_LPUART1=y
CONFIG_STM32_LPUART1=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_RXBUFSIZE=256
CONFIG_LPUART1_TXBUFSIZE=256

8
Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst
View file

@ -84,7 +84,7 @@ the STLINK Virtual COM Port.
Use make menuconfig to configure USART1 as the console::
CONFIG_STM32L5_USART1=y
CONFIG_STM32_USART1=y
CONFIG_USART1_SERIALDRIVER=y
CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USART1_RXBUFSIZE=256
@ -220,9 +220,9 @@ NOTES:
output on USART1, as described above under "Serial Console". The
elevant configuration settings are listed below::
CONFIG_STM32L5_USART1=y
CONFIG_STM32L5_USART1_SERIALDRIVER=y
CONFIG_STM32L5_USART=y
CONFIG_STM32_USART1=y
CONFIG_STM32_USART1_SERIALDRIVER=y
CONFIG_STM32_USART=y
CONFIG_USART1_SERIALDRIVER=y
CONFIG_USART1_SERIAL_CONSOLE=y

1
arch/arm/Kconfig
View file

@ -700,6 +700,7 @@ config ARCH_CHIP_STM32N6
config ARCH_CHIP_STM32L5
bool "STMicro STM32 L5"
select ARCH_CHIP_STM32
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP

6
arch/arm/include/stm32l5/chip.h
View file

@ -33,14 +33,14 @@
* Pre-processor Prototypes
****************************************************************************/
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
#else
# error "Unsupported STM32L5 chip"
#endif
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# define STM32_NFSMC 1 /* Have FSMC memory controller */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
@ -69,7 +69,7 @@
# define STM32_NCRC 1 /* CRC */
# define STM32_NCOMP 2 /* Comparators */
# define STM32_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32L5_STM32L562XX */
#endif /* CONFIG_STM32_STM32L562XX */
/* NVIC priority levels *****************************************************/

2
arch/arm/include/stm32l5/irq.h
View file

@ -33,7 +33,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include <arch/stm32l5/stm32l562xx_irq.h>
#else
# error "Unsupported STM32 L5 chip"

2
arch/arm/include/stm32l5/stm32l562xx_irq.h
View file

@ -160,7 +160,7 @@
#define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */
#define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# define STM32_IRQ_NEXTINTS 109
#else
# error "Unsupported STM32L5 chip"

2
arch/arm/src/stm32l5/CMakeLists.txt
View file

@ -61,7 +61,7 @@ endif()
# Required chip type specific files
if(CONFIG_STM32L5_STM32L562XX)
if(CONFIG_STM32_STM32L562XX)
list(APPEND SRCS stm32l562xx_rcc.c)
endif()

3231
arch/arm/src/stm32l5/Kconfig
View file

File diff suppressed because it is too large Load diff

2
arch/arm/src/stm32l5/Make.defs
View file

@ -56,6 +56,6 @@ endif
# Required chip type specific files
ifeq ($(CONFIG_STM32L5_STM32L562XX),y)
ifeq ($(CONFIG_STM32_STM32L562XX),y)
CHIP_CSRCS += stm32l562xx_rcc.c
endif

4
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
/****************************************************************************
* Pre-processor Definitions
@ -865,5 +865,5 @@
# define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT)
# define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT)
#endif /* CONFIG_STM32L5_STM32L562XX */
#endif /* CONFIG_STM32_STM32L562XX */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H */

4
arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
/****************************************************************************
* Pre-processor Definitions
@ -133,5 +133,5 @@
#define SYSCFG_RSSCMDR_SHIFT 0
#define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT)
#endif /* CONFIG_STM32L5_STM32L562XX */
#endif /* CONFIG_STM32_STM32L562XX */
#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H */

32
arch/arm/src/stm32l5/hardware/stm32l5_flash.h
View file

@ -35,7 +35,7 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT is set the
* When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32L5_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number. This value can be overridden with
* CONFIG_STM32L5_FLASH_OVERRIDE_x
@ -46,33 +46,33 @@
* N.B. Only Single bank mode is supported
*/
#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32L5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32L5_FLASH_CONFIG_E)
# define CONFIG_STM32L5_FLASH_OVERRIDE_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E)
# define CONFIG_STM32_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32L5_FLASH_CONFIG_C
# undef CONFIG_STM32L5_FLASH_CONFIG_E
# if defined(CONFIG_STM32L5_FLASH_OVERRIDE_C)
# define CONFIG_STM32L5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32L5_FLASH_OVERRIDE_E)
# define CONFIG_STM32L5_FLASH_CONFIG_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32_FLASH_CONFIG_C
# undef CONFIG_STM32_FLASH_CONFIG_E
# if defined(CONFIG_STM32_FLASH_OVERRIDE_C)
# define CONFIG_STM32_FLASH_CONFIG_C
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32_FLASH_CONFIG_E
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */
#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */
# define STM32_FLASH_NPAGES 64
# define STM32_FLASH_PAGESIZE 4096
#elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */
#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */
# define STM32_FLASH_NPAGES 128
# define STM32_FLASH_PAGESIZE 4096
#else

2
arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include "hardware/stm32l562xx_pinmap.h"
#else
# error "Unsupported STM32 L5 pin map"

2
arch/arm/src/stm32l5/hardware/stm32l5_spi.h
View file

@ -36,7 +36,7 @@
/* Maximum allowed speed as per specifications for all SPIs */
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# define STM32_SPI_CLK_MAX 55000000UL
#else
# error "Unsupported STM32 L5 chip"

2
arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include "hardware/stm32l562xx_syscfg.h"
#else
# error "Unsupported STM32 L5 chip"

108
arch/arm/src/stm32l5/stm32l562xx_rcc.c
View file

@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32_USE_CLK48)
#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
# define STM32_USE_HSI48
# endif
@ -92,19 +92,19 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
#ifdef CONFIG_STM32L5_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHB1ENR_DMA1EN;
#endif
#ifdef CONFIG_STM32L5_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHB1ENR_DMA2EN;
#endif
#ifdef CONFIG_STM32L5_DMAMUX1
#ifdef CONFIG_STM32_DMAMUX1
/* DMAMUX1 clock enable */
regval |= RCC_AHB1ENR_DMAMUX1EN;
@ -116,13 +116,13 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_FLASHEN;
#endif
#ifdef CONFIG_STM32L5_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32L5_TSC
#ifdef CONFIG_STM32_TSC
/* TSC clock enable */
regval |= RCC_AHB1ENR_TSCEN;
@ -183,25 +183,25 @@ static inline void rcc_enableahb2(void)
);
#endif
#if defined(CONFIG_STM32L5_ADC)
#if defined(CONFIG_STM32_ADC)
/* ADC clock enable */
regval |= RCC_AHB2ENR_ADCEN;
#endif
#ifdef CONFIG_STM32L5_AES
#ifdef CONFIG_STM32_AES
/* Cryptographic modules clock enable */
regval |= RCC_AHB2ENR_AESEN;
#endif
#ifdef CONFIG_STM32L5_HASH
#ifdef CONFIG_STM32_HASH
/* Hash module enable */
regval |= RCC_AHB2ENR_HASHEN
#endif
#ifdef CONFIG_STM32L5_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
@ -246,13 +246,13 @@ static inline void rcc_enableahb3(void)
regval = getreg32(STM32_RCC_AHB3ENR);
#ifdef CONFIG_STM32L5_FMC
#ifdef CONFIG_STM32_FMC
/* Flexible memory controller clock enable */
regval |= RCC_AHB3ENR_FMCEN;
#endif
#ifdef CONFIG_STM32L5_OCTOSPI1
#ifdef CONFIG_STM32_OCTOSPI1
/* OCTOSPI1 module clock enable */
regval |= RCC_AHB3ENR_OSPI1EN;
@ -279,43 +279,43 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR1);
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
/* TIM2 clock enable */
regval |= RCC_APB1ENR1_TIM2EN;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
/* TIM3 clock enable */
regval |= RCC_APB1ENR1_TIM3EN;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
/* TIM4 clock enable */
regval |= RCC_APB1ENR1_TIM4EN;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
/* TIM5 clock enable */
regval |= RCC_APB1ENR1_TIM5EN;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
/* TIM6 clock enable */
regval |= RCC_APB1ENR1_TIM6EN;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
/* TIM7 clock enable */
regval |= RCC_APB1ENR1_TIM7EN;
#endif
#ifdef CONFIG_STM32L5_RTC
#ifdef CONFIG_STM32_RTC
/* RTC APB clock enable */
regval |= RCC_APB1ENR1_RTCAPBEN;
@ -327,55 +327,55 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR1_WWDGEN;
#endif
#ifdef CONFIG_STM32L5_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI2 clock enable */
regval |= RCC_APB1ENR1_SPI2EN;
#endif
#ifdef CONFIG_STM32L5_SPI3
#ifdef CONFIG_STM32_SPI3
/* SPI3 clock enable */
regval |= RCC_APB1ENR1_SPI3EN;
#endif
#ifdef CONFIG_STM32L5_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR1_USART2EN;
#endif
#ifdef CONFIG_STM32L5_USART3
#ifdef CONFIG_STM32_USART3
/* USART3 clock enable */
regval |= RCC_APB1ENR1_USART3EN;
#endif
#ifdef CONFIG_STM32L5_UART4
#ifdef CONFIG_STM32_UART4
/* UART4 clock enable */
regval |= RCC_APB1ENR1_UART4EN;
#endif
#ifdef CONFIG_STM32L5_UART5
#ifdef CONFIG_STM32_UART5
/* UART5 clock enable */
regval |= RCC_APB1ENR1_UART5EN;
#endif
#ifdef CONFIG_STM32L5_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C1 clock enable */
regval |= RCC_APB1ENR1_I2C1EN;
#endif
#ifdef CONFIG_STM32L5_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C2 clock enable */
regval |= RCC_APB1ENR1_I2C2EN;
#endif
#ifdef CONFIG_STM32L5_I2C3
#ifdef CONFIG_STM32_I2C3
/* I2C3 clock enable */
regval |= RCC_APB1ENR1_I2C3EN;
@ -396,19 +396,19 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR1_PWREN;
#if defined (CONFIG_STM32L5_DAC1)
#if defined (CONFIG_STM32_DAC1)
/* DAC1 interface clock enable */
regval |= RCC_APB1ENR1_DAC1EN;
#endif
#ifdef CONFIG_STM32L5_OPAMP
#ifdef CONFIG_STM32_OPAMP
/* OPAMP clock enable */
regval |= RCC_APB1ENR1_OPAMPEN;
#endif
#ifdef CONFIG_STM32L5_LPTIM1
#ifdef CONFIG_STM32_LPTIM1
/* Low power timer 1 clock enable */
regval |= RCC_APB1ENR1_LPTIM1EN;
@ -420,43 +420,43 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR2);
#ifdef CONFIG_STM32L5_LPUART1
#ifdef CONFIG_STM32_LPUART1
/* Low power uart clock enable */
regval |= RCC_APB1ENR2_LPUART1EN;
#endif
#ifdef CONFIG_STM32L5_I2C4
#ifdef CONFIG_STM32_I2C4
/* I2C4 clock enable */
regval |= RCC_APB1ENR2_I2C4EN;
#endif
#ifdef CONFIG_STM32L5_LPTIM2
#ifdef CONFIG_STM32_LPTIM2
/* Low power timer 2 clock enable */
regval |= RCC_APB1ENR2_LPTIM2EN;
#endif
#ifdef CONFIG_STM32L5_LPTIM3
#ifdef CONFIG_STM32_LPTIM3
/* Low power timer 3 clock enable */
regval |= RCC_APB1ENR2_LPTIM3EN;
#endif
#ifdef CONFIG_STM32L5_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* FDCAN1 clock enable */
regval |= RCC_APB1ENR2_FDCAN1EN;
#endif
#ifdef CONFIG_STM32L5_USBFS
#ifdef CONFIG_STM32_USBFS
/* USB FS clock enable */
regval |= RCC_APB1ENR2_USBFSEN;
#endif
#ifdef CONFIG_STM32L5_UCPD1
#ifdef CONFIG_STM32_UCPD1
/* UCPD1 clock enable */
regval |= RCC_APB1ENR2_UCPD1EN;
@ -483,7 +483,7 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#if defined(CONFIG_STM32L5_SYSCFG) || defined(CONFIG_STM32L5_COMP)
#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP)
/* System configuration controller, comparators, and voltage reference
* buffer clock enable
*/
@ -491,61 +491,61 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
/* TIM1 clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32L5_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
/* TIM8 clock enable */
regval |= RCC_APB2ENR_TIM8EN;
#endif
#ifdef CONFIG_STM32L5_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
/* TIM15 clock enable */
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
/* TIM16 clock enable */
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
/* TIM17 clock enable */
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32L5_SAI1
#ifdef CONFIG_STM32_SAI1
/* SAI1 clock enable */
regval |= RCC_APB2ENR_SAI1EN;
#endif
#ifdef CONFIG_STM32L5_SAI2
#ifdef CONFIG_STM32_SAI2
/* SAI2 clock enable */
regval |= RCC_APB2ENR_SAI2EN;
#endif
#ifdef CONFIG_STM32L5_DFSDM1
#ifdef CONFIG_STM32_DFSDM1
/* DFSDM clock enable */
regval |= RCC_APB2ENR_DFSDMEN;
@ -598,7 +598,7 @@ void stm32_rcc_enableperipherals(void)
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void)
{
uint32_t regval;
@ -753,7 +753,7 @@ void stm32_stdclockconfig(void)
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#ifdef CONFIG_STM32L5_RTC_HSECLOCK
#ifdef CONFIG_STM32_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR);
@ -812,7 +812,7 @@ void stm32_stdclockconfig(void)
{
}
#ifdef CONFIG_STM32L5_SAI1PLL
#ifdef CONFIG_STM32_SAI1PLL
/* Configure SAI1 PLL */
regval = getreg32(STM32_RCC_PLLSAI1CFG);
@ -847,7 +847,7 @@ void stm32_stdclockconfig(void)
}
#endif
#ifdef CONFIG_STM32L5_SAI2PLL
#ifdef CONFIG_STM32_SAI2PLL
/* Configure SAI2 PLL */
regval = getreg32(STM32_RCC_PLLSAI2CFG);
@ -898,7 +898,7 @@ void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32L5_IWDG) || defined(CONFIG_STM32L5_RTC_LSICLOCK)
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();

16
arch/arm/src/stm32l5/stm32l5_allocateheap.c
View file

@ -60,7 +60,7 @@
* FSMC. In order to use FSMC SRAM, the following additional things need to
* be present in the NuttX configuration file:
*
* CONFIG_STM32L5_FSMC=y : Enables the FSMC
* CONFIG_STM32_FSMC=y : Enables the FSMC
* CONFIG_STM32L5_FSMC_SRAM=y : Indicates that SRAM is available via the
* FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
@ -71,7 +71,7 @@
* include the additional regions.
*/
#ifndef CONFIG_STM32L5_FSMC
#ifndef CONFIG_STM32_FSMC
# undef CONFIG_STM32L5_FSMC_SRAM
#endif
@ -116,14 +116,14 @@
* that we have been asked to add to the heap.
*/
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L5_SRAM2_HEAP) + \
defined(CONFIG_STM32L5_SRAM3_HEAP) + \
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \
defined(CONFIG_STM32_SRAM3_HEAP) + \
defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1
# error "You need more memory manager regions to support selected heap components"
#endif
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L5_SRAM2_HEAP) + \
defined(CONFIG_STM32L5_SRAM3_HEAP) + \
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \
defined(CONFIG_STM32_SRAM3_HEAP) + \
defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1
# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
#endif
@ -312,7 +312,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifdef CONFIG_STM32L5_SRAM2_HEAP
#ifdef CONFIG_STM32_SRAM2_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
@ -332,7 +332,7 @@ void arm_addregion(void)
#endif /* SRAM2 */
#ifdef CONFIG_STM32L5_SRAM3_HEAP
#ifdef CONFIG_STM32_SRAM3_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)

2
arch/arm/src/stm32l5/stm32l5_dbgmcu.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include "hardware/stm32l562xx_dbgmcu.h"
#else
# error "Unsupported STM32L5 chip"

2
arch/arm/src/stm32l5/stm32l5_exti.h
View file

@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
*
****************************************************************************/
#ifdef CONFIG_STM32L5_COMP
#ifdef CONFIG_STM32_COMP
int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
#endif

4
arch/arm/src/stm32l5/stm32l5_flash.c
View file

@ -50,11 +50,11 @@
#include "stm32l5_flash.h"
#include "arm_internal.h"
#if !defined(CONFIG_STM32L5_STM32L562XX)
#if !defined(CONFIG_STM32_STM32L562XX)
# error "Unrecognized STM32 chip"
#endif
#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT)
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# warning "Flash Configuration has been overridden - make sure it is correct"
#endif

2
arch/arm/src/stm32l5/stm32l5_gpio.h
View file

@ -39,7 +39,7 @@
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include "hardware/stm32l5_gpio.h"
#else
# error "Unsupported STM32L5 chip"

2
arch/arm/src/stm32l5/stm32l5_idle.c
View file

@ -92,7 +92,7 @@ void up_idle(void)
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();

20
arch/arm/src/stm32l5/stm32l5_lse.c
View file

@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void)
bool writable;
uint32_t regval;
volatile int32_t timeout;
#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
volatile int32_t drive = 0;
#endif
@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void)
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. LSE must be OFF
* to change drive strength.
*/
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
regval |= RCC_BDCR_LSEON;
#endif
#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
do
{
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
if (timeout != 0)
{
break;
@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */

10
arch/arm/src/stm32l5/stm32l5_rcc.c
View file

@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
*
****************************************************************************/
#if defined(CONFIG_STM32L5_PWR) && defined(CONFIG_STM32L5_RTC)
#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC)
static inline void rcc_resetbkp(void)
{
bool init_stat;
@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void)
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -171,7 +171,7 @@ void stm32_clockconfig(void)
rcc_resetbkp();
#endif
#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@ -205,7 +205,7 @@ void stm32_clockconfig(void)
* stm32_clockconfig()
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -220,7 +220,7 @@ void stm32_clockconfig(void)
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */

10
arch/arm/src/stm32l5/stm32l5_rcc.h
View file

@ -32,7 +32,7 @@
#include "arm_internal.h"
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include "hardware/stm32l562xx_rcc.h"
#else
# error "Unsupported STM32L5 chip"
@ -100,7 +100,7 @@ static inline void stm32_mcoconfig(uint32_t source)
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -123,7 +123,7 @@ void stm32_clockconfig(void);
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG
#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
@ -138,7 +138,7 @@ void stm32_board_clockconfig(void);
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void);
#endif
@ -155,7 +155,7 @@ void stm32_stdclockconfig(void);
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*

98
arch/arm/src/stm32l5/stm32l5_serial.c
View file

@ -82,14 +82,14 @@
*/
# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA)
# if !defined(CONFIG_STM32L5_DMA1) && !defined(CONFIG_STM32L5_DMAMUX)
# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32L5_DMA1
# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX)
# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32_DMA1
# endif
# endif
# if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA)
# if !defined(CONFIG_STM32L5_DMA2) && !defined(CONFIG_STM32L5_DMAMUX)
# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32L5_DMA2
# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX)
# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32_DMA2
# endif
# endif
@ -116,7 +116,7 @@
/* UART2-5 have no alternate channels without DMAMUX */
# ifndef CONFIG_STM32L5_HAVE_DMAMUX
# ifndef CONFIG_STM32_HAVE_DMAMUX
# define DMAMAP_USART2_RX DMACHAN_USART2_RX
# define DMAMAP_USART3_RX DMACHAN_USART3_RX
# define DMAMAP_UART4_RX DMACHAN_UART4_RX
@ -149,11 +149,11 @@
* can be individually invalidated.
*/
# if !defined(CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE == 0
# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0
# define RXDMA_BUFFER_SIZE 32
# else
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# endif
/* DMA priority */
@ -185,8 +185,8 @@
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32L5_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32L5_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
/* Keep track if a Break was set
@ -200,7 +200,7 @@
* See stm32l5serial_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops =
/* I/O buffers */
#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE];
static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE];
# ifdef CONFIG_LPUART1_RXDMA
@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_USART1_RXDMA
@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_USART2_RXDMA
@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
# ifdef CONFIG_USART3_RXDMA
@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_UART4_RXDMA
@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
# ifdef CONFIG_UART5_RXDMA
@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static struct stm32_serial_s g_lpuart1priv =
{
.dev =
@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv =
};
#endif
#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static struct stm32_serial_s g_usart1priv =
{
.dev =
@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static struct stm32_serial_s g_usart2priv =
{
.dev =
@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv =
/* This describes the state of the STM32 USART3 port. */
#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
static struct stm32_serial_s g_usart3priv =
{
.dev =
@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv =
/* This describes the state of the STM32 UART4 port. */
#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
static struct stm32_serial_s g_uart4priv =
{
.dev =
@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv =
/* This describes the state of the STM32 UART5 port. */
#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
static struct stm32_serial_s g_uart5priv =
{
.dev =
@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv =
static struct stm32_serial_s * const
g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] =
{
#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
[0] = &g_lpuart1priv,
#endif
#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
[1] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
[2] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
[3] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
[4] = &g_uart4priv,
#endif
#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
[5] = &g_uart5priv,
#endif
};
@ -1021,7 +1021,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev)
uint32_t cr1;
uint32_t brr;
#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
if (priv->usartbase == STM32_LPUART1_BASE)
{
/* LPUART BRR = 256 * fCK / baud */
@ -1111,7 +1111,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev)
regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -1315,37 +1315,37 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
case STM32_LPUART1_BASE:
rcc_en = RCC_APB1ENR2_LPUART1EN;
regaddr = STM32_RCC_APB1ENR2;
break;
#endif
#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
case STM32_USART2_BASE:
rcc_en = RCC_APB1ENR1_USART2EN;
regaddr = STM32_RCC_APB1ENR1;
break;
#endif
#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
case STM32_USART3_BASE:
rcc_en = RCC_APB1ENR1_USART3EN;
regaddr = STM32_RCC_APB1ENR1;
break;
#endif
#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
case STM32_UART4_BASE:
rcc_en = RCC_APB1ENR1_UART4EN;
regaddr = STM32_RCC_APB1ENR1;
break;
#endif
#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
case STM32_UART5_BASE:
rcc_en = RCC_APB1ENR1_UART5EN;
regaddr = STM32_RCC_APB1ENR1;
@ -1414,7 +1414,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32L5_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -1765,8 +1765,8 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32L5_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L5_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -1909,7 +1909,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32L5_USART_SINGLEWIRE
#ifdef CONFIG_STM32_USART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
uint32_t cr1;
@ -1987,7 +1987,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32L5_USART_INVERT
#ifdef CONFIG_STM32_USART_INVERT
case TIOCSINVERT:
{
uint32_t cr1;
@ -2038,7 +2038,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32L5_USART_SWAP
#ifdef CONFIG_STM32_USART_SWAP
case TIOCSSWAP:
{
uint32_t cr1;
@ -2175,8 +2175,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd,
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32L5_USART_BREAKS
# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -2404,7 +2404,7 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev,
(struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -2756,7 +2756,7 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable)
}
# endif
# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{
leave_critical_section(flags);
@ -3097,7 +3097,7 @@ void arm_serialinit(void)
#if CONSOLE_UART > 0
uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
* it from initializing it further down
*/
@ -3126,7 +3126,7 @@ void arm_serialinit(void)
continue;
}
#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

80
arch/arm/src/stm32l5/stm32l5_spi.c
View file

@ -76,15 +76,15 @@
#include "chip.h"
#include "stm32.h"
#include "stm32l5_gpio.h"
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# include "stm32l5_dma.h"
#endif
#include "stm32l5_spi.h"
#include <arch/board/board.h>
#if defined(CONFIG_STM32L5_SPI1) || defined(CONFIG_STM32L5_SPI2) || \
defined(CONFIG_STM32L5_SPI3)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \
defined(CONFIG_STM32_SPI3)
/****************************************************************************
* Pre-processor Definitions
@ -94,19 +94,19 @@
/* SPI interrupts */
#ifdef CONFIG_STM32L5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
# error "Interrupt driven SPI not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32L5_SPI_INTERRUPTS) && defined(CONFIG_STM32L5_SPI_DMA)
#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
@ -140,10 +140,10 @@ struct stm32_spidev_s
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
uint32_t spibase; /* SPIn base address */
uint32_t spiclock; /* Clocking for the SPI module */
#ifdef CONFIG_STM32L5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
uint8_t spiirq; /* SPI IRQ number */
#endif
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the RX DMA */
#ifdef CONFIG_SPI_TRIGGER
@ -187,7 +187,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv);
/* DMA support */
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxwait(struct stm32_spidev_s *priv);
static void spi_dmatxwait(struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv);
@ -247,7 +247,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI1
#ifdef CONFIG_STM32_SPI1
static const struct spi_ops_s g_spi1ops =
{
.lock = spi_lock,
@ -287,10 +287,10 @@ static struct stm32_spidev_s g_spi1dev =
},
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32L5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI1,
#endif
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
/* lines must be configured in board.h */
.rxch = DMACHAN_SPI1_RX,
@ -305,7 +305,7 @@ static struct stm32_spidev_s g_spi1dev =
};
#endif
#ifdef CONFIG_STM32L5_SPI2
#ifdef CONFIG_STM32_SPI2
static const struct spi_ops_s g_spi2ops =
{
.lock = spi_lock,
@ -345,10 +345,10 @@ static struct stm32_spidev_s g_spi2dev =
},
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
#ifdef CONFIG_STM32L5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI2,
#endif
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
.rxch = DMACHAN_SPI2_RX,
.txch = DMACHAN_SPI2_TX,
.rxsem = SEM_INITIALIZER(0),
@ -361,7 +361,7 @@ static struct stm32_spidev_s g_spi2dev =
};
#endif
#ifdef CONFIG_STM32L5_SPI3
#ifdef CONFIG_STM32_SPI3
static const struct spi_ops_s g_spi3ops =
{
.lock = spi_lock,
@ -401,10 +401,10 @@ static struct stm32_spidev_s g_spi3dev =
},
.spibase = STM32_SPI3_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
#ifdef CONFIG_STM32L5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
.spiirq = STM32_IRQ_SPI3,
#endif
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
.rxch = DMACHAN_SPI3_RX,
.txch = DMACHAN_SPI3_TX,
.rxsem = SEM_INITIALIZER(0),
@ -635,7 +635,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -666,7 +666,7 @@ static void spi_dmarxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -697,7 +697,7 @@ static void spi_dmatxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->rxsem);
@ -712,7 +712,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->txsem);
@ -727,7 +727,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -747,7 +747,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -767,7 +767,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer, void *rxdummy,
size_t nwords)
@ -818,7 +818,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer, const void *txdummy,
size_t nwords)
@ -869,7 +869,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
{
priv->rxresult = 0;
@ -885,7 +885,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmatxstart(struct stm32_spidev_s *priv)
{
priv->txresult = 0;
@ -1353,8 +1353,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
*
****************************************************************************/
#if !defined(CONFIG_STM32L5_SPI_DMA) || defined(CONFIG_STM32L5_DMACAPABLE)
#if !defined(CONFIG_STM32L5_SPI_DMA)
#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE)
#if !defined(CONFIG_STM32_SPI_DMA)
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
#else
@ -1437,7 +1437,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
}
}
}
#endif /* !CONFIG_STM32L5_SPI_DMA || CONFIG_STM32L5_DMACAPABLE */
#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */
/****************************************************************************
* Name: spi_exchange (with DMA capability)
@ -1460,13 +1460,13 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
#ifdef CONFIG_STM32L5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
if ((txbuffer &&
!stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) ||
(rxbuffer &&
@ -1524,7 +1524,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#endif
}
}
#endif /* CONFIG_STM32L5_SPI_DMA */
#endif /* CONFIG_STM32_SPI_DMA */
/****************************************************************************
* Name: spi_trigger
@ -1545,7 +1545,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#ifdef CONFIG_SPI_TRIGGER
static int spi_trigger(struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
@ -1748,7 +1748,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7);
#ifdef CONFIG_STM32L5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
/* Get DMA channels.
* NOTE: stm32_dmachannel() will always assign the DMA channel.
* If the channel is not available, then stm32_dmachannel() will
@ -1804,7 +1804,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
irqstate_t flags = enter_critical_section();
#ifdef CONFIG_STM32L5_SPI1
#ifdef CONFIG_STM32_SPI1
if (bus == 1)
{
/* Select SPI1 */
@ -1829,7 +1829,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32L5_SPI2
#ifdef CONFIG_STM32_SPI2
if (bus == 2)
{
/* Select SPI2 */
@ -1854,7 +1854,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32L5_SPI3
#ifdef CONFIG_STM32_SPI3
if (bus == 3)
{
/* Select SPI3 */
@ -1887,4 +1887,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
return (struct spi_dev_s *)priv;
}
#endif /* CONFIG_STM32L5_SPI1 || CONFIG_STM32L5_SPI2 || CONFIG_STM32L5_SPI3 */
#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */

12
arch/arm/src/stm32l5/stm32l5_spi.h
View file

@ -104,21 +104,21 @@ struct spi_dev_s *stm32_spibus_initialize(int bus);
*
****************************************************************************/
#ifdef CONFIG_STM32L5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32L5_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32L5_SPI3
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid);
@ -146,19 +146,19 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32L5_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1register(struct spi_dev_s *dev,
spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32L5_SPI2
#ifdef CONFIG_STM32_SPI2
int stm32_spi2register(struct spi_dev_s *dev,
spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32L5_SPI3
#ifdef CONFIG_STM32_SPI3
int stm32_spi3register(struct spi_dev_s *dev,
spi_mediachange_t callback,
void *arg);

2
arch/arm/src/stm32l5/stm32l5_start.c
View file

@ -131,7 +131,7 @@ void __start(void)
("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32L5_SRAM2_INIT
#ifdef CONFIG_STM32_SRAM2_INIT
/* The SRAM2 region is parity checked, but upon power up, it will be in
* a random state and probably invalid with respect to parity, potentially
* generating faults if accessed. If elected, we will write zeros to the

246
arch/arm/src/stm32l5/stm32l5_tim.c
View file

@ -73,118 +73,118 @@
* In any of these cases, the timer will not be used by this timer module.
*/
#if defined(CONFIG_STM32L5_TIM1_PWM) || defined (CONFIG_STM32L5_TIM1_ADC) || \
defined(CONFIG_STM32L5_TIM1_DAC) || defined(CONFIG_STM32L5_TIM1_QE)
# undef CONFIG_STM32L5_TIM1
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \
defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE)
# undef CONFIG_STM32_TIM1
#endif
#if defined(CONFIG_STM32L5_TIM2_PWM) || defined (CONFIG_STM32L5_TIM2_ADC) || \
defined(CONFIG_STM32L5_TIM2_DAC) || defined(CONFIG_STM32L5_TIM2_QE)
# undef CONFIG_STM32L5_TIM2
#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \
defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE)
# undef CONFIG_STM32_TIM2
#endif
#if defined(CONFIG_STM32L5_TIM3_PWM) || defined (CONFIG_STM32L5_TIM3_ADC) || \
defined(CONFIG_STM32L5_TIM3_DAC) || defined(CONFIG_STM32L5_TIM3_QE)
# undef CONFIG_STM32L5_TIM3
#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \
defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE)
# undef CONFIG_STM32_TIM3
#endif
#if defined(CONFIG_STM32L5_TIM4_PWM) || defined (CONFIG_STM32L5_TIM4_ADC) || \
defined(CONFIG_STM32L5_TIM4_DAC) || defined(CONFIG_STM32L5_TIM4_QE)
# undef CONFIG_STM32L5_TIM4
#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \
defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE)
# undef CONFIG_STM32_TIM4
#endif
#if defined(CONFIG_STM32L5_TIM5_PWM) || defined (CONFIG_STM32L5_TIM5_ADC) || \
defined(CONFIG_STM32L5_TIM5_DAC) || defined(CONFIG_STM32L5_TIM5_QE)
# undef CONFIG_STM32L5_TIM5
#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \
defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE)
# undef CONFIG_STM32_TIM5
#endif
#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32L5_TIM6_ADC) || \
defined(CONFIG_STM32L5_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE)
# undef CONFIG_STM32L5_TIM6
#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE)
# undef CONFIG_STM32_TIM6
#endif
#if defined(CONFIG_STM32L5_TIM7_PWM) || defined (CONFIG_STM32L5_TIM7_ADC) || \
defined(CONFIG_STM32L5_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE)
# undef CONFIG_STM32L5_TIM7
defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE)
# undef CONFIG_STM32_TIM7
#endif
#if defined(CONFIG_STM32L5_TIM8_PWM) || defined (CONFIG_STM32L5_TIM8_ADC) || \
defined(CONFIG_STM32L5_TIM8_DAC) || defined(CONFIG_STM32L5_TIM8_QE)
# undef CONFIG_STM32L5_TIM8
#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \
defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE)
# undef CONFIG_STM32_TIM8
#endif
#if defined(CONFIG_STM32L5_TIM15_PWM) || defined (CONFIG_STM32L5_TIM15_ADC) || \
#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
defined(CONFIG_STM32L5_TIM15_DAC) || defined(CONFIG_STM32L5_TIM15_QE)
# undef CONFIG_STM32L5_TIM15
# undef CONFIG_STM32_TIM15
#endif
#if defined(CONFIG_STM32L5_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \
#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \
defined(CONFIG_STM32L5_TIM16_DAC) || defined(CONFIG_STM32L5_TIM16_QE)
# undef CONFIG_STM32L5_TIM16
# undef CONFIG_STM32_TIM16
#endif
#if defined(CONFIG_STM32L5_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \
#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \
defined(CONFIG_STM32L5_TIM17_DAC) || defined(CONFIG_STM32L5_TIM17_QE)
# undef CONFIG_STM32L5_TIM17
# undef CONFIG_STM32_TIM17
#endif
#if defined(CONFIG_STM32L5_TIM1)
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)
# define HAVE_TIM1_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM2)
#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM3)
#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM4)
#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM5)
#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM8)
#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)
# define HAVE_TIM8_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM15)
#if defined(CONFIG_STM32_TIM15)
# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\
defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT)
# define HAVE_TIM15_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM16)
#if defined(CONFIG_STM32_TIM16)
# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\
defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT)
# define HAVE_TIM16_GPIOCONFIG 1
#endif
#endif
#if defined(CONFIG_STM32L5_TIM17)
#if defined(CONFIG_STM32_TIM17)
# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\
defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT)
# define HAVE_TIM17_GPIOCONFIG 1
@ -195,12 +195,12 @@
* intended for some other purpose.
*/
#if defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \
defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \
defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \
defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \
defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \
defined(CONFIG_STM32L5_TIM17)
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
defined(CONFIG_STM32_TIM17)
/****************************************************************************
* Private Types
@ -301,7 +301,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops =
.checkint = stm32_tim_checkint,
};
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
struct stm32_tim_priv_s stm32_tim1_priv =
{
.ops = &stm32_tim_ops,
@ -309,7 +309,7 @@ struct stm32_tim_priv_s stm32_tim1_priv =
.base = STM32_TIM1_BASE,
};
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
.ops = &stm32_tim_ops,
@ -318,7 +318,7 @@ struct stm32_tim_priv_s stm32_tim2_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv =
{
.ops = &stm32_tim_ops,
@ -327,7 +327,7 @@ struct stm32_tim_priv_s stm32_tim3_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv =
{
.ops = &stm32_tim_ops,
@ -336,7 +336,7 @@ struct stm32_tim_priv_s stm32_tim4_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv =
{
.ops = &stm32_tim_ops,
@ -345,7 +345,7 @@ struct stm32_tim_priv_s stm32_tim5_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
.ops = &stm32_tim_ops,
@ -354,7 +354,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
.ops = &stm32_tim_ops,
@ -363,7 +363,7 @@ struct stm32_tim_priv_s stm32_tim7_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv =
{
.ops = &stm32_tim_ops,
@ -372,7 +372,7 @@ struct stm32_tim_priv_s stm32_tim8_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
struct stm32_tim_priv_s stm32_tim15_priv =
{
.ops = &stm32_tim_ops,
@ -381,7 +381,7 @@ struct stm32_tim_priv_s stm32_tim15_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
struct stm32_tim_priv_s stm32_tim16_priv =
{
.ops = &stm32_tim_ops,
@ -390,7 +390,7 @@ struct stm32_tim_priv_s stm32_tim16_priv =
};
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
struct stm32_tim_priv_s stm32_tim17_priv =
{
.ops = &stm32_tim_ops,
@ -654,66 +654,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = BOARD_TIM1_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = BOARD_TIM2_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = BOARD_TIM3_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
freqin = BOARD_TIM4_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
freqin = BOARD_TIM5_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = BOARD_TIM6_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = BOARD_TIM7_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
freqin = BOARD_TIM8_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = BOARD_TIM15_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = BOARD_TIM16_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = BOARD_TIM17_FREQUENCY;
break;
@ -769,64 +769,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = BOARD_TIM1_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = BOARD_TIM2_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = BOARD_TIM3_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
freqin = BOARD_TIM4_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
freqin = BOARD_TIM5_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = BOARD_TIM6_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = BOARD_TIM7_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
freqin = BOARD_TIM8_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = BOARD_TIM15_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = BOARD_TIM16_FREQUENCY;
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = BOARD_TIM17_FREQUENCY;
break;
@ -875,13 +875,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev)
* reset it it result when not TIM2 or TIM5.
*/
#if defined(CONFIG_STM32L5_TIM2) || defined(CONFIG_STM32L5_TIM5)
#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
#endif
return counter;
@ -987,7 +987,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
@ -1020,7 +1020,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
@ -1053,7 +1053,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
@ -1086,7 +1086,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
@ -1118,7 +1118,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
@ -1151,7 +1151,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
@ -1184,7 +1184,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
switch (channel)
{
@ -1217,7 +1217,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
switch (channel)
{
@ -1250,7 +1250,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
switch (channel)
{
@ -1366,65 +1366,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1UP;
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
vectorno = STM32_IRQ_TIM4;
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
vectorno = STM32_IRQ_TIM5;
break;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
vectorno = STM32_IRQ_TIM15;
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
vectorno = STM32_IRQ_TIM16;
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
vectorno = STM32_IRQ_TIM17;
break;
@ -1509,76 +1509,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
@ -1616,66 +1616,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
break;
@ -1692,4 +1692,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev)
return OK;
}
#endif /* defined(CONFIG_STM32L5_TIM1 || ... || TIM17) */
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */

56
arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c
View file

@ -41,12 +41,12 @@
#include "stm32l5_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \
defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \
defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \
defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \
defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \
defined(CONFIG_STM32L5_TIM17))
(defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \
defined(CONFIG_STM32_TIM17))
/****************************************************************************
* Pre-processor Definitions
@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops =
.ioctl = NULL,
};
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf =
};
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer)
switch (timer)
{
#ifdef CONFIG_STM32L5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32L5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;

104
arch/arm/src/stm32l5/stm32l5_uart.h
View file

@ -32,7 +32,7 @@
#include "chip.h"
#if defined(CONFIG_STM32L5_STM32L562XX)
#if defined(CONFIG_STM32_STM32L562XX)
# include "hardware/stm32l5_uart.h"
#else
# error "Unsupported STM32L5 chip"
@ -46,63 +46,63 @@
* device.
*/
#if !defined(CONFIG_STM32L5_HAVE_UART5)
# undef CONFIG_STM32L5_UART5
#if !defined(CONFIG_STM32_HAVE_UART5)
# undef CONFIG_STM32_UART5
#endif
#if !defined(CONFIG_STM32L5_HAVE_UART4)
# undef CONFIG_STM32L5_UART4
#if !defined(CONFIG_STM32_HAVE_UART4)
# undef CONFIG_STM32_UART4
#endif
#if !defined(CONFIG_STM32L5_HAVE_USART3)
# undef CONFIG_STM32L5_USART3
#if !defined(CONFIG_STM32_HAVE_USART3)
# undef CONFIG_STM32_USART3
#endif
#if !defined(CONFIG_STM32L5_HAVE_USART2)
# undef CONFIG_STM32L5_USART2
#if !defined(CONFIG_STM32_HAVE_USART2)
# undef CONFIG_STM32_USART2
#endif
#if !defined(CONFIG_STM32L5_HAVE_USART1)
# undef CONFIG_STM32L5_USART1
#if !defined(CONFIG_STM32_HAVE_USART1)
# undef CONFIG_STM32_USART1
#endif
#if !defined(CONFIG_STM32L5_HAVE_LPUART1)
# undef CONFIG_STM32L5_LPUART1
#if !defined(CONFIG_STM32_HAVE_LPUART1)
# undef CONFIG_STM32_LPUART1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32L5_LPUART1)
# undef CONFIG_STM32L5_LPUART1_SERIALDRIVER
# undef CONFIG_STM32L5_LPUART1_1WIREDRIVER
#if !defined(CONFIG_STM32_LPUART1)
# undef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_STM32_LPUART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32L5_USART1)
# undef CONFIG_STM32L5_USART1_SERIALDRIVER
# undef CONFIG_STM32L5_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32_USART1)
# undef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32L5_USART2)
# undef CONFIG_STM32L5_USART2_SERIALDRIVER
# undef CONFIG_STM32L5_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32_USART2)
# undef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32L5_USART3)
# undef CONFIG_STM32L5_USART3_SERIALDRIVER
# undef CONFIG_STM32L5_USART3_1WIREDRIVER
#if !defined(CONFIG_STM32_USART3)
# undef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_STM32_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32L5_UART4)
# undef CONFIG_STM32L5_UART4_SERIALDRIVER
# undef CONFIG_STM32L5_UART4_1WIREDRIVER
#if !defined(CONFIG_STM32_UART4)
# undef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_STM32_UART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32L5_UART5)
# undef CONFIG_STM32L5_UART5_SERIALDRIVER
# undef CONFIG_STM32L5_UART5_1WIREDRIVER
#if !defined(CONFIG_STM32_UART5)
# undef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_STM32_UART5_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32L5_LPUART1) || defined(CONFIG_STM32L5_USART1) || \
defined(CONFIG_STM32L5_USART2) || defined(CONFIG_STM32L5_USART3) || \
defined(CONFIG_STM32L5_UART4) || defined(CONFIG_STM32L5_UART5)
#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER)
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -110,7 +110,7 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART1_SERIALDRIVER)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -118,28 +118,28 @@
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART3_SERIALDRIVER)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART4_SERIALDRIVER)
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART5_SERIALDRIVER)
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -170,27 +170,27 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32L5_LPUART1_SERIALDRIVER
#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_LPUART1_RXDMA
#endif
#ifndef CONFIG_STM32L5_USART1_SERIALDRIVER
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32L5_USART2_SERIALDRIVER
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32L5_USART3_SERIALDRIVER
#ifndef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32L5_UART4_SERIALDRIVER
#ifndef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_UART4_RXDMA
#endif
#ifndef CONFIG_STM32L5_UART5_SERIALDRIVER
#ifndef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_UART5_RXDMA
#endif
@ -223,17 +223,17 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32L5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32L5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32L5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32L5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32L5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif

7
boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-l552ze"
CONFIG_ARCH_BOARD_NUCLEO_L552ZE=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32l5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32L552ZE=y
CONFIG_ARCH_CHIP_STM32L5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -49,9 +50,9 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32L5_LPUART1=y
CONFIG_STM32L5_RTC=y
CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y
CONFIG_STM32_LPUART1=y
CONFIG_STM32_RTC=y
CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_STACKMONITOR=y
CONFIG_SYSTEM_TEE=y

2
boards/arm/stm32l5/nucleo-l552ze/include/board.h
View file

@ -108,7 +108,7 @@
/* Enable CLK48; get it from HSI48 */
#if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG)
#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG)
# define STM32_USE_CLK48 1
# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
# define STM32_HSI48_SYNCSRC SYNCSRC_NONE

2
boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c
View file

@ -56,7 +56,7 @@ void stm32_board_initialize(void)
{
stm32_pwr_vddio2_valid(true);
#if defined(CONFIG_STM32L5_LPUART1)
#if defined(CONFIG_STM32_LPUART1)
/* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in
* stm32_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes
* silently fail. Reconfigure here after VDDIO2 is valid.

5
boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig
View file

@ -10,9 +10,10 @@
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="stm32l562e-dk"
CONFIG_ARCH_BOARD_STM32L562E_DK=y
CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32l5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32L562QE=y
CONFIG_ARCH_CHIP_STM32L5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -44,7 +45,7 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32L5_USART1=y
CONFIG_STM32_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_STACKMONITOR=y
CONFIG_SYSTEM_TEE=y

4
boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c
View file

@ -37,13 +37,13 @@
* Currently the STM32L562E-DK board support is restricted to running NuttX
* in the Non-Secure domain together with TrustedFirmware-M (TFM). In this
* setup the clock configuration is done by TFM, not by NuttX. Thus, the
* board's configuration sets CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG
* board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
* to avoid the standard clock config logic to run and instead do just
* nothing in this function.
*
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
void stm32_board_clockconfig(void)
{
}