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!arch/stm32f7: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32F7 Kconfig symbols were renamed from CONFIG_STM32F7_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_STM32F7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-18 18:02:30 +02:00 • committed by Alan C. Assis
parent a704a9b8ea
commit c306e4129d
231 changed files with 4277 additions and 10541 deletions
Download patch file Download diff file Expand all files Collapse all files

12
Documentation/guides/port_drivers_to_stm32f7.rst
View file

@ -262,7 +262,7 @@ the buffers to the Cortex-M7 D-Cache line size:
#define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK)
#define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK)
#ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC
#ifndef CONFIG_STM32_ETH_ENHANCEDDESC
# define RXDESC_SIZE 16
# define TXDESC_SIZE 16
#else
@ -274,10 +274,10 @@ the buffers to the Cortex-M7 D-Cache line size:
#define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE)
#define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE)
#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC)
#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NTXDESC)
#define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE)
#define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE)
@ -366,8 +366,8 @@ Here is an example where the RX descriptors are invalidated:
for (i = 0;
(rxdesc->rdes0 & ETH_RDES0_OWN) == 0 &&
i < CONFIG_STM32F7_ETH_NRXDESC &&
priv->inflight < CONFIG_STM32F7_ETH_NTXDESC;
i < CONFIG_STM32_ETH_NRXDESC &&
priv->inflight < CONFIG_STM32_ETH_NTXDESC;
i++)
{
...

4
Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst
View file

@ -177,7 +177,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
Use make menuconfig to configure USART6 as the console::
CONFIG_STM32F7_USART6=y
CONFIG_STM32_USART6=y
CONFIG_USARTs_SERIALDRIVER=y
CONFIG_USARTS_SERIAL_CONSOLE=y
CONFIG_USART6_RXBUFSIZE=256
@ -213,7 +213,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL::
Use make menuconfig to configure USART8 as the console::
CONFIG_STM32F7_UART8=y
CONFIG_STM32_UART8=y
CONFIG_UART8_SERIALDRIVER=y
CONFIG_UART8_SERIAL_CONSOLE=y
CONFIG_UART8_RXBUFSIZE=256

4
Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst
View file

@ -219,7 +219,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
Use make menuconfig to configure USART6 as the console::
CONFIG_STM32F7_USART6=y
CONFIG_STM32_USART6=y
CONFIG_USARTs_SERIALDRIVER=y
CONFIG_USARTS_SERIAL_CONSOLE=y
CONFIG_USART6_RXBUFSIZE=256
@ -255,7 +255,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL::
Use make menuconfig to configure USART8 as the console::
CONFIG_STM32F7_UART8=y
CONFIG_STM32_UART8=y
CONFIG_UART8_SERIALDRIVER=y
CONFIG_UART8_SERIAL_CONSOLE=y
CONFIG_UART8_RXBUFSIZE=256

4
Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst
View file

@ -221,7 +221,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
Use make menuconfig to configure USART6 as the console::
CONFIG_STM32F7_USART6=y
CONFIG_STM32_USART6=y
CONFIG_USARTs_SERIALDRIVER=y
CONFIG_USARTS_SERIAL_CONSOLE=y
CONFIG_USART6_RXBUFSIZE=256
@ -257,7 +257,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL::
Use make menuconfig to configure USART8 as the console::
CONFIG_STM32F7_UART8=y
CONFIG_STM32_UART8=y
CONFIG_UART8_SERIALDRIVER=y
CONFIG_UART8_SERIAL_CONSOLE=y
CONFIG_UART8_RXBUFSIZE=256

6
Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst
View file

@ -129,9 +129,9 @@ configuration no builtin applications are selected.
And these for enabling the STM32 timer PWM channel:
CONFIG_STM32F7_TIM1=y
CONFIG_STM32F7_TIM1_PWM=y
CONFIG_STM32F7_TIM1_CHANNEL=4
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM1_PWM=y
CONFIG_STM32_TIM1_CHANNEL=4
nsh-ehternet
------------

96
Documentation/platforms/arm/stm32f7/index.rst
View file

@ -106,7 +106,7 @@ managed with dtcm_malloc(), dtcm_free(), etc.
In order to use FMC SRAM, the following additional things need to be
present in the NuttX configuration file:
- CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the
- CONFIG_STM32_FMC_SRAM - Indicates that SRAM is available via the
FMC (as opposed to an LCD or FLASH).
- CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex)
@ -123,10 +123,10 @@ present in the NuttX configuration file:
Clock
-----
- CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG - Enables special STM32F7 clock
- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
configuration features.::
CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG=n
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops
@ -134,23 +134,23 @@ Timers
------
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn
to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
is defined (as above) then the following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation, ADC conversion,
or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
to assign the timer (n) for used by the ADC or DAC, but then you also have to
configure which ADC or DAC (m) it is assigned to.:
- CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
- CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
- CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
- CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
- CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
For each timer that is enabled for PWM usage, we need the following additional
configuration settings:
- CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
NOTE: The STM32 timers are each capable of generating different signals on
each of the four channels with different duty cycles. That capability is
@ -206,11 +206,11 @@ CAN
- CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined.
- CONFIG_STM32F7_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
- CONFIG_STM32F7_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
- CONFIG_STM32F7_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
dump of all CAN registers.
CAN SocketCAN
@ -221,12 +221,12 @@ TODO
SPI
---
- CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI
- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
support. Non-interrupt-driven, poll-waiting is recommended if the
interrupt rate would be to high in the interrupt driven case.
- CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance.
Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT.
- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
SDIO
----
@ -238,41 +238,41 @@ ETH
Options:
- CONFIG_STM32F7_PHYADDR - The 5-bit address of the PHY on the board
- CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
- CONFIG_STM32F7_MII - Support Ethernet MII interface
- CONFIG_STM32_MII - Support Ethernet MII interface
- CONFIG_STM32F7_MII_MCO1 - Use MCO1 to clock the MII interface
- CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
- CONFIG_STM32F7_MII_MCO2 - Use MCO2 to clock the MII interface
- CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
- CONFIG_STM32F7_RMII - Support Ethernet RMII interface
- CONFIG_STM32_RMII - Support Ethernet RMII interface
- CONFIG_STM32F7_AUTONEG - Use PHY autonegotiation to determine speed and mode
- CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode
- CONFIG_STM32F7_ETHFD - If CONFIG_STM32F7_AUTONEG is not defined, then this
- CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
may be defined to select full duplex mode. Default: half-duplex
- CONFIG_STM32F7_ETH100MBPS - If CONFIG_STM32F7_AUTONEG is not defined, then this
- CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
may be defined to select 100 MBps speed. Default: 10 Mbps
- CONFIG_STM32F7_PHYSR - This must be provided if CONFIG_STM32F7_AUTONEG is
- CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
defined. The PHY status register address may diff from PHY to PHY. This
configuration sets the address of the PHY status register.
- CONFIG_STM32F7_PHYSR_SPEED - This must be provided if CONFIG_STM32F7_AUTONEG is
- CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provides bit mask indicating 10 or 100MBps speed.
- CONFIG_STM32F7_PHYSR_100MBPS - This must be provided if CONFIG_STM32F7_AUTONEG is
- CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provides the value of the speed bit(s) indicating 100MBps speed.
- CONFIG_STM32F7_PHYSR_MODE - This must be provided if CONFIG_STM32F7_AUTONEG is
- CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provide bit mask indicating full or half duplex modes.
- CONFIG_STM32F7_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32F7_AUTONEG is
- CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provides the value of the mode bits indicating full duplex mode.
- CONFIG_STM32F7_ETH_PTP - Precision Time Protocol (PTP). Not supported
- CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
but some hooks are indicated with this condition.
USB OTG FS
@ -284,30 +284,30 @@ Pre-requisites:
- CONFIG_USBDEV - Enable USB device support
- CONFIG_USBHOST - Enable USB host support
- CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
- CONFIG_STM32F7_SYSCFG - Needed
- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
- CONFIG_STM32_SYSCFG - Needed
- CONFIG_SCHED_WORKQUEUE - Worker thread support is required
Options:
- CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
Default 128 (512 bytes)
- CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
in 32-bit words. Default 96 (384 bytes)
- CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
words. Default 96 (384 bytes)
- CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
- CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
want to do that?
- CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access
- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
debug. Depends on CONFIG_DEBUG_FEATURES.
- CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
packets. Depends on CONFIG_DEBUG_FEATURES.
USB OTG HS
@ -353,16 +353,16 @@ Available for some Nucleo boards.
The builtin SPI test facility can be enabled with the following settings::
+CONFIG_STM32F7_SPI=y
+CONFIG_STM32F7_SPI1=y
+CONFIG_STM32F7_SPI2=y
+CONFIG_STM32F7_SPI3=y
+CONFIG_STM32_SPI=y
+CONFIG_STM32_SPI1=y
+CONFIG_STM32_SPI2=y
+CONFIG_STM32_SPI3=y
+# CONFIG_STM32F7_SPI_INTERRUPTS is not set
+# CONFIG_STM32F7_SPI1_DMA is not set
+# CONFIG_STM32F7_SPI2_DMA is not set
+# CONFIG_STM32F7_SPI3_DMA is not set
# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set
+# CONFIG_STM32_SPI_INTERRUPTS is not set
+# CONFIG_STM32_SPI1_DMA is not set
+# CONFIG_STM32_SPI2_DMA is not set
+# CONFIG_STM32_SPI3_DMA is not set
# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
+CONFIG_NUCLEO_SPI_TEST=y
+CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World"

1
arch/arm/Kconfig
View file

@ -622,6 +622,7 @@ config ARCH_CHIP_STM32C0
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_CHIP_STM32
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD

40
arch/arm/include/stm32f7/chip.h
View file

@ -264,7 +264,7 @@
/* Size SRAM */
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
@ -277,7 +277,7 @@
# else
# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
@ -290,7 +290,7 @@
# else
# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
# endif
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
# if defined(CONFIG_ARMV7M_HAVE_DTCM)
@ -309,7 +309,7 @@
/* Common to all Advanced (vs Foundation) Family members */
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# define STM32_NSPDIFRX 0 /* Not supported */
# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */
# define STM32_NI2C 3 /* I2C1-3 */
@ -350,75 +350,75 @@
/* Diversification based on Family and package */
#if defined(CONFIG_STM32F7_HAVE_FMC)
#if defined(CONFIG_STM32_HAVE_FMC)
# define STM32_NFMC 1 /* Have FMC memory controller */
#else
# define STM32_NFMC 0 /* No FMC memory controller */
#endif
#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
#if defined(CONFIG_STM32_HAVE_ETHRNET)
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
#else
# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
#if defined(CONFIG_STM32F7_HAVE_RNG)
#if defined(CONFIG_STM32_HAVE_RNG)
# define STM32_NRNG 1 /* Random number generator (RNG) */
#else
# define STM32_NRNG 0 /* No Random number generator (RNG) */
#endif
#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
#if defined(CONFIG_STM32_HAVE_SPI5) && defined(CONFIG_STM32_HAVE_SPI6)
# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */
#elif defined(CONFIG_STM32F7_HAVE_SPI5)
#elif defined(CONFIG_STM32_HAVE_SPI5)
# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */
#elif defined(CONFIG_STM32F7_HAVE_SPI4)
#elif defined(CONFIG_STM32_HAVE_SPI4)
# define STM32_NSPI 4 /* SPI1-4 V series */
#else
# define STM32_NSPI 3 /* SPI1-3 R series */
#endif
#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
#if defined(CONFIG_STM32_HAVE_SDMMC2)
# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */
#else
# define STM32_NSDMMC 1 /* 1 SDMMC interface */
#endif
#if defined(CONFIG_STM32F7_HAVE_CAN3)
#if defined(CONFIG_STM32_HAVE_CAN3)
# define STM32_NCAN 3 /* CAN1-3 */
#elif defined(CONFIG_STM32F7_HAVE_CAN2)
#elif defined(CONFIG_STM32_HAVE_CAN2)
# define STM32_NCAN 2 /* CAN1-2 */
#else
# define STM32_NCAN 1 /* CAN1 only */
#endif
#if defined(CONFIG_STM32F7_HAVE_DCMI)
#if defined(CONFIG_STM32_HAVE_DCMI)
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */
#endif
#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
#if defined(CONFIG_STM32_HAVE_DSIHOST)
# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */
#else
# define STM32_NDSIHOST 0 /* No MIPI DSI Host */
#endif
#if defined (CONFIG_STM32F7_HAVE_LTDC)
#if defined (CONFIG_STM32_HAVE_LTDC)
# define STM32_NLCDTFT 1 /* One LCD-TFT */
#else
# define STM32_NLCDTFT 0 /* No LCD-TFT */
#endif
#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */
#if defined(CONFIG_STM32_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */
# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
#else
# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
#endif
#if defined(CONFIG_STM32F7_HAVE_JPEG)
#if defined(CONFIG_STM32_HAVE_JPEG)
#define STM32_NJPEG 1 /* One JPEG Converter */
#else
#define STM32_NJPEG 0 /* No JPEG Converter */
#endif
#if defined(CONFIG_STM32F7_HAVE_CRYP)
#if defined(CONFIG_STM32_HAVE_CRYP)
#define STM32_NCRYP 1 /* One CRYP engine */
#else
#define STM32_NCRYP 0 /* No CRYP engine */
#endif
#if defined(CONFIG_STM32F7_HAVE_HASH)
#if defined(CONFIG_STM32_HAVE_HASH)
#define STM32_NHASH 1 /* One HASH engine */
#else
#define STM32_NHASH 0 /* No HASH engine */

6
arch/arm/include/stm32f7/irq.h
View file

@ -69,11 +69,11 @@
* Included Files
****************************************************************************/
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include <arch/stm32f7/stm32f72xx73xx_irq.h>
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include <arch/stm32f7/stm32f74xx75xx_irq.h>
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include <arch/stm32f7/stm32f76xx77xx_irq.h>
#else
# error "Unsupported STM32 F7 chip"

52
arch/arm/src/stm32f7/CMakeLists.txt
View file

@ -37,13 +37,13 @@ list(
stm32_uid.c
stm32_waste.c)
if(CONFIG_STM32F7_TICKLESS_TIMER)
if(CONFIG_STM32_TICKLESS_TIMER)
list(APPEND SRCS stm32_tickless.c)
else()
list(APPEND SRCS stm32_timerisr.c)
endif()
if(CONFIG_STM32F7_PROGMEM)
if(CONFIG_STM32_PROGMEM)
list(APPEND SRCS stm32_flash.c)
endif()
@ -55,7 +55,7 @@ if(CONFIG_ARMV7M_DTCM)
list(APPEND SRCS stm32_dtcm.c)
endif()
if(CONFIG_STM32F7_DMA)
if(CONFIG_STM32_DMA)
list(APPEND SRCS stm32_dma.c)
endif()
@ -66,11 +66,11 @@ if(CONFIG_PM)
endif()
endif()
if(CONFIG_STM32F7_PWR)
if(CONFIG_STM32_PWR)
list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c)
endif()
if(CONFIG_STM32F7_RTC)
if(CONFIG_STM32_RTC)
list(APPEND SRCS stm32_rtc.c)
if(CONFIG_RTC_ALARM)
list(APPEND SRCS stm32_exti_alarm.c)
@ -83,27 +83,31 @@ if(CONFIG_STM32F7_RTC)
endif()
endif()
if(CONFIG_STM32F7_IWDG OR CONFIG_STM32F7_RTC_LSICLOCK)
if(CONFIG_STM32_FMC)
list(APPEND SRCS stm32_fmc.c)
endif()
if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK)
list(APPEND SRCS stm32_lsi.c)
endif()
if(CONFIG_STM32F7_RTC_LSECLOCK)
if(CONFIG_STM32_RTC_LSECLOCK)
list(APPEND SRCS stm32_lse.c)
endif()
if(CONFIG_STM32F7_I2C)
if(CONFIG_STM32_I2C)
list(APPEND SRCS stm32_i2c.c)
endif()
if(CONFIG_STM32F7_I2S)
if(CONFIG_STM32_I2S)
list(APPEND SRCS stm32_i2s.c)
endif()
if(CONFIG_STM32F7_SPI)
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi.c)
endif()
if(CONFIG_STM32F7_SDMMC)
if(CONFIG_STM32_SDMMC)
list(APPEND SRCS stm32_sdmmc.c)
endif()
@ -120,19 +124,19 @@ if(CONFIG_USBHOST)
endif()
endif()
if(CONFIG_STM32F7_TIM)
if(CONFIG_STM32_TIM)
list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c)
endif()
if(CONFIG_STM32F7_ADC)
if(CONFIG_STM32_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_STM32F7_QSPI)
if(CONFIG_STM32_QSPI)
list(APPEND SRCS stm32_qspi.c)
endif()
if(CONFIG_STM32F7_ETHMAC)
if(CONFIG_STM32_ETHMAC)
list(APPEND SRCS stm32_ethernet.c)
endif()
@ -140,19 +144,19 @@ if(CONFIG_DEBUG_FEATURES)
list(APPEND SRCS stm32_dumpgpio.c)
endif()
if(CONFIG_STM32F7_BBSRAM)
if(CONFIG_STM32_BBSRAM)
list(APPEND SRCS stm32_bbsram.c)
endif()
if(CONFIG_STM32F7_RNG)
if(CONFIG_STM32_RNG)
list(APPEND SRCS stm32_rng.c)
endif()
if(CONFIG_STM32F7_LTDC)
if(CONFIG_STM32_LTDC)
list(APPEND SRCS stm32_ltdc.c)
endif()
if(CONFIG_STM32F7_DMA2D)
if(CONFIG_STM32_DMA2D)
list(APPEND SRCS stm32_dma2d.c)
endif()
@ -160,19 +164,19 @@ if(CONFIG_SENSORS_QENCODER)
list(APPEND SRCS stm32_qencoder.c)
endif()
if(CONFIG_STM32F7_CAN_CHARDRIVER)
if(CONFIG_STM32_CAN_CHARDRIVER)
list(APPEND SRCS stm32_can.c)
endif()
if(CONFIG_STM32F7_CAN_SOCKET)
if(CONFIG_STM32_CAN_SOCKET)
list(APPEND SRCS stm32_can_sock.c)
endif()
if(CONFIG_STM32F7_SAI)
if(CONFIG_STM32_SAI)
list(APPEND SRCS stm32_sai.c)
endif()
if(CONFIG_STM32F7_PWM)
if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
@ -180,7 +184,7 @@ if(CONFIG_PULSECOUNT)
list(APPEND SRCS stm32_pulsecount.c)
endif()
if(CONFIG_STM32F7_FOC)
if(CONFIG_STM32_FOC)
list(APPEND SRCS stm32_foc.c)
endif()

7433
arch/arm/src/stm32f7/Kconfig
View file

File diff suppressed because it is too large Load diff

50
arch/arm/src/stm32f7/Make.defs
View file

@ -39,7 +39,7 @@ else
CHIP_CSRCS += stm32_tickless.c
endif
ifeq ($(CONFIG_STM32F7_PROGMEM),y)
ifeq ($(CONFIG_STM32_PROGMEM),y)
CHIP_CSRCS += stm32_flash.c
endif
@ -51,11 +51,11 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y)
CHIP_CSRCS += stm32_dtcm.c
endif
ifeq ($(CONFIG_STM32F7_DMA),y)
ifeq ($(CONFIG_STM32_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
ifeq ($(CONFIG_STM32F7_FMC),y)
ifeq ($(CONFIG_STM32_FMC),y)
CHIP_CSRCS += stm32_fmc.c
endif
@ -66,11 +66,11 @@ CHIP_CSRCS += stm32_pminitialize.c
endif
endif
ifeq ($(CONFIG_STM32F7_PWR),y)
ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c
endif
ifeq ($(CONFIG_STM32F7_RTC),y)
ifeq ($(CONFIG_STM32_RTC),y)
CHIP_CSRCS += stm32_rtc.c
ifeq ($(CONFIG_RTC_ALARM),y)
CHIP_CSRCS += stm32_exti_alarm.c
@ -83,27 +83,27 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c
endif
endif
ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y)
ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y)
CHIP_CSRCS += stm32_lsi.c
endif
ifeq ($(CONFIG_STM32F7_RTC_LSECLOCK),y)
ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y)
CHIP_CSRCS += stm32_lse.c
endif
ifeq ($(CONFIG_STM32F7_I2C),y)
ifeq ($(CONFIG_STM32_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
ifeq ($(CONFIG_STM32F7_I2S),y)
ifeq ($(CONFIG_STM32_I2S),y)
CHIP_CSRCS += stm32_i2s.c
endif
ifeq ($(CONFIG_STM32F7_SPI),y)
ifeq ($(CONFIG_STM32_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32F7_SDMMC),y)
ifeq ($(CONFIG_STM32_SDMMC),y)
CHIP_CSRCS += stm32_sdmmc.c
endif
@ -122,19 +122,19 @@ endif
endif
endif
ifeq ($(CONFIG_STM32F7_TIM),y)
ifeq ($(CONFIG_STM32_TIM),y)
CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c
endif
ifeq ($(CONFIG_STM32F7_ADC),y)
ifeq ($(CONFIG_STM32_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32F7_QSPI),y)
ifeq ($(CONFIG_STM32_QSPI),y)
CHIP_CSRCS += stm32_qspi.c
endif
ifeq ($(CONFIG_STM32F7_ETHMAC),y)
ifeq ($(CONFIG_STM32_ETHMAC),y)
CHIP_CSRCS += stm32_ethernet.c
endif
@ -142,19 +142,19 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += stm32_dumpgpio.c
endif
ifeq ($(CONFIG_STM32F7_BBSRAM),y)
ifeq ($(CONFIG_STM32_BBSRAM),y)
CHIP_CSRCS += stm32_bbsram.c
endif
ifeq ($(CONFIG_STM32F7_RNG),y)
ifeq ($(CONFIG_STM32_RNG),y)
CHIP_CSRCS += stm32_rng.c
endif
ifeq ($(CONFIG_STM32F7_LTDC),y)
ifeq ($(CONFIG_STM32_LTDC),y)
CHIP_CSRCS += stm32_ltdc.c
endif
ifeq ($(CONFIG_STM32F7_DMA2D),y)
ifeq ($(CONFIG_STM32_DMA2D),y)
CHIP_CSRCS += stm32_dma2d.c
endif
@ -162,26 +162,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y)
CHIP_CSRCS += stm32_qencoder.c
endif
ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y)
ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y)
CHIP_CSRCS += stm32_can.c
endif
ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y)
ifeq ($(CONFIG_STM32_CAN_SOCKET),y)
CHIP_CSRCS += stm32_can_sock.c
endif
ifeq ($(CONFIG_STM32F7_SAI),y)
ifeq ($(CONFIG_STM32_SAI),y)
CHIP_CSRCS += stm32_sai.c
endif
ifeq ($(CONFIG_STM32F7_PWM),y)
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32F7_PULSECOUNT),y)
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
ifeq ($(CONFIG_STM32F7_FOC),y)
ifeq ($(CONFIG_STM32_FOC),y)
CHIP_CSRCS += stm32_foc.c
endif

6
arch/arm/src/stm32f7/hardware/stm32_adc.h
View file

@ -30,10 +30,10 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_adc.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f74xx77xx_adc.h"
#else
# error "Unsupported STM32 F7 sub family"

6
arch/arm/src/stm32f7/hardware/stm32_can.h
View file

@ -123,7 +123,7 @@
/* Register Addresses *******************************************************/
#if defined(CONFIG_STM32F7_CAN1)
#if defined(CONFIG_STM32_CAN1)
# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET)
# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET)
# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET)
@ -177,7 +177,7 @@
# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i))
#endif
#if defined(CONFIG_STM32F7_CAN2)
#if defined(CONFIG_STM32_CAN2)
# define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET)
# define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET)
# define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET)
@ -231,7 +231,7 @@
# define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i))
#endif
#if defined(CONFIG_STM32F7_CAN3)
#if defined(CONFIG_STM32_CAN3)
# define STM32_CAN3_MCR (STM32_CAN3_BASE+STM32_CAN_MCR_OFFSET)
# define STM32_CAN3_MSR (STM32_CAN3_BASE+STM32_CAN_MSR_OFFSET)
# define STM32_CAN3_TSR (STM32_CAN3_BASE+STM32_CAN_TSR_OFFSET)

6
arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_dbgmcu.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_dbgmcu.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_dbgmcu.h"
#else
# error "Unsupported STM32 F7 part"

6
arch/arm/src/stm32f7/hardware/stm32_dma.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_dma.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_dma.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_dma.h"
#else
# error "Unsupported STM32 F7 part"

10
arch/arm/src/stm32f7/hardware/stm32_ethernet.h
View file

@ -33,8 +33,8 @@
* families
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -810,7 +810,7 @@ struct eth_txdesc_s
/* Enhanced DMA descriptor words with time stamp */
#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC
#ifdef CONFIG_STM32_ETH_ENHANCEDDESC
volatile uint32_t tdes4; /* Reserved */
volatile uint32_t tdes5; /* Reserved */
volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */
@ -829,7 +829,7 @@ struct eth_rxdesc_s
/* Enhanced DMA descriptor words with time stamp and PTP support */
#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC
#ifdef CONFIG_STM32_ETH_ENHANCEDDESC
volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */
volatile uint32_t rdes5; /* Reserved */
volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */
@ -842,5 +842,5 @@ struct eth_rxdesc_s
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H */

8
arch/arm/src/stm32f7/hardware/stm32_exti.h
View file

@ -34,9 +34,9 @@
* families
*/
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \
defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -116,5 +116,5 @@
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32_EXTI_MASK
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H */

6
arch/arm/src/stm32f7/hardware/stm32_flash.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_flash.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_flash.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_flash.h"
#else
# error "Unsupported STM32 F7 part"

6
arch/arm/src/stm32f7/hardware/stm32_gpio.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_gpio.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_gpio.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_gpio.h"
#else
# error "Unsupported STM32 F7 part"

6
arch/arm/src/stm32f7/hardware/stm32_i2c.h
View file

@ -30,9 +30,9 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \
defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f74xx77xx_i2c.h"
#else
# error "Unsupported STM32 F7 sub family"

6
arch/arm/src/stm32f7/hardware/stm32_memorymap.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_memorymap.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_memorymap.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_memorymap.h"
#else
# error "Unsupported STM32 F7 memory map"

6
arch/arm/src/stm32f7/hardware/stm32_pinmap.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_pinmap.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_pinmap.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_pinmap.h"
#else
# error "Unsupported STM32 F7 Pin map"

6
arch/arm/src/stm32f7/hardware/stm32_pwr.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_pwr.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_pwr.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_pwr.h"
#else
# error "Unsupported STM32 F7 part"

6
arch/arm/src/stm32f7/hardware/stm32_rcc.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_rcc.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_rcc.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_rcc.h"
#else
# error "Unsupported STM32 F7 part"

6
arch/arm/src/stm32f7/hardware/stm32_sdmmc.h
View file

@ -30,9 +30,9 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \
defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
#else
# error "Unsupported STM32 F7 part"
#endif

6
arch/arm/src/stm32f7/hardware/stm32_spi.h
View file

@ -30,10 +30,10 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_spi.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f74xx77xx_spi.h"
#else
# error "Unsupported STM32 F7 sub family"

6
arch/arm/src/stm32f7/hardware/stm32_syscfg.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_syscfg.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_syscfg.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_syscfg.h"
#else
# error "Unsupported STM32 F7 part"

6
arch/arm/src/stm32f7/hardware/stm32_tim.h
View file

@ -30,11 +30,11 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_tim.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "hardware/stm32f74xx75xx_tim.h"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f76xx77xx_tim.h"
#else
# error "Unsupported STM32 F7 sub family"

6
arch/arm/src/stm32f7/hardware/stm32_uart.h
View file

@ -30,10 +30,10 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "hardware/stm32f72xx73xx_uart.h"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "hardware/stm32f74xx77xx_uart.h"
#else
# error "Unsupported STM32 F7 part"

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -539,5 +539,5 @@
#define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11)
#define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11)
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_DMA_H */

34
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h
View file

@ -29,7 +29,7 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
* When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number.
* This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
@ -44,38 +44,38 @@
#define _K(x) ((x)*1024)
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_C)
# define CONFIG_STM32F7_FLASH_OVERRIDE_C
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_C)
# define CONFIG_STM32_FLASH_OVERRIDE_C
# warning "Flash size not defined defaulting to 256KiB (C)"
#endif
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT)
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32F7_FLASH_CONFIG_C
# undef CONFIG_STM32F7_FLASH_CONFIG_E
# undef CONFIG_STM32F7_FLASH_CONFIG_G
# undef CONFIG_STM32_FLASH_CONFIG_C
# undef CONFIG_STM32_FLASH_CONFIG_E
# undef CONFIG_STM32_FLASH_CONFIG_G
# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C)
# define CONFIG_STM32F7_FLASH_CONFIG_C
# if defined(CONFIG_STM32_FLASH_OVERRIDE_C)
# define CONFIG_STM32_FLASH_CONFIG_C
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E)
# define CONFIG_STM32F7_FLASH_CONFIG_E
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32_FLASH_CONFIG_E
# endif
#endif
#if defined(CONFIG_STM32F7_FLASH_CONFIG_C)
#if defined(CONFIG_STM32_FLASH_CONFIG_C)
# define STM32_FLASH_NPAGES 6
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128))
# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128)}
#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E)
#elif defined(CONFIG_STM32_FLASH_CONFIG_E)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128))

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include <arch/stm32f7/chip.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -386,5 +386,5 @@
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H */

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -188,5 +188,5 @@
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_MEMORYMAP_H */

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h
View file

@ -31,7 +31,7 @@
#include "stm32_gpio.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -923,5 +923,5 @@
#define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
#define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H */

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -144,5 +144,5 @@
#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H */

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -677,5 +677,5 @@
# define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */
# define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC clock */
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -145,5 +145,5 @@
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H */

4
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
/****************************************************************************
* Pre-processor Definitions
@ -354,5 +354,5 @@
#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H */

4
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -545,5 +545,5 @@
#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_DMA_H */

32
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
View file

@ -29,7 +29,7 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
* When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number.
* This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
@ -42,39 +42,39 @@
#define _K(x) ((x)*1024)
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_G)
# define CONFIG_STM32F7_FLASH_OVERRIDE_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_G)
# define CONFIG_STM32_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT)
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32F7_FLASH_CONFIG_E
# undef CONFIG_STM32F7_FLASH_CONFIG_G
# undef CONFIG_STM32_FLASH_CONFIG_E
# undef CONFIG_STM32_FLASH_CONFIG_G
# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E)
# if defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32F7_FLASH_CONFIG_E
# define CONFIG_STM32_FLASH_CONFIG_E
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G)
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G)
# define CONFIG_STM32F7_FLASH_CONFIG_G
# define CONFIG_STM32_FLASH_CONFIG_G
# endif
#endif
#if defined(CONFIG_STM32F7_FLASH_CONFIG_E)
#if defined(CONFIG_STM32_FLASH_CONFIG_E)
# define STM32_FLASH_NPAGES 6
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256))
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
_K(128), _K(256)}
#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G)
#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256))

4
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include <arch/stm32f7/chip.h>
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -386,5 +386,5 @@
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H */

4
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -199,5 +199,5 @@
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */

6
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h
View file

@ -31,7 +31,7 @@
#include "stm32_gpio.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -808,7 +808,7 @@
*
* Note that the below configures GPIO_SPEED_50MHz I/O, that means for using
* the SDIO that you must enable I/O Compensation via the configuration
* option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y.
* option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y.
*/
#define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
@ -1171,5 +1171,5 @@
#define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
#define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H */

4
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -144,5 +144,5 @@
#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H */

4
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -723,5 +723,5 @@
# define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */
# define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */

4
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
/****************************************************************************
* Pre-processor Definitions
@ -143,5 +143,5 @@
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H */

4
arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h
View file

@ -38,9 +38,9 @@
* (both pclk1 and pclk2)
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# define STM32_SPI_CLK_MAX 50000000UL
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# define STM32_SPI_CLK_MAX 54000000UL
#endif

6
arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h
View file

@ -29,8 +29,8 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -356,5 +356,5 @@
#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */
#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H */

4
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -585,5 +585,5 @@
#define DMAMAP_QUADSPI_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11)
#define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11)
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_DMA_H */

44
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h
View file

@ -29,7 +29,7 @@
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the
* When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number.
* This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x
@ -42,53 +42,53 @@
#define _K(x) ((x)*1024)
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_G) && \
!defined(CONFIG_STM32F7_FLASH_CONFIG_I)
# define CONFIG_STM32F7_FLASH_OVERRIDE_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_G) && \
!defined(CONFIG_STM32_FLASH_CONFIG_I)
# define CONFIG_STM32_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT)
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32F7_FLASH_CONFIG_E
# undef CONFIG_STM32F7_FLASH_CONFIG_G
# undef CONFIG_STM32F7_FLASH_CONFIG_I
# undef CONFIG_STM32_FLASH_CONFIG_E
# undef CONFIG_STM32_FLASH_CONFIG_G
# undef CONFIG_STM32_FLASH_CONFIG_I
# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E)
# if defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32F7_FLASH_CONFIG_E
# define CONFIG_STM32_FLASH_CONFIG_E
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G)
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G)
# define CONFIG_STM32F7_FLASH_CONFIG_G
# define CONFIG_STM32_FLASH_CONFIG_G
# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I)
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I)
# define CONFIG_STM32F7_FLASH_CONFIG_I
# define CONFIG_STM32_FLASH_CONFIG_I
# endif
#endif
#if defined(CONFIG_STM32F7_FLASH_CONFIG_E)
#if defined(CONFIG_STM32_FLASH_CONFIG_E)
# define STM32_FLASH_NPAGES 6
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256))
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
_K(128), _K(256)}
#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G)
#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
# define STM32_FLASH_NPAGES 8
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256))
# define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \
_K(128), _K(256), _K(256), _K(256)}
#elif defined(CONFIG_STM32F7_FLASH_CONFIG_I)
#elif defined(CONFIG_STM32_FLASH_CONFIG_I)
# define STM32_FLASH_NPAGES 12
# define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256))

4
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include <arch/stm32f7/chip.h>
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -386,5 +386,5 @@
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H */

4
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -205,5 +205,5 @@
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_MEMORYMAP_H */

6
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h
View file

@ -31,7 +31,7 @@
#include "stm32_gpio.h"
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -916,7 +916,7 @@
*
* Note that the below configures GPIO_SPEED_50MHz I/O, that means for using
* the SDIO that you must enable I/O Compensation via the configuration
* option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y.
* option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y.
*/
#define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
@ -1330,5 +1330,5 @@
#define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
#define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H */

4
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -143,5 +143,5 @@
#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */
#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H */

4
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -756,5 +756,5 @@
# define RCC_DCKCFGR2_DSISEL_PHY (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* DSI PHY sources DSI clock */
# define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H */

4
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -163,5 +163,5 @@
#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */
#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */
#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */
#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H */

176
arch/arm/src/stm32f7/stm32_adc.c
View file

@ -59,7 +59,7 @@
/* STM32 ADC "lower-half" support must be enabled */
#ifdef CONFIG_STM32F7_ADC
#ifdef CONFIG_STM32_ADC
/* This implementation is for the STM32 ADC IP version 1 */
@ -121,21 +121,21 @@
/* ADC scan mode support */
#ifndef CONFIG_STM32F7_ADC1_SCAN
# define CONFIG_STM32F7_ADC1_SCAN 0
#ifndef CONFIG_STM32_ADC1_SCAN
# define CONFIG_STM32_ADC1_SCAN 0
#endif
#ifndef CONFIG_STM32F7_ADC2_SCAN
# define CONFIG_STM32F7_ADC2_SCAN 0
#ifndef CONFIG_STM32_ADC2_SCAN
# define CONFIG_STM32_ADC2_SCAN 0
#endif
#ifndef CONFIG_STM32F7_ADC3_SCAN
# define CONFIG_STM32F7_ADC3_SCAN 0
#ifndef CONFIG_STM32_ADC3_SCAN
# define CONFIG_STM32_ADC3_SCAN 0
#endif
/* We have to support ADC callbacks if default ADC interrupts or
* DMA transfer are enabled
*/
#if !defined(CONFIG_STM32F7_ADC_NOIRQ) || defined(ADC_HAVE_DMA)
#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA)
# define ADC_HAVE_CB
#else
# undef ADC_HAVE_CB
@ -184,7 +184,7 @@ struct adccmn_data_s
struct stm32_dev_s
{
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */
struct adc_dev_s *dev; /* Upper-half ADC reference */
#endif
@ -210,7 +210,7 @@ struct stm32_dev_s
uint16_t dmabatch; /* Number of conversions for DMA batch */
#endif
bool scan; /* True: Scan mode */
#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Sample time selection. These bits must be written only when ADON=0.
* REVISIT: this takes too much space. We need only 3 bits per channel.
*/
@ -252,7 +252,7 @@ struct stm32_dev_s
/* List of selected ADC channels to sample */
uint8_t r_chanlist[CONFIG_STM32F7_ADC_MAX_SAMPLES];
uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES];
#ifdef ADC_HAVE_INJECTED
/* List of selected ADC injected channels to sample */
@ -293,10 +293,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset);
/* ADC Interrupt Handler */
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
static int adc_interrupt(struct adc_dev_s *dev);
static int adc123_interrupt(int irq, void *context, void *arg);
#endif /* CONFIG_STM32F7_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
/* ADC Driver Methods */
@ -321,7 +321,7 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable);
static int adc_timinit(struct stm32_dev_s *priv);
#endif
#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ)
#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ)
static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
void *arg);
#endif
@ -346,7 +346,7 @@ static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg);
static void adc_dumpregs(struct stm32_dev_s *priv);
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
static int adc_llops_setup(struct stm32_adc_dev_s *dev);
static void adc_llops_shutdown(struct stm32_adc_dev_s *dev);
static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source);
@ -375,7 +375,7 @@ static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan);
static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev,
bool enable);
# endif
# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
static void adc_sampletime_set(struct stm32_adc_dev_s *dev,
struct adc_sample_time_s *time_samples);
static void adc_sampletime_write(struct stm32_adc_dev_s *dev);
@ -403,7 +403,7 @@ static const struct adc_ops_s g_adcops =
/* Publicly visible ADC lower-half operations */
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
static const struct stm32_adc_ops_s g_adc_llops =
{
.setup = adc_llops_setup,
@ -428,7 +428,7 @@ static const struct stm32_adc_ops_s g_adc_llops =
.inj_get = adc_injget,
.inj_startconv = adc_llops_inj_startconv,
# endif
# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
.stime_set = adc_sampletime_set,
.stime_write = adc_sampletime_write,
# endif
@ -454,27 +454,27 @@ struct adccmn_data_s g_adc123_cmn =
/* ADC1 state */
#ifdef CONFIG_STM32F7_ADC1
#ifdef CONFIG_STM32_ADC1
#ifdef ADC1_HAVE_DMA
static uint16_t g_adc1_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES *
CONFIG_STM32F7_ADC1_DMA_BATCH];
static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC1_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv1 =
{
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
.llops = &g_adc_llops,
#endif
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
#endif /* CONFIG_STM32F7_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
.cmn = &ADC1CMN_DATA,
.intf = 1,
.initialized = 0,
.anioc_trg = CONFIG_STM32F7_ADC1_ANIOC_TRIGGER,
.resolution = CONFIG_STM32F7_ADC1_RESOLUTION,
.anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER,
.resolution = CONFIG_STM32_ADC1_RESOLUTION,
.base = STM32_ADC1_BASE,
#ifdef ADC1_HAVE_EXTCFG
.extcfg = ADC1_EXTCFG_VALUE,
@ -483,19 +483,19 @@ static struct stm32_dev_s g_adcpriv1 =
.jextcfg = ADC1_JEXTCFG_VALUE,
#endif
#ifdef ADC1_HAVE_TIMER
.trigger = CONFIG_STM32F7_ADC1_TIMTRIG,
.trigger = CONFIG_STM32_ADC1_TIMTRIG,
.tbase = ADC1_TIMER_BASE,
.pclck = ADC1_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
#endif
#ifdef ADC1_HAVE_DMA
.dmachan = ADC1_DMA_CHAN,
.dmacfg = CONFIG_STM32F7_ADC1_DMA_CFG,
.dmacfg = CONFIG_STM32_ADC1_DMA_CFG,
.hasdma = true,
.r_dmabuffer = g_adc1_dmabuffer,
.dmabatch = CONFIG_STM32F7_ADC1_DMA_BATCH,
.dmabatch = CONFIG_STM32_ADC1_DMA_BATCH,
#endif
.scan = CONFIG_STM32F7_ADC1_SCAN,
.scan = CONFIG_STM32_ADC1_SCAN,
#ifdef CONFIG_PM
.pm_callback =
{
@ -513,27 +513,27 @@ static struct adc_dev_s g_adcdev1 =
/* ADC2 state */
#ifdef CONFIG_STM32F7_ADC2
#ifdef CONFIG_STM32_ADC2
#ifdef ADC2_HAVE_DMA
static uint16_t g_adc2_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES *
CONFIG_STM32F7_ADC2_DMA_BATCH];
static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC2_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv2 =
{
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
.llops = &g_adc_llops,
#endif
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
#endif /* CONFIG_STM32F7_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
.cmn = &ADC2CMN_DATA,
.intf = 2,
.initialized = 0,
.anioc_trg = CONFIG_STM32F7_ADC2_ANIOC_TRIGGER,
.resolution = CONFIG_STM32F7_ADC2_RESOLUTION,
.anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER,
.resolution = CONFIG_STM32_ADC2_RESOLUTION,
.base = STM32_ADC2_BASE,
#ifdef ADC2_HAVE_EXTCFG
.extcfg = ADC2_EXTCFG_VALUE,
@ -542,19 +542,19 @@ static struct stm32_dev_s g_adcpriv2 =
.jextcfg = ADC2_JEXTCFG_VALUE,
#endif
#ifdef ADC2_HAVE_TIMER
.trigger = CONFIG_STM32F7_ADC2_TIMTRIG,
.trigger = CONFIG_STM32_ADC2_TIMTRIG,
.tbase = ADC2_TIMER_BASE,
.pclck = ADC2_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY,
#endif
#ifdef ADC2_HAVE_DMA
.dmachan = ADC2_DMA_CHAN,
.dmacfg = CONFIG_STM32F7_ADC2_DMA_CFG,
.dmacfg = CONFIG_STM32_ADC2_DMA_CFG,
.hasdma = true,
.r_dmabuffer = g_adc2_dmabuffer,
.dmabatch = CONFIG_STM32F7_ADC2_DMA_BATCH,
.dmabatch = CONFIG_STM32_ADC2_DMA_BATCH,
#endif
.scan = CONFIG_STM32F7_ADC2_SCAN,
.scan = CONFIG_STM32_ADC2_SCAN,
#ifdef CONFIG_PM
.pm_callback =
{
@ -572,27 +572,27 @@ static struct adc_dev_s g_adcdev2 =
/* ADC3 state */
#ifdef CONFIG_STM32F7_ADC3
#ifdef CONFIG_STM32_ADC3
#ifdef ADC3_HAVE_DMA
static uint16_t g_adc3_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES *
CONFIG_STM32F7_ADC3_DMA_BATCH];
static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES *
CONFIG_STM32_ADC3_DMA_BATCH];
#endif
static struct stm32_dev_s g_adcpriv3 =
{
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
.llops = &g_adc_llops,
#endif
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
.irq = STM32_IRQ_ADC,
.isr = adc123_interrupt,
#endif /* CONFIG_STM32F7_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
.cmn = &ADC3CMN_DATA,
.intf = 3,
.initialized = 0,
.anioc_trg = CONFIG_STM32F7_ADC3_ANIOC_TRIGGER,
.resolution = CONFIG_STM32F7_ADC3_RESOLUTION,
.anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER,
.resolution = CONFIG_STM32_ADC3_RESOLUTION,
.base = STM32_ADC3_BASE,
#ifdef ADC3_HAVE_EXTCFG
.extcfg = ADC3_EXTCFG_VALUE,
@ -601,19 +601,19 @@ static struct stm32_dev_s g_adcpriv3 =
.jextcfg = ADC3_JEXTCFG_VALUE,
#endif
#ifdef ADC3_HAVE_TIMER
.trigger = CONFIG_STM32F7_ADC3_TIMTRIG,
.trigger = CONFIG_STM32_ADC3_TIMTRIG,
.tbase = ADC3_TIMER_BASE,
.pclck = ADC3_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY,
#endif
#ifdef ADC3_HAVE_DMA
.dmachan = ADC3_DMA_CHAN,
.dmacfg = CONFIG_STM32F7_ADC3_DMA_CFG,
.dmacfg = CONFIG_STM32_ADC3_DMA_CFG,
.hasdma = true,
.r_dmabuffer = g_adc3_dmabuffer,
.dmabatch = CONFIG_STM32F7_ADC3_DMA_BATCH,
.dmabatch = CONFIG_STM32_ADC3_DMA_BATCH,
#endif
.scan = CONFIG_STM32F7_ADC3_SCAN,
.scan = CONFIG_STM32_ADC3_SCAN,
#ifdef CONFIG_PM
.pm_callback =
{
@ -1455,7 +1455,7 @@ static void adc_enable(struct stm32_dev_s *priv, bool enable)
*
****************************************************************************/
#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ)
#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ)
static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
void *arg)
{
@ -1587,7 +1587,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev)
* During sample cycles channel selection bits must remain unchanged.
*/
#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv);
#else
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv;
@ -1673,7 +1673,7 @@ static void adc_dma_start(struct adc_dev_s *dev)
priv->dma = stm32_dmachannel(priv->dmachan);
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
/* Start DMA only if standard ADC interrupts used */
stm32_dmasetup(priv->dma,
@ -1853,7 +1853,7 @@ static int adc_setup(struct adc_dev_s *dev)
/* Attach the ADC interrupt */
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
ret = irq_attach(priv->irq, priv->isr, NULL);
if (ret < 0)
{
@ -1885,7 +1885,7 @@ static int adc_setup(struct adc_dev_s *dev)
/* As default conversion is started here */
#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV
/* Start regular conversion */
adc_reg_startconv(priv, true);
@ -1909,7 +1909,7 @@ static int adc_setup(struct adc_dev_s *dev)
{
/* Enable the ADC interrupt */
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
up_enable_irq(priv->irq);
#endif
@ -1967,7 +1967,7 @@ static void adc_shutdown(struct adc_dev_s *dev)
if (priv->cmn->refcount <= 1)
{
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
/* Disable ADC interrupts and detach the ADC interrupt handler */
up_disable_irq(priv->irq);
@ -2469,7 +2469,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
return ret;
}
#ifndef CONFIG_STM32F7_ADC_NOIRQ
#ifndef CONFIG_STM32_ADC_NOIRQ
/****************************************************************************
* Name: adc_interrupt
@ -2570,23 +2570,23 @@ static int adc_interrupt(struct adc_dev_s *dev)
static int adc123_interrupt(int irq, void *context, void *arg)
{
#ifdef CONFIG_STM32F7_ADC1
#ifdef CONFIG_STM32_ADC1
adc_interrupt(&g_adcdev1);
#endif
#ifdef CONFIG_STM32F7_ADC2
#ifdef CONFIG_STM32_ADC2
adc_interrupt(&g_adcdev2);
#endif
#ifdef CONFIG_STM32F7_ADC3
#ifdef CONFIG_STM32_ADC3
adc_interrupt(&g_adcdev3);
#endif
return OK;
}
#endif /* CONFIG_STM32F7_ADC_NOIRQ */
#endif /* CONFIG_STM32_ADC_NOIRQ */
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
/****************************************************************************
* Name: adc_llops_setup
@ -2821,7 +2821,7 @@ static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
static void adc_sampletime_write(struct stm32_adc_dev_s *dev)
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
@ -2911,7 +2911,7 @@ void adc_sampletime_set(struct stm32_adc_dev_s *dev,
}
}
}
#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */
#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */
/****************************************************************************
* Name: adc_llops_dumpregs
@ -3017,7 +3017,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable)
adc_enable(priv, enable);
}
#endif /* CONFIG_STM32F7_ADC_LL_OPS */
#endif /* CONFIG_STM32_ADC_LL_OPS */
/****************************************************************************
* Public Functions
@ -3085,12 +3085,12 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
switch (intf)
{
#ifdef CONFIG_STM32F7_ADC1
#ifdef CONFIG_STM32_ADC1
case 1:
{
ainfo("ADC1 selected\n");
dev = &g_adcdev1;
cj_channels = CONFIG_STM32F7_ADC1_INJECTED_CHAN;
cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN;
cr_channels = channels - cj_channels;
# ifdef ADC_HAVE_INJECTED
if (cj_channels > 0)
@ -3100,14 +3100,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
# endif
break;
}
#endif /* CONFIG_STM32F7_ADC1 */
#endif /* CONFIG_STM32_ADC1 */
#ifdef CONFIG_STM32F7_ADC2
#ifdef CONFIG_STM32_ADC2
case 2:
{
ainfo("ADC2 selected\n");
dev = &g_adcdev2;
cj_channels = CONFIG_STM32F7_ADC2_INJECTED_CHAN;
cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN;
cr_channels = channels - cj_channels;
# ifdef ADC_HAVE_INJECTED
if (cj_channels > 0)
@ -3117,14 +3117,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
# endif
break;
}
#endif /* CONFIG_STM32F7_ADC2 */
#endif /* CONFIG_STM32_ADC2 */
#ifdef CONFIG_STM32F7_ADC3
#ifdef CONFIG_STM32_ADC3
case 3:
{
ainfo("ADC3 selected\n");
dev = &g_adcdev3;
cj_channels = CONFIG_STM32F7_ADC3_INJECTED_CHAN;
cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN;
cr_channels = channels - cj_channels;
# ifdef ADC_HAVE_INJECTED
if (cj_channels > 0)
@ -3135,7 +3135,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
break;
}
#endif /* CONFIG_STM32F7_ADC3 */
#endif /* CONFIG_STM32_ADC3 */
default:
{
@ -3150,10 +3150,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
/* Configure regular channels */
DEBUGASSERT(cr_channels <= CONFIG_STM32F7_ADC_MAX_SAMPLES);
if (cr_channels > CONFIG_STM32F7_ADC_MAX_SAMPLES)
DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES);
if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES)
{
cr_channels = CONFIG_STM32F7_ADC_MAX_SAMPLES;
cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES;
}
priv->cr_channels = cr_channels;
@ -3172,14 +3172,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
memcpy(priv->j_chanlist, j_chanlist, cj_channels);
#endif
#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Assign default values for the sample time table */
memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER);
priv->adc_channels = ADC_CHANNELS_NUMBER;
#endif
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
/* Store reference to the upper-half ADC device */
priv->dev = dev;
@ -3195,4 +3195,4 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
return dev;
}
#endif /* CONFIG_STM32F7_ADC */
#endif /* CONFIG_STM32_ADC */

486
arch/arm/src/stm32f7/stm32_adc.h
View file

@ -63,75 +63,75 @@
* is intended to be used for that purpose. Timers 1-6 and 8 may be used.
*/
#ifndef CONFIG_STM32F7_TIM1
# undef CONFIG_STM32F7_TIM1_ADC
# undef CONFIG_STM32F7_TIM1_ADC1
# undef CONFIG_STM32F7_TIM1_ADC2
# undef CONFIG_STM32F7_TIM1_ADC3
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_ADC
# undef CONFIG_STM32_TIM1_ADC1
# undef CONFIG_STM32_TIM1_ADC2
# undef CONFIG_STM32_TIM1_ADC3
#endif
#ifndef CONFIG_STM32F7_TIM2
# undef CONFIG_STM32F7_TIM2_ADC
# undef CONFIG_STM32F7_TIM2_ADC1
# undef CONFIG_STM32F7_TIM2_ADC2
# undef CONFIG_STM32F7_TIM2_ADC3
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_ADC
# undef CONFIG_STM32_TIM2_ADC1
# undef CONFIG_STM32_TIM2_ADC2
# undef CONFIG_STM32_TIM2_ADC3
#endif
#ifndef CONFIG_STM32F7_TIM3
# undef CONFIG_STM32F7_TIM3_ADC
# undef CONFIG_STM32F7_TIM3_ADC1
# undef CONFIG_STM32F7_TIM3_ADC2
# undef CONFIG_STM32F7_TIM3_ADC3
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_ADC
# undef CONFIG_STM32_TIM3_ADC1
# undef CONFIG_STM32_TIM3_ADC2
# undef CONFIG_STM32_TIM3_ADC3
#endif
#ifndef CONFIG_STM32F7_TIM4
# undef CONFIG_STM32F7_TIM4_ADC
# undef CONFIG_STM32F7_TIM4_ADC1
# undef CONFIG_STM32F7_TIM4_ADC2
# undef CONFIG_STM32F7_TIM4_ADC3
#ifndef CONFIG_STM32_TIM4
# undef CONFIG_STM32_TIM4_ADC
# undef CONFIG_STM32_TIM4_ADC1
# undef CONFIG_STM32_TIM4_ADC2
# undef CONFIG_STM32_TIM4_ADC3
#endif
#ifndef CONFIG_STM32F7_TIM5
# undef CONFIG_STM32F7_TIM5_ADC
# undef CONFIG_STM32F7_TIM5_ADC1
# undef CONFIG_STM32F7_TIM5_ADC2
# undef CONFIG_STM32F7_TIM5_ADC3
#ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_ADC
# undef CONFIG_STM32_TIM5_ADC1
# undef CONFIG_STM32_TIM5_ADC2
# undef CONFIG_STM32_TIM5_ADC3
#endif
#ifndef CONFIG_STM32F7_TIM6
# undef CONFIG_STM32F7_TIM6_ADC
# undef CONFIG_STM32F7_TIM6_ADC1
# undef CONFIG_STM32F7_TIM6_ADC2
# undef CONFIG_STM32F7_TIM6_ADC3
#ifndef CONFIG_STM32_TIM6
# undef CONFIG_STM32_TIM6_ADC
# undef CONFIG_STM32_TIM6_ADC1
# undef CONFIG_STM32_TIM6_ADC2
# undef CONFIG_STM32_TIM6_ADC3
#endif
#ifndef CONFIG_STM32F7_TIM8
# undef CONFIG_STM32F7_TIM8_ADC
# undef CONFIG_STM32F7_TIM8_ADC1
# undef CONFIG_STM32F7_TIM8_ADC2
# undef CONFIG_STM32F7_TIM8_ADC3
#ifndef CONFIG_STM32_TIM8
# undef CONFIG_STM32_TIM8_ADC
# undef CONFIG_STM32_TIM8_ADC1
# undef CONFIG_STM32_TIM8_ADC2
# undef CONFIG_STM32_TIM8_ADC3
#endif
/* Up to 3 ADC interfaces are supported */
#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \
defined(CONFIG_STM32F7_ADC3)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
defined(CONFIG_STM32_ADC3)
/* DMA support */
#undef ADC_HAVE_DMA
#if defined(CONFIG_STM32F7_ADC1_DMA) || defined(CONFIG_STM32F7_ADC2_DMA) || \
defined(CONFIG_STM32F7_ADC3_DMA)
#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \
defined(CONFIG_STM32_ADC3_DMA)
# define ADC_HAVE_DMA 1
#endif
#ifdef CONFIG_STM32F7_ADC1_DMA
#ifdef CONFIG_STM32_ADC1_DMA
# define ADC1_HAVE_DMA 1
#else
# undef ADC1_HAVE_DMA
#endif
#ifdef CONFIG_STM32F7_ADC2_DMA
#ifdef CONFIG_STM32_ADC2_DMA
# define ADC2_HAVE_DMA 1
#else
# undef ADC2_HAVE_DMA
#endif
#ifdef CONFIG_STM32F7_ADC3_DMA
#ifdef CONFIG_STM32_ADC3_DMA
# define ADC3_HAVE_DMA 1
#else
# undef ADC3_HAVE_DMA
@ -139,9 +139,9 @@
/* Injected channels support */
#if (defined(CONFIG_STM32F7_ADC1) && (CONFIG_STM32F7_ADC1_INJECTED_CHAN > 0)) || \
(defined(CONFIG_STM32F7_ADC2) && (CONFIG_STM32F7_ADC2_INJECTED_CHAN > 0)) || \
(defined(CONFIG_STM32F7_ADC3) && (CONFIG_STM32F7_ADC3_INJECTED_CHAN > 0))
#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \
(defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \
(defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0))
# define ADC_HAVE_INJECTED
#endif
@ -149,31 +149,31 @@
* information about the timer.
*/
#if defined(CONFIG_STM32F7_TIM1_ADC1)
#if defined(CONFIG_STM32_TIM1_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM1_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32F7_TIM2_ADC1)
#elif defined(CONFIG_STM32_TIM2_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM2_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32F7_TIM3_ADC1)
#elif defined(CONFIG_STM32_TIM3_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM3_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32F7_TIM4_ADC1)
#elif defined(CONFIG_STM32_TIM4_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM4_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32F7_TIM5_ADC1)
#elif defined(CONFIG_STM32_TIM5_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM5_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
#elif defined(CONFIG_STM32F7_TIM6_ADC1)
#elif defined(CONFIG_STM32_TIM6_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM6_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
#elif defined(CONFIG_STM32F7_TIM8_ADC1)
#elif defined(CONFIG_STM32_TIM8_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM8_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
@ -182,40 +182,40 @@
#endif
#ifdef ADC1_HAVE_TIMER
# ifndef CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY not defined"
# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32F7_ADC1_TIMTRIG
# error "CONFIG_STM32F7_ADC1_TIMTRIG not defined"
# ifndef CONFIG_STM32_ADC1_TIMTRIG
# error "CONFIG_STM32_ADC1_TIMTRIG not defined"
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2"
# endif
#endif
#if defined(CONFIG_STM32F7_TIM1_ADC2)
#if defined(CONFIG_STM32_TIM1_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM1_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32F7_TIM2_ADC2)
#elif defined(CONFIG_STM32_TIM2_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM2_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32F7_TIM3_ADC2)
#elif defined(CONFIG_STM32_TIM3_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM3_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32F7_TIM4_ADC2)
#elif defined(CONFIG_STM32_TIM4_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM4_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32F7_TIM5_ADC2)
#elif defined(CONFIG_STM32_TIM5_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM5_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
#elif defined(CONFIG_STM32F7_TIM6_ADC2)
#elif defined(CONFIG_STM32_TIM6_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM6_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
#elif defined(CONFIG_STM32F7_TIM8_ADC2)
#elif defined(CONFIG_STM32_TIM8_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM8_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
@ -224,36 +224,36 @@
#endif
#ifdef ADC2_HAVE_TIMER
# ifndef CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY
# error "CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY not defined"
# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY
# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32F7_ADC2_TIMTRIG
# error "CONFIG_STM32F7_ADC2_TIMTRIG not defined"
# ifndef CONFIG_STM32_ADC2_TIMTRIG
# error "CONFIG_STM32_ADC2_TIMTRIG not defined"
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2"
# endif
#endif
#if defined(CONFIG_STM32F7_TIM1_ADC3)
#if defined(CONFIG_STM32_TIM1_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM1_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
#elif defined(CONFIG_STM32F7_TIM2_ADC3)
#elif defined(CONFIG_STM32_TIM2_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM2_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
#elif defined(CONFIG_STM32F7_TIM3_ADC3)
#elif defined(CONFIG_STM32_TIM3_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM3_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
#elif defined(CONFIG_STM32F7_TIM4_ADC3)
#elif defined(CONFIG_STM32_TIM4_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM4_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
#elif defined(CONFIG_STM32F7_TIM5_ADC3)
#elif defined(CONFIG_STM32_TIM5_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM5_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN
#elif defined(CONFIG_STM32F7_TIM8_ADC3)
#elif defined(CONFIG_STM32_TIM8_ADC3)
# define ADC3_HAVE_TIMER 1
# define ADC3_TIMER_BASE STM32_TIM8_BASE
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
@ -262,11 +262,11 @@
#endif
#ifdef ADC3_HAVE_TIMER
# ifndef CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY
# error "CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY not defined"
# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY
# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32F7_ADC3_TIMTRIG
# error "CONFIG_STM32F7_ADC3_TIMTRIG not defined"
# ifndef CONFIG_STM32_ADC3_TIMTRIG
# error "CONFIG_STM32_ADC3_TIMTRIG not defined"
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2"
# endif
#endif
@ -413,315 +413,315 @@
* CONFIG_STM32F7_ADCx_EXTSEL option.
*/
#if defined(CONFIG_STM32F7_TIM1_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#if defined(CONFIG_STM32_TIM1_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM2_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM2_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM3_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM3_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM4_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM4_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM5_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM5_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM6_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM6_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM8_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM8_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO
# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2
# else
# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
# endif
#endif
#if defined(CONFIG_STM32F7_TIM1_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#if defined(CONFIG_STM32_TIM1_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM2_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM2_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM3_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM3_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM4_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM4_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM5_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM5_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM6_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM6_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM8_ADC2)
# if CONFIG_STM32F7_ADC2_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM8_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO
# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2
# else
# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
# endif
#endif
#if defined(CONFIG_STM32F7_TIM1_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#if defined(CONFIG_STM32_TIM1_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5
# elif CONFIG_STM32_ADC3_TIMTRIG == 5
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM2_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM2_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM3_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM3_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM4_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM4_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM5_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM5_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM6_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM6_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#elif defined(CONFIG_STM32F7_TIM8_ADC3)
# if CONFIG_STM32F7_ADC3_TIMTRIG == 0
#elif defined(CONFIG_STM32_TIM8_ADC3)
# if CONFIG_STM32_ADC3_TIMTRIG == 0
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO
# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5
# elif CONFIG_STM32_ADC3_TIMTRIG == 5
# define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2
# else
# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range"
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
# endif
#endif
@ -730,7 +730,7 @@
#ifdef ADC1_EXTSEL_VALUE
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32F7_ADC1_EXTSEL)
#elif defined(CONFIG_STM32_ADC1_EXTSEL)
# define ADC1_HAVE_EXTCFG 1
# define ADC1_EXTCFG_VALUE 0
#else
@ -739,7 +739,7 @@
#ifdef ADC2_EXTSEL_VALUE
# define ADC2_HAVE_EXTCFG 1
# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32F7_ADC2_EXTSEL)
#elif defined(CONFIG_STM32_ADC2_EXTSEL)
# define ADC2_HAVE_EXTCFG 1
# define ADC2_EXTCFG_VALUE 0
#else
@ -748,7 +748,7 @@
#ifdef ADC3_EXTSEL_VALUE
# define ADC3_HAVE_EXTCFG 1
# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
#elif defined(CONFIG_STM32F7_ADC3_EXTSEL)
#elif defined(CONFIG_STM32_ADC3_EXTSEL)
# define ADC3_HAVE_EXTCFG 1
# define ADC3_EXTCFG_VALUE 0
#else
@ -771,7 +771,7 @@
#ifdef ADC1_JEXTSEL_VALUE
# define ADC1_HAVE_JEXTCFG 1
# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32F7_ADC1_JEXTSEL)
#elif defined(CONFIG_STM32_ADC1_JEXTSEL)
# define ADC1_HAVE_JEXTCFG 1
# define ADC1_JEXTCFG_VALUE 0
#else
@ -780,7 +780,7 @@
#ifdef ADC2_JEXTSEL_VALUE
# define ADC2_HAVE_JEXTCFG 1
# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32F7_ADC2_JEXTSEL)
#elif defined(CONFIG_STM32_ADC2_JEXTSEL)
# define ADC2_HAVE_JEXTCFG 1
# define ADC2_JEXTCFG_VALUE 0
#else
@ -789,7 +789,7 @@
#ifdef ADC3_JEXTSEL_VALUE
# define ADC3_HAVE_JEXTCFG 1
# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
#elif defined(CONFIG_STM32F7_ADC3_JEXTSEL)
#elif defined(CONFIG_STM32_ADC3_JEXTSEL)
# define ADC3_HAVE_JEXTCFG 1
# define ADC3_JEXTCFG_VALUE 0
#else
@ -914,9 +914,9 @@ enum stm32_adc_multimode_e
ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */
};
#ifdef CONFIG_STM32F7_ADC_LL_OPS
#ifdef CONFIG_STM32_ADC_LL_OPS
#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Channel and sample time pair */
@ -941,7 +941,7 @@ struct adc_sample_time_s
* same value of the sample time */
uint8_t all_ch_sample_time:3; /* Sample time for all channels */
};
#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */
#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */
/* This structure provides the publicly visible representation of the
* "lower-half" ADC driver structure.
@ -1024,7 +1024,7 @@ struct stm32_adc_ops_s
void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state);
#endif
#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Set ADC sample time */
void (*stime_set)(struct stm32_adc_dev_s *dev,
@ -1046,7 +1046,7 @@ struct stm32_adc_ops_s
void (*enable)(struct stm32_adc_dev_s *dev, bool enable);
};
#endif /* CONFIG_STM32F7_ADC_LL_OPS */
#endif /* CONFIG_STM32_ADC_LL_OPS */
/****************************************************************************
* Public Function Prototypes
@ -1088,7 +1088,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf,
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 ||
* CONFIG_STM32F7_ADC3
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
* CONFIG_STM32_ADC3
*/
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_ADC_H */

8
arch/arm/src/stm32f7/stm32_allocateheap.c
View file

@ -62,7 +62,7 @@
* the FMC. In order to use FMC RAM, the following additional things need
* to be present in the NuttX configuration file:
*
* CONFIG_STM32F7_FMC=y : Enables the FMC
* CONFIG_STM32_FMC=y : Enables the FMC
* CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC.
* Either of these autoselects
* CONFIG_ARCH_HAVE_HEAP2
@ -94,15 +94,15 @@
/* DTCM to be excluded from the main heap. */
#ifdef CONFIG_STM32F7_DTCMEXCLUDE
#ifdef CONFIG_STM32_DTCMEXCLUDE
# undef HAVE_DTCM
#endif
/* We can't possibly have FMC external RAM if the FMC is not enabled */
#ifndef CONFIG_STM32F7_FMC
#ifndef CONFIG_STM32_FMC
# ifdef CONFIG_ARCH_HAVE_HEAP2
# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed?
# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32_FMC! Kconfig flawed?
# endif
# undef CONFIG_ARCH_HAVE_HEAP2
#endif

14
arch/arm/src/stm32f7/stm32_bbsram.c
View file

@ -51,14 +51,14 @@
#include "stm32_pwr.h"
#include "stm32_rtc.h"
#ifdef CONFIG_STM32F7_BBSRAM
#ifdef CONFIG_STM32_BBSRAM
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_STM32F7_BKPSRAM)
#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled
#if !defined(CONFIG_STM32_BKPSRAM)
#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled
#endif
#define MAX_OPENCNT (255) /* Limit of uint8_t */
@ -147,7 +147,7 @@ static const struct file_operations g_stm32_bbsram_fops =
#endif
};
static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES];
static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES];
/****************************************************************************
* Private Functions
@ -633,7 +633,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
int ret = -EFBIG;
struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE;
for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0);
for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0);
i++)
{
/* Validate the actual allocations against what is in the BBSRAM */
@ -784,7 +784,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes)
*
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
#if defined(CONFIG_STM32_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length)
{
struct bbsramfh_s *bbf;
@ -802,7 +802,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length)
{
once = true;
DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES);
DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES);
bbf = g_bbsram[fileno].bbf;

14
arch/arm/src/stm32f7/stm32_bbsram.h
View file

@ -44,15 +44,15 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \
defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# define STM32_BBSRAM_SIZE 4096
#else
# error "No backup SRAM on this STM32 Device"
#endif
#if !defined(CONFIG_STM32F7_BBSRAM_FILES)
# define CONFIG_STM32F7_BBSRAM_FILES 4
#if !defined(CONFIG_STM32_BBSRAM_FILES)
# define CONFIG_STM32_BBSRAM_FILES 4
#endif
/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique
@ -110,8 +110,8 @@ extern "C"
* the last entry should be 0
* A size of -1 will use all the remaining spaces
*
* If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES
* CONFIG_STM32F7_BBSRAM_FILES will be returned.
* If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES
* CONFIG_STM32_BBSRAM_FILES will be returned.
*
* Returned Value:
* Number of files created on success; Negated errno on failure.
@ -140,7 +140,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes);
*
****************************************************************************/
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
#if defined(CONFIG_STM32_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length);
#endif

36
arch/arm/src/stm32f7/stm32_can.c
View file

@ -48,8 +48,8 @@
#include "stm32_gpio.h"
#if defined(CONFIG_CAN) && \
(defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) || \
defined(CONFIG_STM32F7_CAN3))
(defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) || \
defined(CONFIG_STM32_CAN3))
/****************************************************************************
* Pre-processor Definitions
@ -63,7 +63,7 @@
/* Bit timing ***************************************************************/
#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1)
#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1)
#ifndef CONFIG_DEBUG_CAN_INFO
# undef CONFIG_STM32_CAN_REGDEBUG
@ -179,7 +179,7 @@ static const struct can_ops_s g_canops =
.co_txempty = stm32can_txempty,
};
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
static struct stm32_can_s g_can1priv =
{
.port = 1,
@ -192,7 +192,7 @@ static struct stm32_can_s g_can1priv =
.filter = 0,
.base = STM32_CAN1_BASE,
.fbase = STM32_CAN1_BASE,
.baud = CONFIG_STM32F7_CAN1_BAUD,
.baud = CONFIG_STM32_CAN1_BAUD,
};
static struct can_dev_s g_can1dev =
@ -202,7 +202,7 @@ static struct can_dev_s g_can1dev =
};
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
static struct stm32_can_s g_can2priv =
{
.port = 2,
@ -215,7 +215,7 @@ static struct stm32_can_s g_can2priv =
.filter = CAN_NFILTERS / 2,
.base = STM32_CAN2_BASE,
.fbase = STM32_CAN1_BASE,
.baud = CONFIG_STM32F7_CAN2_BAUD,
.baud = CONFIG_STM32_CAN2_BAUD,
};
static struct can_dev_s g_can2dev =
@ -225,7 +225,7 @@ static struct can_dev_s g_can2dev =
};
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
static struct stm32_can_s g_can3priv =
{
.port = 3,
@ -238,7 +238,7 @@ static struct stm32_can_s g_can3priv =
.filter = 0,
.base = STM32_CAN3_BASE,
.fbase = STM32_CAN3_BASE,
.baud = CONFIG_STM32F7_CAN3_BAUD,
.baud = CONFIG_STM32_CAN3_BAUD,
};
static struct can_dev_s g_can3dev =
@ -582,21 +582,21 @@ static void stm32can_reset(struct can_dev_s *dev)
/* Get the bits in the AHB1RSTR register needed to reset this CAN device */
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
if (priv->port == 1)
{
regbit = RCC_APB1RSTR_CAN1RST;
}
else
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
if (priv->port == 2)
{
regbit = RCC_APB1RSTR_CAN2RST;
}
else
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
if (priv->port == 3)
{
regbit = RCC_APB1RSTR_CAN3RST;
@ -1789,8 +1789,8 @@ static int stm32can_bittiming(struct stm32_can_s *priv)
else
{
ts1 = CONFIG_STM32F7_CAN_TSEG1;
ts2 = CONFIG_STM32F7_CAN_TSEG2;
ts1 = CONFIG_STM32_CAN_TSEG1;
ts2 = CONFIG_STM32_CAN_TSEG2;
brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA;
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
@ -2038,7 +2038,7 @@ static int stm32can_filterinit(struct stm32_can_s *priv)
regval |= CAN_FMR_FINIT;
stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
#if defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2)
#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)
if (priv->port == 1 || priv->port == 2)
{
/* Assign half the filters to CAN1, half to CAN2 */
@ -2270,7 +2270,7 @@ struct can_dev_s *stm32_caninitialize(int port)
* by stm32_clockconfig() early in the reset sequence.
*/
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
if (port == 1)
{
/* Select the CAN1 device structure */
@ -2286,7 +2286,7 @@ struct can_dev_s *stm32_caninitialize(int port)
}
else
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
if (port == 2)
{
/* Select the CAN2 device structure */
@ -2302,7 +2302,7 @@ struct can_dev_s *stm32_caninitialize(int port)
}
else
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
if (port == 3)
{
/* Select the CAN3 device structure */

40
arch/arm/src/stm32f7/stm32_can.h
View file

@ -40,45 +40,45 @@
/* Configuration ************************************************************/
#if defined(CONFIG_CAN) && (defined(CONFIG_STM32F7_CAN1) || \
defined(CONFIG_STM32F7_CAN2) || defined(CONFIG_STM32F7_CAN3))
#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || \
defined(CONFIG_STM32_CAN2) || defined(CONFIG_STM32_CAN3))
/* CAN BAUD */
#if defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN1_BAUD)
# error "CONFIG_STM32F7_CAN1_BAUD is not defined"
#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD)
# error "CONFIG_STM32_CAN1_BAUD is not defined"
#endif
#if defined(CONFIG_STM32F7_CAN2) && !defined(CONFIG_STM32F7_CAN2_BAUD)
# error "CONFIG_STM32F7_CAN2_BAUD is not defined"
#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD)
# error "CONFIG_STM32_CAN2_BAUD is not defined"
#endif
#if defined(CONFIG_STM32F7_CAN3) && !defined(CONFIG_STM32F7_CAN3_BAUD)
# error "CONFIG_STM32F7_CAN3_BAUD is not defined"
#if defined(CONFIG_STM32_CAN3) && !defined(CONFIG_STM32_CAN3_BAUD)
# error "CONFIG_STM32_CAN3_BAUD is not defined"
#endif
/* User-defined TSEG1 and TSEG2 settings may be used.
*
* CONFIG_STM32F7_CAN_TSEG1 = the number of CAN time quanta in segment 1
* CONFIG_STM32F7_CAN_TSEG2 = the number of CAN time quanta in segment 2
* CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1
* CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2
* CAN_BIT_QUANTA = The number of CAN time quanta in on bit time
*/
#ifndef CONFIG_STM32F7_CAN_TSEG1
# define CONFIG_STM32F7_CAN_TSEG1 6
#ifndef CONFIG_STM32_CAN_TSEG1
# define CONFIG_STM32_CAN_TSEG1 6
#endif
#if CONFIG_STM32F7_CAN_TSEG1 < 1 || \
CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX
#if CONFIG_STM32_CAN_TSEG1 < 1 || \
CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX
# error "CONFIG_STM32_CAN_TSEG1 is out of range"
#endif
#ifndef CONFIG_STM32F7_CAN_TSEG2
# define CONFIG_STM32F7_CAN_TSEG2 7
#ifndef CONFIG_STM32_CAN_TSEG2
# define CONFIG_STM32_CAN_TSEG2 7
#endif
#if CONFIG_STM32F7_CAN_TSEG2 < 1 || \
CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX
#if CONFIG_STM32_CAN_TSEG2 < 1 || \
CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX
# error "CONFIG_STM32_CAN_TSEG2 is out of range"
#endif
@ -105,7 +105,7 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_CHARDRIVER
#ifdef CONFIG_STM32_CAN_CHARDRIVER
/****************************************************************************
* Name: stm32_caninitialize
@ -125,7 +125,7 @@ struct can_dev_s;
struct can_dev_s *stm32_caninitialize(int port);
#endif
#ifdef CONFIG_STM32F7_CAN_SOCKET
#ifdef CONFIG_STM32_CAN_SOCKET
/****************************************************************************
* Name: stm32_cansockinitialize

60
arch/arm/src/stm32f7/stm32_can_sock.c
View file

@ -63,10 +63,10 @@
/* Bit timing ***************************************************************/
#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1)
#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1)
#ifndef CONFIG_DEBUG_CAN_INFO
# undef CONFIG_STM32F7_CAN_REGDEBUG
# undef CONFIG_STM32_CAN_REGDEBUG
#endif
/* Pool configuration *******************************************************/
@ -146,7 +146,7 @@ static void stm32can_putreg(struct stm32_can_s *priv, int offset,
uint32_t value);
static void stm32can_putfreg(struct stm32_can_s *priv, int offset,
uint32_t value);
#ifdef CONFIG_STM32F7_CAN_REGDEBUG
#ifdef CONFIG_STM32_CAN_REGDEBUG
static void stm32can_dumpctrlregs(struct stm32_can_s *priv,
const char *msg);
static void stm32can_dumpmbregs(struct stm32_can_s *priv,
@ -233,7 +233,7 @@ static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
static struct stm32_can_s g_can1priv =
{
@ -250,12 +250,12 @@ static struct stm32_can_s g_can1priv =
.filter = 0,
.base = STM32_CAN1_BASE,
.fbase = STM32_CAN1_BASE,
.baud = CONFIG_STM32F7_CAN1_BAUD,
.baud = CONFIG_STM32_CAN1_BAUD,
};
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
static struct stm32_can_s g_can2priv =
{
@ -272,12 +272,12 @@ static struct stm32_can_s g_can2priv =
.filter = CAN_NFILTERS / 2,
.base = STM32_CAN2_BASE,
.fbase = STM32_CAN1_BASE,
.baud = CONFIG_STM32F7_CAN2_BAUD,
.baud = CONFIG_STM32_CAN2_BAUD,
};
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
static struct stm32_can_s g_can3priv =
{
@ -294,7 +294,7 @@ static struct stm32_can_s g_can3priv =
.filter = CAN_NFILTERS / 2,
.base = STM32_CAN3_BASE,
.fbase = STM32_CAN3_BASE,
.baud = CONFIG_STM32F7_CAN3_BAUD,
.baud = CONFIG_STM32_CAN3_BAUD,
};
#endif
@ -312,7 +312,7 @@ static struct stm32_can_s g_can3priv =
*
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_REGDEBUG
#ifdef CONFIG_STM32_CAN_REGDEBUG
static uint32_t stm32can_vgetreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -398,7 +398,7 @@ static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_REGDEBUG
#ifdef CONFIG_STM32_CAN_REGDEBUG
static void stm32can_vputreg(uint32_t addr, uint32_t value)
{
/* Show the register value being written */
@ -451,7 +451,7 @@ static void stm32can_putfreg(struct stm32_can_s *priv, int offset,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_REGDEBUG
#ifdef CONFIG_STM32_CAN_REGDEBUG
static void stm32can_dumpctrlregs(struct stm32_can_s *priv,
const char *msg)
{
@ -497,7 +497,7 @@ static void stm32can_dumpctrlregs(struct stm32_can_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_REGDEBUG
#ifdef CONFIG_STM32_CAN_REGDEBUG
static void stm32can_dumpmbregs(struct stm32_can_s *priv,
const char *msg)
{
@ -564,7 +564,7 @@ static void stm32can_dumpmbregs(struct stm32_can_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_CAN_REGDEBUG
#ifdef CONFIG_STM32_CAN_REGDEBUG
static void stm32can_dumpfiltregs(struct stm32_can_s *priv,
const char *msg)
{
@ -1860,15 +1860,15 @@ static int stm32can_bittiming(struct stm32_can_s *priv)
}
}
/* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32F7_CAN_TSEG1,
* ts2 is CONFIG_STM32F7_CAN_TSEG2 and we calculate brp to achieve
/* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1,
* ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve
* CAN_BIT_QUANTA quanta in the bit time
*/
else
{
ts1 = CONFIG_STM32F7_CAN_TSEG1;
ts2 = CONFIG_STM32F7_CAN_TSEG2;
ts1 = CONFIG_STM32_CAN_TSEG1;
ts2 = CONFIG_STM32_CAN_TSEG2;
brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA;
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
@ -2036,21 +2036,21 @@ static void stm32can_reset(struct stm32_can_s *priv)
/* Get the bits in the AHB1RSTR register needed to reset this CAN device */
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
if (priv->port == 1)
{
regbit = RCC_APB1RSTR_CAN1RST;
}
else
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
if (priv->port == 2)
{
regbit = RCC_APB1RSTR_CAN2RST;
}
else
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
if (priv->port == 3)
{
regbit = RCC_APB1RSTR_CAN3RST;
@ -2298,9 +2298,9 @@ static int stm32can_filterinit(struct stm32_can_s *priv)
/* Assign half the filters to CAN1, half to CAN2 */
#if defined(CONFIG_STM32F7_CONNECTIVITYLINE) || \
defined(CONFIG_STM32F7_STM32F20XX) || \
defined(CONFIG_STM32F7_STM32F4XXX)
#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F4XXX)
regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET);
regval &= CAN_FMR_CAN2SB_MASK;
regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT;
@ -2432,7 +2432,7 @@ int stm32_cansockinitialize(int port)
* by stm32_clockconfig() early in the reset sequence.
*/
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
if (port == 1)
{
/* Select the CAN1 device structure */
@ -2448,7 +2448,7 @@ int stm32_cansockinitialize(int port)
}
else
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
if (port == 2)
{
/* Select the CAN2 device structure */
@ -2464,7 +2464,7 @@ int stm32_cansockinitialize(int port)
}
else
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
if (port == 3)
{
/* Select the CAN3 device structure */
@ -2526,15 +2526,15 @@ errout:
#if !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void)
{
#ifdef CONFIG_STM32F7_CAN1
#ifdef CONFIG_STM32_CAN1
stm32_cansockinitialize(1);
#endif
#ifdef CONFIG_STM32F7_CAN2
#ifdef CONFIG_STM32_CAN2
stm32_cansockinitialize(2);
#endif
#ifdef CONFIG_STM32F7_CAN3
#ifdef CONFIG_STM32_CAN3
stm32_cansockinitialize(3);
#endif
}

122
arch/arm/src/stm32f7/stm32_capture.c
View file

@ -92,18 +92,18 @@
* intended for some other purpose.
*/
#if defined(CONFIG_STM32F7_TIM1_CAP) || \
defined(CONFIG_STM32F7_TIM2_CAP) || \
defined(CONFIG_STM32F7_TIM3_CAP) || \
defined(CONFIG_STM32F7_TIM4_CAP) || \
defined(CONFIG_STM32F7_TIM5_CAP) || \
defined(CONFIG_STM32F7_TIM8_CAP) || \
defined(CONFIG_STM32F7_TIM9_CAP) || \
defined(CONFIG_STM32F7_TIM10_CAP) || \
defined(CONFIG_STM32F7_TIM11_CAP) || \
defined(CONFIG_STM32F7_TIM12_CAP) || \
defined(CONFIG_STM32F7_TIM13_CAP) || \
defined(CONFIG_STM32F7_TIM14_CAP)
#if defined(CONFIG_STM32_TIM1_CAP) || \
defined(CONFIG_STM32_TIM2_CAP) || \
defined(CONFIG_STM32_TIM3_CAP) || \
defined(CONFIG_STM32_TIM4_CAP) || \
defined(CONFIG_STM32_TIM5_CAP) || \
defined(CONFIG_STM32_TIM8_CAP) || \
defined(CONFIG_STM32_TIM9_CAP) || \
defined(CONFIG_STM32_TIM10_CAP) || \
defined(CONFIG_STM32_TIM11_CAP) || \
defined(CONFIG_STM32_TIM12_CAP) || \
defined(CONFIG_STM32_TIM13_CAP) || \
defined(CONFIG_STM32_TIM14_CAP)
/****************************************************************************
* Private Types
@ -182,7 +182,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
{
switch (priv->base)
{
#ifdef CONFIG_STM32F7_TIM1_CAP
#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
switch (channel)
{
@ -209,7 +209,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
}
break;
#endif
#ifdef CONFIG_STM32F7_TIM2_CAP
#ifdef CONFIG_STM32_TIM2_CAP
case STM32_TIM2_BASE:
switch (channel)
{
@ -236,7 +236,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
}
break;
#endif
#ifdef CONFIG_STM32F7_TIM3_CAP
#ifdef CONFIG_STM32_TIM3_CAP
case STM32_TIM3_BASE:
switch (channel)
{
@ -263,7 +263,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
}
break;
#endif
#ifdef CONFIG_STM32F7_TIM4_CAP
#ifdef CONFIG_STM32_TIM4_CAP
case STM32_TIM4_BASE:
switch (channel)
{
@ -290,7 +290,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
}
break;
#endif
#ifdef CONFIG_STM32F7_TIM5_CAP
#ifdef CONFIG_STM32_TIM5_CAP
case STM32_TIM5_BASE:
switch (channel)
{
@ -320,7 +320,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32F7_TIM8_CAP
#ifdef CONFIG_STM32_TIM8_CAP
case STM32_TIM8_BASE:
switch (channel)
{
@ -348,7 +348,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
break;
#endif
#ifdef CONFIG_STM32F7_TIM9_CAP
#ifdef CONFIG_STM32_TIM9_CAP
case STM32_TIM9_BASE:
switch (channel)
{
@ -376,7 +376,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
break;
#endif
#ifdef CONFIG_STM32F7_TIM10_CAP
#ifdef CONFIG_STM32_TIM10_CAP
case STM32_TIM10_BASE:
switch (channel)
{
@ -404,7 +404,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
break;
#endif
#ifdef CONFIG_STM32F7_TIM11_CAP
#ifdef CONFIG_STM32_TIM11_CAP
case STM32_TIM11_BASE:
switch (channel)
{
@ -432,7 +432,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
break;
#endif
#ifdef CONFIG_STM32F7_TIM12_CAP
#ifdef CONFIG_STM32_TIM12_CAP
case STM32_TIM12_BASE:
switch (channel)
{
@ -460,7 +460,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
break;
#endif
#ifdef CONFIG_STM32F7_TIM13_CAP
#ifdef CONFIG_STM32_TIM13_CAP
case STM32_TIM13_BASE:
switch (channel)
{
@ -488,7 +488,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel)
break;
#endif
#ifdef CONFIG_STM32F7_TIM14_CAP
#ifdef CONFIG_STM32_TIM14_CAP
case STM32_TIM14_BASE:
switch (channel)
{
@ -528,31 +528,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv,
switch (priv->base)
{
#ifdef CONFIG_STM32F7_TIM1_CAP
#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM2_CAP
#ifdef CONFIG_STM32_TIM2_CAP
case STM32_TIM2_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM3_CAP
#ifdef CONFIG_STM32_TIM3_CAP
case STM32_TIM3_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM4_CAP
#ifdef CONFIG_STM32_TIM4_CAP
case STM32_TIM4_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM4EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM5_CAP
#ifdef CONFIG_STM32_TIM5_CAP
case STM32_TIM5_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM5EN;
@ -561,43 +561,43 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv,
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32F7_TIM8_CAP
#ifdef CONFIG_STM32_TIM8_CAP
case STM32_TIM8_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM8EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM9_CAP
#ifdef CONFIG_STM32_TIM9_CAP
case STM32_TIM9_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM9EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM10_CAP
#ifdef CONFIG_STM32_TIM10_CAP
case STM32_TIM10_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM10EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM11_CAP
#ifdef CONFIG_STM32_TIM11_CAP
case STM32_TIM11_BASE:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM11EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM12_CAP
#ifdef CONFIG_STM32_TIM12_CAP
case STM32_TIM12_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM12EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM13_CAP
#ifdef CONFIG_STM32_TIM13_CAP
case STM32_TIM13_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM13EN;
break;
#endif
#ifdef CONFIG_STM32F7_TIM14_CAP
#ifdef CONFIG_STM32_TIM14_CAP
case STM32_TIM14_BASE:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM14EN;
@ -1082,7 +1082,7 @@ struct stm32_cap_ops_s stm32_cap_ops =
.getflags = &stm32_cap_getflags
};
#ifdef CONFIG_STM32F7_TIM1_CAP
#ifdef CONFIG_STM32_TIM1_CAP
const struct stm32_cap_priv_s stm32_tim1_priv =
{
.ops = &stm32_cap_ops,
@ -1094,7 +1094,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM2_CAP
#ifdef CONFIG_STM32_TIM2_CAP
const struct stm32_cap_priv_s stm32_tim2_priv =
{
.ops = &stm32_cap_ops,
@ -1106,7 +1106,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM3_CAP
#ifdef CONFIG_STM32_TIM3_CAP
const struct stm32_cap_priv_s stm32_tim3_priv =
{
.ops = &stm32_cap_ops,
@ -1118,7 +1118,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM4_CAP
#ifdef CONFIG_STM32_TIM4_CAP
const struct stm32_cap_priv_s stm32_tim4_priv =
{
.ops = &stm32_cap_ops,
@ -1130,7 +1130,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM5_CAP
#ifdef CONFIG_STM32_TIM5_CAP
const struct stm32_cap_priv_s stm32_tim5_priv =
{
.ops = &stm32_cap_ops,
@ -1144,7 +1144,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv =
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32F7_TIM8_CAP
#ifdef CONFIG_STM32_TIM8_CAP
const struct stm32_cap_priv_s stm32_tim8_priv =
{
.ops = &stm32_cap_ops,
@ -1156,7 +1156,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM9_CAP
#ifdef CONFIG_STM32_TIM9_CAP
const struct stm32_cap_priv_s stm32_tim9_priv =
{
.ops = &stm32_cap_ops,
@ -1168,7 +1168,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM10_CAP
#ifdef CONFIG_STM32_TIM10_CAP
const struct stm32_cap_priv_s stm32_tim10_priv =
{
.ops = &stm32_cap_ops,
@ -1180,7 +1180,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM11_CAP
#ifdef CONFIG_STM32_TIM11_CAP
const struct stm32_cap_priv_s stm32_tim11_priv =
{
.ops = &stm32_cap_ops,
@ -1192,7 +1192,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM12_CAP
#ifdef CONFIG_STM32_TIM12_CAP
const struct stm32_cap_priv_s stm32_tim12_priv =
{
.ops = &stm32_cap_ops,
@ -1204,7 +1204,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM13_CAP
#ifdef CONFIG_STM32_TIM13_CAP
const struct stm32_cap_priv_s stm32_tim13_priv =
{
.ops = &stm32_cap_ops,
@ -1216,7 +1216,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv =
};
#endif
#ifdef CONFIG_STM32F7_TIM14_CAP
#ifdef CONFIG_STM32_TIM14_CAP
const struct stm32_cap_priv_s stm32_tim14_priv =
{
.ops = &stm32_cap_ops,
@ -1232,54 +1232,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer)
{
switch (timer)
{
#ifdef CONFIG_STM32F7_TIM1_CAP
#ifdef CONFIG_STM32_TIM1_CAP
case 1:
return &stm32_tim1_priv;
#endif
#ifdef CONFIG_STM32F7_TIM2_CAP
#ifdef CONFIG_STM32_TIM2_CAP
case 2:
return &stm32_tim2_priv;
#endif
#ifdef CONFIG_STM32F7_TIM3_CAP
#ifdef CONFIG_STM32_TIM3_CAP
case 3:
return &stm32_tim3_priv;
#endif
#ifdef CONFIG_STM32F7_TIM4_CAP
#ifdef CONFIG_STM32_TIM4_CAP
case 4:
return &stm32_tim4_priv;
#endif
#ifdef CONFIG_STM32F7_TIM5_CAP
#ifdef CONFIG_STM32_TIM5_CAP
case 5:
return &stm32_tim5_priv;
#endif
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32F7_TIM8_CAP
#ifdef CONFIG_STM32_TIM8_CAP
case 8:
return &stm32_tim8_priv;
#endif
#ifdef CONFIG_STM32F7_TIM9_CAP
#ifdef CONFIG_STM32_TIM9_CAP
case 9:
return &stm32_tim9_priv;
#endif
#ifdef CONFIG_STM32F7_TIM10_CAP
#ifdef CONFIG_STM32_TIM10_CAP
case 10:
return &stm32_tim10_priv;
#endif
#ifdef CONFIG_STM32F7_TIM11_CAP
#ifdef CONFIG_STM32_TIM11_CAP
case 11:
return &stm32_tim11_priv;
#endif
#ifdef CONFIG_STM32F7_TIM12_CAP
#ifdef CONFIG_STM32_TIM12_CAP
case 12:
return &stm32_tim12_priv;
#endif
#ifdef CONFIG_STM32F7_TIM13_CAP
#ifdef CONFIG_STM32_TIM13_CAP
case 13:
return &stm32_tim13_priv;
#endif
#ifdef CONFIG_STM32F7_TIM14_CAP
#ifdef CONFIG_STM32_TIM14_CAP
case 14:
return &stm32_tim14_priv;
#endif
@ -1336,4 +1336,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev)
return OK;
}
#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM14) */
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */

42
arch/arm/src/stm32f7/stm32_config.h
View file

@ -71,21 +71,21 @@
# undef CONFIG_STM32F7_UART1
# undef CONFIG_STM32F7_UART2
# undef CONFIG_STM32F7_UART3
# undef CONFIG_STM32F7_UART4
# undef CONFIG_STM32_UART4
#elif STM32_NUART < 2
# undef CONFIG_STM32F7_UART1
# undef CONFIG_STM32F7_UART2
# undef CONFIG_STM32F7_UART3
# undef CONFIG_STM32F7_UART4
# undef CONFIG_STM32_UART4
#elif STM32_NUART < 3
# undef CONFIG_STM32F7_UART2
# undef CONFIG_STM32F7_UART3
# undef CONFIG_STM32F7_UART4
# undef CONFIG_STM32_UART4
#elif STM32_NUART < 4
# undef CONFIG_STM32F7_UART3
# undef CONFIG_STM32F7_UART4
# undef CONFIG_STM32_UART4
#elif STM32_NUART < 5
# undef CONFIG_STM32F7_UART4
# undef CONFIG_STM32_UART4
#endif
/* Are any UARTs enabled? */
@ -93,7 +93,7 @@
#undef HAVE_UART_DEVICE
#if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \
defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \
defined(CONFIG_STM32F7_UART4)
defined(CONFIG_STM32_UART4)
# define HAVE_UART_DEVICE 1
#endif
@ -107,29 +107,29 @@
# undef CONFIG_STM32F7_USART0
#endif
#ifndef CONFIG_USART1_SERIALDRIVER
# undef CONFIG_STM32F7_USART1
# undef CONFIG_STM32_USART1
#endif
#ifndef CONFIG_USART2_SERIALDRIVER
# undef CONFIG_STM32F7_USART2
# undef CONFIG_STM32_USART2
#endif
/* Don't enable USARTs not supported by the chip. */
#if STM32_NUSART < 1
# undef CONFIG_STM32F7_USART0
# undef CONFIG_STM32F7_USART1
# undef CONFIG_STM32F7_USART2
# undef CONFIG_STM32_USART1
# undef CONFIG_STM32_USART2
#elif STM32_NUSART < 2
# undef CONFIG_STM32F7_USART1
# undef CONFIG_STM32F7_USART2
# undef CONFIG_STM32_USART1
# undef CONFIG_STM32_USART2
#elif STM32_NUSART < 3
# undef CONFIG_STM32F7_USART2
# undef CONFIG_STM32_USART2
#endif
/* Are any USARTs enabled? */
#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \
defined(CONFIG_STM32F7_USART2)
#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2)
# undef HAVE_UART_DEVICE
# define HAVE_UART_DEVICE 1
#endif
@ -199,7 +199,7 @@
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4)
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -217,7 +217,7 @@
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -226,7 +226,7 @@
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
@ -252,14 +252,14 @@
#if CHIP_NSPI < 1
# undef CONFIG_STM32F7_SPI0
# undef CONFIG_STM32F7_SPI1
# undef CONFIG_STM32_SPI1
#elif CHIP_NSPI < 2
# undef CONFIG_STM32F7_SPI1
# undef CONFIG_STM32_SPI1
#endif
#ifndef CONFIG_STM32F7_HAVE_SPI
# undef CONFIG_STM32F7_SPI0
# undef CONFIG_STM32F7_SPI1
# undef CONFIG_STM32_SPI1
#endif
/* Are any SPI peripherals enabled? */

14
arch/arm/src/stm32f7/stm32_dma.c
View file

@ -46,9 +46,9 @@
* families
*/
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \
|| defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \
|| defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Pre-processor Definitions
@ -596,7 +596,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
" ntransfers: %zu scr: %08" PRIx32 "\n",
paddr, maddr, ntransfers, scr);
#ifdef CONFIG_STM32F7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr));
#endif
@ -895,7 +895,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr)
{
uint32_t transfer_size;
@ -958,7 +958,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr)
dmawarn("stm32_dmacapable:"
" dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08"
PRIx32 "\n", maddr, mend);
#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED)
return false;
#endif
}
@ -1121,4 +1121,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
}
#endif
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */

2
arch/arm/src/stm32f7/stm32_dma.h
View file

@ -242,7 +242,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
*
****************************************************************************/
#ifdef CONFIG_STM32F7_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
#else
# define stm32_dmacapable(maddr, count, ccr) (true)

42
arch/arm/src/stm32f7/stm32_dma2d.c
View file

@ -91,7 +91,7 @@
/* Debug option */
#ifdef CONFIG_STM32F7_DMA2D_REGDEBUG
#ifdef CONFIG_STM32_DMA2D_REGDEBUG
# define regerr lcderr
# define reginfo lcdinfo
#else
@ -109,7 +109,7 @@ struct stm32_dma2d_s
{
struct dma2d_layer_s dma2d; /* Public dma2d interface */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
uint32_t *clut; /* Color lookup table */
#endif
@ -172,7 +172,7 @@ static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] =
STM32_DMA2D_OCOLR
};
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
/* DMA2D clut memory address register */
static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] =
@ -192,7 +192,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits);
static int stm32_dma2dirq(int irq, void *context, void *arg);
static int stm32_dma2d_waitforirq(void);
static int stm32_dma2d_start(void);
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static int stm32_dma2d_loadclut(uintptr_t reg);
#endif
static uint32_t
@ -212,7 +212,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
/* Public Functions */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap);
#endif
static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo,
@ -239,15 +239,15 @@ static bool g_initialized;
/* Allocate clut */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static uint32_t g_clut[STM32_DMA2D_NCLUT *
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
4
# else
3
# endif
/ 4];
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/* The DMA2D mutex that enforces mutually exclusive access */
@ -270,14 +270,14 @@ static struct stm32_dma2d_s g_dma2ddev =
{
.dma2d =
{
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
.setclut = stm32_dma2d_setclut,
#endif
.fillcolor = stm32_dma2d_fillcolor,
.blit = stm32_dma2d_blit,
.blend = stm32_dma2d_blend
},
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
.clut = g_clut,
#endif
.lock = &g_lock
@ -344,7 +344,7 @@ static int stm32_dma2dirq(int irq, void *context, void *arg)
putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR);
priv->error = OK;
}
#ifdef CONFIG_STM32F7_DMA2D_L8
#ifdef CONFIG_STM32_DMA2D_L8
else if (regval & DMA2D_ISR_CTCIF)
{
/* CLUT transfer complete interrupt */
@ -461,7 +461,7 @@ static int stm32_dma2d_waitforirq(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_DMA2D_L8
#ifdef CONFIG_STM32_DMA2D_L8
static int stm32_dma2d_loadclut(uintptr_t pfcreg)
{
int ret;
@ -681,7 +681,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
pfccrreg = DMA2D_XGPFCCR_CM(fmt);
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
if (fmt == DMA2D_PF_L8)
{
struct stm32_dma2d_s *layer = &g_dma2ddev;
@ -692,7 +692,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
/* Set the CLUT color mode */
# ifndef CONFIG_STM32F7_FB_TRANSPARENCY
# ifndef CONFIG_STM32_FB_TRANSPARENCY
pfccrreg |= DMA2D_XGPFCCR_CCM;
# endif
@ -708,7 +708,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]);
}
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/* Set alpha blend mode */
@ -744,7 +744,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap)
{
int n;
@ -760,7 +760,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap)
* blit operation becomes active
*/
# ifndef CONFIG_STM32F7_FB_TRANSPARENCY
# ifndef CONFIG_STM32_FB_TRANSPARENCY
uint8_t *clut = (uint8_t *)g_dma2ddev.clut;
uint16_t offset = 3 * n;
@ -789,7 +789,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap)
nxmutex_unlock(priv->lock);
return OK;
}
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/****************************************************************************
* Name: stm32_dma2d_fillcolor
@ -822,7 +822,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo,
lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb);
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
if (oinfo->fmt == DMA2D_PF_L8)
{
/* CLUT output not supported */
@ -1006,7 +1006,7 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay,
"barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos,
foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h);
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
if (doverlay->fmt == DMA2D_PF_L8)
{
/* CLUT output not supported */
@ -1095,7 +1095,7 @@ int stm32_dma2dinitialize(void)
* arch/arm/src/stm32f7/stm32f7xxxx_rcc.c
*/
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
/* Enable dma2d transfer and clut loading interrupts only */
stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE |

2
arch/arm/src/stm32f7/stm32_dma2d.h
View file

@ -65,7 +65,7 @@ struct dma2d_layer_s
* On error - -EINVAL
*/
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
int (*setclut)(const struct fb_cmap_s * cmap);
#endif

8
arch/arm/src/stm32f7/stm32_dtcm.h
View file

@ -43,11 +43,11 @@
/* The STM32 F7 have DTCM memory */
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \
|| defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# define DTCM_START 0x20000000
# define DTCM_END 0x20010000
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# define DTCM_START 0x20000000
# define DTCM_END 0x20020000
#else
@ -58,7 +58,7 @@
* heap.
*/
#ifndef CONFIG_STM32F7_DTCMEXCLUDE
#ifndef CONFIG_STM32_DTCMEXCLUDE
# undef HAVE_DTCM_HEAP
#endif

8
arch/arm/src/stm32f7/stm32_dumpgpio.c
View file

@ -44,9 +44,9 @@
* families
*/
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \
|| defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \
|| defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Private Data
@ -144,5 +144,5 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
return OK;
}
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */
#endif /* CONFIG_DEBUG_GPIO_INFO */

242
arch/arm/src/stm32f7/stm32_ethernet.c
View file

@ -66,11 +66,11 @@
#include <arch/board/board.h>
/* STM32_NETHERNET determines the number of physical interfaces that can
* be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if
* be supported by the hardware. CONFIG_STM32_ETHMAC will defined if
* any STM32F7 Ethernet support is enabled in the configuration.
*/
#if STM32_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC)
#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC)
/****************************************************************************
* Pre-processor Definitions
@ -101,76 +101,76 @@
#define ETHWORK LPWORK
#ifndef CONFIG_STM32F7_PHYADDR
# error "CONFIG_STM32F7_PHYADDR must be defined in the NuttX configuration"
#ifndef CONFIG_STM32_PHYADDR
# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration"
#endif
#if !defined(CONFIG_STM32F7_MII) && !defined(CONFIG_STM32F7_RMII)
# warning "Neither CONFIG_STM32F7_MII nor CONFIG_STM32F7_RMII defined"
#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII)
# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined"
#endif
#if defined(CONFIG_STM32F7_MII) && defined(CONFIG_STM32F7_RMII)
# error "Both CONFIG_STM32F7_MII and CONFIG_STM32F7_RMII defined"
#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII)
# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined"
#endif
#ifdef CONFIG_STM32F7_MII
# if !defined(CONFIG_STM32F7_MII_MCO1) && !defined(CONFIG_STM32F7_MII_MCO2) && \
!defined(CONFIG_STM32F7_MII_EXTCLK)
# warning "Neither CONFIG_STM32F7_MII_MCO1, CONFIG_STM32F7_MII_MCO2, nor CONFIG_STM32F7_MII_EXTCLK defined"
#ifdef CONFIG_STM32_MII
# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \
!defined(CONFIG_STM32_MII_EXTCLK)
# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined"
# endif
# if defined(CONFIG_STM32F7_MII_MCO1) && defined(CONFIG_STM32F7_MII_MCO2)
# error "Both CONFIG_STM32F7_MII_MCO1 and CONFIG_STM32F7_MII_MCO2 defined"
# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2)
# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined"
# endif
#endif
#ifdef CONFIG_STM32F7_RMII
# if !defined(CONFIG_STM32F7_RMII_MCO1) && !defined(CONFIG_STM32F7_RMII_MCO2) && \
!defined(CONFIG_STM32F7_RMII_EXTCLK)
# warning "Neither CONFIG_STM32F7_RMII_MCO1, CONFIG_STM32F7_RMII_MCO2, nor CONFIG_STM32F7_RMII_EXTCLK defined"
#ifdef CONFIG_STM32_RMII
# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \
!defined(CONFIG_STM32_RMII_EXTCLK)
# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined"
# endif
# if defined(CONFIG_STM32F7_RMII_MCO1) && defined(CONFIG_STM32F7_RMII_MCO2)
# error "Both CONFIG_STM32F7_RMII_MCO1 and CONFIG_STM32F7_RMII_MCO2 defined"
# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2)
# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined"
# endif
#endif
#ifdef CONFIG_STM32F7_AUTONEG
# ifndef CONFIG_STM32F7_PHYSR
# error "CONFIG_STM32F7_PHYSR must be defined in the NuttX configuration"
#ifdef CONFIG_STM32_AUTONEG
# ifndef CONFIG_STM32_PHYSR
# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration"
# endif
# ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG
# ifndef CONFIG_STM32F7_PHYSR_ALTMODE
# error "CONFIG_STM32F7_PHYSR_ALTMODE must be defined in the NuttX configuration"
# ifdef CONFIG_STM32_PHYSR_ALTCONFIG
# ifndef CONFIG_STM32_PHYSR_ALTMODE
# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_10HD
# error "CONFIG_STM32F7_PHYSR_10HD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_10HD
# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_100HD
# error "CONFIG_STM32F7_PHYSR_100HD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_100HD
# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_10FD
# error "CONFIG_STM32F7_PHYSR_10FD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_10FD
# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_100FD
# error "CONFIG_STM32F7_PHYSR_100FD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_100FD
# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration"
# endif
# else
# ifndef CONFIG_STM32F7_PHYSR_SPEED
# error "CONFIG_STM32F7_PHYSR_SPEED must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_SPEED
# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_100MBPS
# error "CONFIG_STM32F7_PHYSR_100MBPS must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_100MBPS
# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_MODE
# error "CONFIG_STM32F7_PHYSR_MODE must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_MODE
# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32F7_PHYSR_FULLDUPLEX
# error "CONFIG_STM32F7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX
# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# endif
# endif
#endif
#ifdef CONFIG_STM32F7_ETH_PTP
# warning "CONFIG_STM32F7_ETH_PTP is not yet supported"
#ifdef CONFIG_STM32_ETH_PTP
# warning "CONFIG_STM32_ETH_PTP is not yet supported"
#endif
/* This driver does not use enhanced descriptors. Enhanced descriptors must
@ -178,8 +178,8 @@
* supported.
*/
#undef CONFIG_STM32F7_ETH_ENHANCEDDESC
#undef CONFIG_STM32F7_ETH_HWCHECKSUM
#undef CONFIG_STM32_ETH_ENHANCEDDESC
#undef CONFIG_STM32_ETH_HWCHECKSUM
/* Add 4 to the configured buffer size to account for the 2 byte checksum
* memory needed at the end of the maximum size packet. Buffer sizes must
@ -207,16 +207,16 @@
# warning "You using an incomplete/untested configuration"
#endif
#ifndef CONFIG_STM32F7_ETH_NRXDESC
# define CONFIG_STM32F7_ETH_NRXDESC 8
#ifndef CONFIG_STM32_ETH_NRXDESC
# define CONFIG_STM32_ETH_NRXDESC 8
#endif
#ifndef CONFIG_STM32F7_ETH_NTXDESC
# define CONFIG_STM32F7_ETH_NTXDESC 4
#ifndef CONFIG_STM32_ETH_NTXDESC
# define CONFIG_STM32_ETH_NTXDESC 4
#endif
/* We need at least one more free buffer than transmit buffers */
#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32F7_ETH_NTXDESC+1)
#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1)
/* Buffers use for DMA access must begin on an address aligned with the
* D-Cache line and must be an even multiple of the D-Cache line size.
@ -231,7 +231,7 @@
#define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK)
#define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK)
#ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC
#ifndef CONFIG_STM32_ETH_ENHANCEDDESC
# define RXDESC_SIZE 16
# define TXDESC_SIZE 16
#else
@ -243,10 +243,10 @@
#define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE)
#define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE)
#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC)
#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC)
#define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE)
#define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE)
@ -257,7 +257,7 @@
*/
#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_STM32F7_ETHMAC_REGDEBUG
# undef CONFIG_STM32_ETHMAC_REGDEBUG
#endif
/* Clocking *****************************************************************/
@ -338,7 +338,7 @@
* ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled)
* ETH_MACCR_RD Retry disable 1 (disabled)
* ETH_MACCR_IPCO IPv4 checksum offload Depends on
* CONFIG_STM32F7_ETH_HWCHECKSUM
* CONFIG_STM32_ETH_HWCHECKSUM
* ETH_MACCR_LM Loopback mode 0 (disabled)
* ETH_MACCR_ROD Receive own disable 0 (enabled)
* ETH_MACCR_CSD Carrier sense disable 0 (enabled)
@ -353,7 +353,7 @@
* ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100
*/
#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
# define MACCR_SET_BITS \
(ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96))
#else
@ -471,13 +471,13 @@
* ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes)
* ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush)
* ETH_DMAOMR_TSF Transmit store and forward Depends on
* CONFIG_STM32F7_ETH_HWCHECKSUM
* CONFIG_STM32_ETH_HWCHECKSUM
* ETH_DMAOMR_DFRF Disable flushing of 0 (enabled)
* received frames
* ETH_DMAOMR_RSF Receive store and forward Depends on
* CONFIG_STM32F7_ETH_HWCHECKSUM
* CONFIG_STM32_ETH_HWCHECKSUM
* TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on
* error frames disable CONFIG_STM32F7_ETH_HWCHECKSUM
* error frames disable CONFIG_STM32_ETH_HWCHECKSUM
*
* When the checksum offload feature is enabled, we need to enable the Store
* and Forward mode: the store and forward guarantee that a whole frame is
@ -485,7 +485,7 @@
* checksum is OK the DMA can handle the frame otherwise the frame is dropped
*/
#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
# define DMAOMR_SET_MASK \
(ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \
ETH_DMAOMR_TSF | ETH_DMAOMR_RSF)
@ -525,7 +525,7 @@
* ETH_DMABMR_DA DMA Arbitration 0 (round robin)
* ETH_DMABMR_DSL Descriptor skip length 0
* ETH_DMABMR_EDFE Enhanced descriptor Depends on
* format enable CONFIG_STM32F7_ETH_ENHANCEDDESC
* format enable CONFIG_STM32_ETH_ENHANCEDDESC
* ETH_DMABMR_PBL Programmable burst length 32 beats
* ETH_DMABMR_RTPR RX TX priority ratio 2:1
* ETH_DMABMR_FB Fixed burst 1 (enabled)
@ -536,7 +536,7 @@
* ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only)
*/
#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC
#ifdef CONFIG_STM32_ETH_ENHANCEDDESC
# define DMABMR_SET_MASK \
(ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \
ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB)
@ -667,7 +667,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET];
/* Register operations ******************************************************/
#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint32_t val, uint32_t addr);
static void stm32_checksetup(void);
@ -754,10 +754,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv);
/* MAC/DMA Initialization */
#ifdef CONFIG_STM32F7_MII
#ifdef CONFIG_STM32_MII
static inline void stm32_selectmii(void);
#endif
#ifdef CONFIG_STM32F7_RMII
#ifdef CONFIG_STM32_RMII
static inline void stm32_selectrmii(void);
#endif
static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv);
@ -787,7 +787,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv);
*
****************************************************************************/
#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -859,7 +859,7 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
@ -886,7 +886,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_checksetup(void)
{
}
@ -1210,7 +1210,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* un-stoppable transmit events.
*/
if (priv->inflight >= CONFIG_STM32F7_ETH_NTXDESC)
if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC)
{
stm32_disableint(priv, ETH_DMAINT_RI);
}
@ -1284,7 +1284,7 @@ static int stm32_txpoll(struct net_driver_s *dev)
* In a race condition, ETH_TDES0_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC).
* nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 ||
@ -1353,7 +1353,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv)
* In a race condition, ETH_TDES0_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC).
* nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC).
*/
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 &&
@ -1582,8 +1582,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
for (i = 0;
(rxdesc->rdes0 & ETH_RDES0_OWN) == 0 &&
i < CONFIG_STM32F7_ETH_NRXDESC &&
priv->inflight < CONFIG_STM32F7_ETH_NTXDESC;
i < CONFIG_STM32_ETH_NRXDESC &&
priv->inflight < CONFIG_STM32_ETH_NTXDESC;
i++)
{
/* Check if this is the first segment in the frame */
@ -2657,7 +2657,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
/* Initialize each TX descriptor */
for (i = 0; i < CONFIG_STM32F7_ETH_NTXDESC; i++)
for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++)
{
txdesc = &txtable[i].txdesc;
@ -2681,7 +2681,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
* the Next Descriptor Polling Enable
*/
if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1))
if (i < (CONFIG_STM32_ETH_NTXDESC - 1))
{
/* Set next descriptor address register with next descriptor base
* address
@ -2751,7 +2751,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
/* Initialize each RX descriptor */
for (i = 0; i < CONFIG_STM32F7_ETH_NRXDESC; i++)
for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++)
{
rxdesc = &rxtable[i].rxdesc;
@ -2773,7 +2773,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
* the Next Descriptor Polling Enable
*/
if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1))
if (i < (CONFIG_STM32_ETH_NRXDESC - 1))
{
/* Set next descriptor address register with next descriptor base
* address
@ -2863,7 +2863,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = CONFIG_STM32F7_PHYADDR;
req->phy_id = CONFIG_STM32_PHYADDR;
ret = OK;
}
break;
@ -3070,7 +3070,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
* indication that check if the DM9161 PHY CHIP is not ready.
*/
ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_PHYID1, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY ID1: %d\n", ret);
@ -3090,7 +3090,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
/* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */
ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, 16, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret);
@ -3128,7 +3128,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
static int stm32_phyinit(struct stm32_ethmac_s *priv)
{
#ifdef CONFIG_STM32F7_AUTONEG
#ifdef CONFIG_STM32_AUTONEG
volatile uint32_t timeout;
#endif
uint32_t regval;
@ -3149,7 +3149,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Put the PHY in reset mode */
ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_RESET);
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
nerr("ERROR: Failed to reset the PHY: %d\n", ret);
@ -3160,7 +3160,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Perform any necessary, board-specific PHY initialization */
#ifdef CONFIG_STM32F7_PHYINIT
#ifdef CONFIG_STM32_PHYINIT
ret = stm32_phy_boardinitialize(0);
if (ret < 0)
{
@ -3181,12 +3181,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Perform auto-negotiation if so configured */
#ifdef CONFIG_STM32F7_AUTONEG
#ifdef CONFIG_STM32_AUTONEG
/* Wait for link status */
for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
{
ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
@ -3208,7 +3208,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Enable auto-negotiation */
ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE);
if (ret < 0)
{
nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret);
@ -3219,7 +3219,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
{
ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
@ -3241,7 +3241,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Read the result of the auto-negotiation from the PHY-specific register */
ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, CONFIG_STM32F7_PHYSR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read PHY status register\n");
@ -3250,38 +3250,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Remember the selected speed and duplex modes */
ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32F7_PHYSR, phyval);
ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval);
/* Different PHYs present speed and mode information in different ways.
* IF This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that
* IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that
* the PHY represents speed and mode information are combined, for example,
* with separate bits for 10HD, 100HD, 10FD and 100FD.
*/
#ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG
switch (phyval & CONFIG_STM32F7_PHYSR_ALTMODE)
#ifdef CONFIG_STM32_PHYSR_ALTCONFIG
switch (phyval & CONFIG_STM32_PHYSR_ALTMODE)
{
default:
nerr("ERROR: Unrecognized PHY status setting\n");
/* Falls through */
case CONFIG_STM32F7_PHYSR_10HD:
case CONFIG_STM32_PHYSR_10HD:
priv->fduplex = 0;
priv->mbps100 = 0;
break;
case CONFIG_STM32F7_PHYSR_100HD:
case CONFIG_STM32_PHYSR_100HD:
priv->fduplex = 0;
priv->mbps100 = 1;
break;
case CONFIG_STM32F7_PHYSR_10FD:
case CONFIG_STM32_PHYSR_10FD:
priv->fduplex = 1;
priv->mbps100 = 0;
break;
case CONFIG_STM32F7_PHYSR_100FD:
case CONFIG_STM32_PHYSR_100FD:
priv->fduplex = 1;
priv->mbps100 = 1;
break;
@ -3294,13 +3294,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
*/
#else
if ((phyval & CONFIG_STM32F7_PHYSR_MODE) ==
CONFIG_STM32F7_PHYSR_FULLDUPLEX)
if ((phyval & CONFIG_STM32_PHYSR_MODE) ==
CONFIG_STM32_PHYSR_FULLDUPLEX)
{
priv->fduplex = 1;
}
if ((phyval & CONFIG_STM32F7_PHYSR_SPEED) == CONFIG_STM32F7_PHYSR_100MBPS)
if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS)
{
priv->mbps100 = 1;
}
@ -3309,14 +3309,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
#else /* Auto-negotiation not selected */
phyval = 0;
#ifdef CONFIG_STM32F7_ETHFD
#ifdef CONFIG_STM32_ETHFD
phyval |= MII_MCR_FULLDPLX;
#endif
#ifdef CONFIG_STM32F7_ETH100MBPS
#ifdef CONFIG_STM32_ETH100MBPS
phyval |= MII_MCR_SPEED100;
#endif
ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, phyval);
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval);
if (ret < 0)
{
nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
@ -3327,10 +3327,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Remember the selected speed and duplex modes */
#ifdef CONFIG_STM32F7_ETHFD
#ifdef CONFIG_STM32_ETHFD
priv->fduplex = 1;
#endif
#ifdef CONFIG_STM32F7_ETH100MBPS
#ifdef CONFIG_STM32_ETH100MBPS
priv->mbps100 = 1;
#endif
#endif
@ -3356,7 +3356,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_MII
#ifdef CONFIG_STM32_MII
static inline void stm32_selectmii(void)
{
uint32_t regval;
@ -3381,7 +3381,7 @@ static inline void stm32_selectmii(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_RMII
#ifdef CONFIG_STM32_RMII
static inline void stm32_selectrmii(void)
{
uint32_t regval;
@ -3412,7 +3412,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
{
/* Configure GPIO pins to support Ethernet */
#if defined(CONFIG_STM32F7_MII) || defined(CONFIG_STM32F7_RMII)
#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII)
/* MDC and MDIO are common to both modes */
@ -3421,7 +3421,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the MII interface */
# if defined(CONFIG_STM32F7_MII)
# if defined(CONFIG_STM32_MII)
/* Select the MII interface */
@ -3436,7 +3436,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_STM32F7_MII_MCO1)
# if defined(CONFIG_STM32_MII_MCO1)
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
* info.
*/
@ -3444,7 +3444,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO1);
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
# elif defined(CONFIG_STM32F7_MII_MCO2)
# elif defined(CONFIG_STM32_MII_MCO2)
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
* info.
*/
@ -3452,7 +3452,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO2);
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
# elif defined(CONFIG_STM32F7_MII_MCO)
# elif defined(CONFIG_STM32_MII_MCO)
/* Setup MCO pin for alternative usage */
stm32_configgpio(GPIO_MCO);
@ -3483,7 +3483,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the RMII interface. */
# elif defined(CONFIG_STM32F7_RMII)
# elif defined(CONFIG_STM32_RMII)
/* Select the RMII interface */
@ -3498,7 +3498,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_STM32F7_RMII_MCO1)
# if defined(CONFIG_STM32_RMII_MCO1)
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
* info.
*/
@ -3506,7 +3506,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO1);
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
# elif defined(CONFIG_STM32F7_RMII_MCO2)
# elif defined(CONFIG_STM32_RMII_MCO2)
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
* info.
*/
@ -3514,7 +3514,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO2);
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
# elif defined(CONFIG_STM32F7_RMII_MCO)
# elif defined(CONFIG_STM32_RMII_MCO)
/* Setup MCO pin for alternative usage */
stm32_configgpio(GPIO_MCO);
@ -3538,7 +3538,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
# endif
#endif
#ifdef CONFIG_STM32F7_ETH_PTP
#ifdef CONFIG_STM32_ETH_PTP
/* Enable pulse-per-second (PPS) output signal */
stm32_configgpio(GPIO_ETH_PPS_OUT);
@ -3861,12 +3861,12 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
/* Initialize TX Descriptors list: Chain Mode */
stm32_txdescinit(priv,
&g_txtable[priv->intf * CONFIG_STM32F7_ETH_NTXDESC]);
&g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]);
/* Initialize RX Descriptors list: Chain Mode */
stm32_rxdescinit(priv,
&g_rxtable[priv->intf * CONFIG_STM32F7_ETH_NRXDESC],
&g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC],
&g_rxbuffer[priv->intf * RXBUFFER_SIZE]);
/* Enable normal MAC operation */
@ -3995,4 +3995,4 @@ void arm_netinitialize(void)
}
#endif
#endif /* STM32_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */
#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */

4
arch/arm/src/stm32f7/stm32_ethernet.h
View file

@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf);
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_STM32F7_PHYINIT is defined in the
* the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the
* configuration then the board specific logic must provide
* stm32_phyinitialize(); The STM32 Ethernet driver will call this
* function one time before it first uses the PHY.
@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf);
*
****************************************************************************/
#ifdef CONFIG_STM32F7_PHYINIT
#ifdef CONFIG_STM32_PHYINIT
int stm32_phy_boardinitialize(int intf);
#endif

8
arch/arm/src/stm32f7/stm32_exti_gpio.c
View file

@ -44,9 +44,9 @@
* families
*/
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \
|| defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \
|| defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Private Types
@ -376,4 +376,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
return OK;
}
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */

4
arch/arm/src/stm32f7/stm32_fmc.c
View file

@ -26,7 +26,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_FMC)
#if defined(CONFIG_STM32_FMC)
#include <assert.h>
#include <nuttx/debug.h>
@ -234,4 +234,4 @@ void stm32_fmc_sdram_command(uint32_t cmd)
putreg32(val, STM32_FMC_SDCMR);
}
#endif /* CONFIG_STM32F7_FMC */
#endif /* CONFIG_STM32_FMC */

156
arch/arm/src/stm32f7/stm32_foc.c
View file

@ -89,22 +89,22 @@
/* PWM lower-half ops and ADC lower-half ops must be enabled */
#ifndef CONFIG_STM32F7_PWM_LL_OPS
#ifndef CONFIG_STM32_PWM_LL_OPS
# error PWM low-level operations interface must be enabled
#endif
#ifndef CONFIG_STM32F7_ADC_LL_OPS
#ifndef CONFIG_STM32_ADC_LL_OPS
# error ADC low-level operations interface must be enabled
#endif
/* We don't want start conversion during ADC setup */
#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV
#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV
# error ADC startup conversion must be disabled
#endif
/* We need interface to change ADC sample-time */
#ifndef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME
#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
# error ADC sample-time configuration interface must be enabled
#endif
@ -114,35 +114,35 @@
/* FOC0 always use TIMER1 for PWM */
#ifdef CONFIG_STM32F7_FOC_FOC0
#ifdef CONFIG_STM32_FOC_FOC0
# define FOC0_PWM (1)
# define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS)
# define FOC0_PWM_BASE (STM32_TIM1_BASE)
# define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP)
# if CONFIG_STM32F7_TIM1_MODE != 2
# if CONFIG_STM32_TIM1_MODE != 2
# error TIM1 must be configured in center-aligned mode 1
# endif
#endif /* CONFIG_STM32F7_FOC_FOC0 */
#endif /* CONFIG_STM32_FOC_FOC0 */
/* FOC1 always use TIMER8 for PWM */
#ifdef CONFIG_STM32F7_FOC_FOC1
#ifdef CONFIG_STM32_FOC_FOC1
# define FOC1_PWM (8)
# define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS)
# define FOC1_PWM_BASE (STM32_TIM8_BASE)
# define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP)
# if CONFIG_STM32F7_TIM8_MODE != 2
# if CONFIG_STM32_TIM8_MODE != 2
# error TIM8 must be configured in center-aligned mode 1
# endif
#endif
/* The maximum supported number of phases depends on the ADC trigger */
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
# if CONFIG_MOTOR_FOC_PHASES > 3
# error max 3 phases supported
# endif
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
# if CONFIG_MOTOR_FOC_PHASES > 4
# error max 4 phases supported
# endif
@ -158,7 +158,7 @@
/* Only one ADC trigger must be selected */
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) && defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO)
# error Invalid ADC trigger configuration
#endif
@ -174,7 +174,7 @@
* V0 for CNTR = 0
*/
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
/* FOC ADC trigger on CCR4 **************************************************/
@ -183,12 +183,12 @@
* - 1 channel for ADC injection sequence trigger (CCR4)
*/
# if defined(CONFIG_STM32F7_FOC_FOC0)
# if defined(CONFIG_STM32_FOC_FOC0)
# if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1)
# error Invalid channels configuration
# endif
# endif
# if defined(CONFIG_STM32F7_FOC_FOC1)
# if defined(CONFIG_STM32_FOC_FOC1)
# if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1)
# error Invalid channels configuration
# endif
@ -202,10 +202,10 @@
* TIMx CCR4 = (ARR - trigger_offset)
*/
#ifdef CONFIG_STM32F7_FOC_USE_TIM1
#ifdef CONFIG_STM32_FOC_USE_TIM1
# define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4)
#endif
#ifdef CONFIG_STM32F7_FOC_USE_TIM8
#ifdef CONFIG_STM32_FOC_USE_TIM8
# define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4)
#endif
@ -213,20 +213,20 @@
# define ADC_TRIGGER_OFFSET (1)
# ifdef CONFIG_STM32F7_FOC_FOC0
# ifdef CONFIG_STM32_FOC_FOC0
# define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4)
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1
# ifdef CONFIG_STM32_FOC_FOC1
# define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4)
# endif
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
/* FOC ADC trigger on TRGO **************************************************/
/* PWM TRGO support must be enabled */
# ifndef CONFIG_STM32F7_PWM_TRGO
# ifndef CONFIG_STM32_PWM_TRGO
# error PWM TRGO support must be enabled
# endif
@ -238,12 +238,12 @@
* - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4)
*/
# if defined(CONFIG_STM32F7_FOC_FOC0)
# if defined(CONFIG_STM32_FOC_FOC0)
# if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES)
# error Invalid channels configuration
# endif
# endif
# if defined(CONFIG_STM32F7_FOC_FOC1)
# if defined(CONFIG_STM32_FOC_FOC1)
# if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES)
# error Invalid channels configuration
# endif
@ -257,17 +257,17 @@
* TIMx TRGO = (ARR)
*/
#ifdef CONFIG_STM32F7_FOC_USE_TIM1
#ifdef CONFIG_STM32_FOC_USE_TIM1
# define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO)
#endif
#ifdef CONFIG_STM32F7_FOC_USE_TIM8
#ifdef CONFIG_STM32_FOC_USE_TIM8
# error TIM8 and TRGO trigger not supported for ADC IPv1
#endif
# ifdef CONFIG_STM32F7_FOC_FOC0
# ifdef CONFIG_STM32_FOC_FOC0
# define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO)
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1
# ifdef CONFIG_STM32_FOC_FOC1
# define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO)
# endif
@ -280,28 +280,28 @@
/* Phase current samples for FOC0 */
#ifdef CONFIG_STM32F7_FOC_FOC0
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1
#ifdef CONFIG_STM32_FOC_FOC0
# ifdef CONFIG_STM32_FOC_FOC0_ADC1
# define FOC0_ADC 1
# endif
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2
# ifdef CONFIG_STM32_FOC_FOC0_ADC2
# define FOC0_ADC 2
# endif
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3
# ifdef CONFIG_STM32_FOC_FOC0_ADC3
# define FOC0_ADC 3
# endif
#endif
/* Phase current samples for FOC1 */
#ifdef CONFIG_STM32F7_FOC_FOC1
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1
#ifdef CONFIG_STM32_FOC_FOC1
# ifdef CONFIG_STM32_FOC_FOC1_ADC1
# define FOC1_ADC 1
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2
# ifdef CONFIG_STM32_FOC_FOC1_ADC2
# define FOC1_ADC 2
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3
# ifdef CONFIG_STM32_FOC_FOC1_ADC3
# define FOC1_ADC 3
# endif
#endif
@ -316,55 +316,55 @@
* 3. ADC software trigger starts only regular conversion.
*/
#ifdef CONFIG_STM32F7_FOC_USE_ADC1
# ifndef CONFIG_STM32F7_ADC1
#ifdef CONFIG_STM32_FOC_USE_ADC1
# ifndef CONFIG_STM32_ADC1
# error ADC1 not supported !
# endif
# ifndef ADC1_HAVE_JEXTCFG
# error ADC1 must support JEXTCFG
# endif
# if CONFIG_STM32F7_ADC1_ANIOC_TRIGGER != 1
# error CONFIG_STM32F7_ADC1_ANIOC_TRIGGER must be 1
# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1
# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1
# endif
# if CONFIG_STM32F7_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED
# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED
# error Invalid configuration for ADC1 injected channels
# endif
#endif
#ifdef CONFIG_STM32F7_FOC_USE_ADC2
# ifndef CONFIG_STM32F7_ADC2
#ifdef CONFIG_STM32_FOC_USE_ADC2
# ifndef CONFIG_STM32_ADC2
# error ADC2 not supported !
# endif
# ifndef ADC2_HAVE_JEXTCFG
# error ADC2 must support JEXTCFG
# endif
# if CONFIG_STM32F7_ADC2_ANIOC_TRIGGER != 1
# error CONFIG_STM32F7_ADC2_ANIOC_TRIGGER must be 1
# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1
# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1
# endif
# if CONFIG_STM32F7_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED
# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED
# error Invalid configuration for ADC2 injected channels
# endif
#endif
#ifdef CONFIG_STM32F7_FOC_USE_ADC3
# ifndef CONFIG_STM32F7_ADC3
#ifdef CONFIG_STM32_FOC_USE_ADC3
# ifndef CONFIG_STM32_ADC3
# error ADC3 not supported !
# endif
# ifndef ADC3_HAVE_JEXTCFG
# error ADC3 must support JEXTCFG
# endif
# if CONFIG_STM32F7_ADC3_ANIOC_TRIGGER != 1
# error CONFIG_STM32F7_ADC3_ANIOC_TRIGGER must be 1
# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1
# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1
# endif
# if CONFIG_STM32F7_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED
# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED
# error Invalid configuration for ADC3 injected channels
# endif
#endif
/* Combine JEXTSEL with JEXTEN default */
#ifdef CONFIG_STM32F7_FOC_FOC0
#ifdef CONFIG_STM32_FOC_FOC0
# define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL)
#endif
#ifdef CONFIG_STM32F7_FOC_FOC1
#ifdef CONFIG_STM32_FOC_FOC1
# define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL)
#endif
@ -390,39 +390,39 @@
/* FOC ADC configuration ****************************************************/
#ifdef CONFIG_STM32F7_FOC_FOC0
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1
#ifdef CONFIG_STM32_FOC_FOC0
# ifdef CONFIG_STM32_FOC_FOC0_ADC1
# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC
# define FOC0_ADC_CMN FOC_ADC1_CMN
# endif
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2
# ifdef CONFIG_STM32_FOC_FOC0_ADC2
# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC
# define FOC0_ADC_CMN FOC_ADC2_CMN
# endif
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3
# ifdef CONFIG_STM32_FOC_FOC0_ADC3
# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC
# define FOC0_ADC_CMN FOC_ADC3_CMN
# endif
# ifdef CONFIG_STM32F7_FOC_FOC0_ADC4
# ifdef CONFIG_STM32_FOC_FOC0_ADC4
# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC
# define FOC0_ADC_CMN FOC_ADC4_CMN
# endif
#endif
#ifdef CONFIG_STM32F7_FOC_FOC1
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1
#ifdef CONFIG_STM32_FOC_FOC1
# ifdef CONFIG_STM32_FOC_FOC1_ADC1
# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC
# define FOC1_ADC_CMN FOC_ADC1_CMN
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2
# ifdef CONFIG_STM32_FOC_FOC1_ADC2
# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC
# define FOC1_ADC_CMN FOC_ADC2_CMN
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3
# ifdef CONFIG_STM32_FOC_FOC1_ADC3
# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC
# define FOC1_ADC_CMN FOC_ADC3_CMN
# endif
# ifdef CONFIG_STM32F7_FOC_FOC1_ADC4
# ifdef CONFIG_STM32_FOC_FOC1_ADC4
# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC
# define FOC1_ADC_CMN FOC_ADC4_CMN
# endif
@ -502,7 +502,7 @@
/* Define PWM all outputs */
#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY
#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY
# define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \
STM32_PWM_OUT2N| \
STM32_PWM_OUT3N)
@ -510,7 +510,7 @@
# define PMW_OUTPUTS_ALL_COMP (0)
#endif
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3)
#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3)
# define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4)
#else
# define PMW_OUTPUTS_ALL_OUT4 (0)
@ -683,10 +683,10 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state);
static int stm32_foc_calibration_start(struct foc_dev_s *dev);
static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq);
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev,
uint32_t offset);
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev,
uint8_t rcr);
#else
@ -813,7 +813,7 @@ static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq)
goto errout;
}
#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY
#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY
/* Configure deadtime */
PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt);
@ -1015,7 +1015,7 @@ static int stm32_foc_adc_cfg(struct foc_dev_s *dev)
return OK;
}
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
/****************************************************************************
* Name: stm32_foc_adc_ccr4_trg_set
@ -1047,7 +1047,7 @@ static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev,
PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset);
}
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
/****************************************************************************
* Name: stm32_foc_adc_trgo_trg_set
@ -1140,9 +1140,9 @@ static int stm32_foc_configure(struct foc_dev_s *dev,
DEBUGASSERT(priv->data.per != 0);
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET));
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq /
priv->data.adc_freq) * 2);
#else
@ -1156,7 +1156,7 @@ static int stm32_foc_configure(struct foc_dev_s *dev,
/* REVISIT: synchronise instances if TRGO trigger selected */
#if (CONFIG_MOTOR_FOC_INST > 1)
# if defined(CONFIG_STM32F7_FOC_ADC_TRGO)
# if defined(CONFIG_STM32_FOC_ADC_TRGO)
# error stm32_foc_sync_all breaks TRGO event on V0 vector
# endif
@ -1704,9 +1704,9 @@ static int stm32_foc_calibration_start(struct foc_dev_s *dev)
DEBUGASSERT(priv->data.per != 0);
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET));
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
stm32_foc_adc_trgo_trg_set(dev, 1);
#else
# error Invalid FOC ADC trigger
@ -2039,7 +2039,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq)
goto errout;
}
#if defined(CONFIG_STM32F7_FOC_ADC_CCR4)
#if defined(CONFIG_STM32_FOC_ADC_CCR4)
/* ADC interrupts frequency is PWM frequency */
priv->data.adc_freq = dev->cfg.pwm_freq;
@ -2048,7 +2048,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq)
priv->data.notifier_div = (dev->cfg.pwm_freq / freq);
#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO)
#elif defined(CONFIG_STM32_FOC_ADC_TRGO)
/* Call work on every ADC interrupt */
priv->data.notifier_div = 1;
@ -2250,7 +2250,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board)
switch (inst)
{
#ifdef CONFIG_STM32F7_FOC_FOC0
#ifdef CONFIG_STM32_FOC_FOC0
case 0:
{
pwm_inst = FOC0_PWM;
@ -2264,7 +2264,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board)
}
#endif
#ifdef CONFIG_STM32F7_FOC_FOC1
#ifdef CONFIG_STM32_FOC_FOC1
case 1:
{
pwm_inst = FOC1_PWM;

8
arch/arm/src/stm32f7/stm32_gpio.c
View file

@ -44,9 +44,9 @@
* families
*/
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \
|| defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \
|| defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \
|| defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \
|| defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Private Data
@ -502,4 +502,4 @@ void stm32_iocompensation(void)
}
}
#endif /* CONFIG_STM32F7_STM32F72XX || ... || CONFIG_STM32F7_STM32F77XX */
#endif /* CONFIG_STM32_STM32F72XX || ... || CONFIG_STM32_STM32F77XX */

112
arch/arm/src/stm32f7/stm32_i2c.c
View file

@ -155,34 +155,34 @@
*
* One of:
*
* CONFIG_STM32F7_STM32F72XX
* CONFIG_STM32F7_STM32F73XX
* CONFIG_STM32F7_STM32F74XX
* CONFIG_STM32F7_STM32F75XX
* CONFIG_STM32F7_STM32F76XX
* CONFIG_STM32F7_STM32F77XX
* CONFIG_STM32_STM32F72XX
* CONFIG_STM32_STM32F73XX
* CONFIG_STM32_STM32F74XX
* CONFIG_STM32_STM32F75XX
* CONFIG_STM32_STM32F76XX
* CONFIG_STM32_STM32F77XX
*
*
* and one or more interfaces:
*
* CONFIG_STM32F7_I2C1
* CONFIG_STM32F7_I2C2
* CONFIG_STM32F7_I2C3
* CONFIG_STM32F7_I2C4
* CONFIG_STM32_I2C1
* CONFIG_STM32_I2C2
* CONFIG_STM32_I2C3
* CONFIG_STM32_I2C4
*
* To configure the ISR timeout using fixed values
* (CONFIG_STM32F7_I2C_DYNTIMEO=n):
* (CONFIG_STM32_I2C_DYNTIMEO=n):
*
* CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks)
* CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks)
*
* To configure the ISR timeout using dynamic values
* (CONFIG_STM32F7_I2C_DYNTIMEO=y):
* (CONFIG_STM32_I2C_DYNTIMEO=y):
*
* CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE
* CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE
* (Timeout in microseconds per byte)
* CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP
* CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
* (Timeout for start/stop in milliseconds)
*
* Debugging output enabled with:
@ -256,8 +256,8 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \
defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4)
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4)
/****************************************************************************
* Pre-processor Definitions
@ -265,25 +265,25 @@
#undef INVALID_CLOCK_SOURCE
#ifdef CONFIG_STM32F7_I2C1
#ifdef CONFIG_STM32_I2C1
# if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI
# warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI"
# define INVALID_CLOCK_SOURCE
# endif
#endif
#ifdef CONFIG_STM32F7_I2C2
#ifdef CONFIG_STM32_I2C2
# if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI
# warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI"
# define INVALID_CLOCK_SOURCE
# endif
#endif
#ifdef CONFIG_STM32F7_I2C3
#ifdef CONFIG_STM32_I2C3
# if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI
# warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI"
# define INVALID_CLOCK_SOURCE
# endif
#endif
#ifdef CONFIG_STM32F7_I2C4
#ifdef CONFIG_STM32_I2C4
# if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI
# warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI"
# define INVALID_CLOCK_SOURCE
@ -300,25 +300,25 @@
/* Interrupt wait timeout in seconds and milliseconds */
#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS)
# define CONFIG_STM32F7_I2CTIMEOSEC 0
# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */
#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOSEC 0
# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */
# warning "Using Default 500 Ms Timeout"
#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC)
# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32F7_I2CTIMEOMS)
# define CONFIG_STM32F7_I2CTIMEOMS 0 /* User provided seconds */
#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */
#endif
/* Interrupt wait time timeout in system timer ticks */
#ifndef CONFIG_STM32F7_I2CTIMEOTICKS
# define CONFIG_STM32F7_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32F7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F7_I2CTIMEOMS))
#ifndef CONFIG_STM32_I2CTIMEOTICKS
# define CONFIG_STM32_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
#endif
#ifndef CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS)
#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
#endif
/* Macros to convert a I2C pin to a GPIO output */
@ -482,9 +482,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv,
static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */
#endif /* CONFIG_STM32_I2C_DYNTIMEO */
static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv);
#ifdef CONFIG_I2C_TRACE
@ -534,7 +534,7 @@ static const struct i2c_ops_s stm32_i2c_ops =
#endif
};
#ifdef CONFIG_STM32F7_I2C1
#ifdef CONFIG_STM32_I2C1
static const struct stm32_i2c_config_s stm32_i2c1_config =
{
.base = STM32_I2C1_BASE,
@ -571,7 +571,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
};
#endif
#ifdef CONFIG_STM32F7_I2C2
#ifdef CONFIG_STM32_I2C2
static const struct stm32_i2c_config_s stm32_i2c2_config =
{
.base = STM32_I2C2_BASE,
@ -608,7 +608,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
};
#endif
#ifdef CONFIG_STM32F7_I2C3
#ifdef CONFIG_STM32_I2C3
static const struct stm32_i2c_config_s stm32_i2c3_config =
{
.base = STM32_I2C3_BASE,
@ -645,7 +645,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
};
#endif
#ifdef CONFIG_STM32F7_I2C4
#ifdef CONFIG_STM32_I2C4
static const struct stm32_i2c_config_s stm32_i2c4_config =
{
.base = STM32_I2C4_BASE,
@ -766,7 +766,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
{
size_t bytecount = 0;
@ -783,7 +783,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
* factor.
*/
return USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE * bytecount);
return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
}
#endif
@ -839,12 +839,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
{
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
stm32_i2c_toticks(priv->msgc, priv->msgv));
#else
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
CONFIG_STM32F7_I2CTIMEOTICKS);
CONFIG_STM32_I2CTIMEOTICKS);
#endif
if (ret < 0)
{
@ -882,10 +882,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
/* Get the timeout value */
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = stm32_i2c_toticks(priv->msgc, priv->msgv);
#else
timeout = CONFIG_STM32F7_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
@ -1023,10 +1023,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv)
/* Select a timeout */
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP);
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
#else
timeout = CONFIG_STM32F7_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Wait as stop might still be in progress */
@ -2740,22 +2740,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port)
switch (port)
{
#ifdef CONFIG_STM32F7_I2C1
#ifdef CONFIG_STM32_I2C1
case 1:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
break;
#endif
#ifdef CONFIG_STM32F7_I2C2
#ifdef CONFIG_STM32_I2C2
case 2:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
break;
#endif
#ifdef CONFIG_STM32F7_I2C3
#ifdef CONFIG_STM32_I2C3
case 3:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
break;
#endif
#ifdef CONFIG_STM32F7_I2C4
#ifdef CONFIG_STM32_I2C4
case 4:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
break;
@ -2827,5 +2827,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || \
* CONFIG_STM32F7_I2C3 || CONFIG_STM32F7_I2C4 */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \
* CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */

8
arch/arm/src/stm32f7/stm32_i2c.h
View file

@ -41,10 +41,10 @@
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32F7_I2C_DYNTIMEO
# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32F7_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32_I2C_DYNTIMEO
# endif
#endif

178
arch/arm/src/stm32f7/stm32_i2s.c
View file

@ -76,7 +76,7 @@
#include "stm32_spi.h"
#include "stm32_rcc.h"
#if defined(CONFIG_STM32F7_I2S1) || defined(CONFIG_STM32F7_I2S2) || defined(CONFIG_STM32F7_I2S3)
#if defined(CONFIG_STM32_I2S1) || defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3)
/****************************************************************************
* Pre-processor Definitions
@ -92,8 +92,8 @@
# error CONFIG_AUDIO required by this driver
#endif
#ifndef CONFIG_STM32F7_I2S_MAXINFLIGHT
# define CONFIG_STM32F7_I2S_MAXINFLIGHT 16
#ifndef CONFIG_STM32_I2S_MAXINFLIGHT
# define CONFIG_STM32_I2S_MAXINFLIGHT 16
#endif
/* Assume no RX/TX support until we learn better */
@ -103,28 +103,28 @@
/* Check for I2S RX support */
# if defined(CONFIG_STM32F7_I2S1_RX)
# if defined(CONFIG_STM32_I2S1_RX)
# define I2S_HAVE_RX 1
# ifdef CONFIG_STM32F7_I2S1_MCK
# ifdef CONFIG_STM32_I2S1_MCK
# define I2S_HAVE_MCK 1
# endif
# endif
# if defined(CONFIG_STM32F7_I2S2_RX)
# if defined(CONFIG_STM32_I2S2_RX)
# define I2S_HAVE_RX 1
# ifdef CONFIG_STM32F7_I2S2_MCK
# ifdef CONFIG_STM32_I2S2_MCK
# define I2S_HAVE_MCK 1
# endif
# endif
# if defined(CONFIG_STM32F7_I2S3_RX)
# if defined(CONFIG_STM32_I2S3_RX)
# define I2S_HAVE_RX 1
# ifdef CONFIG_STM32F7_I2S3_MCK
# ifdef CONFIG_STM32_I2S3_MCK
# define I2S_HAVE_MCK 1
# endif
@ -132,28 +132,28 @@
/* Check for I2S3 TX support */
# if defined(CONFIG_STM32F7_I2S1_TX)
# if defined(CONFIG_STM32_I2S1_TX)
# define I2S_HAVE_TX 1
# ifdef CONFIG_STM32F7_I2S1_MCK
# ifdef CONFIG_STM32_I2S1_MCK
# define I2S_HAVE_MCK 1
# endif
# endif
# if defined(CONFIG_STM32F7_I2S2_TX)
# if defined(CONFIG_STM32_I2S2_TX)
# define I2S_HAVE_TX 1
# ifdef CONFIG_STM32F7_I2S2_MCK
# ifdef CONFIG_STM32_I2S2_MCK
# define I2S_HAVE_MCK 1
# endif
# endif
# if defined(CONFIG_STM32F7_I2S3_TX)
# if defined(CONFIG_STM32_I2S3_TX)
# define I2S_HAVE_TX 1
# ifdef CONFIG_STM32F7_I2S3_MCK
# ifdef CONFIG_STM32_I2S3_MCK
# define I2S_HAVE_MCK 1
# endif
@ -163,19 +163,19 @@
/* I2S interrupts */
#ifdef CONFIG_STM32F7_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
# error "Interrupt driven I2S not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA)
#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32F7_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
@ -200,7 +200,7 @@
# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P)
# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P)
#endif /* CONFIG_STM32F7_SPI_DMA */
#endif /* CONFIG_STM32_SPI_DMA */
/* Debug ********************************************************************/
@ -209,8 +209,8 @@
*/
#ifndef CONFIG_DEBUG_I2S_INFO
# undef CONFIG_STM32F7_I2S_DMADEBUG
# undef CONFIG_STM32F7_I2S_REGDEBUG
# undef CONFIG_STM32_I2S_DMADEBUG
# undef CONFIG_STM32_I2S_REGDEBUG
# undef CONFIG_STM32F7_I2S_QDEBUG
# undef CONFIG_STM32F7_I2S_DUMPBUFFERS
#endif
@ -219,46 +219,46 @@
* logic here is constrained to byte, half-word, and word sizes.
*/
#ifndef CONFIG_STM32F7_I2S1_DATALEN
# define CONFIG_STM32F7_I2S1_DATALEN 16
#ifndef CONFIG_STM32_I2S1_DATALEN
# define CONFIG_STM32_I2S1_DATALEN 16
#endif
#ifndef CONFIG_STM32F7_I2S2_DATALEN
# define CONFIG_STM32F7_I2S2_DATALEN 16
#ifndef CONFIG_STM32_I2S2_DATALEN
# define CONFIG_STM32_I2S2_DATALEN 16
#endif
#ifndef CONFIG_STM32F7_I2S3_DATALEN
# define CONFIG_STM32F7_I2S3_DATALEN 16
#ifndef CONFIG_STM32_I2S3_DATALEN
# define CONFIG_STM32_I2S3_DATALEN 16
#endif
#if CONFIG_STM32F7_I2S1_DATALEN == 8
#if CONFIG_STM32_I2S1_DATALEN == 8
# define STM32_I2S1_DATAMASK 0
#elif CONFIG_STM32F7_I2S1_DATALEN == 16
#elif CONFIG_STM32_I2S1_DATALEN == 16
# define STM32_I2S1_DATAMASK 1
#elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16
# error Invalid value for CONFIG_STM32F7_I2S1_DATALEN
#elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16
# error Invalid value for CONFIG_STM32_I2S1_DATALEN
#else
# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN
# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN
#endif
#if CONFIG_STM32F7_I2S2_DATALEN == 8
#if CONFIG_STM32_I2S2_DATALEN == 8
# define STM32_I2S2_DATAMASK 0
#elif CONFIG_STM32F7_I2S2_DATALEN == 16
#elif CONFIG_STM32_I2S2_DATALEN == 16
# define STM32_I2S2_DATAMASK 1
#elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16
# error Invalid value for CONFIG_STM32F7_I2S2_DATALEN
#elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16
# error Invalid value for CONFIG_STM32_I2S2_DATALEN
#else
# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN
# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN
#endif
#if CONFIG_STM32F7_I2S3_DATALEN == 8
#if CONFIG_STM32_I2S3_DATALEN == 8
# define STM32_I2S3_DATAMASK 0
#elif CONFIG_STM32F7_I2S3_DATALEN == 16
#elif CONFIG_STM32_I2S3_DATALEN == 16
# define STM32_I2S3_DATAMASK 1
#elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16
# error Invalid value for CONFIG_STM32F7_I2S3_DATALEN
#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16
# error Invalid value for CONFIG_STM32_I2S3_DATALEN
#else
# error Valid but supported value for CONFIG_STM32F7_I2S3_DATALEN
# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN
#endif
/* Check if we need to build RX and/or TX support */
@ -266,7 +266,7 @@
#if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX)
#ifndef CONFIG_DEBUG_DMA
# undef CONFIG_STM32F7_I2S_DMADEBUG
# undef CONFIG_STM32_I2S_DMADEBUG
#endif
#define DMA_INITIAL 0
@ -309,7 +309,7 @@ struct stm32_transport_s
sq_queue_t done; /* A queue of completed transfers */
struct work_s work; /* Supports worker thread operations */
#ifdef CONFIG_STM32F7_I2S_DMADEBUG
#ifdef CONFIG_STM32_I2S_DMADEBUG
struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES];
#endif
};
@ -344,11 +344,11 @@ struct stm32_i2s_s
sem_t bufsem; /* Buffer wait semaphore */
struct stm32_buffer_s *freelist; /* A list a free buffer containers */
struct stm32_buffer_s containers[CONFIG_STM32F7_I2S_MAXINFLIGHT];
struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT];
/* Debug stuff */
#ifdef CONFIG_STM32F7_I2S_REGDEBUG
#ifdef CONFIG_STM32_I2S_REGDEBUG
bool wr; /* Last was a write */
uint32_t regaddr; /* Last address */
uint16_t regval; /* Last value */
@ -362,7 +362,7 @@ struct stm32_i2s_s
/* Register helpers */
#ifdef CONFIG_STM32F7_I2S_REGDEBUG
#ifdef CONFIG_STM32_I2S_REGDEBUG
static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr,
uint16_t regval, uint32_t regaddr);
#else
@ -397,12 +397,12 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv);
/* DMA support */
#ifdef CONFIG_STM32F7_I2S_DMADEBUG
#ifdef CONFIG_STM32_I2S_DMADEBUG
static void i2s_dma_sampleinit(struct stm32_i2s_s *priv,
struct stm32_transport_s *xpt);
#endif
#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX)
#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX)
# define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i])
# define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx)
static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result);
@ -414,7 +414,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result);
#endif
#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX)
#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX)
# define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i])
# define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx)
static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result);
@ -467,15 +467,15 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv);
static int i2s_dma_allocate(struct stm32_i2s_s *priv);
static void i2s_dma_free(struct stm32_i2s_s *priv);
#ifdef CONFIG_STM32F7_I2S1
#ifdef CONFIG_STM32_I2S1
static void i2s1_configure(struct stm32_i2s_s *priv);
#endif
#ifdef CONFIG_STM32F7_I2S2
#ifdef CONFIG_STM32_I2S2
static void i2s2_configure(struct stm32_i2s_s *priv);
#endif
#ifdef CONFIG_STM32F7_I2S3
#ifdef CONFIG_STM32_I2S3
static void i2s3_configure(struct stm32_i2s_s *priv);
#endif
@ -520,7 +520,7 @@ static const struct i2s_ops_s g_i2sops =
*
****************************************************************************/
#ifdef CONFIG_STM32F7_I2S_REGDEBUG
#ifdef CONFIG_STM32_I2S_REGDEBUG
static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval,
uint32_t regaddr)
{
@ -579,7 +579,7 @@ static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv,
uint32_t regaddr = priv->base + offset;
uint16_t regval = getreg16(regaddr);
#ifdef CONFIG_STM32F7_I2S_REGDEBUG
#ifdef CONFIG_STM32_I2S_REGDEBUG
if (i2s_checkreg(priv, false, regval, regaddr))
{
i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval);
@ -610,7 +610,7 @@ static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset,
{
uint32_t regaddr = priv->base + offset;
#ifdef CONFIG_STM32F7_I2S_REGDEBUG
#ifdef CONFIG_STM32_I2S_REGDEBUG
if (i2s_checkreg(priv, true, regval, regaddr))
{
i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval);
@ -759,9 +759,9 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv)
int i;
priv->freelist = NULL;
nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_I2S_MAXINFLIGHT);
nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT);
for (i = 0; i < CONFIG_STM32F7_I2S_MAXINFLIGHT; i++)
for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++)
{
i2s_buf_free(priv, &priv->containers[i]);
}
@ -771,7 +771,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv)
* Name: i2s_dma_sampleinit
*
* Description:
* Initialize sampling of DMA registers (if CONFIG_STM32F7_I2S_DMADEBUG)
* Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG)
*
* Input Parameters:
* priv - I2S state instance
@ -781,7 +781,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv)
*
****************************************************************************/
#if defined(CONFIG_STM32F7_I2S_DMADEBUG)
#if defined(CONFIG_STM32_I2S_DMADEBUG)
static void i2s_dma_sampleinit(struct stm32_i2s_s *priv,
struct stm32_transport_s *xpt)
{
@ -809,7 +809,7 @@ static void i2s_dma_sampleinit(struct stm32_i2s_s *priv,
*
****************************************************************************/
#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX)
#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX)
static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result)
{
i2sinfo("result: %d\n", result);
@ -875,7 +875,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result)
*
****************************************************************************/
#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX)
#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX)
static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result)
{
i2sinfo("result: %d\n", result);
@ -1145,7 +1145,7 @@ static void i2s_rx_worker(void *arg)
if (sq_empty(&priv->rx.act))
{
#ifdef CONFIG_STM32F7_I2S_DMADEBUG
#ifdef CONFIG_STM32_I2S_DMADEBUG
bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done);
if (bfcontainer)
{
@ -1543,7 +1543,7 @@ static void i2s_tx_worker(void *arg)
if (sq_empty(&priv->tx.act))
{
#ifdef CONFIG_STM32F7_I2S_DMADEBUG
#ifdef CONFIG_STM32_I2S_DMADEBUG
bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done);
if (bfcontainer)
{
@ -2441,7 +2441,7 @@ static void i2s_dma_free(struct stm32_i2s_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_I2S1
#ifdef CONFIG_STM32_I2S1
static void i2s1_configure(struct stm32_i2s_s *priv)
{
/* Configure multiplexed pins as connected on the board. Chip
@ -2450,7 +2450,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv)
priv->base = STM32_I2S1_BASE;
#ifdef CONFIG_STM32F7_I2S1_RX
#ifdef CONFIG_STM32_I2S1_RX
priv->rxenab = true;
if (!priv->initialized)
@ -2463,9 +2463,9 @@ static void i2s1_configure(struct stm32_i2s_s *priv)
stm32_configgpio(GPIO_I2S1_WS);
priv->initialized = true;
}
#endif /* CONFIG_STM32F7_I2S1_RX */
#endif /* CONFIG_STM32_I2S1_RX */
#ifdef CONFIG_STM32F7_I2S1_TX
#ifdef CONFIG_STM32_I2S1_TX
priv->txenab = true;
/* Only configure if the port is not already configured */
@ -2480,16 +2480,16 @@ static void i2s1_configure(struct stm32_i2s_s *priv)
stm32_configgpio(GPIO_I2S1_WS);
priv->initialized = true;
}
#endif /* CONFIG_STM32F7_I2S1_TX */
#endif /* CONFIG_STM32_I2S1_TX */
/* Configure driver state specific to this I2S peripheral */
priv->datalen = CONFIG_STM32F7_I2S1_DATALEN;
priv->datalen = CONFIG_STM32_I2S1_DATALEN;
#ifdef CONFIG_DEBUG
priv->align = STM32_I2S2_DATAMASK;
#endif
}
#endif /* CONFIG_STM32F7_I2S1 */
#endif /* CONFIG_STM32_I2S1 */
/****************************************************************************
* Name: i2s2_configure
@ -2506,7 +2506,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_I2S2
#ifdef CONFIG_STM32_I2S2
static void i2s2_configure(struct stm32_i2s_s *priv)
{
/* Configure multiplexed pins as connected on the board. Chip
@ -2515,7 +2515,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv)
priv->base = STM32_I2S2_BASE;
#ifdef CONFIG_STM32F7_I2S2_RX
#ifdef CONFIG_STM32_I2S2_RX
priv->rxenab = true;
if (!priv->initialized)
@ -2528,9 +2528,9 @@ static void i2s2_configure(struct stm32_i2s_s *priv)
stm32_configgpio(GPIO_I2S2_WS);
priv->initialized = true;
}
#endif /* CONFIG_STM32F7_I2S2_RX */
#endif /* CONFIG_STM32_I2S2_RX */
#ifdef CONFIG_STM32F7_I2S2_TX
#ifdef CONFIG_STM32_I2S2_TX
priv->txenab = true;
/* Only configure if the port is not already configured */
@ -2545,16 +2545,16 @@ static void i2s2_configure(struct stm32_i2s_s *priv)
stm32_configgpio(GPIO_I2S2_WS);
priv->initialized = true;
}
#endif /* CONFIG_STM32F7_I2S2_TX */
#endif /* CONFIG_STM32_I2S2_TX */
/* Configure driver state specific to this I2S peripheral */
priv->datalen = CONFIG_STM32F7_I2S2_DATALEN;
priv->datalen = CONFIG_STM32_I2S2_DATALEN;
#ifdef CONFIG_DEBUG
priv->align = STM32_I2S2_DATAMASK;
#endif
}
#endif /* CONFIG_STM32F7_I2S2 */
#endif /* CONFIG_STM32_I2S2 */
/****************************************************************************
* Name: i2s3_configure
@ -2571,7 +2571,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_I2S3
#ifdef CONFIG_STM32_I2S3
static void i2s3_configure(struct stm32_i2s_s *priv)
{
/* Configure multiplexed pins as connected on the board. Chip
@ -2580,7 +2580,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv)
priv->base = STM32_I2S3_BASE;
#ifdef CONFIG_STM32F7_I2S3_RX
#ifdef CONFIG_STM32_I2S3_RX
priv->rxenab = true;
if (!priv->initialized)
@ -2593,9 +2593,9 @@ static void i2s3_configure(struct stm32_i2s_s *priv)
stm32_configgpio(GPIO_I2S3_WS);
priv->initialized = true;
}
#endif /* CONFIG_STM32F7_I2S3_RX */
#endif /* CONFIG_STM32_I2S3_RX */
#ifdef CONFIG_STM32F7_I2S3_TX
#ifdef CONFIG_STM32_I2S3_TX
priv->txenab = true;
/* Only configure if the port is not already configured */
@ -2610,16 +2610,16 @@ static void i2s3_configure(struct stm32_i2s_s *priv)
stm32_configgpio(GPIO_I2S3_WS);
priv->initialized = true;
}
#endif /* CONFIG_STM32F7_I2S3_TX */
#endif /* CONFIG_STM32_I2S3_TX */
/* Configure driver state specific to this I2S peripheral */
priv->datalen = CONFIG_STM32F7_I2S3_DATALEN;
priv->datalen = CONFIG_STM32_I2S3_DATALEN;
#ifdef CONFIG_DEBUG
priv->align = STM32_I2S3_DATAMASK;
#endif
}
#endif /* CONFIG_STM32F7_I2S3 */
#endif /* CONFIG_STM32_I2S3 */
/****************************************************************************
* Public Functions
@ -2677,7 +2677,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port)
flags = enter_critical_section();
#ifdef CONFIG_STM32F7_I2S1
#ifdef CONFIG_STM32_I2S1
if (port == 1)
{
/* Select I2S1 */
@ -2686,7 +2686,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port)
}
else
#endif
#ifdef CONFIG_STM32F7_I2S2
#ifdef CONFIG_STM32_I2S2
if (port == 2)
{
/* Select I2S2 */
@ -2695,7 +2695,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port)
}
else
#endif
#ifdef CONFIG_STM32F7_I2S3
#ifdef CONFIG_STM32_I2S3
if (port == 3)
{
/* Select I2S3 */
@ -2736,4 +2736,4 @@ errout_with_alloc:
}
#endif /* I2S_HAVE_RX || I2S_HAVE_TX */
#endif /* CONFIG_STM32F7_I2S1 || CONFIG_STM32F7_I2S2 || CONFIG_STM32F7_I2S3 */
#endif /* CONFIG_STM32_I2S1 || CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */

32
arch/arm/src/stm32f7/stm32_lse.c
View file

@ -41,16 +41,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
@ -59,7 +59,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
@ -85,7 +85,7 @@ void stm32_rcc_enablelse(void)
{
uint32_t regval;
volatile int32_t timeout;
#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
volatile int32_t drive = 0;
#endif
@ -109,17 +109,17 @@ void stm32_rcc_enablelse(void)
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. With the
* enable on.
*/
regval &= ~(RCC_BDCR_LSEDRV_MASK);
regval |= CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY <<
regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
#endif
#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
do
{
regval &= ~(RCC_BDCR_LSEDRV_MASK);
@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
if (timeout != 0)
{
break;
@ -153,13 +153,13 @@ void stm32_rcc_enablelse(void)
}
while (drive < sizeof(drives) / sizeof(drives[0]));
#endif
#if defined(CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \
CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY != \
CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \
CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */
regval &= ~RCC_BDCR_LSEDRV_MASK;
regval |= CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
#endif

300
arch/arm/src/stm32f7/stm32_ltdc.c
View file

@ -129,8 +129,8 @@
/* Configuration ************************************************************/
#ifndef CONFIG_STM32F7_LTDC_DEFBACKLIGHT
# define CONFIG_STM32F7_LTDC_DEFBACKLIGHT 0xf0
#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT
# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0
#endif
#define STM32_LTDC_BACKLIGHT_OFF 0x00
@ -138,23 +138,23 @@
/* Layer 1 format */
#if defined(CONFIG_STM32F7_LTDC_L1_L8)
#if defined(CONFIG_STM32_LTDC_L1_L8)
# define STM32_LTDC_L1_BPP 8
# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8
# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8)
# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8
# define STM32_LTDC_L1CMAP
#elif defined(CONFIG_STM32F7_LTDC_L1_RGB565)
#elif defined(CONFIG_STM32_LTDC_L1_RGB565)
# define STM32_LTDC_L1_BPP 16
# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565
# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565)
# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565
#elif defined(CONFIG_STM32F7_LTDC_L1_RGB888)
#elif defined(CONFIG_STM32_LTDC_L1_RGB888)
# define STM32_LTDC_L1_BPP 24
# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24
# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888)
# define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888
#elif defined(CONFIG_STM32F7_LTDC_L1_ARGB8888)
#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888)
# define STM32_LTDC_L1_BPP 32
# define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32
# define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888)
@ -165,24 +165,24 @@
/* Layer 2 format */
#ifdef CONFIG_STM32F7_LTDC_L2
# if defined(CONFIG_STM32F7_LTDC_L2_L8)
#ifdef CONFIG_STM32_LTDC_L2
# if defined(CONFIG_STM32_LTDC_L2_L8)
# define STM32_LTDC_L2_BPP 8
# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8
# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8)
# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8
# define STM32_LTDC_L2CMAP
# elif defined(CONFIG_STM32F7_LTDC_L2_RGB565)
# elif defined(CONFIG_STM32_LTDC_L2_RGB565)
# define STM32_LTDC_L2_BPP 16
# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565
# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565)
# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565
# elif defined(CONFIG_STM32F7_LTDC_L2_RGB888)
# elif defined(CONFIG_STM32_LTDC_L2_RGB888)
# define STM32_LTDC_L2_BPP 24
# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24
# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888)
# define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888
# elif defined(CONFIG_STM32F7_LTDC_L2_ARGB8888)
# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888)
# define STM32_LTDC_L2_BPP 32
# define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32
# define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888)
@ -190,7 +190,7 @@
# else
# error "LTDC pixel format not supported"
# endif
#endif /* CONFIG_STM32F7_LTDC_L2 */
#endif /* CONFIG_STM32_LTDC_L2 */
/* Framebuffer sizes in bytes */
@ -212,7 +212,7 @@
#define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT)
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
# ifndef CONFIG_STM32F7_LTDC_L2_WIDTH
# define CONFIG_STM32F7_LTDC_L2_WIDTH STM32_LTDC_WIDTH
# endif
@ -256,7 +256,7 @@
/* Debug option */
#ifdef CONFIG_STM32F7_LTDC_REGDEBUG
#ifdef CONFIG_STM32_LTDC_REGDEBUG
# define regerr lcderr
# define reginfo lcdinfo
#else
@ -271,10 +271,10 @@
* against wild framebuffer writes.
*/
#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32F7_LTDC_FB_SIZE
#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE
#define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \
STM32_LTDC_TOTAL_FBSIZE)
#define STM32_LTDC_BUFFER_START (CONFIG_STM32F7_LTDC_FB_BASE + \
#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \
STM32_LTDC_BUFFER_FREE/2)
#if STM32_LTDC_BUFFER_FREE < 0
@ -287,7 +287,7 @@
#define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \
STM32_LTDC_L1_FBSIZE)
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
# define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1
# define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \
STM32_LTDC_L2_FBSIZE)
@ -297,7 +297,7 @@
/* LTDC layer */
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
# define LTDC_NLAYERS 2
#else
# define LTDC_NLAYERS 1
@ -305,27 +305,27 @@
/* DMA2D layer */
#ifdef CONFIG_STM32F7_DMA2D
# define DMA2D_NLAYERS CONFIG_STM32F7_DMA2D_NLAYERS
#ifdef CONFIG_STM32_DMA2D
# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS
# if DMA2D_NLAYERS < 1
# error "DMA2D must at least support 1 overlay"
# endif
#define STM32_DMA2D_WIDTH CONFIG_STM32F7_DMA2D_LAYER_PPLINE
#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE
# if defined(CONFIG_STM32F7_DMA2D_L8)
# if defined(CONFIG_STM32_DMA2D_L8)
# define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH)
# define STM32_DMA2D_BPP 8
# define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8
# elif defined(CONFIG_STM32F7_DMA2D_RGB565)
# elif defined(CONFIG_STM32_DMA2D_RGB565)
# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8)
# define STM32_DMA2D_BPP 16
# define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565
# elif defined(CONFIG_STM32F7_DMA2D_RGB888)
# elif defined(CONFIG_STM32_DMA2D_RGB888)
# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8)
# define STM32_DMA2D_BPP 24
# define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888
# elif defined(CONFIG_STM32F7_DMA2D_ARGB8888)
# elif defined(CONFIG_STM32_DMA2D_ARGB8888)
# define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8)
# define STM32_DMA2D_BPP 32
# define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888
@ -333,63 +333,63 @@
# error "DMA2D pixel format not supported"
# endif
# ifdef CONFIG_STM32F7_DMA2D_LAYER_SHARED
# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE
# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED
# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE
# define STM32_DMA2D_LAYER_SIZE 0
# else
# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE / DMA2D_NLAYERS
# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS
# define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE
# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32F7_DMA2D_FB_SIZE
# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE
# error "DMA2D framebuffer size to small for configured number of overlays"
# endif
# endif /* CONFIG_STM32F7_DMA2D_LAYER_SHARED */
# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */
# define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE
# define STM32_DMA2D_BUFFER_START CONFIG_STM32F7_DMA2D_FB_BASE
# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE
#else
# define DMA2D_NLAYERS 0
#endif /* CONFIG_STM32F7_DMA2D */
#endif /* CONFIG_STM32_DMA2D */
#define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS
/* Dithering */
#ifndef CONFIG_STM32F7_LTDC_DITHER_RED
#ifndef CONFIG_STM32_LTDC_DITHER_RED
# define STM32_LTDC_DITHER_RED 0
#else
# define STM32_LTDC_DITHER_RED CONFIG_STM32F7_LTDC_DITHER_RED
# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED
#endif
#ifndef CONFIG_STM32F7_LTDC_DITHER_GREEN
#ifndef CONFIG_STM32_LTDC_DITHER_GREEN
# define STM32_LTDC_DITHER_GREEN 0
#else
# define STM32_LTDC_DITHER_GREEN CONFIG_STM32F7_LTDC_DITHER_GREEN
# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN
#endif
#ifndef CONFIG_STM32F7_LTDC_DITHER_BLUE
#ifndef CONFIG_STM32_LTDC_DITHER_BLUE
# define STM32_LTDC_DITHER_BLUE 0
#else
# define STM32_LTDC_DITHER_BLUE CONFIG_STM32F7_LTDC_DITHER_BLUE
# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE
#endif
/* Background color */
#ifndef CONFIG_STM32F7_LTDC_BACKCOLOR
#ifndef CONFIG_STM32_LTDC_BACKCOLOR
# define STM32_LTDC_BACKCOLOR 0
#else
# define STM32_LTDC_BACKCOLOR CONFIG_STM32F7_LTDC_BACKCOLOR
# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR
#endif
/* Layer default color */
#ifdef CONFIG_STM32F7_LTDC_L1_COLOR
# define STM32_LTDC_L1_COLOR CONFIG_STM32F7_LTDC_L1_COLOR
#ifdef CONFIG_STM32_LTDC_L1_COLOR
# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR
#else
# define STM32_LTDC_L1_COLOR 0x000000
#endif
#ifdef CONFIG_STM32F7_LTDC_L2
# ifdef CONFIG_STM32F7_LTDC_L2_COLOR
# define STM32_LTDC_L2_COLOR CONFIG_STM32F7_LTDC_L2_COLOR
#ifdef CONFIG_STM32_LTDC_L2
# ifdef CONFIG_STM32_LTDC_L2_COLOR
# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR
# else
# define STM32_LTDC_L2_COLOR 0x000000
# endif
@ -423,28 +423,28 @@
/* Check pixel format support by DMA2D driver */
#ifdef CONFIG_STM32F7_DMA2D
# if defined(CONFIG_STM32F7_LTDC_L1_L8) || \
defined(CONFIG_STM32F7_LTDC_L2_L8)
# if !defined(CONFIG_STM32F7_DMA2D_L8)
#ifdef CONFIG_STM32_DMA2D
# if defined(CONFIG_STM32_LTDC_L1_L8) || \
defined(CONFIG_STM32_LTDC_L2_L8)
# if !defined(CONFIG_STM32_DMA2D_L8)
# error "DMA2D must support FB_FMT_RGB8 pixel format"
# endif
# endif
# if defined(CONFIG_STM32F7_LTDC_L1_RGB565) || \
defined(CONFIG_STM32F7_LTDC_L2_RGB565)
# if !defined(CONFIG_STM32F7_DMA2D_RGB565)
# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \
defined(CONFIG_STM32_LTDC_L2_RGB565)
# if !defined(CONFIG_STM32_DMA2D_RGB565)
# error "DMA2D must support FB_FMT_RGB16_565 pixel format"
# endif
# endif
# if defined(CONFIG_STM32F7_LTDC_L1_RGB888) || \
defined(CONFIG_STM32F7_LTDC_L2_RGB888)
# if !defined(CONFIG_STM32F7_DMA2D_RGB888)
# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \
defined(CONFIG_STM32_LTDC_L2_RGB888)
# if !defined(CONFIG_STM32_DMA2D_RGB888)
# error "DMA2D must support FB_FMT_RGB24 pixel format"
# endif
# endif
# if defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) || \
defined(CONFIG_STM32F7_LTDC_L2_ARGB8888)
# if !defined(CONFIG_STM32F7_DMA2D_ARGB8888)
# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \
defined(CONFIG_STM32_LTDC_L2_ARGB8888)
# if !defined(CONFIG_STM32_DMA2D_ARGB8888)
# error "DMA2D must support FB_FMT_RGB32 pixel format"
# endif
# endif
@ -452,12 +452,12 @@
/* Calculate the size of the layers clut table */
#ifdef CONFIG_STM32F7_FB_CMAP
# if defined(CONFIG_STM32F7_DMA2D) && !defined(CONFIG_STM32F7_DMA2D_L8)
#ifdef CONFIG_STM32_FB_CMAP
# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8)
# error "DMA2D must also support L8 CLUT pixel format if supported by LTDC"
# endif
# ifdef STM32_LTDC_L1CMAP
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t)
# else
# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t)
@ -465,7 +465,7 @@
# endif
# ifdef STM32_LTDC_L2CMAP
# undef STM32_LAYER_CLUT_SIZE
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2
# else
# define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2
@ -473,7 +473,7 @@
# endif
#endif
#ifndef CONFIG_STM32F7_FB_CMAP
#ifndef CONFIG_STM32_FB_CMAP
# if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP)
# undef STM32_LTDC_L1CMAP
# undef STM32_LTDC_L2CMAP
@ -510,9 +510,9 @@
/* Acceleration support for LTDC overlays */
#ifdef CONFIG_STM32F7_LTDC_L1_CHROMAKEYEN
#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN
# define STM32_LTDC_L1_CHROMAEN true
# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32F7_LTDC_L1_CHROMAKEY
# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY
# define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA
#else
# define STM32_LTDC_L1_CHROMAEN false
@ -520,9 +520,9 @@
# define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP
#endif
#ifdef CONFIG_STM32F7_LTDC_L2_CHROMAKEYEN
#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN
# define STM32_LTDC_L2_CHROMAEN true
# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32F7_LTDC_L2_CHROMAKEY
# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY
# define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA
#else
# define STM32_LTDC_L2_CHROMAEN false
@ -530,34 +530,34 @@
# define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP
#endif
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
# ifdef CONFIG_FB_OVERLAY_BLIT
# ifdef CONFIG_STM32F7_FB_CMAP
# ifdef CONFIG_STM32_FB_CMAP
# define LTDC_BLIT_ACCL FB_ACCL_BLIT
# else
# define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND
# endif /* CONFIG_STM32F7_FB_CMAP */
# endif /* CONFIG_STM32_FB_CMAP */
# else
# define LTDC_BLIT_ACCL 0
# endif /* CONFIG_FB_OVERLAY_BLIT */
# ifdef CONFIG_STM32F7_FB_CMAP
# ifdef CONFIG_STM32_FB_CMAP
# define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL
# else
# define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL
# endif /* CONFIG_STM32F7_FB_CMAP */
# endif /* CONFIG_STM32_FB_CMAP */
#else
# define LTDC_DMA2D_ACCL 0
#endif /* CONFIG_STM32F7_DMA2D */
#endif /* CONFIG_STM32_DMA2D */
#define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
# define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL
#endif
/* Acceleration support for DMA2D overlays */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
# ifdef CONFIG_FB_OVERLAY_BLIT
# define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA
# else
@ -579,7 +579,7 @@
/* Color normalization */
#if defined(CONFIG_STM32F7_LTDC_L1_RGB565)
#if defined(CONFIG_STM32_LTDC_L1_RGB565)
# define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6)
# define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6)
# define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6)
@ -612,7 +612,7 @@ struct stm32_ltdc_s
struct fb_overlayinfo_s oinfo; /* Overlay info */
#endif
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */
#endif
@ -637,7 +637,7 @@ struct stm32_ltdcdev_s
/* Cmap information */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
struct fb_cmap_s cmap;
#endif
@ -645,7 +645,7 @@ struct stm32_ltdcdev_s
struct stm32_ltdc_s layer[LTDC_NOVERLAYS];
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
/* Interface to the dma2d controller */
struct dma2d_layer_s *dma2d;
@ -693,7 +693,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer,
bool enable);
static void stm32_ltdc_linit(uint8_t lid);
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
static void stm32_ltdc_dma2dlinit(void);
# ifdef CONFIG_FB_OVERLAY_BLIT
@ -702,7 +702,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer,
# endif
#endif
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer,
const struct fb_cmap_s *cmap);
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
@ -725,7 +725,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable,
* mapping
*/
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static int stm32_getcmap(struct fb_vtable_s *vtable,
struct fb_cmap_s *cmap);
static int stm32_putcmap(struct fb_vtable_s *vtable,
@ -795,16 +795,16 @@ static const uint32_t g_ltdcpins[] =
#define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t))
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
/* The layers clut table entries */
static uint8_t g_redclut[STM32_LTDC_NCLUT];
static uint8_t g_greenclut[STM32_LTDC_NCLUT];
static uint8_t g_blueclut[STM32_LTDC_NCLUT];
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
static uint8_t g_transpclut[STM32_LTDC_NCLUT];
# endif
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/* The LTDC mutex that enforces mutually exclusive access */
@ -836,7 +836,7 @@ static struct stm32_ltdcdev_s g_vtable =
.waitforvsync = stm32_waitforvsync
#endif
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
,
.getcmap = stm32_getcmap,
.putcmap = stm32_putcmap
@ -857,7 +857,7 @@ static struct stm32_ltdcdev_s g_vtable =
# endif
#endif /* CONFIG_FB_OVERLAY */
},
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
.pinfo =
{
.fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2,
@ -895,9 +895,9 @@ static struct stm32_ltdcdev_s g_vtable =
.noverlays = LTDC_NOVERLAYS
# endif
}
#endif /* CONFIG_STM32F7_LTDC_L2 */
#endif /* CONFIG_STM32_LTDC_L2 */
,
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
.cmap =
{
.first = 0,
@ -905,7 +905,7 @@ static struct stm32_ltdcdev_s g_vtable =
.red = g_redclut,
.green = g_greenclut,
.blue = g_blueclut,
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
.transp = g_transpclut
# endif
}
@ -941,7 +941,7 @@ static struct stm32_ltdcdev_s g_vtable =
},
#endif
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
.dma2dinfo =
{
.fmt = STM32_LTDC_L1_DMA2D_PF,
@ -953,7 +953,7 @@ static struct stm32_ltdcdev_s g_vtable =
#endif
.lock = &g_lock
}
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
,
.layer[LTDC_LAYER_L2] =
{
@ -985,7 +985,7 @@ static struct stm32_ltdcdev_s g_vtable =
},
#endif
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
.dma2dinfo =
{
.fmt = STM32_LTDC_L2_DMA2D_PF,
@ -1007,7 +1007,7 @@ static struct stm32_ltdcdev_s g_vtable =
static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_WIDTH
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_WIDTH
#endif
};
@ -1017,7 +1017,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_HEIGHT
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_HEIGHT
#endif
};
@ -1027,7 +1027,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1_STRIDE
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2_STRIDE
#endif
};
@ -1037,7 +1037,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1_BPP
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2_BPP
#endif
};
@ -1047,7 +1047,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1_FBSIZE
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2_FBSIZE
#endif
};
@ -1057,7 +1057,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_BUFFER_L1
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_BUFFER_L2
#endif
};
@ -1067,7 +1067,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1_COLOR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2_COLOR
#endif
};
@ -1077,7 +1077,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1_CHROMAKEY
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2_CHROMAKEY
#endif
};
@ -1087,7 +1087,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] =
static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1_CHROMAEN
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2_CHROMAEN
#endif
};
@ -1097,7 +1097,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] =
static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1PFCR_PF
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2PFCR_PF
#endif
};
@ -1109,7 +1109,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CR
#endif
};
@ -1119,7 +1119,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1WHPCR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2WHPCR
#endif
};
@ -1129,7 +1129,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1WVPCR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2WVPCR
#endif
};
@ -1139,7 +1139,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1PFCR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2PFCR
#endif
};
@ -1149,7 +1149,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1DCCR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2DCCR
#endif
};
@ -1159,7 +1159,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CKCR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CKCR
#endif
};
@ -1169,7 +1169,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CACR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CACR
#endif
};
@ -1179,7 +1179,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1BFCR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2BFCR
#endif
};
@ -1189,7 +1189,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CFBAR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CFBAR
#endif
};
@ -1199,7 +1199,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CFBLR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CFBLR
#endif
};
@ -1209,22 +1209,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] =
static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CFBLNR
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CFBLNR
#endif
};
/* LTDC_LxCLUTWR */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1CLUTWR
# ifdef CONFIG_STM32F7_LTDC_L2
# ifdef CONFIG_STM32_LTDC_L2
, STM32_LTDC_L2CLUTWR
# endif
};
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/* The initialized state of the driver */
@ -1648,7 +1648,7 @@ static void stm32_ltdc_globalconfig(void)
/* Configure dither */
stm32_ltdc_dither(
#ifdef CONFIG_STM32F7_LTDC_DITHER
#ifdef CONFIG_STM32_LTDC_DITHER
true,
#else
false,
@ -1920,7 +1920,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer,
/* Set chromakey */
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
uint8_t r = g_vtable.cmap.red[chroma];
uint8_t g = g_vtable.cmap.green[chroma];
uint8_t b = g_vtable.cmap.blue[chroma];
@ -1990,7 +1990,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer,
bool enable)
{
@ -2095,7 +2095,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++)
{
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
cmap->transp[n] = priv_cmap->transp[n];
# endif
cmap->red[n] = priv_cmap->red[n];
@ -2104,7 +2104,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n",
n,
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
cmap->transp[n],
# endif
cmap->red[n],
@ -2112,7 +2112,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
cmap->blue[n]);
}
}
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/****************************************************************************
* Name: stm32_ltdc_lclear
@ -2144,7 +2144,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno)
*
****************************************************************************/
#if defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT)
#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT)
static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer,
const struct fb_area_s *area)
{
@ -2155,7 +2155,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer,
return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0);
}
#endif /* defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */
#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */
/****************************************************************************
* Name: stm32_ltdc_linit
@ -2215,7 +2215,7 @@ static void stm32_ltdc_linit(uint8_t overlay)
stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]);
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
/* Disable clut by default */
if (dev->vinfo.fmt == FB_FMT_RGB8)
@ -2255,7 +2255,7 @@ static void stm32_ltdc_linit(uint8_t overlay)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
static void stm32_ltdc_dma2dlinit(void)
{
int n;
@ -2291,7 +2291,7 @@ static void stm32_ltdc_dma2dlinit(void)
layer->dma2dinfo.oinfo = &layer->oinfo;
}
}
#endif /* CONFIG_STM32F7_DMA2D */
#endif /* CONFIG_STM32_DMA2D */
/****************************************************************************
* Public Functions
@ -2378,7 +2378,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
*
****************************************************************************/
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
static int stm32_getcmap(struct fb_vtable_s *vtable,
struct fb_cmap_s *cmap)
{
@ -2408,7 +2408,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable,
*/
struct stm32_ltdc_s *layer;
# ifdef CONFIG_STM32F7_LTDC_L2
# ifdef CONFIG_STM32_LTDC_L2
layer = &priv->layer[LTDC_LAYER_L2];
# else
layer = &priv->layer[LTDC_LAYER_L1];
@ -2478,7 +2478,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
priv_cmap->red[n] = cmap->red[n];
priv_cmap->green[n] = cmap->green[n];
priv_cmap->blue[n] = cmap->blue[n];
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
/* Not supported by LTDC */
priv_cmap->transp[n] = cmap->transp[n];
@ -2498,7 +2498,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
stm32_ltdc_lputclut(layer, priv_cmap);
}
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
/* Update dma2d cmap */
priv->dma2d->setclut(cmap);
@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
return ret;
}
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/****************************************************************************
* Name: stm32_ioctl_waitforvsync
@ -2589,7 +2589,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable,
layer->oinfo.transp.transp = oinfo->transp.transp;
layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode;
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
if (layer->oinfo.transp.transp_mode == 0)
{
layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST;
@ -2636,14 +2636,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
int ret;
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
# ifndef CONFIG_STM32F7_LTDC_L1_CHROMAKEY
# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY
if (oinfo->overlay == LTDC_LAYER_L1)
{
return -ENOSYS;
}
# endif
# ifndef CONFIG_STM32F7_LTDC_L2_CHROMAKEY
# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY
if (oinfo->overlay == LTDC_LAYER_L2)
{
return -ENOSYS;
@ -2651,7 +2651,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
# endif
nxmutex_lock(layer->lock);
# ifdef CONFIG_STM32F7_FB_CMAP
# ifdef CONFIG_STM32_FB_CMAP
if (oinfo->chromakey >= g_vtable.cmap.len)
{
lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey);
@ -2671,7 +2671,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
nxmutex_unlock(layer->lock);
return ret;
}
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
else if (oinfo->overlay < LTDC_NOVERLAYS)
{
/* Chromakey not supported by DMA2D */
@ -2699,7 +2699,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NOVERLAYS)
{
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
/* Set color within the active overlay is not supported by LTDC. So use
* DMA2D controller instead when configured.
@ -2760,7 +2760,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable,
return OK;
}
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
else if (oinfo->overlay < LTDC_NOVERLAYS)
{
/* DMA2D overlays are non visible */
@ -2794,7 +2794,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable,
return -ENOSYS;
}
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
if (oinfo->overlay < LTDC_NOVERLAYS)
{
struct stm32_ltdcdev_s *priv =
@ -2830,7 +2830,7 @@ static int stm32_blit(struct fb_vtable_s *vtable,
if (blit->dest.overlay < LTDC_NOVERLAYS &&
blit->src.overlay < LTDC_NOVERLAYS)
{
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
int ret;
struct fb_area_s sarea;
const struct fb_area_s *darea = &blit->dest.area;
@ -2892,7 +2892,7 @@ static int stm32_blend(struct fb_vtable_s *vtable,
blend->foreground.overlay < LTDC_NOVERLAYS &&
blend->background.overlay < LTDC_NOVERLAYS)
{
# ifdef CONFIG_STM32F7_DMA2D
# ifdef CONFIG_STM32_DMA2D
int ret;
struct fb_area_s barea;
const struct fb_area_s *darea = &blend->dest.area;
@ -3006,7 +3006,7 @@ int stm32_ltdcinitialize(void)
lcdinfo("Configure global register\n");
stm32_ltdc_globalconfig();
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
/* Initialize the dma2d controller */
ret = stm32_dma2dinitialize();
@ -3022,26 +3022,26 @@ int stm32_ltdcinitialize(void)
DEBUGASSERT(g_vtable.dma2d != NULL);
#endif
#ifdef CONFIG_STM32F7_FB_CMAP
#ifdef CONFIG_STM32_FB_CMAP
/* Cleanup clut */
memset(&g_redclut, 0, STM32_LTDC_NCLUT);
memset(&g_blueclut, 0, STM32_LTDC_NCLUT);
memset(&g_greenclut, 0, STM32_LTDC_NCLUT);
# ifdef CONFIG_STM32F7_FB_TRANSPARENCY
# ifdef CONFIG_STM32_FB_TRANSPARENCY
memset(&g_transpclut, 0, STM32_LTDC_NCLUT);
# endif
#endif /* CONFIG_STM32F7_FB_CMAP */
#endif /* CONFIG_STM32_FB_CMAP */
/* Initialize ltdc layer */
lcdinfo("Initialize ltdc layer\n");
stm32_ltdc_linit(LTDC_LAYER_L1);
#ifdef CONFIG_STM32F7_LTDC_L2
#ifdef CONFIG_STM32_LTDC_L2
stm32_ltdc_linit(LTDC_LAYER_L2);
#endif
#ifdef CONFIG_STM32F7_DMA2D
#ifdef CONFIG_STM32_DMA2D
stm32_ltdc_dma2dlinit();
#endif
/* Enable the backlight */
@ -3135,7 +3135,7 @@ void stm32_ltdcuninitialize(void)
#ifdef CONFIG_STM32F7_LCD_BACKLIGHT
void stm32_backlight(bool blon)
{
/* Set default backlight level CONFIG_STM32F7_LTDC_DEFBACKLIGHT */
/* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */
lcderr("ERROR: Not supported\n");
}

8
arch/arm/src/stm32f7/stm32_otg.h
View file

@ -34,7 +34,7 @@
#include "chip.h"
#include "hardware/stm32_otg.h"
#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)
#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS)
/****************************************************************************
* Pre-processor Definitions
@ -46,7 +46,7 @@
# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
#if defined(CONFIG_STM32F7_OTGFS)
#if defined(CONFIG_STM32_OTGFS)
# define STM32_IRQ_OTG STM32_IRQ_OTGFS
# define STM32_OTG_BASE STM32_USBOTGFS_BASE
# define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */
@ -58,7 +58,7 @@
# define STM32_OTG_FIFO_SIZE 1280
#endif
#if defined(CONFIG_STM32F7_OTGFSHS)
#if defined(CONFIG_STM32_OTGFSHS)
# define STM32_IRQ_OTG STM32_IRQ_OTGHS
# define STM32_OTG_BASE STM32_USBOTGHS_BASE
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
@ -135,5 +135,5 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F7_OTGFS */
#endif /* CONFIG_STM32_OTGFS */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */

42
arch/arm/src/stm32f7/stm32_otgdev.c
View file

@ -52,8 +52,8 @@
#include "stm32_rcc.h"
#include "arm_internal.h"
#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \
defined(CONFIG_STM32F7_OTGFSHS))
#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \
defined(CONFIG_STM32_OTGFSHS))
/****************************************************************************
* Pre-processor Definitions
@ -254,7 +254,7 @@
* present
*/
# ifdef CONFIG_STM32F7_OTGFSHS
# ifdef CONFIG_STM32_OTGFSHS
# define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS
# define OTG_GINT_RC_W1 OTG_GINT_RC_W1_HS
# else
@ -373,7 +373,7 @@
/* Maximum packet sizes for full speed endpoints */
# ifdef CONFIG_STM32F7_OTGFSHS
# ifdef CONFIG_STM32_OTGFSHS
# define STM32_MAXPACKET (512) /* Max packet size (1-512) */
# else
# define STM32_MAXPACKET (64) /* Max packet size (1-64) */
@ -573,7 +573,7 @@ struct stm32_usbdev_s
/* Register operations ******************************************************/
# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint32_t val, uint32_t addr);
# else
@ -898,7 +898,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
*
****************************************************************************/
# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -961,7 +961,7 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
@ -2163,7 +2163,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv)
stm32_setaddress(priv, 0);
priv->devstate = DEVSTATE_DEFAULT;
# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI)
priv->usbdev.speed = USB_SPEED_HIGH;
# else
priv->usbdev.speed = USB_SPEED_FULL;
@ -3461,7 +3461,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTG_GUSBCFG);
regval &= ~OTG_GUSBCFG_TRDT_MASK;
# ifdef CONFIG_STM32F7_OTGFSHS
# ifdef CONFIG_STM32_OTGFSHS
regval |= OTG_GUSBCFG_TRDT(9);
# else
regval |= OTG_GUSBCFG_TRDT(6);
@ -5345,15 +5345,15 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG);
# ifdef CONFIG_STM32F7_OTGFSHS
# ifdef CONFIG_STM32_OTGFSHS
# ifdef CONFIG_STM32F7_NO_ULPI
# ifdef CONFIG_STM32_NO_ULPI
regval = stm32_getreg(STM32_OTG_GUSBCFG);
regval |= OTG_GUSBCFG_PHYSEL;
stm32_putreg(regval, STM32_OTG_GUSBCFG);
# else /* CONFIG_STM32F7_NO_ULPI */
# else /* CONFIG_STM32_NO_ULPI */
/* Switch off FS transceiver */
@ -5376,7 +5376,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI);
stm32_putreg(regval, STM32_OTG_GUSBCFG);
# ifdef CONFIG_STM32F7_INTERNAL_ULPI
# ifdef CONFIG_STM32_INTERNAL_ULPI
/* Select UTMI/ULPI Interface */
@ -5421,9 +5421,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
up_udelay(2000);
# endif /* CONFIG_STM32F7_INTERNAL_ULPI */
# endif /* CONFIG_STM32F7_NO_ULPI */
# endif /* CONFIG_STM32F7_OTGFSHS */
# endif /* CONFIG_STM32_INTERNAL_ULPI */
# endif /* CONFIG_STM32_NO_ULPI */
# endif /* CONFIG_STM32_OTGFSHS */
/* Common USB OTG core initialization */
@ -5465,7 +5465,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTG_GCCFG);
# if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI))
# if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_NO_ULPI))
regval |= OTG_GCCFG_PWRDWN;
# endif
@ -5509,7 +5509,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTG_DCFG);
regval &= ~OTG_DCFG_DSPD_MASK;
# ifdef CONFIG_STM32F7_OTGFSHS
# ifdef CONFIG_STM32_OTGFSHS
regval |= OTG_DCFG_DSPD_HS;
# else
regval |= OTG_DCFG_DSPD_FS;
@ -5652,7 +5652,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv)
regval &= OTG_GINT_RESERVED;
stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS);
# if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI)
# if defined(CONFIG_STM32_OTGFSHS) && defined(CONFIG_STM32_NO_ULPI)
/* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done
* because if both the ULPI and the FS PHY clock enable bits are set at the
* same time, the ARM never awakens from WFI due to some bug / errata in
@ -5747,7 +5747,7 @@ void arm_usbinitialize(void)
/* SOF output pin configuration is configurable. */
# ifdef CONFIG_STM32F7_OTG_SOFOUTPUT
# ifdef CONFIG_STM32_OTG_SOFOUTPUT
stm32_configgpio(GPIO_OTG_SOF);
# endif
@ -5919,7 +5919,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
*/
stm32_pullup(&priv->usbdev, true);
# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI)
priv->usbdev.speed = USB_SPEED_HIGH;
# else
priv->usbdev.speed = USB_SPEED_FULL;

34
arch/arm/src/stm32f7/stm32_otghost.c
View file

@ -60,7 +60,7 @@
#include "stm32_otg.h"
#include "stm32_usbhost.h"
#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS)
#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS)
/****************************************************************************
* Pre-processor Definitions
@ -73,8 +73,8 @@
* Pre-requisites
*
* CONFIG_USBHOST - Enable general USB host support
* CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
* CONFIG_STM32F7_SYSCFG_IOCOMPENSATION - Needed
* CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
* CONFIG_STM32_SYSCFG_IOCOMPENSATION - Needed
*
* Options:
*
@ -87,16 +87,16 @@
* CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128
* CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
* CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access
* CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
* debug. Depends on CONFIG_DEBUG_FEATURES.
* CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
* CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
* packets. Depends on CONFIG_DEBUG_FEATURES.
*/
/* Pre-requisites (partial) */
#ifndef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION
# error "CONFIG_STM32F7_SYSCFG_IOCOMPENSATION is required"
#ifndef CONFIG_STM32_SYSCFG_IOCOMPENSATION
# error "CONFIG_STM32_SYSCFG_IOCOMPENSATION is required"
#endif
/* Default RxFIFO size */
@ -126,8 +126,8 @@
/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */
#ifndef CONFIG_DEBUG_FEATURES
# undef CONFIG_STM32F7_USBHOST_REGDEBUG
# undef CONFIG_STM32F7_USBHOST_PKTDUMP
# undef CONFIG_STM32_USBHOST_REGDEBUG
# undef CONFIG_STM32_USBHOST_PKTDUMP
#endif
/* HCD Setup ****************************************************************/
@ -272,7 +272,7 @@ struct stm32_usbhost_s
/* Register operations ******************************************************/
#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite);
static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t stm32_getreg(uint32_t addr);
@ -285,7 +285,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value);
static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits,
uint32_t setbits);
#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP
#ifdef CONFIG_STM32_USBHOST_PKTDUMP
# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n)
#else
# define stm32_pktdump(m,b,n)
@ -496,7 +496,7 @@ static struct usbhost_connection_s g_usbconn =
*
****************************************************************************/
#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val);
@ -511,7 +511,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
static uint32_t prevaddr = 0;
@ -575,7 +575,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
/* Read the value from the register */
@ -597,7 +597,7 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG
#ifdef CONFIG_STM32_USBHOST_REGDEBUG
static void stm32_putreg(uint32_t addr, uint32_t val)
{
/* Check if we need to print this value */
@ -5407,7 +5407,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller)
/* SOF output pin configuration is configurable */
#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT
#ifdef CONFIG_STM32_OTG_SOFOUTPUT
stm32_configgpio(GPIO_OTG_SOF);
#endif
@ -5433,4 +5433,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller)
return &g_usbconn;
}
#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */
#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */

88
arch/arm/src/stm32f7/stm32_pulsecount.c
View file

@ -173,10 +173,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev);
static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
const struct pulsecount_info_s *info);
static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev);
# ifdef CONFIG_STM32F7_TIM1_PULSECOUNT
# ifdef CONFIG_STM32_TIM1_PULSECOUNT
static int pulsecount_tim1interrupt(int irq, void *context, void *arg);
# endif
# ifdef CONFIG_STM32F7_TIM8_PULSECOUNT
# ifdef CONFIG_STM32_TIM8_PULSECOUNT
static int pulsecount_tim8interrupt(int irq, void *context, void *arg);
# endif
static uint8_t pulsecount_count(uint32_t count);
@ -203,107 +203,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static struct stm32_tim_s g_pulsecount1dev =
{
.channel =
{
.channel = CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL,
#if CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 1
.channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL,
#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH1OUT,
},
#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 2
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH2OUT,
},
#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 3
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH3OUT,
},
#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 4
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH4OUT,
},
#endif
},
.timid = 1,
.timtype = TIMTYPE_TIM1,
.t_dts = CONFIG_STM32F7_TIM1_PULSECOUNT_TDTS,
.t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS,
.irq = STM32_IRQ_TIM1UP,
.base = STM32_TIM1_BASE,
.pclk = TIMCLK_TIM1,
};
#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */
#endif /* CONFIG_STM32_TIM1_PULSECOUNT */
#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
static struct stm32_tim_s g_pulsecount8dev =
{
.channel =
{
.channel = CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL,
#if CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 1
.channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL,
#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH1OUT,
},
#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 2
#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH2OUT,
},
#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 3
#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH3OUT,
},
#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 4
#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH4OUT,
},
#endif
},
.timid = 8,
.timtype = TIMTYPE_TIM8,
.t_dts = CONFIG_STM32F7_TIM8_PULSECOUNT_TDTS,
.t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS,
.irq = STM32_IRQ_TIM8UP,
.base = STM32_TIM8_BASE,
.pclk = TIMCLK_TIM8,
};
#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */
#endif /* CONFIG_STM32_TIM8_PULSECOUNT */
static const struct pulsecount_ops_s g_pulsecountops =
{
@ -314,7 +314,7 @@ static const struct pulsecount_ops_s g_pulsecountops =
.ioctl = pulsecount_ioctl,
};
#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static struct stm32_pulsecount_s g_pulsecount1lower =
{
.ops = &g_pulsecountops,
@ -322,7 +322,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower =
};
#endif
#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
static struct stm32_pulsecount_s g_pulsecount8lower =
{
.ops = &g_pulsecountops,
@ -1303,21 +1303,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static int pulsecount_tim1interrupt(int irq, void *context, void *arg)
{
return pulsecount_interrupt((struct pulsecount_lowerhalf_s *)
&g_pulsecount1dev);
}
#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */
#endif /* CONFIG_STM32_TIM1_PULSECOUNT */
#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
static int pulsecount_tim8interrupt(int irq, void *context, void *arg)
{
return pulsecount_interrupt((struct pulsecount_lowerhalf_s *)
&g_pulsecount8dev);
}
#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */
#endif /* CONFIG_STM32_TIM8_PULSECOUNT */
/****************************************************************************
* Name: pulsecount_count
@ -1390,7 +1390,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on)
switch (priv->timid)
{
#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
{
regaddr = TIMRCCEN_TIM1;
@ -1399,7 +1399,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on)
}
#endif
#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
case 8:
{
regaddr = TIMRCCEN_TIM8;
@ -1717,7 +1717,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer)
switch (timer)
{
#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
{
lower = &g_pulsecount1lower;
@ -1727,7 +1727,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer)
}
#endif
#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
case 8:
{
lower = &g_pulsecount8lower;

564
arch/arm/src/stm32f7/stm32_pwm.c
View file

File diff suppressed because it is too large Load diff

514
arch/arm/src/stm32f7/stm32_pwm.h
View file

@ -39,7 +39,7 @@
#include "chip.h"
#ifdef CONFIG_STM32F7_PWM
#ifdef CONFIG_STM32_PWM
# include <arch/board/board.h>
# include "hardware/stm32_tim.h"
#endif
@ -57,41 +57,41 @@
* pulsed output signal generation.
*/
#ifndef CONFIG_STM32F7_TIM1
# undef CONFIG_STM32F7_TIM1_PWM
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_PWM
#endif
#ifndef CONFIG_STM32F7_TIM2
# undef CONFIG_STM32F7_TIM2_PWM
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_PWM
#endif
#ifndef CONFIG_STM32F7_TIM3
# undef CONFIG_STM32F7_TIM3_PWM
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_PWM
#endif
#ifndef CONFIG_STM32F7_TIM4
# undef CONFIG_STM32F7_TIM4_PWM
#ifndef CONFIG_STM32_TIM4
# undef CONFIG_STM32_TIM4_PWM
#endif
#ifndef CONFIG_STM32F7_TIM5
# undef CONFIG_STM32F7_TIM5_PWM
#ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_PWM
#endif
#ifndef CONFIG_STM32F7_TIM8
# undef CONFIG_STM32F7_TIM8_PWM
#ifndef CONFIG_STM32_TIM8
# undef CONFIG_STM32_TIM8_PWM
#endif
#ifndef CONFIG_STM32F7_TIM9
# undef CONFIG_STM32F7_TIM9_PWM
#ifndef CONFIG_STM32_TIM9
# undef CONFIG_STM32_TIM9_PWM
#endif
#ifndef CONFIG_STM32F7_TIM10
# undef CONFIG_STM32F7_TIM10_PWM
#ifndef CONFIG_STM32_TIM10
# undef CONFIG_STM32_TIM10_PWM
#endif
#ifndef CONFIG_STM32F7_TIM11
# undef CONFIG_STM32F7_TIM11_PWM
#ifndef CONFIG_STM32_TIM11
# undef CONFIG_STM32_TIM11_PWM
#endif
#ifndef CONFIG_STM32F7_TIM12
# undef CONFIG_STM32F7_TIM12_PWM
#ifndef CONFIG_STM32_TIM12
# undef CONFIG_STM32_TIM12_PWM
#endif
#ifndef CONFIG_STM32F7_TIM13
# undef CONFIG_STM32F7_TIM13_PWM
#ifndef CONFIG_STM32_TIM13
# undef CONFIG_STM32_TIM13_PWM
#endif
#ifndef CONFIG_STM32F7_TIM14
# undef CONFIG_STM32F7_TIM14_PWM
#ifndef CONFIG_STM32_TIM14
# undef CONFIG_STM32_TIM14_PWM
#endif
/* The basic timers (timer 6 and 7) are not capable of generating output
@ -103,38 +103,38 @@
/* Check if PWM support for any channel is enabled. */
#ifdef CONFIG_STM32F7_PWM
#ifdef CONFIG_STM32_PWM
/* PWM driver channels configuration */
#ifdef CONFIG_STM32F7_PWM_MULTICHAN
#ifdef CONFIG_STM32_PWM_MULTICHAN
#ifdef CONFIG_STM32F7_TIM1_CHANNEL1
#ifdef CONFIG_STM32_TIM1_CHANNEL1
# define PWM_TIM1_CHANNEL1 1
#else
# define PWM_TIM1_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CHANNEL2
#ifdef CONFIG_STM32_TIM1_CHANNEL2
# define PWM_TIM1_CHANNEL2 1
#else
# define PWM_TIM1_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CHANNEL3
#ifdef CONFIG_STM32_TIM1_CHANNEL3
# define PWM_TIM1_CHANNEL3 1
#else
# define PWM_TIM1_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CHANNEL4
#ifdef CONFIG_STM32_TIM1_CHANNEL4
# define PWM_TIM1_CHANNEL4 1
#else
# define PWM_TIM1_CHANNEL4 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CHANNEL5
#ifdef CONFIG_STM32_TIM1_CHANNEL5
# define PWM_TIM1_CHANNEL5 1
#else
# define PWM_TIM1_CHANNEL5 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CHANNEL6
#ifdef CONFIG_STM32_TIM1_CHANNEL6
# define PWM_TIM1_CHANNEL6 1
#else
# define PWM_TIM1_CHANNEL6 0
@ -143,22 +143,22 @@
PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \
PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6)
#ifdef CONFIG_STM32F7_TIM2_CHANNEL1
#ifdef CONFIG_STM32_TIM2_CHANNEL1
# define PWM_TIM2_CHANNEL1 1
#else
# define PWM_TIM2_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CHANNEL2
#ifdef CONFIG_STM32_TIM2_CHANNEL2
# define PWM_TIM2_CHANNEL2 1
#else
# define PWM_TIM2_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CHANNEL3
#ifdef CONFIG_STM32_TIM2_CHANNEL3
# define PWM_TIM2_CHANNEL3 1
#else
# define PWM_TIM2_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CHANNEL4
#ifdef CONFIG_STM32_TIM2_CHANNEL4
# define PWM_TIM2_CHANNEL4 1
#else
# define PWM_TIM2_CHANNEL4 0
@ -166,22 +166,22 @@
#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
#ifdef CONFIG_STM32F7_TIM3_CHANNEL1
#ifdef CONFIG_STM32_TIM3_CHANNEL1
# define PWM_TIM3_CHANNEL1 1
#else
# define PWM_TIM3_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CHANNEL2
#ifdef CONFIG_STM32_TIM3_CHANNEL2
# define PWM_TIM3_CHANNEL2 1
#else
# define PWM_TIM3_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CHANNEL3
#ifdef CONFIG_STM32_TIM3_CHANNEL3
# define PWM_TIM3_CHANNEL3 1
#else
# define PWM_TIM3_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CHANNEL4
#ifdef CONFIG_STM32_TIM3_CHANNEL4
# define PWM_TIM3_CHANNEL4 1
#else
# define PWM_TIM3_CHANNEL4 0
@ -189,22 +189,22 @@
#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
#ifdef CONFIG_STM32F7_TIM4_CHANNEL1
#ifdef CONFIG_STM32_TIM4_CHANNEL1
# define PWM_TIM4_CHANNEL1 1
#else
# define PWM_TIM4_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CHANNEL2
#ifdef CONFIG_STM32_TIM4_CHANNEL2
# define PWM_TIM4_CHANNEL2 1
#else
# define PWM_TIM4_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CHANNEL3
#ifdef CONFIG_STM32_TIM4_CHANNEL3
# define PWM_TIM4_CHANNEL3 1
#else
# define PWM_TIM4_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CHANNEL4
#ifdef CONFIG_STM32_TIM4_CHANNEL4
# define PWM_TIM4_CHANNEL4 1
#else
# define PWM_TIM4_CHANNEL4 0
@ -212,22 +212,22 @@
#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
#ifdef CONFIG_STM32F7_TIM5_CHANNEL1
#ifdef CONFIG_STM32_TIM5_CHANNEL1
# define PWM_TIM5_CHANNEL1 1
#else
# define PWM_TIM5_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CHANNEL2
#ifdef CONFIG_STM32_TIM5_CHANNEL2
# define PWM_TIM5_CHANNEL2 1
#else
# define PWM_TIM5_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CHANNEL3
#ifdef CONFIG_STM32_TIM5_CHANNEL3
# define PWM_TIM5_CHANNEL3 1
#else
# define PWM_TIM5_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CHANNEL4
#ifdef CONFIG_STM32_TIM5_CHANNEL4
# define PWM_TIM5_CHANNEL4 1
#else
# define PWM_TIM5_CHANNEL4 0
@ -235,32 +235,32 @@
#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
#ifdef CONFIG_STM32F7_TIM8_CHANNEL1
#ifdef CONFIG_STM32_TIM8_CHANNEL1
# define PWM_TIM8_CHANNEL1 1
#else
# define PWM_TIM8_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CHANNEL2
#ifdef CONFIG_STM32_TIM8_CHANNEL2
# define PWM_TIM8_CHANNEL2 1
#else
# define PWM_TIM8_CHANNEL2 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CHANNEL3
#ifdef CONFIG_STM32_TIM8_CHANNEL3
# define PWM_TIM8_CHANNEL3 1
#else
# define PWM_TIM8_CHANNEL3 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CHANNEL4
#ifdef CONFIG_STM32_TIM8_CHANNEL4
# define PWM_TIM8_CHANNEL4 1
#else
# define PWM_TIM8_CHANNEL4 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CHANNEL5
#ifdef CONFIG_STM32_TIM8_CHANNEL5
# define PWM_TIM8_CHANNEL5 1
#else
# define PWM_TIM8_CHANNEL5 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CHANNEL6
#ifdef CONFIG_STM32_TIM8_CHANNEL6
# define PWM_TIM8_CHANNEL6 1
#else
# define PWM_TIM8_CHANNEL6 0
@ -269,59 +269,59 @@
PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \
PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6)
#ifdef CONFIG_STM32F7_TIM9_CHANNEL1
#ifdef CONFIG_STM32_TIM9_CHANNEL1
# define PWM_TIM9_CHANNEL1 1
#else
# define PWM_TIM9_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM9_CHANNEL2
#ifdef CONFIG_STM32_TIM9_CHANNEL2
# define PWM_TIM9_CHANNEL2 1
#else
# define PWM_TIM9_CHANNEL2 0
#endif
#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2)
#ifdef CONFIG_STM32F7_TIM10_CHANNEL1
#ifdef CONFIG_STM32_TIM10_CHANNEL1
# define PWM_TIM10_CHANNEL1 1
#else
# define PWM_TIM10_CHANNEL1 0
#endif
#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1)
#ifdef CONFIG_STM32F7_TIM11_CHANNEL1
#ifdef CONFIG_STM32_TIM11_CHANNEL1
# define PWM_TIM11_CHANNEL1 1
#else
# define PWM_TIM11_CHANNEL1 0
#endif
#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1)
#ifdef CONFIG_STM32F7_TIM12_CHANNEL1
#ifdef CONFIG_STM32_TIM12_CHANNEL1
# define PWM_TIM12_CHANNEL1 1
#else
# define PWM_TIM12_CHANNEL1 0
#endif
#ifdef CONFIG_STM32F7_TIM12_CHANNEL2
#ifdef CONFIG_STM32_TIM12_CHANNEL2
# define PWM_TIM12_CHANNEL2 1
#else
# define PWM_TIM12_CHANNEL2 0
#endif
#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2)
#ifdef CONFIG_STM32F7_TIM13_CHANNEL1
#ifdef CONFIG_STM32_TIM13_CHANNEL1
# define PWM_TIM13_CHANNEL1 1
#else
# define PWM_TIM13_CHANNEL1 0
#endif
#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1)
#ifdef CONFIG_STM32F7_TIM14_CHANNEL1
#ifdef CONFIG_STM32_TIM14_CHANNEL1
# define PWM_TIM14_CHANNEL1 1
#else
# define PWM_TIM14_CHANNEL1 0
#endif
#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1)
#else /* !CONFIG_STM32F7_PWM_MULTICHAN */
#else /* !CONFIG_STM32_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
@ -336,410 +336,410 @@
* not supported by this driver: Only one output channel per timer.
*/
#ifdef CONFIG_STM32F7_TIM1_PWM
# if !defined(CONFIG_STM32F7_TIM1_CHANNEL)
# error "CONFIG_STM32F7_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM1_CHANNEL == 1
# define CONFIG_STM32F7_TIM1_CHANNEL1 1
# define CONFIG_STM32F7_TIM1_CH1MODE CONFIG_STM32F7_TIM1_CHMODE
# elif CONFIG_STM32F7_TIM1_CHANNEL == 2
# define CONFIG_STM32F7_TIM1_CHANNEL2 1
# define CONFIG_STM32F7_TIM1_CH2MODE CONFIG_STM32F7_TIM1_CHMODE
# elif CONFIG_STM32F7_TIM1_CHANNEL == 3
# define CONFIG_STM32F7_TIM1_CHANNEL3 1
# define CONFIG_STM32F7_TIM1_CH3MODE CONFIG_STM32F7_TIM1_CHMODE
# elif CONFIG_STM32F7_TIM1_CHANNEL == 4
# define CONFIG_STM32F7_TIM1_CHANNEL4 1
# define CONFIG_STM32F7_TIM1_CH4MODE CONFIG_STM32F7_TIM1_CHMODE
#ifdef CONFIG_STM32_TIM1_PWM
# if !defined(CONFIG_STM32_TIM1_CHANNEL)
# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32_TIM1_CHANNEL == 1
# define CONFIG_STM32_TIM1_CHANNEL1 1
# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE
# elif CONFIG_STM32_TIM1_CHANNEL == 2
# define CONFIG_STM32_TIM1_CHANNEL2 1
# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE
# elif CONFIG_STM32_TIM1_CHANNEL == 3
# define CONFIG_STM32_TIM1_CHANNEL3 1
# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE
# elif CONFIG_STM32_TIM1_CHANNEL == 4
# define CONFIG_STM32_TIM1_CHANNEL4 1
# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM1_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
# endif
# define PWM_TIM1_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM2_PWM
# if !defined(CONFIG_STM32F7_TIM2_CHANNEL)
# error "CONFIG_STM32F7_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM2_CHANNEL == 1
# define CONFIG_STM32F7_TIM2_CHANNEL1 1
# define CONFIG_STM32F7_TIM2_CH1MODE CONFIG_STM32F7_TIM2_CHMODE
# elif CONFIG_STM32F7_TIM2_CHANNEL == 2
# define CONFIG_STM32F7_TIM2_CHANNEL2 1
# define CONFIG_STM32F7_TIM2_CH2MODE CONFIG_STM32F7_TIM2_CHMODE
# elif CONFIG_STM32F7_TIM2_CHANNEL == 3
# define CONFIG_STM32F7_TIM2_CHANNEL3 1
# define CONFIG_STM32F7_TIM2_CH3MODE CONFIG_STM32F7_TIM2_CHMODE
# elif CONFIG_STM32F7_TIM2_CHANNEL == 4
# define CONFIG_STM32F7_TIM2_CHANNEL4 1
# define CONFIG_STM32F7_TIM2_CH4MODE CONFIG_STM32F7_TIM2_CHMODE
#ifdef CONFIG_STM32_TIM2_PWM
# if !defined(CONFIG_STM32_TIM2_CHANNEL)
# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32_TIM2_CHANNEL == 1
# define CONFIG_STM32_TIM2_CHANNEL1 1
# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE
# elif CONFIG_STM32_TIM2_CHANNEL == 2
# define CONFIG_STM32_TIM2_CHANNEL2 1
# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE
# elif CONFIG_STM32_TIM2_CHANNEL == 3
# define CONFIG_STM32_TIM2_CHANNEL3 1
# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE
# elif CONFIG_STM32_TIM2_CHANNEL == 4
# define CONFIG_STM32_TIM2_CHANNEL4 1
# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM2_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
# endif
# define PWM_TIM2_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM3_PWM
# if !defined(CONFIG_STM32F7_TIM3_CHANNEL)
# error "CONFIG_STM32F7_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM3_CHANNEL == 1
# define CONFIG_STM32F7_TIM3_CHANNEL1 1
# define CONFIG_STM32F7_TIM3_CH1MODE CONFIG_STM32F7_TIM3_CHMODE
# elif CONFIG_STM32F7_TIM3_CHANNEL == 2
# define CONFIG_STM32F7_TIM3_CHANNEL2 1
# define CONFIG_STM32F7_TIM3_CH2MODE CONFIG_STM32F7_TIM3_CHMODE
# elif CONFIG_STM32F7_TIM3_CHANNEL == 3
# define CONFIG_STM32F7_TIM3_CHANNEL3 1
# define CONFIG_STM32F7_TIM3_CH3MODE CONFIG_STM32F7_TIM3_CHMODE
# elif CONFIG_STM32F7_TIM3_CHANNEL == 4
# define CONFIG_STM32F7_TIM3_CHANNEL4 1
# define CONFIG_STM32F7_TIM3_CH4MODE CONFIG_STM32F7_TIM3_CHMODE
#ifdef CONFIG_STM32_TIM3_PWM
# if !defined(CONFIG_STM32_TIM3_CHANNEL)
# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32_TIM3_CHANNEL == 1
# define CONFIG_STM32_TIM3_CHANNEL1 1
# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE
# elif CONFIG_STM32_TIM3_CHANNEL == 2
# define CONFIG_STM32_TIM3_CHANNEL2 1
# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE
# elif CONFIG_STM32_TIM3_CHANNEL == 3
# define CONFIG_STM32_TIM3_CHANNEL3 1
# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE
# elif CONFIG_STM32_TIM3_CHANNEL == 4
# define CONFIG_STM32_TIM3_CHANNEL4 1
# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM3_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
# endif
# define PWM_TIM3_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM4_PWM
# if !defined(CONFIG_STM32F7_TIM4_CHANNEL)
# error "CONFIG_STM32F7_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM4_CHANNEL == 1
# define CONFIG_STM32F7_TIM4_CHANNEL1 1
# define CONFIG_STM32F7_TIM4_CH1MODE CONFIG_STM32F7_TIM4_CHMODE
# elif CONFIG_STM32F7_TIM4_CHANNEL == 2
# define CONFIG_STM32F7_TIM4_CHANNEL2 1
# define CONFIG_STM32F7_TIM4_CH2MODE CONFIG_STM32F7_TIM4_CHMODE
# elif CONFIG_STM32F7_TIM4_CHANNEL == 3
# define CONFIG_STM32F7_TIM4_CHANNEL3 1
# define CONFIG_STM32F7_TIM4_CH3MODE CONFIG_STM32F7_TIM4_CHMODE
# elif CONFIG_STM32F7_TIM4_CHANNEL == 4
# define CONFIG_STM32F7_TIM4_CHANNEL4 1
# define CONFIG_STM32F7_TIM4_CH4MODE CONFIG_STM32F7_TIM4_CHMODE
#ifdef CONFIG_STM32_TIM4_PWM
# if !defined(CONFIG_STM32_TIM4_CHANNEL)
# error "CONFIG_STM32_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32_TIM4_CHANNEL == 1
# define CONFIG_STM32_TIM4_CHANNEL1 1
# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE
# elif CONFIG_STM32_TIM4_CHANNEL == 2
# define CONFIG_STM32_TIM4_CHANNEL2 1
# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE
# elif CONFIG_STM32_TIM4_CHANNEL == 3
# define CONFIG_STM32_TIM4_CHANNEL3 1
# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE
# elif CONFIG_STM32_TIM4_CHANNEL == 4
# define CONFIG_STM32_TIM4_CHANNEL4 1
# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM4_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL"
# endif
# define PWM_TIM4_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM5_PWM
# if !defined(CONFIG_STM32F7_TIM5_CHANNEL)
# error "CONFIG_STM32F7_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM5_CHANNEL == 1
# define CONFIG_STM32F7_TIM5_CHANNEL1 1
# define CONFIG_STM32F7_TIM5_CH1MODE CONFIG_STM32F7_TIM5_CHMODE
# elif CONFIG_STM32F7_TIM5_CHANNEL == 2
# define CONFIG_STM32F7_TIM5_CHANNEL2 1
# define CONFIG_STM32F7_TIM5_CH2MODE CONFIG_STM32F7_TIM5_CHMODE
# elif CONFIG_STM32F7_TIM5_CHANNEL == 3
# define CONFIG_STM32F7_TIM5_CHANNEL3 1
# define CONFIG_STM32F7_TIM5_CH3MODE CONFIG_STM32F7_TIM5_CHMODE
# elif CONFIG_STM32F7_TIM5_CHANNEL == 4
# define CONFIG_STM32F7_TIM5_CHANNEL4 1
# define CONFIG_STM32F7_TIM5_CH4MODE CONFIG_STM32F7_TIM5_CHMODE
#ifdef CONFIG_STM32_TIM5_PWM
# if !defined(CONFIG_STM32_TIM5_CHANNEL)
# error "CONFIG_STM32_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32_TIM5_CHANNEL == 1
# define CONFIG_STM32_TIM5_CHANNEL1 1
# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE
# elif CONFIG_STM32_TIM5_CHANNEL == 2
# define CONFIG_STM32_TIM5_CHANNEL2 1
# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE
# elif CONFIG_STM32_TIM5_CHANNEL == 3
# define CONFIG_STM32_TIM5_CHANNEL3 1
# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE
# elif CONFIG_STM32_TIM5_CHANNEL == 4
# define CONFIG_STM32_TIM5_CHANNEL4 1
# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM5_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL"
# endif
# define PWM_TIM5_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM8_PWM
# if !defined(CONFIG_STM32F7_TIM8_CHANNEL)
# error "CONFIG_STM32F7_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM8_CHANNEL == 1
# define CONFIG_STM32F7_TIM8_CHANNEL1 1
# define CONFIG_STM32F7_TIM8_CH1MODE CONFIG_STM32F7_TIM8_CHMODE
# elif CONFIG_STM32F7_TIM8_CHANNEL == 2
# define CONFIG_STM32F7_TIM8_CHANNEL2 1
# define CONFIG_STM32F7_TIM8_CH2MODE CONFIG_STM32F7_TIM8_CHMODE
# elif CONFIG_STM32F7_TIM8_CHANNEL == 3
# define CONFIG_STM32F7_TIM8_CHANNEL3 1
# define CONFIG_STM32F7_TIM8_CH3MODE CONFIG_STM32F7_TIM8_CHMODE
# elif CONFIG_STM32F7_TIM8_CHANNEL == 4
# define CONFIG_STM32F7_TIM8_CHANNEL4 1
# define CONFIG_STM32F7_TIM8_CH4MODE CONFIG_STM32F7_TIM8_CHMODE
#ifdef CONFIG_STM32_TIM8_PWM
# if !defined(CONFIG_STM32_TIM8_CHANNEL)
# error "CONFIG_STM32_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32_TIM8_CHANNEL == 1
# define CONFIG_STM32_TIM8_CHANNEL1 1
# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE
# elif CONFIG_STM32_TIM8_CHANNEL == 2
# define CONFIG_STM32_TIM8_CHANNEL2 1
# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE
# elif CONFIG_STM32_TIM8_CHANNEL == 3
# define CONFIG_STM32_TIM8_CHANNEL3 1
# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE
# elif CONFIG_STM32_TIM8_CHANNEL == 4
# define CONFIG_STM32_TIM8_CHANNEL4 1
# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM8_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL"
# endif
# define PWM_TIM8_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM9_PWM
# if !defined(CONFIG_STM32F7_TIM9_CHANNEL)
# error "CONFIG_STM32F7_TIM9_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM9_CHANNEL == 1
# define CONFIG_STM32F7_TIM9_CHANNEL1 1
# define CONFIG_STM32F7_TIM9_CH1MODE CONFIG_STM32F7_TIM9_CHMODE
# elif CONFIG_STM32F7_TIM9_CHANNEL == 2
# define CONFIG_STM32F7_TIM9_CHANNEL2 1
# define CONFIG_STM32F7_TIM9_CH2MODE CONFIG_STM32F7_TIM9_CHMODE
#ifdef CONFIG_STM32_TIM9_PWM
# if !defined(CONFIG_STM32_TIM9_CHANNEL)
# error "CONFIG_STM32_TIM9_CHANNEL must be provided"
# elif CONFIG_STM32_TIM9_CHANNEL == 1
# define CONFIG_STM32_TIM9_CHANNEL1 1
# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE
# elif CONFIG_STM32_TIM9_CHANNEL == 2
# define CONFIG_STM32_TIM9_CHANNEL2 1
# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM9_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL"
# endif
# define PWM_TIM9_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM10_PWM
# if !defined(CONFIG_STM32F7_TIM10_CHANNEL)
# error "CONFIG_STM32F7_TIM10_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM10_CHANNEL == 1
# define CONFIG_STM32F7_TIM10_CHANNEL1 1
# define CONFIG_STM32F7_TIM10_CH1MODE CONFIG_STM32F7_TIM10_CHMODE
#ifdef CONFIG_STM32_TIM10_PWM
# if !defined(CONFIG_STM32_TIM10_CHANNEL)
# error "CONFIG_STM32_TIM10_CHANNEL must be provided"
# elif CONFIG_STM32_TIM10_CHANNEL == 1
# define CONFIG_STM32_TIM10_CHANNEL1 1
# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM10_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL"
# endif
# define PWM_TIM10_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM11_PWM
# if !defined(CONFIG_STM32F7_TIM11_CHANNEL)
# error "CONFIG_STM32F7_TIM11_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM11_CHANNEL == 1
# define CONFIG_STM32F7_TIM11_CHANNEL1 1
# define CONFIG_STM32F7_TIM11_CH1MODE CONFIG_STM32F7_TIM11_CHMODE
#ifdef CONFIG_STM32_TIM11_PWM
# if !defined(CONFIG_STM32_TIM11_CHANNEL)
# error "CONFIG_STM32_TIM11_CHANNEL must be provided"
# elif CONFIG_STM32_TIM11_CHANNEL == 1
# define CONFIG_STM32_TIM11_CHANNEL1 1
# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM11_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL"
# endif
# define PWM_TIM11_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM12_PWM
# if !defined(CONFIG_STM32F7_TIM12_CHANNEL)
# error "CONFIG_STM32F7_TIM12_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM12_CHANNEL == 1
# define CONFIG_STM32F7_TIM12_CHANNEL1 1
# define CONFIG_STM32F7_TIM12_CH1MODE CONFIG_STM32F7_TIM12_CHMODE
# elif CONFIG_STM32F7_TIM12_CHANNEL == 2
# define CONFIG_STM32F7_TIM12_CHANNEL2 1
# define CONFIG_STM32F7_TIM12_CH2MODE CONFIG_STM32F7_TIM12_CHMODE
#ifdef CONFIG_STM32_TIM12_PWM
# if !defined(CONFIG_STM32_TIM12_CHANNEL)
# error "CONFIG_STM32_TIM12_CHANNEL must be provided"
# elif CONFIG_STM32_TIM12_CHANNEL == 1
# define CONFIG_STM32_TIM12_CHANNEL1 1
# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE
# elif CONFIG_STM32_TIM12_CHANNEL == 2
# define CONFIG_STM32_TIM12_CHANNEL2 1
# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM12_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL"
# endif
# define PWM_TIM12_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM13_PWM
# if !defined(CONFIG_STM32F7_TIM13_CHANNEL)
# error "CONFIG_STM32F7_TIM13_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM13_CHANNEL == 1
# define CONFIG_STM32F7_TIM13_CHANNEL1 1
# define CONFIG_STM32F7_TIM13_CH1MODE CONFIG_STM32F7_TIM13_CHMODE
#ifdef CONFIG_STM32_TIM13_PWM
# if !defined(CONFIG_STM32_TIM13_CHANNEL)
# error "CONFIG_STM32_TIM13_CHANNEL must be provided"
# elif CONFIG_STM32_TIM13_CHANNEL == 1
# define CONFIG_STM32_TIM13_CHANNEL1 1
# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM13_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL"
# endif
# define PWM_TIM13_NCHANNELS 1
#endif
#ifdef CONFIG_STM32F7_TIM14_PWM
# if !defined(CONFIG_STM32F7_TIM14_CHANNEL)
# error "CONFIG_STM32F7_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32F7_TIM14_CHANNEL == 1
# define CONFIG_STM32F7_TIM14_CHANNEL1 1
# define CONFIG_STM32F7_TIM14_CH1MODE CONFIG_STM32F7_TIM14_CHMODE
#ifdef CONFIG_STM32_TIM14_PWM
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32_TIM14_CHANNEL == 1
# define CONFIG_STM32_TIM14_CHANNEL1 1
# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE
# else
# error "Unsupported value of CONFIG_STM32F7_TIM14_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
# endif
# define PWM_TIM14_NCHANNELS 1
#endif
#endif /* CONFIG_STM32F7_PWM_MULTICHAN */
#endif /* CONFIG_STM32_PWM_MULTICHAN */
#ifdef CONFIG_STM32F7_TIM1_CH1OUT
#ifdef CONFIG_STM32_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
#else
# define PWM_TIM1_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CH1NOUT
#ifdef CONFIG_STM32_TIM1_CH1NOUT
# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT
#else
# define PWM_TIM1_CH1NCFG 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CH2OUT
#ifdef CONFIG_STM32_TIM1_CH2OUT
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
#else
# define PWM_TIM1_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CH2NOUT
#ifdef CONFIG_STM32_TIM1_CH2NOUT
# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT
#else
# define PWM_TIM1_CH2NCFG 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CH3OUT
#ifdef CONFIG_STM32_TIM1_CH3OUT
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
#else
# define PWM_TIM1_CH3CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CH3NOUT
#ifdef CONFIG_STM32_TIM1_CH3NOUT
# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT
#else
# define PWM_TIM1_CH3NCFG 0
#endif
#ifdef CONFIG_STM32F7_TIM1_CH4OUT
#ifdef CONFIG_STM32_TIM1_CH4OUT
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
#else
# define PWM_TIM1_CH4CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CH1OUT
#ifdef CONFIG_STM32_TIM2_CH1OUT
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
#else
# define PWM_TIM2_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CH2OUT
#ifdef CONFIG_STM32_TIM2_CH2OUT
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
#else
# define PWM_TIM2_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CH3OUT
#ifdef CONFIG_STM32_TIM2_CH3OUT
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
#else
# define PWM_TIM2_CH3CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM2_CH4OUT
#ifdef CONFIG_STM32_TIM2_CH4OUT
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
#else
# define PWM_TIM2_CH4CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CH1OUT
#ifdef CONFIG_STM32_TIM3_CH1OUT
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
#else
# define PWM_TIM3_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CH2OUT
#ifdef CONFIG_STM32_TIM3_CH2OUT
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
#else
# define PWM_TIM3_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CH3OUT
#ifdef CONFIG_STM32_TIM3_CH3OUT
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
#else
# define PWM_TIM3_CH3CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM3_CH4OUT
#ifdef CONFIG_STM32_TIM3_CH4OUT
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
#else
# define PWM_TIM3_CH4CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CH1OUT
#ifdef CONFIG_STM32_TIM4_CH1OUT
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
#else
# define PWM_TIM4_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CH2OUT
#ifdef CONFIG_STM32_TIM4_CH2OUT
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
#else
# define PWM_TIM4_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CH3OUT
#ifdef CONFIG_STM32_TIM4_CH3OUT
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
#else
# define PWM_TIM4_CH3CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM4_CH4OUT
#ifdef CONFIG_STM32_TIM4_CH4OUT
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
#else
# define PWM_TIM4_CH4CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CH1OUT
#ifdef CONFIG_STM32_TIM5_CH1OUT
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
#else
# define PWM_TIM5_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CH2OUT
#ifdef CONFIG_STM32_TIM5_CH2OUT
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
#else
# define PWM_TIM5_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CH3OUT
#ifdef CONFIG_STM32_TIM5_CH3OUT
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
#else
# define PWM_TIM5_CH3CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM5_CH4OUT
#ifdef CONFIG_STM32_TIM5_CH4OUT
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
#else
# define PWM_TIM5_CH4CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH1OUT
#ifdef CONFIG_STM32_TIM8_CH1OUT
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
#else
# define PWM_TIM8_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH1NOUT
#ifdef CONFIG_STM32_TIM8_CH1NOUT
# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT
#else
# define PWM_TIM8_CH1NCFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH2OUT
#ifdef CONFIG_STM32_TIM8_CH2OUT
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
#else
# define PWM_TIM8_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH2NOUT
#ifdef CONFIG_STM32_TIM8_CH2NOUT
# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT
#else
# define PWM_TIM8_CH2NCFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH3OUT
#ifdef CONFIG_STM32_TIM8_CH3OUT
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
#else
# define PWM_TIM8_CH3CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH3NOUT
#ifdef CONFIG_STM32_TIM8_CH3NOUT
# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT
#else
# define PWM_TIM8_CH3NCFG 0
#endif
#ifdef CONFIG_STM32F7_TIM8_CH4OUT
#ifdef CONFIG_STM32_TIM8_CH4OUT
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
#else
# define PWM_TIM8_CH4CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM9_CH1OUT
#ifdef CONFIG_STM32_TIM9_CH1OUT
# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
#else
# define PWM_TIM9_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM9_CH2OUT
#ifdef CONFIG_STM32_TIM9_CH2OUT
# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
#else
# define PWM_TIM9_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM10_CH1OUT
#ifdef CONFIG_STM32_TIM10_CH1OUT
# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
#else
# define PWM_TIM10_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM11_CH1OUT
#ifdef CONFIG_STM32_TIM11_CH1OUT
# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
#else
# define PWM_TIM11_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM12_CH1OUT
#ifdef CONFIG_STM32_TIM12_CH1OUT
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
#else
# define PWM_TIM12_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM12_CH2OUT
#ifdef CONFIG_STM32_TIM12_CH2OUT
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
#else
# define PWM_TIM12_CH2CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM13_CH1OUT
#ifdef CONFIG_STM32_TIM13_CH1OUT
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
#else
# define PWM_TIM13_CH1CFG 0
#endif
#ifdef CONFIG_STM32F7_TIM14_CH1OUT
#ifdef CONFIG_STM32_TIM14_CH1OUT
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
#else
# define PWM_TIM14_CH1CFG 0
@ -747,12 +747,12 @@
/* Complementary outputs support */
#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined(CONFIG_STM32F7_TIM1_CH2NOUT) || \
defined(CONFIG_STM32F7_TIM1_CH3NOUT)
#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \
defined(CONFIG_STM32_TIM1_CH3NOUT)
# define HAVE_TIM1_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32F7_TIM8_CH1NOUT) || defined(CONFIG_STM32F7_TIM8_CH2NOUT) || \
defined(CONFIG_STM32F7_TIM8_CH3NOUT)
#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \
defined(CONFIG_STM32_TIM8_CH3NOUT)
# define HAVE_TIM8_COMPLEMENTARY
#endif
#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY)
@ -761,7 +761,7 @@
/* Low-level ops helpers ****************************************************/
#ifdef CONFIG_STM32F7_PWM_LL_OPS
#ifdef CONFIG_STM32_PWM_LL_OPS
/* NOTE:
* low-level ops accept pwm_lowerhalf_s as first argument, but llops access
@ -786,7 +786,7 @@
(dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr)
#define PWM_RCR_GET(dev) \
(dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev)
#ifdef CONFIG_STM32F7_PWM_TRGO
#ifdef CONFIG_STM32_PWM_TRGO
# define PWM_TRGO_SET(dev, trgo) \
(dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo)
#endif
@ -898,7 +898,7 @@ enum stm32_pwm_output_e
/* 1 << 11 reserved - no complementary output for CH6 */
};
#ifdef CONFIG_STM32F7_PWM_LL_OPS
#ifdef CONFIG_STM32_PWM_LL_OPS
/* This structure provides the publicly visible representation of the
* "lower-half" PWM driver structure.
@ -954,7 +954,7 @@ struct stm32_pwm_ops_s
uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev);
#ifdef CONFIG_STM32F7_PWM_TRGO
#ifdef CONFIG_STM32_PWM_TRGO
/* Set TRGO/TRGO2 register */
int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo);
@ -998,7 +998,7 @@ struct stm32_pwm_ops_s
#endif
};
#endif /* CONFIG_STM32F7_PWM_LL_OPS */
#endif /* CONFIG_STM32_PWM_LL_OPS */
/****************************************************************************
* Public Data
@ -1044,5 +1044,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F7_PWM */
#endif /* CONFIG_STM32_PWM */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWM_H */

2
arch/arm/src/stm32f7/stm32_pwr.c
View file

@ -35,7 +35,7 @@
#include "arm_internal.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32F7_PWR)
#if defined(CONFIG_STM32_PWR)
/****************************************************************************
* Private Data

106
arch/arm/src/stm32f7/stm32_qencoder.c
View file

@ -60,14 +60,14 @@
/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */
#if defined(CONFIG_STM32F7_TIM2_QE) || defined(CONFIG_STM32F7_TIM5_QE)
#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE)
# define HAVE_32BIT_TIMERS 1
#endif
/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */
#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM3_QE) || \
defined(CONFIG_STM32F7_TIM4_QE) || defined(CONFIG_STM32F7_TIM8_QE)
#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \
defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE)
# define HAVE_16BIT_TIMERS 1
#endif
@ -89,51 +89,51 @@
/* Input filter *************************************************************/
#ifdef CONFIG_STM32F7_QENCODER_FILTER
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_1)
#ifdef CONFIG_STM32_QENCODER_FILTER
# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
# endif
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_CKINT)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_2)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_4)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8
# endif
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_2)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28
# endif
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_4)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48
# endif
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_8)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88
# endif
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_16)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168
# endif
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_32)
# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32)
# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326
# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8)
# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8)
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328
# endif
# endif
@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks =
/* Per-timer state structures */
#ifdef CONFIG_STM32F7_TIM1_QE
#ifdef CONFIG_STM32_TIM1_QE
static const struct stm32_qeconfig_s g_tim1config =
{
.timid = 1,
@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config =
.regaddr = STM32_RCC_APB2ENR,
.enable = RCC_APB2ENR_TIM1EN,
.base = STM32_TIM1_BASE,
.psc = CONFIG_STM32F7_TIM1_QEPSC,
.psc = CONFIG_STM32_TIM1_QEPSC,
.ti1cfg = GPIO_TIM1_CH1IN,
.ti2cfg = GPIO_TIM1_CH2IN,
};
@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower =
#endif
#ifdef CONFIG_STM32F7_TIM2_QE
#ifdef CONFIG_STM32_TIM2_QE
static const struct stm32_qeconfig_s g_tim2config =
{
.timid = 2,
@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config =
.regaddr = STM32_RCC_APB1ENR,
.enable = RCC_APB1ENR_TIM2EN,
.base = STM32_TIM2_BASE,
.psc = CONFIG_STM32F7_TIM2_QEPSC,
.psc = CONFIG_STM32_TIM2_QEPSC,
.ti1cfg = GPIO_TIM2_CH1IN,
.ti2cfg = GPIO_TIM2_CH2IN,
};
@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower =
#endif
#ifdef CONFIG_STM32F7_TIM3_QE
#ifdef CONFIG_STM32_TIM3_QE
static const struct stm32_qeconfig_s g_tim3config =
{
.timid = 3,
@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config =
.regaddr = STM32_RCC_APB1ENR,
.enable = RCC_APB1ENR_TIM3EN,
.base = STM32_TIM3_BASE,
.psc = CONFIG_STM32F7_TIM3_QEPSC,
.psc = CONFIG_STM32_TIM3_QEPSC,
.ti1cfg = GPIO_TIM3_CH1IN,
.ti2cfg = GPIO_TIM3_CH2IN,
};
@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower =
#endif
#ifdef CONFIG_STM32F7_TIM4_QE
#ifdef CONFIG_STM32_TIM4_QE
static const struct stm32_qeconfig_s g_tim4config =
{
.timid = 4,
@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config =
.regaddr = STM32_RCC_APB1ENR,
.enable = RCC_APB1ENR_TIM4EN,
.base = STM32_TIM4_BASE,
.psc = CONFIG_STM32F7_TIM4_QEPSC,
.psc = CONFIG_STM32_TIM4_QEPSC,
.ti1cfg = GPIO_TIM4_CH1IN,
.ti2cfg = GPIO_TIM4_CH2IN,
};
@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower =
#endif
#ifdef CONFIG_STM32F7_TIM5_QE
#ifdef CONFIG_STM32_TIM5_QE
static const struct stm32_qeconfig_s g_tim5config =
{
.timid = 5,
@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config =
.regaddr = STM32_RCC_APB1ENR,
.enable = RCC_APB1ENR_TIM5EN,
.base = STM32_TIM5_BASE,
.psc = CONFIG_STM32F7_TIM5_QEPSC,
.psc = CONFIG_STM32_TIM5_QEPSC,
.ti1cfg = GPIO_TIM5_CH1IN,
.ti2cfg = GPIO_TIM5_CH2IN,
};
@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower =
#endif
#ifdef CONFIG_STM32F7_TIM8_QE
#ifdef CONFIG_STM32_TIM8_QE
static const struct stm32_qeconfig_s g_tim8config =
{
.timid = 8,
@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config =
.regaddr = STM32_RCC_APB2ENR,
.enable = RCC_APB2ENR_TIM8EN,
.base = STM32_TIM8_BASE,
.psc = CONFIG_STM32F7_TIM8_QEPSC,
.psc = CONFIG_STM32_TIM8_QEPSC,
.ti1cfg = GPIO_TIM8_CH1IN,
.ti2cfg = GPIO_TIM8_CH2IN,
};
@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv,
stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET),
stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET));
#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE)
#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE)
if (priv->config->timid == 1 || priv->config->timid == 8)
{
sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim)
{
switch (tim)
{
#ifdef CONFIG_STM32F7_TIM1_QE
#ifdef CONFIG_STM32_TIM1_QE
case 1:
return &g_tim1lower;
#endif
#ifdef CONFIG_STM32F7_TIM2_QE
#ifdef CONFIG_STM32_TIM2_QE
case 2:
return &g_tim2lower;
#endif
#ifdef CONFIG_STM32F7_TIM3_QE
#ifdef CONFIG_STM32_TIM3_QE
case 3:
return &g_tim3lower;
#endif
#ifdef CONFIG_STM32F7_TIM4_QE
#ifdef CONFIG_STM32_TIM4_QE
case 4:
return &g_tim4lower;
#endif
#ifdef CONFIG_STM32F7_TIM5_QE
#ifdef CONFIG_STM32_TIM5_QE
case 5:
return &g_tim5lower;
#endif
#ifdef CONFIG_STM32F7_TIM8_QE
#ifdef CONFIG_STM32_TIM8_QE
case 8:
return &g_tim8lower;
#endif
@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower)
stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc);
#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE)
#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE)
if (priv->config->timid == 1 || priv->config->timid == 8)
{
/* Clear the Repetition Counter value */
@ -943,37 +943,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower)
switch (priv->config->timid)
{
#ifdef CONFIG_STM32F7_TIM1_QE
#ifdef CONFIG_STM32_TIM1_QE
case 1:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM1RST;
break;
#endif
#ifdef CONFIG_STM32F7_TIM2_QE
#ifdef CONFIG_STM32_TIM2_QE
case 2:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM2RST;
break;
#endif
#ifdef CONFIG_STM32F7_TIM3_QE
#ifdef CONFIG_STM32_TIM3_QE
case 3:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM3RST;
break;
#endif
#ifdef CONFIG_STM32F7_TIM4_QE
#ifdef CONFIG_STM32_TIM4_QE
case 4:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM4RST;
break;
#endif
#ifdef CONFIG_STM32F7_TIM5_QE
#ifdef CONFIG_STM32_TIM5_QE
case 5:
regaddr = STM32_RCC_APB1RSTR;
resetbit = RCC_APB1RSTR_TIM5RST;
break;
#endif
#ifdef CONFIG_STM32F7_TIM8_QE
#ifdef CONFIG_STM32_TIM8_QE
case 8:
regaddr = STM32_RCC_APB2RSTR;
resetbit = RCC_APB2RSTR_TIM8RST;

24
arch/arm/src/stm32f7/stm32_qencoder.h
View file

@ -43,23 +43,23 @@
* timer "n" is intended to be used for as a quadrature encoder.
*/
#ifndef CONFIG_STM32F7_TIM1
# undef CONFIG_STM32F7_TIM1_QE
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_QE
#endif
#ifndef CONFIG_STM32F7_TIM2
# undef CONFIG_STM32F7_TIM2_QE
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_QE
#endif
#ifndef CONFIG_STM32F7_TIM3
# undef CONFIG_STM32F7_TIM3_QE
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_QE
#endif
#ifndef CONFIG_STM32F7_TIM4
# undef CONFIG_STM32F7_TIM4_QE
#ifndef CONFIG_STM32_TIM4
# undef CONFIG_STM32_TIM4_QE
#endif
#ifndef CONFIG_STM32F7_TIM5
# undef CONFIG_STM32F7_TIM5_QE
#ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_QE
#endif
#ifndef CONFIG_STM32F7_TIM8
# undef CONFIG_STM32F7_TIM8_QE
#ifndef CONFIG_STM32_TIM8
# undef CONFIG_STM32_TIM8_QE
#endif
/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder

102
arch/arm/src/stm32f7/stm32_qspi.c
View file

@ -56,7 +56,7 @@
#include "stm32_rcc.h"
#include "hardware/stm32_qspi.h"
#ifdef CONFIG_STM32F7_QSPI
#ifdef CONFIG_STM32_QSPI
/****************************************************************************
* Pre-processor Definitions
@ -67,7 +67,7 @@
/* Check if QSPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
# undef CONFIG_STM32F7_QSPI_DMADEBUG
# undef CONFIG_STM32_QSPI_DMADEBUG
#endif
#define DMA_INITIAL 0
@ -80,7 +80,7 @@
/* Can't have both interrupt-driven QSPI and DMA QSPI */
#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) && defined(CONFIG_STM32F7_QSPI_DMA)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for QSPI"
#endif
@ -92,7 +92,7 @@
GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h
#endif
#ifdef CONFIG_STM32F7_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
# ifdef DMAMAP_QUADSPI
@ -104,26 +104,26 @@
# define DMACHAN_QUADSPI DMAMAP_QUADSPI
# endif
# if defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_LOW)
# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW)
# define QSPI_DMA_PRIO DMA_SCR_PRILO
# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_MEDIUM)
# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM)
# define QSPI_DMA_PRIO DMA_SCR_PRIMED
# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_HIGH)
# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH)
# define QSPI_DMA_PRIO DMA_SCR_PRIHI
# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_VERYHIGH)
# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH)
# define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI
# else
# define QSPI_DMA_PRIO DMA_SCR_PRIMED
# endif
#endif /* CONFIG_STM32F7_QSPI_DMA */
#endif /* CONFIG_STM32_QSPI_DMA */
#ifndef STM32_SYSCLK_FREQUENCY
# error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY
#endif
#if !defined(CONFIG_STM32F7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32F7_QSPI_FLASH_SIZE
# error you must specify a positive flash size via CONFIG_STM32F7_QSPI_FLASH_SIZE
#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE
# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE
#endif
/* DMA timeout. The value is not critical; we just don't want the system to
@ -164,14 +164,14 @@ struct stm32f7_qspidev_s
mutex_t lock; /* Assures mutually exclusive access to QSPI */
bool memmap; /* TRUE: Controller is in memory mapped mode */
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
xcpt_t handler; /* Interrupt handler */
uint8_t irq; /* Interrupt number */
sem_t op_sem; /* Block until complete */
struct qspi_xctnspec_s *xctn; /* context of transaction in progress */
#endif
#ifdef CONFIG_STM32F7_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
bool candma; /* DMA is supported */
sem_t dmawait; /* Used to wait for DMA completion */
int result; /* DMA result */
@ -181,11 +181,11 @@ struct stm32f7_qspidev_s
/* Debug stuff */
#ifdef CONFIG_STM32F7_QSPI_DMADEBUG
#ifdef CONFIG_STM32_QSPI_DMADEBUG
struct stm32f7_dmaregs_s dmaregs[DMA_NSAMPLES];
#endif
#ifdef CONFIG_STM32F7_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
bool wrlast; /* Last was a write */
uint32_t addresslast; /* Last address */
uint32_t valuelast; /* Last value */
@ -222,7 +222,7 @@ struct qspi_xctnspec_s
uint8_t isddr; /* true if 'double data rate' */
uint8_t issioo; /* true if 'send instruction only once' mode */
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
uint8_t function; /* functional mode; to distinguish a read or write */
int8_t disposition; /* how it all turned out */
uint32_t idxnow; /* index into databuffer of current byte in transfer */
@ -235,7 +235,7 @@ struct qspi_xctnspec_s
/* Helpers */
#ifdef CONFIG_STM32F7_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr,
uint32_t value, uint32_t address);
#else
@ -262,16 +262,16 @@ static void qspi_dumpgpioconfig(const char *msg);
/* Interrupts */
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
static int qspi0_interrupt(int irq, void *context, void *arg);
#endif
/* DMA support */
#ifdef CONFIG_STM32F7_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
# ifdef CONFIG_STM32F7_QSPI_DMADEBUG
# ifdef CONFIG_STM32_QSPI_DMADEBUG
# define qspi_dma_sample(s,i) stm32f7_dmasample((s)->dmach, &(s)->dmaregs[i])
static void qspi_dma_sampleinit(struct stm32f7_qspidev_s *priv);
static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv);
@ -281,8 +281,8 @@ static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv);
# define qspi_dma_sampledone(s)
# endif
# ifndef CONFIG_STM32F7_QSPI_DMATHRESHOLD
# define CONFIG_STM32F7_QSPI_DMATHRESHOLD 4
# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD
# define CONFIG_STM32_QSPI_DMATHRESHOLD 4
# endif
#endif
@ -336,13 +336,13 @@ static struct stm32f7_qspidev_s g_qspi0dev =
},
.base = STM32_QUADSPI_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
.handler = qspi0_interrupt,
.irq = STM32_IRQ_QUADSPI,
.op_sem = SEM_INITIALIZER(0),
#endif
.intf = 0,
#ifdef CONFIG_STM32F7_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
.candma = true,
.dmawait = SEM_INITIALIZER(0),
#endif
@ -368,7 +368,7 @@ static struct stm32f7_qspidev_s g_qspi0dev =
*
****************************************************************************/
#ifdef CONFIG_STM32F7_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr,
uint32_t value, uint32_t address)
{
@ -420,7 +420,7 @@ static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv,
uint32_t address = priv->base + offset;
uint32_t value = getreg32(address);
#ifdef CONFIG_STM32F7_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
if (qspi_checkreg(priv, false, value, address))
{
spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value);
@ -443,7 +443,7 @@ static inline void qspi_putreg(struct stm32f7_qspidev_s *priv,
{
uint32_t address = priv->base + offset;
#ifdef CONFIG_STM32F7_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
if (qspi_checkreg(priv, true, value, address))
{
spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value);
@ -625,7 +625,7 @@ static void qspi_dumpgpioconfig(const char *msg)
}
#endif
#ifdef CONFIG_STM32F7_QSPI_DMADEBUG
#ifdef CONFIG_STM32_QSPI_DMADEBUG
/****************************************************************************
* Name: qspi_dma_sampleinit
*
@ -831,7 +831,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
xctn->isddr = 0;
}
#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS)
xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR :
CCR_FMODE_INDRD;
xctn->disposition = - EIO;
@ -962,7 +962,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
xctn->isddr = 0;
#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS)
xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR :
CCR_FMODE_INDRD;
xctn->disposition = - EIO;
@ -1086,7 +1086,7 @@ static void qspi_ccrconfig(struct stm32f7_qspidev_s *priv,
}
}
#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS)
/****************************************************************************
* Name: qspi0_interrupt
*
@ -1313,7 +1313,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
return OK;
}
#elif defined(CONFIG_STM32F7_QSPI_DMA)
#elif defined(CONFIG_STM32_QSPI_DMA)
/****************************************************************************
* Name: qspi_dma_timeout
*
@ -1579,7 +1579,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv,
}
#endif
#if !defined(CONFIG_STM32F7_QSPI_INTERRUPTS)
#if !defined(CONFIG_STM32_QSPI_INTERRUPTS)
/****************************************************************************
* Name: qspi_receive_blocking
*
@ -2011,7 +2011,7 @@ static int qspi_command(struct qspi_dev_s *dev,
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
STM32_QUADSPI_FCR_OFFSET);
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* interrupt mode will need access to the transaction context */
priv->xctn = &xctn;
@ -2192,7 +2192,7 @@ static int qspi_memory(struct qspi_dev_s *dev,
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
STM32_QUADSPI_FCR_OFFSET);
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* interrupt mode will need access to the transaction context */
priv->xctn = &xctn;
@ -2253,11 +2253,11 @@ static int qspi_memory(struct qspi_dev_s *dev,
ret = xctn.disposition;
#elif defined(CONFIG_STM32F7_QSPI_DMA)
#elif defined(CONFIG_STM32_QSPI_DMA)
/* Can we perform DMA? Should we perform DMA? */
if (priv->candma &&
meminfo->buflen > CONFIG_STM32F7_QSPI_DMATHRESHOLD &&
meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD &&
IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
IS_ALIGNED(meminfo->buflen, 4))
{
@ -2419,18 +2419,18 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv)
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE |
QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM);
#if defined(CONFIG_STM32F7_QSPI_MODE_BANK2)
#if defined(CONFIG_STM32_QSPI_MODE_BANK2)
regval |= QSPI_CR_FSEL;
#endif
#if defined(CONFIG_STM32F7_QSPI_MODE_DUAL)
#if defined(CONFIG_STM32_QSPI_MODE_DUAL)
regval |= QSPI_CR_DFM;
#endif
/* Configure QSPI FIFO Threshold */
regval &= ~(QSPI_CR_FTHRES_MASK);
regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1)
regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1)
<< QSPI_CR_FTHRES_SHIFT);
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
@ -2451,10 +2451,10 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv)
regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET);
regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK);
regval |= (0x00);
regval |= ((CONFIG_STM32F7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT);
if (0 != CONFIG_STM32F7_QSPI_FLASH_SIZE)
regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT);
if (0 != CONFIG_STM32_QSPI_FLASH_SIZE)
{
unsigned int nsize = CONFIG_STM32F7_QSPI_FLASH_SIZE;
unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE;
int nlog2size = 31;
while ((nsize & 0x80000000) == 0)
@ -2560,7 +2560,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
{
/* Now perform one time initialization. */
#ifdef CONFIG_STM32F7_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
/* Pre-allocate DMA channels. */
if (priv->candma)
@ -2574,7 +2574,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
}
#endif
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* Attach the interrupt handler */
ret = irq_attach(priv->irq, priv->handler, NULL);
@ -2600,7 +2600,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
priv->initialized = true;
priv->memmap = false;
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
up_enable_irq(priv->irq);
#endif
}
@ -2608,12 +2608,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
return &priv->qspi;
errout_with_irq:
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
irq_detach(priv->irq);
errout_with_dmach:
#endif
#ifdef CONFIG_STM32F7_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
if (priv->dmach)
{
stm32_dmafree(priv->dmach);
@ -2679,7 +2679,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev,
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET);
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* Enable Timeout interrupt */
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
@ -2698,7 +2698,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev,
qspi_setupxctnfrommem(&xctn, meminfo);
#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
priv->xctn = NULL;
#endif
@ -2744,4 +2744,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev)
qspi_lock(dev, false);
}
#endif /* CONFIG_STM32F7_QSPI */
#endif /* CONFIG_STM32_QSPI */

4
arch/arm/src/stm32f7/stm32_qspi.h
View file

@ -35,7 +35,7 @@
#include "chip.h"
#ifdef CONFIG_STM32F7_QSPI
#ifdef CONFIG_STM32_QSPI
/****************************************************************************
* Pre-processor Definitions
@ -127,5 +127,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32F7_QSPI */
#endif /* CONFIG_STM32_QSPI */
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_QSPI_H */

18
arch/arm/src/stm32f7/stm32_rcc.c
View file

@ -63,11 +63,11 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
/* Include chip-specific clocking initialization logic */
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX)
# include "stm32f72xx73xx_rcc.c"
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
# include "stm32f74xx75xx_rcc.c"
#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
# include "stm32f76xx77xx_rcc.c"
#else
# error "Unsupported STM32 F7 chip"
@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configurationfile.
*
* If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
@ -104,14 +104,14 @@ void stm32_clockconfig(void)
rcc_reset();
#if defined(CONFIG_STM32F7_PWR)
#if defined(CONFIG_STM32_PWR)
/* Insure the bkp is initialized */
stm32_pwr_initbkp(false);
#endif
#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@ -131,7 +131,7 @@ void stm32_clockconfig(void)
rcc_enableperipherals();
#ifdef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION
#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
stm32_iocompensation();
@ -151,7 +151,7 @@ void stm32_clockconfig(void)
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
@ -166,7 +166,7 @@ void stm32_clockconfig(void)
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */

16
arch/arm/src/stm32f7/stm32_rcc.h
View file

@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div)
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will be
* enabled by an externally provided, board-specific function called
* stm32_board_clockconfig().
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
* Input Parameters:
* None
@ -147,7 +147,7 @@ void stm32_clockconfig(void);
*
****************************************************************************/
#ifdef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG
#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
@ -164,9 +164,9 @@ void stm32_board_clockconfig(void);
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will
* be enabled by an externally provided, board-specific function called
* stm32_board_clockconfig().
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called stm32_board_clockconfig().
*
* Input Parameters:
* None
@ -216,7 +216,7 @@ void stm32_rcc_enablelsi(void);
void stm32_rcc_disablelsi(void);
#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX)
/****************************************************************************
* Name: stm32_rcc_dsisrcphy
*

4
arch/arm/src/stm32f7/stm32_rng.c
View file

@ -40,7 +40,7 @@
#include "hardware/stm32_rng.h"
#include "arm_internal.h"
#if defined(CONFIG_STM32F7_RNG)
#if defined(CONFIG_STM32_RNG)
#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
/****************************************************************************
@ -329,4 +329,4 @@ void devurandom_register(void)
#endif
#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
#endif /* CONFIG_STM32F7_RNG */
#endif /* CONFIG_STM32_RNG */

44
arch/arm/src/stm32f7/stm32_rtc.c
View file

@ -44,7 +44,7 @@
#include <arch/board/board.h>
#ifdef CONFIG_STM32F7_RTC
#ifdef CONFIG_STM32_RTC
/****************************************************************************
* Pre-processor Definitions
@ -65,17 +65,17 @@
# error "CONFIG_RTC_HIRES must NOT be set with this driver"
#endif
#ifndef CONFIG_STM32F7_PWR
# error "CONFIG_STM32F7_PWR must selected to use this driver"
#ifndef CONFIG_STM32_PWR
# error "CONFIG_STM32_PWR must selected to use this driver"
#endif
/* Constants ****************************************************************/
#if defined(CONFIG_STM32F7_RTC_HSECLOCK)
#if defined(CONFIG_STM32_RTC_HSECLOCK)
# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE
#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
#elif defined(CONFIG_STM32_RTC_LSICLOCK)
# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI
#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
#elif defined(CONFIG_STM32_RTC_LSECLOCK)
# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE
#else
# warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count"
@ -491,7 +491,7 @@ static int rtc_setup(void)
/* Configure RTC pre-scaler with the required values */
#ifdef CONFIG_STM32F7_RTC_HSECLOCK
#ifdef CONFIG_STM32_RTC_HSECLOCK
/* STMicro app note AN4759 suggests using 7999 and 124 to
* get exactly 1MHz when using the RTC at 8MHz.
*/
@ -940,17 +940,17 @@ int up_rtc_initialize(void)
* external high rate clock
*/
#ifdef CONFIG_STM32F7_RTC_HSECLOCK
#ifdef CONFIG_STM32_RTC_HSECLOCK
/* Use the HSE clock as the input to the RTC block */
rtc_dumpregs("On reset HSE");
#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
#elif defined(CONFIG_STM32_RTC_LSICLOCK)
/* Use the LSI clock as the input to the RTC block */
rtc_dumpregs("On reset LSI");
#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
#elif defined(CONFIG_STM32_RTC_LSECLOCK)
/* Use the LSE clock as the input to the RTC block */
rtc_dumpregs("On reset LSE");
@ -1102,7 +1102,7 @@ int up_rtc_initialize(void)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec)
#else
int up_rtc_getdatetime(struct tm *tp)
@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp)
uint32_t dr;
uint32_t tr;
uint32_t tmp;
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
uint32_t ssr;
uint32_t prediv_s;
uint32_t usecs;
@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp)
{
dr = getreg32(STM32_RTC_DR);
tr = getreg32(STM32_RTC_TR);
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
ssr = getreg32(STM32_RTC_SSR);
tmp = getreg32(STM32_RTC_TR);
if (tmp != tr)
@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp)
clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900));
tp->tm_isdst = 0;
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
/* Return RTC sub-seconds if a non-NULL value
* of nsec has been provided to receive the sub-second value.
*/
@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp)
}
rtc_dumptime((const struct tm *)tp, &usecs, "Returning");
#else /* CONFIG_STM32F7_HAVE_RTC_SUBSECONDS */
#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */
rtc_dumptime((const struct tm *)tp, NULL, "Returning");
#endif
@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp)
*
****************************************************************************/
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
int up_rtc_getdatetime(struct tm *tp)
{
return stm32_rtc_getdatetime_with_subseconds(tp, NULL);
@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp)
****************************************************************************/
#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS
# ifndef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
# error "Invalid config, enable CONFIG_STM32F7_HAVE_RTC_SUBSECONDS."
# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS
# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS."
# endif
int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec)
{
@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period,
uint32_t secs;
uint32_t millisecs;
#if defined(CONFIG_STM32F7_RTC_HSECLOCK)
#if defined(CONFIG_STM32_RTC_HSECLOCK)
# error "Periodic wakeup not available for HSE"
#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
#elif defined(CONFIG_STM32_RTC_LSICLOCK)
# error "Periodic wakeup not available for LSI (and it is too inaccurate!)"
#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
#elif defined(CONFIG_STM32_RTC_LSECLOCK)
const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu /
STM32_LSE_FREQUENCY;
#else
@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void)
}
#endif
#endif /* CONFIG_STM32F7_RTC */
#endif /* CONFIG_STM32_RTC */

20
arch/arm/src/stm32f7/stm32_rtc.h
View file

@ -46,21 +46,21 @@
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if !defined(CONFIG_STM32F7_RTC_MAGIC)
# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed)
#if !defined(CONFIG_STM32_RTC_MAGIC)
# define CONFIG_STM32_RTC_MAGIC (0xfacefeed)
#endif
#if !defined(CONFIG_STM32F7_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32F7_RTC_MAGIC_TIME_SET (0xf00dface)
#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface)
#endif
#if !defined(CONFIG_STM32F7_RTC_MAGIC_REG)
# define CONFIG_STM32F7_RTC_MAGIC_REG (0)
#if !defined(CONFIG_STM32_RTC_MAGIC_REG)
# define CONFIG_STM32_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC CONFIG_STM32F7_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_STM32F7_RTC_MAGIC_TIME_SET
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32F7_RTC_MAGIC_REG)
#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG)
/****************************************************************************
* Public Types
@ -106,7 +106,7 @@ extern "C"
*
****************************************************************************/
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec);
#endif

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