diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index 0d552320695..e7c04a2f3e3 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -262,7 +262,7 @@ the buffers to the Cortex-M7 D-Cache line size: #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) - #ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC + #ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -274,10 +274,10 @@ the buffers to the Cortex-M7 D-Cache line size: #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) - #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) - #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) + #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NRXDESC) + #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NTXDESC) - #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) + #define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -366,8 +366,8 @@ Here is an example where the RX descriptors are invalidated: for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { ... diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst index 7beb7bb52a0..0243fbc5dec 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst @@ -177,7 +177,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -213,7 +213,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst index f9ce45c6e3b..f010732432a 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst @@ -219,7 +219,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -255,7 +255,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst index ef64085ad76..addc01caee4 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst @@ -221,7 +221,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -257,7 +257,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst index d510c3e4981..dbe20d4247b 100644 --- a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst @@ -129,9 +129,9 @@ configuration no builtin applications are selected. And these for enabling the STM32 timer PWM channel: - CONFIG_STM32F7_TIM1=y - CONFIG_STM32F7_TIM1_PWM=y - CONFIG_STM32F7_TIM1_CHANNEL=4 + CONFIG_STM32_TIM1=y + CONFIG_STM32_TIM1_PWM=y + CONFIG_STM32_TIM1_CHANNEL=4 nsh-ehternet ------------ diff --git a/Documentation/platforms/arm/stm32f7/index.rst b/Documentation/platforms/arm/stm32f7/index.rst index 5669353e6a0..6f525e8e2fe 100644 --- a/Documentation/platforms/arm/stm32f7/index.rst +++ b/Documentation/platforms/arm/stm32f7/index.rst @@ -106,7 +106,7 @@ managed with dtcm_malloc(), dtcm_free(), etc. In order to use FMC SRAM, the following additional things need to be present in the NuttX configuration file: -- CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the +- CONFIG_STM32_FMC_SRAM - Indicates that SRAM is available via the FMC (as opposed to an LCD or FLASH). - CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex) @@ -123,10 +123,10 @@ present in the NuttX configuration file: Clock ----- -- CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG - Enables special STM32F7 clock +- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock configuration features.:: - CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG=n + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n - CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops @@ -134,23 +134,23 @@ Timers ------ Timer devices may be used for different purposes. One special purpose is -to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn +to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn is defined (as above) then the following may also be defined to indicate that the timer is intended to be used for pulsed output modulation, ADC conversion, or DAC conversion. Note that ADC/DAC require two definition: Not only do you have to assign the timer (n) for used by the ADC or DAC, but then you also have to configure which ADC or DAC (m) it is assigned to.: -- CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 -- CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 -- CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 +- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 +- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 +- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 +- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 +- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 For each timer that is enabled for PWM usage, we need the following additional configuration settings: -- CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} +- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} NOTE: The STM32 timers are each capable of generating different signals on each of the four channels with different duty cycles. That capability is @@ -206,11 +206,11 @@ CAN - CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined. -- CONFIG_STM32F7_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 +- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 -- CONFIG_STM32F7_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 +- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 -- CONFIG_STM32F7_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an +- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an dump of all CAN registers. CAN SocketCAN @@ -221,12 +221,12 @@ TODO SPI --- -- CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI +- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI support. Non-interrupt-driven, poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -- CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance. - Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT. +- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance. + Cannot be used with CONFIG_STM32_SPI_INTERRUPT. SDIO ---- @@ -238,41 +238,41 @@ ETH Options: -- CONFIG_STM32F7_PHYADDR - The 5-bit address of the PHY on the board +- CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board -- CONFIG_STM32F7_MII - Support Ethernet MII interface +- CONFIG_STM32_MII - Support Ethernet MII interface -- CONFIG_STM32F7_MII_MCO1 - Use MCO1 to clock the MII interface +- CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface -- CONFIG_STM32F7_MII_MCO2 - Use MCO2 to clock the MII interface +- CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface -- CONFIG_STM32F7_RMII - Support Ethernet RMII interface +- CONFIG_STM32_RMII - Support Ethernet RMII interface -- CONFIG_STM32F7_AUTONEG - Use PHY autonegotiation to determine speed and mode +- CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode -- CONFIG_STM32F7_ETHFD - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select full duplex mode. Default: half-duplex -- CONFIG_STM32F7_ETH100MBPS - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select 100 MBps speed. Default: 10 Mbps -- CONFIG_STM32F7_PHYSR - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is defined. The PHY status register address may diff from PHY to PHY. This configuration sets the address of the PHY status register. -- CONFIG_STM32F7_PHYSR_SPEED - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides bit mask indicating 10 or 100MBps speed. -- CONFIG_STM32F7_PHYSR_100MBPS - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the speed bit(s) indicating 100MBps speed. -- CONFIG_STM32F7_PHYSR_MODE - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is defined. This provide bit mask indicating full or half duplex modes. -- CONFIG_STM32F7_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the mode bits indicating full duplex mode. -- CONFIG_STM32F7_ETH_PTP - Precision Time Protocol (PTP). Not supported +- CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported but some hooks are indicated with this condition. USB OTG FS @@ -284,30 +284,30 @@ Pre-requisites: - CONFIG_USBDEV - Enable USB device support - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block -- CONFIG_STM32F7_SYSCFG - Needed +- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block +- CONFIG_STM32_SYSCFG - Needed - CONFIG_SCHED_WORKQUEUE - Worker thread support is required Options: -- CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. +- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) -- CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO +- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit +- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 +- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 -- CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever +- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever want to do that? -- CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access +- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. -- CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB +- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB packets. Depends on CONFIG_DEBUG_FEATURES. USB OTG HS @@ -353,16 +353,16 @@ Available for some Nucleo boards. The builtin SPI test facility can be enabled with the following settings:: - +CONFIG_STM32F7_SPI=y - +CONFIG_STM32F7_SPI1=y - +CONFIG_STM32F7_SPI2=y - +CONFIG_STM32F7_SPI3=y + +CONFIG_STM32_SPI=y + +CONFIG_STM32_SPI1=y + +CONFIG_STM32_SPI2=y + +CONFIG_STM32_SPI3=y - +# CONFIG_STM32F7_SPI_INTERRUPTS is not set - +# CONFIG_STM32F7_SPI1_DMA is not set - +# CONFIG_STM32F7_SPI2_DMA is not set - +# CONFIG_STM32F7_SPI3_DMA is not set - # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set + +# CONFIG_STM32_SPI_INTERRUPTS is not set + +# CONFIG_STM32_SPI1_DMA is not set + +# CONFIG_STM32_SPI2_DMA is not set + +# CONFIG_STM32_SPI3_DMA is not set + # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_NUCLEO_SPI_TEST=y +CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d6d54a5fd26..2def7a21314 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -622,6 +622,7 @@ config ARCH_CHIP_STM32C0 config ARCH_CHIP_STM32F7 bool "STMicro STM32 F7" + select ARCH_CHIP_STM32 select ARCH_CORTEXM7 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 99047dd9757..9fe7f2cd2e0 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -264,7 +264,7 @@ /* Size SRAM */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -277,7 +277,7 @@ # else # define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -290,7 +290,7 @@ # else # define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -309,7 +309,7 @@ /* Common to all Advanced (vs Foundation) Family members */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # define STM32_NSPDIFRX 0 /* Not supported */ # define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ # define STM32_NI2C 3 /* I2C1-3 */ @@ -350,75 +350,75 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32F7_HAVE_FMC) +#if defined(CONFIG_STM32_HAVE_FMC) # define STM32_NFMC 1 /* Have FMC memory controller */ #else # define STM32_NFMC 0 /* No FMC memory controller */ #endif -#if defined(CONFIG_STM32F7_HAVE_ETHRNET) +#if defined(CONFIG_STM32_HAVE_ETHRNET) # define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else # define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32F7_HAVE_RNG) +#if defined(CONFIG_STM32_HAVE_RNG) # define STM32_NRNG 1 /* Random number generator (RNG) */ #else # define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif -#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) +#if defined(CONFIG_STM32_HAVE_SPI5) && defined(CONFIG_STM32_HAVE_SPI6) # define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI5) +#elif defined(CONFIG_STM32_HAVE_SPI5) # define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI4) +#elif defined(CONFIG_STM32_HAVE_SPI4) # define STM32_NSPI 4 /* SPI1-4 V series */ #else # define STM32_NSPI 3 /* SPI1-3 R series */ #endif -#if defined(CONFIG_STM32F7_HAVE_SDMMC2) +#if defined(CONFIG_STM32_HAVE_SDMMC2) # define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else # define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif -#if defined(CONFIG_STM32F7_HAVE_CAN3) +#if defined(CONFIG_STM32_HAVE_CAN3) # define STM32_NCAN 3 /* CAN1-3 */ -#elif defined(CONFIG_STM32F7_HAVE_CAN2) +#elif defined(CONFIG_STM32_HAVE_CAN2) # define STM32_NCAN 2 /* CAN1-2 */ #else # define STM32_NCAN 1 /* CAN1 only */ #endif -#if defined(CONFIG_STM32F7_HAVE_DCMI) +#if defined(CONFIG_STM32_HAVE_DCMI) # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else # define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif -#if defined(CONFIG_STM32F7_HAVE_DSIHOST) +#if defined(CONFIG_STM32_HAVE_DSIHOST) # define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else # define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif -#if defined (CONFIG_STM32F7_HAVE_LTDC) +#if defined (CONFIG_STM32_HAVE_LTDC) # define STM32_NLCDTFT 1 /* One LCD-TFT */ #else # define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif -#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ +#if defined(CONFIG_STM32_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ # define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else # define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif -#if defined(CONFIG_STM32F7_HAVE_JPEG) +#if defined(CONFIG_STM32_HAVE_JPEG) #define STM32_NJPEG 1 /* One JPEG Converter */ #else #define STM32_NJPEG 0 /* No JPEG Converter */ #endif -#if defined(CONFIG_STM32F7_HAVE_CRYP) +#if defined(CONFIG_STM32_HAVE_CRYP) #define STM32_NCRYP 1 /* One CRYP engine */ #else #define STM32_NCRYP 0 /* No CRYP engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_HASH) +#if defined(CONFIG_STM32_HAVE_HASH) #define STM32_NHASH 1 /* One HASH engine */ #else #define STM32_NHASH 0 /* No HASH engine */ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index 3c786310d68..c755977dfdc 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -69,11 +69,11 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include #else # error "Unsupported STM32 F7 chip" diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index e7e7126cd17..265a7421098 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -37,13 +37,13 @@ list( stm32_uid.c stm32_waste.c) -if(CONFIG_STM32F7_TICKLESS_TIMER) +if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32F7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -55,7 +55,7 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32F7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() @@ -66,11 +66,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32F7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) endif() -if(CONFIG_STM32F7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -83,27 +83,31 @@ if(CONFIG_STM32F7_RTC) endif() endif() -if(CONFIG_STM32F7_IWDG OR CONFIG_STM32F7_RTC_LSICLOCK) +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_fmc.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32F7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32F7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32F7_I2S) +if(CONFIG_STM32_I2S) list(APPEND SRCS stm32_i2s.c) endif() -if(CONFIG_STM32F7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -120,19 +124,19 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32F7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32F7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F7_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32F7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -140,19 +144,19 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32_dumpgpio.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32F7_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() -if(CONFIG_STM32F7_DMA2D) +if(CONFIG_STM32_DMA2D) list(APPEND SRCS stm32_dma2d.c) endif() @@ -160,19 +164,19 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32F7_CAN_SOCKET) +if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_can_sock.c) endif() -if(CONFIG_STM32F7_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32_sai.c) endif() -if(CONFIG_STM32F7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -180,7 +184,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 825e55ef277..539914fbe7c 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -7,6 +7,49 @@ if ARCH_CHIP_STM32F7 comment "STM32 F7 Configuration Options" +config STM32_F7_PERIPHERALS + bool + default ARCH_CHIP_STM32F7 + select STM32_HAVE_ADC1 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHRNET + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 if !STM32_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_CEC + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_FLASH_ART_ACCELERATOR + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 F7 Chip Selection" default ARCH_CHIP_STM32F746NG @@ -14,7494 +57,1150 @@ choice config ARCH_CHIP_STM32F722RC bool "STM32F722RC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722RE bool "STM32F722RE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VC bool "STM32F722VC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VE bool "STM32F722VE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZC bool "STM32F722ZC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZE bool "STM32F722ZE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IC bool "STM32F722IC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IE bool "STM32F722IE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RC bool "STM32F723RC" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RE bool "STM32F723RE" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VC bool "STM32F723VC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VE bool "STM32F723VE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZC bool "STM32F723ZC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZE bool "STM32F723ZE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IC bool "STM32F723IC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IE bool "STM32F723IE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F745VG bool "STM32F745VG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745VE bool "STM32F745VE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IG bool "STM32F745IG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IE bool "STM32F745IE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZE bool "STM32F745ZE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZG bool "STM32F745ZG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BG bool "STM32F746BG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VG bool "STM32F746VG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VE bool "STM32F746VE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BE bool "STM32F746BE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZG bool "STM32F746ZG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IE bool "STM32F746IE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NG bool "STM32F746NG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NE bool "STM32F746NE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZE bool "STM32F746ZE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IG bool "STM32F746IG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756NG bool "STM32F756NG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756BG bool "STM32F756BG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756IG bool "STM32F756IG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756VG bool "STM32F756VG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756ZG bool "STM32F756ZG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F765NI bool "STM32F765NI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VI bool "STM32F765VI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VG bool "STM32F765VG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BI bool "STM32F765BI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765NG bool "STM32F765NG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZG bool "STM32F765ZG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZI bool "STM32F765ZI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765IG bool "STM32F765IG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BG bool "STM32F765BG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765II bool "STM32F765II" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NG bool "STM32F767NG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767IG bool "STM32F767IG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VG bool "STM32F767VG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZG bool "STM32F767ZG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NI bool "STM32F767NI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VI bool "STM32F767VI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767BG bool "STM32F767BG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZI bool "STM32F767ZI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767II bool "STM32F767II" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BI bool "STM32F769BI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769II bool "STM32F769II" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BG bool "STM32F769BG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NI bool "STM32F769NI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769AI bool "STM32F769AI" - select STM32F7_STM32F769AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NG bool "STM32F769NG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769IG bool "STM32F769IG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777ZI bool "STM32F777ZI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777VI bool "STM32F777VI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777NI bool "STM32F777NI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777BI bool "STM32F777BI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777II bool "STM32F777II" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F778AI bool "STM32F778AI" - select STM32F7_STM32F778AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F778AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779II bool "STM32F779II" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779NI bool "STM32F779NI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779BI bool "STM32F779BI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779AI bool "STM32F779AI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM endchoice # STM32 F7 Chip Selection -config STM32F7_STM32F72XX +config STM32_STM32F72XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F73XX +config STM32_STM32F73XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F74XX +config STM32_STM32F74XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F75XX +config STM32_STM32F75XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F76XX +config STM32_STM32F76XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F77XX +config STM32_STM32F77XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 config STM32F7_IO_CONFIG_R + # Package designator R bool default n config STM32F7_IO_CONFIG_V + # Package designator V bool default n config STM32F7_IO_CONFIG_I + # Package designator I bool default n config STM32F7_IO_CONFIG_Z + # Package designator Z bool default n config STM32F7_IO_CONFIG_N + # Package designator N bool default n config STM32F7_IO_CONFIG_B + # Package designator B bool default n config STM32F7_IO_CONFIG_A + # Package designator A bool default n -config STM32F7_STM32F722XX +config STM32_STM32F722XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_EXTERNAL_ULPI + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_EXTERNAL_ULPI -config STM32F7_STM32F723XX +config STM32_STM32F723XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R -config STM32F7_STM32F745XX +config STM32_STM32F745XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F746XX +config STM32_STM32F746XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - select STM32F7_HAVE_EXTERNAL_ULPI - select STM32F7_HAVE_SAI1 - select STM32F7_HAVE_SAI2 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + select STM32_HAVE_EXTERNAL_ULPI + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 -config STM32F7_STM32F756XX +config STM32_STM32F756XX bool default n - select STM32F7_STM32F75XX + select STM32_STM32F75XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F765XX +config STM32_STM32F765XX bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG # data sheet says yes, Product matrix says no - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG # data sheet says yes, Product matrix says no + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F767XX +config STM32_STM32F767XX bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F768XX # Revisit When parts released +config STM32_STM32F768XX # Revisit When parts released bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F768AX # Revisit When parts released +config STM32_STM32F768AX # Revisit When parts released bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F769XX +config STM32_STM32F769XX bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F769AX # Revisit When parts released +config STM32_STM32F769AX # Revisit When parts released bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F777XX +config STM32_STM32F777XX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F778XX # Revisit when parts released +config STM32_STM32F778XX # Revisit when parts released bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F778AX +config STM32_STM32F778AX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F779XX +config STM32_STM32F779XX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F779AX +config STM32_STM32F779AX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_FLASH_CONFIG_E - bool - default n - -config STM32F7_FLASH_CONFIG_G - bool - default n - -config STM32F7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32F7 - default STM32F7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F7 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32F7xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32F7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32F7_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F7_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F7_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32F7_FLASH_ART_ACCELERATOR - bool "Flash ART Accelerator" - default n - ---help--- - ART Accelerator on the flash memory ITCM interface accelerates code execution - with a system of instruction prefetch and cache lines. - - Enable if code and/or read-only data is accessed through ITCM bus instead of - AXIM bus. - -config STM32F7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_FMC - bool - default n - -config STM32F7_HAVE_ETHRNET - bool - default n - -config STM32F7_HAVE_PHY_POLLED - bool - default n - -config STM32F7_HAVE_RNG - bool - default n - -config STM32F7_HAVE_SPI4 - bool - default n - -config STM32F7_HAVE_SPI5 - bool - default n - -config STM32F7_HAVE_SPI6 - bool - default n - -config STM32F7_HAVE_SDMMC2 - bool - default n - -config STM32F7_HAVE_ADC1_DMA - bool - default n - -config STM32F7_HAVE_ADC2_DMA - bool - default n - -config STM32F7_HAVE_ADC3_DMA - bool - default n - -config STM32F7_HAVE_CAN2 - bool - default n - -config STM32F7_HAVE_CAN3 - bool - default n - -config STM32F7_HAVE_DCMI - bool - default n - -config STM32F7_HAVE_DSIHOST - bool - default n - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_DMA2D - bool - default n - -config STM32F7_HAVE_JPEG - bool - default n - -config STM32F7_HAVE_CRYP - bool - default n - -config STM32F7_HAVE_HASH - bool - default n - -config STM32F7_HAVE_DFSDM1 - bool - default n - -config STM32F7_HAVE_INTERNAL_ULPI - bool - default n - -config STM32F7_HAVE_EXTERNAL_ULPI - bool - default n - -config STM32F7_I2S - bool - default n - select STM32F7_SPI_DMA - -config STM32F7_HAVE_SAI1 - bool - default n - -config STM32F7_HAVE_SAI2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32F7_ADC - bool - default n - -config STM32F7_CAN - bool - default n - -config STM32F7_DAC - bool - default n - -config STM32F7_DMA - bool - default n - -config STM32F7_I2C - bool - default n - -config STM32F7_SAI - bool - default n - -config STM32F7_SDMMC - bool - default n - -config STM32F7_SPI - bool - default n - -config STM32F7_SPI_DMA - bool - default n - -config STM32F7_TIM - bool - default n - -config STM32F7_PWM - bool - default n - -config STM32F7_USART - bool - default n - -# These are the peripheral selections proper - -config STM32F7_ADC1 - bool "ADC1" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2 - -config STM32F7_ADC2 - bool "ADC2" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2 - -config STM32F7_ADC3 - bool "ADC3" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC3_DMA if STM32F7_DMA2 - -config STM32F7_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32F7_CAN1 - bool "CAN1" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN2 - bool "CAN2" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN3 - bool "CAN3" - default n - select CAN - select STM32F7_CAN - depends on STM32F7_HAVE_CAN3 - -config STM32F7_CEC - bool "CEC" - default n - depends on STM32F7_VALUELINE - -config STM32F7_CRC - bool "CRC" - default n - -config STM32F7_CRYP - bool "CRYP" - depends on STM32F7_HAVE_CRYP - default n - -config STM32F7_DFSDM1 - bool "DFSDM1" - default n - depends on STM32F7_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 - -config STM32F7_DMA1 - bool "DMA1" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DMA2 - bool "DMA2" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DAC1 - bool "DAC1" - default n - select STM32F7_DAC - -config STM32F7_DAC2 - bool "DAC2" - default n - select STM32F7_DAC - -config STM32F7_DCMI - bool "DCMI" - default n - depends on STM32F7_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32F7_DSIHOST - bool "DSIHOST" - default n - depends on STM32F7_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI - compliant displays. - -config STM32F7_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32F7_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32 F7 devices. - -config STM32F7_JPEG - bool "JPEG" - default n - depends on STM32F7_HAVE_JPEG - ---help--- - The JPEG codec provides an fast and simple hardware compressor and - decompressor of JPEG images with full management of JPEG headers. - -config STM32F7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32F7_HAVE_ETHRNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32F7_HAVE_PHY_POLLED - -config STM32F7_FMC - bool "FMC" - depends on STM32F7_HAVE_FMC - default n - -config STM32F7_HASH - bool "HASH" - default n - depends on STM32F7_HAVE_HASH - select ARCH_HAVE_HASH - -config STM32F7_CEC - bool "HDMI-CEC" - default n - -config STM32F7_I2C1 - bool "I2C1" - default n - select STM32F7_I2C - -config STM32F7_I2C2 - bool "I2C2" - default n - select STM32F7_I2C - -config STM32F7_I2C3 - bool "I2C3" - default n - select STM32F7_I2C - -config STM32F7_I2C4 - bool "I2C4" - default n - select STM32F7_I2C - -config STM32F7_LPTIM1 - bool "Low-power timer 1" - default n - -config STM32F7_LTDC - bool "LTDC" - default n - select FB - depends on STM32F7_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - With the STM32F7x8/9, the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32F7_DSIHOST and STM32F7_LTDC_USE_DSI. - -config STM32F7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_OTGFSHS - bool "OTG FS/HS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_QSPI - bool "QuadSPI" - default n - -config STM32F7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32F7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32F7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32F7_RTC - bool "RTC" - default n - select RTC - -config STM32F7_PWR - bool "PWR" - default n - -config STM32F7_RNG - bool "RNG" - default n - depends on STM32F7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32F7_I2S1 - bool "I2S1" - default n - depends on !STM32F7_SPI1 - select STM32F7_I2S - -config STM32F7_I2S2 - bool "I2S2" - default n - depends on !STM32F7_SPI2 - select STM32F7_I2S - -config STM32F7_I2S3 - bool "I2S3" - default n - depends on !STM32F7_SPI3 - select STM32F7_I2S - -config STM32F7_SAI1 - bool "SAI1" - default n - depends on STM32F7_HAVE_SAI1 - -config STM32F7_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI2 - bool "SAI2" - default n - select STM32F7_HAVE_SAI2 - -config STM32F7_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SDMMC1 - bool "SDMMC1" - default n - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SDMMC2 - bool "SDMMC2" - default n - depends on STM32F7_HAVE_SDMMC2 - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SPDIFRX - bool "SPDIFRX" - default n - -config STM32F7_SPI1 - bool "SPI1" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI2 - bool "SPI2" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI3 - bool "SPI3" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI4 - bool "SPI4" - default n - depends on STM32F7_HAVE_SPI4 - select SPI - select STM32F7_SPI - -config STM32F7_SPI5 - bool "SPI5" - default n - depends on STM32F7_HAVE_SPI5 - select SPI - select STM32F7_SPI - -config STM32F7_SPI6 - bool "SPI6" - default n - depends on STM32F7_HAVE_SPI6 - select SPI - select STM32F7_SPI - -config STM32F7_SYSCFG - bool "SYSCFG" - default y - -config STM32F7_TIM1 - bool "TIM1" - default n - select STM32F7_TIM - -config STM32F7_TIM2 - bool "TIM2" - default n - select STM32F7_TIM - -config STM32F7_TIM3 - bool "TIM3" - default n - select STM32F7_TIM - -config STM32F7_TIM4 - bool "TIM4" - default n - select STM32F7_TIM - -config STM32F7_TIM5 - bool "TIM5" - default n - select STM32F7_TIM - -config STM32F7_TIM6 - bool "TIM6" - default n - select STM32F7_TIM - -config STM32F7_TIM7 - bool "TIM7" - default n - select STM32F7_TIM - -config STM32F7_TIM8 - bool "TIM8" - default n - select STM32F7_TIM - -config STM32F7_TIM9 - bool "TIM9" - default n - select STM32F7_TIM - -config STM32F7_TIM10 - bool "TIM10" - default n - select STM32F7_TIM - -config STM32F7_TIM11 - bool "TIM11" - default n - select STM32F7_TIM - -config STM32F7_TIM12 - bool "TIM12" - default n - select STM32F7_TIM - -config STM32F7_TIM13 - bool "TIM13" - default n - select STM32F7_TIM - -config STM32F7_TIM14 - bool "TIM14" - default n - select STM32F7_TIM - -config STM32F7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32F7_USART - -config STM32F7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32F7_USART - -config STM32F7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32F7_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32F7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -menu "OTG Configuration" - depends on STM32F7_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - -menu "U[S]ART Configuration" - depends on STM32F7_USART - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32F7_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32F7_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32F7_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32F7_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32F7_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32F7_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32F7_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32F7_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config STM32F7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32F7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32F7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32F7_USART && SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32F7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32F7_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32F7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32F7_USART && STM32F7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32F7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32F7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32F7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F7 serial driver. - -config STM32F7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32F7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32F7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32F7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -if PM - -config STM32F7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu # U[S]ART Configuration - -menu "STM32F7_OTG_HS Configuration" - depends on STM32F7_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32F7_NO_ULPI - -config STM32F7_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32F7_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32F7_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -config STM32F7_EXTERNAL_RAM - bool "External RAM on FMC" - default n - depends on STM32F7_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SDRAM, external RAM may be available through the FMC. - -menu "QuadSPI Configuration" - depends on STM32F7_QSPI - -config STM32F7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32F7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32F7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32F7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32F7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32F7_QSPI_DMA - bool "DMA" - depends on STM32F7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32F7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32F7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32F7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32F7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32F7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32F7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32F7_DMA - ---help--- - 'Highest' priority. - -config STM32F7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32F7_DMA - ---help--- - 'High' priority. - -config STM32F7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32F7_DMA - ---help--- - 'Medium' priority. - -config STM32F7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32F7_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32F7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32F7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32F7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32F7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32F7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - -menu "SPI Configuration" - depends on STM32F7_SPI - -config STM32F7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32F7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32F7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32F7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32F7_SPI1 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32F7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32F7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32F7_SPI2 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32F7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32F7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32F7_SPI3 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32F7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32F7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32F7_SPI4 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32F7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32F7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32F7_SPI5 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32F7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32F7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32F7_SPI6 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32F7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # "SPI Configuration" - -menu "I2S Configuration" - depends on STM32F7_I2S - -config STM32F7_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -if STM32F7_I2S1 - -comment "I2S1 Configuration" - -config STM32F7_I2S1_MCK - bool "I2S1_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S1_RX - bool "Enable I2S1 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S1_TX - bool "Enable I2S1 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S1_DATALEN - int "I2S1 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S1 - -if STM32F7_I2S2 - -comment "I2S2 Configuration" - -config STM32F7_I2S2_MCK - bool "I2S2_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S2_RX - bool "Enable I2S2 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S2_TX - bool "Enable I2S2 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S2_DATALEN - int "I2S2 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S2 - -if STM32F7_I2S3 - -comment "I2S3 Configuration" - -config STM32F7_I2S3_MCK - bool "I2S3_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S3_RX - bool "Enable I2S3 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S3_TX - bool "Enable I2S3 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S3_DATALEN - int "I2S3 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S3 - -config STM32F7_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32F7_I2C - -config STM32F7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "SD/MMC Configuration" - depends on STM32F7_SDMMC - -config STM32F7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32F7_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32F7_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32F7_SDMMC1 - -config STM32F7_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32F7_SDMMC2 - -config STM32F7_SDMMC2_DMAPRIO - hex "SDMMC2 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC2 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32F7_BKPSRAM - -config STM32F7_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32F7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32F7_BBSRAM - -config STM32F7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32F7_BBSRAM - -endif # STM32F7_BKPSRAM - -config STM32F7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32F7_RTC - -config STM32F7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32F7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32F7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32F7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32F7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -endif # STM32F7_RTC_LSECLOCK - -endmenu # RTC Configuration - -config STM32F7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32F7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32F7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32F7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32F7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32F7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32F7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32F7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32F7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32F7_TIM1 - select STM32F7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM1_PWM - -config STM32F7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32F7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32F7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM1_CHANNEL6 - -config STM32F7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM1_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM1_CHANNEL = 1 - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 1 - -if STM32F7_TIM1_CHANNEL = 2 - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 2 - -if STM32F7_TIM1_CHANNEL = 3 - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 3 - -if STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM1_PWM - -config STM32F7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32F7_TIM2 - select STM32F7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM2_PWM - -config STM32F7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM2_CHANNEL4 - -config STM32F7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM2_CHANNEL = 1 - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL = 1 - -if STM32F7_TIM2_CHANNEL = 2 - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL = 2 - -if STM32F7_TIM2_CHANNEL = 3 - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL = 3 - -if STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM2_PWM - -config STM32F7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32F7_TIM3 - select STM32F7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM3_PWM - -config STM32F7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM3_CHANNEL4 - -config STM32F7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM3_CHANNEL = 1 - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL = 1 - -if STM32F7_TIM3_CHANNEL = 2 - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL = 2 - -if STM32F7_TIM3_CHANNEL = 3 - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL = 3 - -if STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM3_PWM - -config STM32F7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32F7_TIM4 - select STM32F7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM4_PWM - -config STM32F7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM4_CHANNEL4 - -config STM32F7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM4_CHANNEL = 1 - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL = 1 - -if STM32F7_TIM4_CHANNEL = 2 - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL = 2 - -if STM32F7_TIM4_CHANNEL = 3 - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL = 3 - -if STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM4_PWM - -config STM32F7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32F7_TIM5 - select STM32F7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM5_PWM - -config STM32F7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM5_CHANNEL4 - -config STM32F7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM5_CHANNEL = 1 - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL = 1 - -if STM32F7_TIM5_CHANNEL = 2 - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL = 2 - -if STM32F7_TIM5_CHANNEL = 3 - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL = 3 - -if STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM5_PWM - -config STM32F7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32F7_TIM8 - select STM32F7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM8_PWM - -config STM32F7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32F7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32F7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM8_CHANNEL6 - -config STM32F7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM8_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM8_CHANNEL = 1 - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 1 - -if STM32F7_TIM8_CHANNEL = 2 - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 2 - -if STM32F7_TIM8_CHANNEL = 3 - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 3 - -if STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM8_PWM - -config STM32F7_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32F7_TIM9 - select STM32F7_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM9_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM9_CHANNEL2 - -config STM32F7_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM9_CHANNEL = 1 - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL = 1 - -if STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM9_PWM - -config STM32F7_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32F7_TIM10 - select STM32F7_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM10_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM10_CHANNEL1 - -config STM32F7_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM10_PWM - -config STM32F7_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32F7_TIM11 - select STM32F7_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM11_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM11_CHANNEL1 - -config STM32F7_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM11_PWM - -config STM32F7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32F7_TIM12 - select STM32F7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM12_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM12_CHANNEL2 - -config STM32F7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM12_CHANNEL = 1 - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL = 1 - -if STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM12_PWM - -config STM32F7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32F7_TIM13 - select STM32F7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM13_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM13_CHANNEL1 - -config STM32F7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM13_PWM - -config STM32F7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32F7_TIM14 - select STM32F7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM14_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM14_CHANNEL1 - -config STM32F7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM14_PWM - -config STM32F7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32F7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32F7_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32F7_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32F7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32F7_TIM1 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32F7_TIM8 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32F7_TIM8_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM8_PULSECOUNT -config STM32F7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32F7_TIM1 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32F7_TIM1_ADC1 - depends on STM32F7_TIM1_ADC - -config STM32F7_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32F7_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32F7_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32F7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32F7_TIM2 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32F7_TIM2_ADC1 - depends on STM32F7_TIM2_ADC - -config STM32F7_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32F7_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32F7_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32F7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32F7_TIM3 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32F7_TIM3_ADC1 - depends on STM32F7_TIM3_ADC - -config STM32F7_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32F7_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32F7_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32F7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32F7_TIM4 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32F7_TIM4_ADC1 - depends on STM32F7_TIM4_ADC - -config STM32F7_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32F7_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32F7_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32F7_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32F7_TIM5 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM5 ADC channel" - default STM32F7_TIM5_ADC1 - depends on STM32F7_TIM5_ADC - -config STM32F7_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32F7_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32F7_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -config STM32F7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32F7_TIM8 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32F7_TIM8_ADC1 - depends on STM32F7_TIM8_ADC - -config STM32F7_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32F7_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32F7_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32F7_HAVE_ADC1_TIMER - bool - -config STM32F7_HAVE_ADC2_TIMER - bool - -config STM32F7_HAVE_ADC3_TIMER - bool - -config STM32F7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32F7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32F7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32F7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32F7_TIM1 && STM32F7_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32F7_TIM1_DAC1 - depends on STM32F7_TIM1_DAC - -config STM32F7_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32F7_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32F7_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32F7_TIM2 && STM32F7_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32F7_TIM2_DAC1 - depends on STM32F7_TIM2_DAC - -config STM32F7_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32F7_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32F7_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32F7_TIM3 && STM32F7_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32F7_TIM3_DAC1 - depends on STM32F7_TIM3_DAC - -config STM32F7_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32F7_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32F7_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32F7_TIM4 && STM32F7_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32F7_TIM4_DAC1 - depends on STM32F7_TIM4_DAC - -config STM32F7_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32F7_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32F7_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32F7_TIM5 && STM32F7_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32F7_TIM5_DAC1 - depends on STM32F7_TIM5_DAC - -config STM32F7_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32F7_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32F7_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32F7_TIM6 && STM32F7_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32F7_TIM6_DAC1 - depends on STM32F7_TIM6_DAC - -config STM32F7_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32F7_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32F7_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32F7_TIM7 && STM32F7_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32F7_TIM7_DAC1 - depends on STM32F7_TIM7_DAC - -config STM32F7_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32F7_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32F7_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32F7_TIM8 && STM32F7_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32F7_TIM8_DAC1 - depends on STM32F7_TIM8_DAC - -config STM32F7_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32F7_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32F7_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32F7_TIM9 && STM32F7_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM9 DAC channel" - default STM32F7_TIM9_DAC1 - depends on STM32F7_TIM9_DAC - -config STM32F7_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32F7_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -config STM32F7_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32F7_TIM10 && STM32F7_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM10 DAC channel" - default STM32F7_TIM10_DAC1 - depends on STM32F7_TIM10_DAC - -config STM32F7_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32F7_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -config STM32F7_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32F7_TIM11 && STM32F7_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM11 DAC channel" - default STM32F7_TIM11_DAC1 - depends on STM32F7_TIM11_DAC - -config STM32F7_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32F7_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -config STM32F7_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32F7_TIM12 && STM32F7_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM12 DAC channel" - default STM32F7_TIM12_DAC1 - depends on STM32F7_TIM12_DAC - -config STM32F7_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32F7_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -config STM32F7_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32F7_TIM13 && STM32F7_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM13 DAC channel" - default STM32F7_TIM13_DAC1 - depends on STM32F7_TIM13_DAC - -config STM32F7_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32F7_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -config STM32F7_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32F7_TIM14 && STM32F7_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM14 DAC channel" - default STM32F7_TIM14_DAC1 - depends on STM32F7_TIM14_DAC - -config STM32F7_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32F7_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -config STM32F7_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32F7_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32F7_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32F7_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32F7_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32F7_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32F7_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32F7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32F7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32F7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32F7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32F7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32F7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32F7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32F7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32F7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32F7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32F7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32F7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32F7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32F7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32F7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32F7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32F7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32F7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32F7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32F7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32F7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32F7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32F7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32F7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32F7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32F7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32F7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32F7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32F7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32F7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32F7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32F7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32F7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32F7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32F7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32F7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32F7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32F7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32F7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32F7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32F7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32F7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32F7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32F7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32F7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32F7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32F7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32F7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32F7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32F7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32F7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32F7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32F7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32F7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32F7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32F7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32F7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32F7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32F7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32F7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32F7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32F7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32F7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32F7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32F7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32F7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32F7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32F7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32F7_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32F7_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32F7_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32F7_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32F7_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32F7_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32F7_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32F7_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32F7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32F7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32F7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32F7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32F7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32F7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32F7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32F7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "CAN driver configuration" - depends on STM32F7_CAN - -choice - prompt "CAN character driver or SocketCAN support" - default STM32F7_CAN_CHARDRIVER - -config STM32F7_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F7_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -config STM32F7_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32F7_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined. - -config STM32F7_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32F7_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN3_BAUD - int "CAN3 BAUD" - default 250000 - depends on STM32F7_CAN3 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32F7_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32F7_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "ADC Configuration" - depends on STM32F7_ADC - -config STM32F7_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32F7_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32F7_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32F7_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32F7_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32F7_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32F7_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32F7_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32F7_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32F7_ADC1_DMA - bool "ADC1 DMA" - depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32F7_ADC1 - default STM32F7_ADC1_DMA - default n - -config STM32F7_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32F7_ADC1_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32F7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32F7_ADC1 && STM32F7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC2_DMA - bool "ADC2 DMA" - depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32F7_ADC2 - default STM32F7_ADC2_DMA - -config STM32F7_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32F7_ADC2_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32F7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32F7_ADC2 && STM32F7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC3_DMA - bool "ADC3 DMA" - depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32F7_ADC3 - default STM32F7_ADC3_DMA - -config STM32F7_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32F7_ADC3_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32F7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32F7_ADC3 && STM32F7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32F7_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32F7_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32F7_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32F7_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32F7_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - -config STM32F7_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32F7_ADC1 && !STM32F7_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32F7_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32F7_ADC2 && !STM32F7_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32F7_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32F7_ADC3 && !STM32F7_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - -config STM32F7_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32F7_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32F7_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32F7_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32F7_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32F7_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - -endmenu # "ADC Configuration" - -menu "Ethernet MAC configuration" - depends on STM32F7_ETHMAC - -config STM32F7_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32F7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32F7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32F7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32F7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32F7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32F7_MII_EXTCLK - depends on STM32F7_MII - -config STM32F7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32F7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32F7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32F7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32F7_ETHFD - bool "Full duplex" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32F7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32F7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32F7_AUTONEG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32F7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32F7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32F7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32F7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32F7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32F7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32F7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32F7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32F7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32F7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32F7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32F7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32F7_RMII - bool - default !STM32F7_MII - -choice - prompt "RMII clock configuration" - default STM32F7_RMII_EXTCLK - depends on STM32F7_RMII - -config STM32F7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32F7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32F7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32F7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -if STM32F7_LTDC - -menu "LTDC Configuration" - -config STM32F7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32F7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32F7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32F7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32F7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32F7_LTDC_DITHER - bool "Dither support" - default n - -config STM32F7_LTDC_DITHER_RED - depends on STM32F7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32F7_LTDC_DITHER_GREEN - depends on STM32F7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32F7_LTDC_DITHER_BLUE - depends on STM32F7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32F7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32F7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32F7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32F7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32F7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32F7_LTDC_L1_RGB565 - -config STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32F7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32F7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32F7_LTDC_L2 - -config STM32F7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32F7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32F7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32F7_LTDC_L2_RGB565 - -config STM32F7_LTDC_L2_L8 - depends on STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32F7_LTDC_L2_AL44 - depends on STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32F7_LTDC_L2_AL88 - depends on STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32F7_LTDC_L2_RGB565 - depends on STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32F7_LTDC_L2_ARGB4444 - depends on STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32F7_LTDC_L2_ARGB1555 - depends on STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32F7_LTDC_L2_RGB888 - depends on STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32F7_LTDC_L2_ARGB8888 - depends on STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32F7_LTDC_L2 - -config STM32F7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32F7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32F7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32F7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu - -endif # STM32F7_LTDC - -if STM32F7_DMA2D - -menu "DMA2D Configuration" - -config STM32F7_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32F7_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32F7_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32F7_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC. - -config STM32F7_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32F7_DMA2D_L8 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32F7_DMA2D_AL44 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32F7_DMA2D_AL88 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32F7_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32F7_LTDC_L1_RGB565 - default y - -config STM32F7_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32F7_LTDC_L1_ARGB4444 - default y - -config STM32F7_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32F7_LTDC_L1_ARGB15555 - default y - -config STM32F7_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32F7_LTDC_L1_RGB888 - default y - -config STM32F7_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32F7_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32F7_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32F7_DMA2D - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32F7_TIM1 || STM32F7_TIM2 || STM32F7_TIM3 || STM32F7_TIM4 || STM32F7_TIM5 || STM32F7_TIM8 - -config STM32F7_TIM1_QE - bool "TIM1" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32F7_TIM1_QE - -config STM32F7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM2_QE - bool "TIM2" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32F7_TIM2_QE - -config STM32F7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM3_QE - bool "TIM3" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32F7_TIM3_QE - -config STM32F7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM4_QE - bool "TIM4" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32F7_TIM4_QE - -config STM32F7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM5_QE - bool "TIM5" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32F7_TIM5_QE - -config STM32F7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM8_QE - bool "TIM8" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32F7_TIM8_QE - -config STM32F7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F7_QENCODER_SAMPLE_FDTS_4 - -config STM32F7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32F7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel event count" - default STM32F7_QENCODER_SAMPLE_EVENT_6 - -config STM32F7_QENCODER_SAMPLE_EVENT_1 - depends on STM32F7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F7_QENCODER_SAMPLE_EVENT_2 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F7_QENCODER_SAMPLE_EVENT_4 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F7_QENCODER_SAMPLE_EVENT_5 - depends on STM32F7_QENCODER_SAMPLE_FDTS_16 || STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F7_QENCODER_SAMPLE_FDTS && !STM32F7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32F7_SAI - -choice - prompt "Operation mode" - default STM32F7_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32F7_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32F7_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32F7_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32F7_SAI1_BOTH_ASYNC - depends on STM32F7_SAI1_A && STM32F7_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32F7_SAI2_BOTH_ASYNC - depends on STM32F7_SAI2_A && STM32F7_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - -menuconfig STM32F7_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32F7_PWM_MULTICHAN - select STM32F7_PWM_LL_OPS - select STM32F7_ADC_LL_OPS - select STM32F7_ADC_CHANGE_SAMPLETIME - select STM32F7_ADC_NO_STARTUP_CONV - -if STM32F7_FOC - -config STM32F7_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32F7_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -choice - prompt "FOC ADC trigger selection" - default STM32F7_FOC_ADC_TRGO - -config STM32F7_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32F7_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on !STM32F7_FOC_FOC1 - select STM32F7_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -if STM32F7_FOC_FOC0 - -choice - prompt "FOC0 device ADC selection" - default STM32F7_FOC_FOC0_ADC1 - -config STM32F7_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC0 - -if STM32F7_FOC_FOC1 - -choice - prompt "FOC1 device ADC selection" - default STM32F7_FOC_FOC1_ADC2 - -config STM32F7_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC1 - -config STM32F7_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32F7_FOC_USE_TIM1 - bool - default n - select STM32F7_TIM1 - select STM32F7_TIM1_PWM - select STM32F7_TIM1_CHANNEL1 - select STM32F7_TIM1_CHANNEL2 - select STM32F7_TIM1_CHANNEL3 - select STM32F7_TIM1_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1OUT - select STM32F7_TIM1_CH2OUT - select STM32F7_TIM1_CH3OUT - select STM32F7_TIM1_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32F7_FOC_USE_TIM8 - bool - default n - select STM32F7_TIM8 - select STM32F7_TIM8_PWM - select STM32F7_TIM8_CHANNEL1 - select STM32F7_TIM8_CHANNEL2 - select STM32F7_TIM8_CHANNEL3 - select STM32F7_TIM8_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1OUT - select STM32F7_TIM8_CH2OUT - select STM32F7_TIM8_CH3OUT - select STM32F7_TIM8_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32F7_FOC_USE_ADC1 - bool - default n - select STM32F7_ADC1 - select STM32F7_ADC1_SCAN - select STM32F7_ADC1_JEXTSEL - -config STM32F7_FOC_USE_ADC2 - bool - default n - select STM32F7_ADC2 - select STM32F7_ADC2_SCAN - select STM32F7_ADC2_JEXTSEL - -config STM32F7_FOC_USE_ADC3 - bool - default n - select STM32F7_ADC3 - select STM32F7_ADC3_SCAN - select STM32F7_ADC3_JEXTSEL - -endif #STM32F7_FOC + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 endif # ARCH_CHIP_STM32F7 diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 01e8d8c4408..b9b5fdb7467 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -39,7 +39,7 @@ else CHIP_CSRCS += stm32_tickless.c endif -ifeq ($(CONFIG_STM32F7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -51,11 +51,11 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32F7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif @@ -66,11 +66,11 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32F7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -83,27 +83,27 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32F7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32F7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F7_I2S),y) +ifeq ($(CONFIG_STM32_I2S),y) CHIP_CSRCS += stm32_i2s.c endif -ifeq ($(CONFIG_STM32F7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -122,19 +122,19 @@ endif endif endif -ifeq ($(CONFIG_STM32F7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32F7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F7_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32F7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -142,19 +142,19 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32_dumpgpio.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32F7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif -ifeq ($(CONFIG_STM32F7_DMA2D),y) +ifeq ($(CONFIG_STM32_DMA2D),y) CHIP_CSRCS += stm32_dma2d.c endif @@ -162,26 +162,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CHIP_CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CHIP_CSRCS += stm32_can_sock.c endif -ifeq ($(CONFIG_STM32F7_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32_sai.c endif -ifeq ($(CONFIG_STM32F7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32F7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CHIP_CSRCS += stm32_foc.c endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_adc.h b/arch/arm/src/stm32f7/hardware/stm32_adc.h index cabbd5921ef..f8e8fb4423c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_adc.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_adc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_adc.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_can.h b/arch/arm/src/stm32f7/hardware/stm32_can.h index c5da101f134..8124ae8815f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_can.h +++ b/arch/arm/src/stm32f7/hardware/stm32_can.h @@ -123,7 +123,7 @@ /* Register Addresses *******************************************************/ -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) # define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) @@ -177,7 +177,7 @@ # define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) # define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET) @@ -231,7 +231,7 @@ # define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN3) +#if defined(CONFIG_STM32_CAN3) # define STM32_CAN3_MCR (STM32_CAN3_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN3_MSR (STM32_CAN3_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN3_TSR (STM32_CAN3_BASE+STM32_CAN_TSR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h index 4bc19f87b6d..2603a97063a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dbgmcu.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_dma.h b/arch/arm/src/stm32f7/hardware/stm32_dma.h index 9df147e2704..1084640b378 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dma.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dma.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h index ff9a5be351c..b2e403ca83d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h @@ -33,8 +33,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -810,7 +810,7 @@ struct eth_txdesc_s /* Enhanced DMA descriptor words with time stamp */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t tdes4; /* Reserved */ volatile uint32_t tdes5; /* Reserved */ volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ @@ -829,7 +829,7 @@ struct eth_rxdesc_s /* Enhanced DMA descriptor words with time stamp and PTP support */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ volatile uint32_t rdes5; /* Reserved */ volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ @@ -842,5 +842,5 @@ struct eth_rxdesc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_exti.h b/arch/arm/src/stm32f7/hardware/stm32_exti.h index b846f19c0f8..62fe35128bc 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32f7/hardware/stm32_exti.h @@ -34,9 +34,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -116,5 +116,5 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_flash.h b/arch/arm/src/stm32f7/hardware/stm32_flash.h index 37551dde1b8..79050bf7c7b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32_flash.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_flash.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_gpio.h b/arch/arm/src/stm32f7/hardware/stm32_gpio.h index 9449df0fa06..03f642dac61 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32_gpio.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_gpio.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_i2c.h b/arch/arm/src/stm32f7/hardware/stm32_i2c.h index 15456f503b3..bacc9e367e8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32_i2c.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_i2c.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h index fe51a5ccc24..57a9b1298f6 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_memorymap.h" #else # error "Unsupported STM32 F7 memory map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h index dad7c1251f8..5c10f75322c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pinmap.h" #else # error "Unsupported STM32 F7 Pin map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pwr.h b/arch/arm/src/stm32f7/hardware/stm32_pwr.h index 9eff00fa492..09792a2458d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pwr.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pwr.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_rcc.h b/arch/arm/src/stm32f7/hardware/stm32_rcc.h index bc41cad8beb..61a34dd8460 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_rcc.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_rcc.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h index 563818cc6c2..59f1f7ad3cb 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_spi.h b/arch/arm/src/stm32f7/hardware/stm32_spi.h index 1411319566d..94fe7c794cf 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_spi.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_spi.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h index 5112e474130..18ff0709820 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_syscfg.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32_tim.h index 46ffb0f4b11..6dfc200978c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32_tim.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_tim.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_uart.h b/arch/arm/src/stm32f7/hardware/stm32_uart.h index 4ef7a625794..0cd6b9c8d96 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32_uart.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_uart.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_uart.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h index 7347b6b06d2..e0b4f0d71fe 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -539,5 +539,5 @@ #define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h index a7596397397..c18724aa2e0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h @@ -29,7 +29,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x @@ -44,38 +44,38 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_C) -# define CONFIG_STM32F7_FLASH_OVERRIDE_C +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) +# define CONFIG_STM32_FLASH_OVERRIDE_C # warning "Flash size not defined defaulting to 256KiB (C)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_C -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) -# define CONFIG_STM32F7_FLASH_CONFIG_C +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_C) +#if defined(CONFIG_STM32_FLASH_CONFIG_C) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ _K(64), _K(128)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index bdb8128244c..3f961686b38 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h index 1e10e0c06b1..0ee93e4ee04 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -188,5 +188,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h index 51ef59e85ac..9e649c192ce 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -923,5 +923,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h index b712b40aa6f..206807751d1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h index a9dc161a5ae..c7e53682bdd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -677,5 +677,5 @@ # define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h index 6c206fcebfc..d777cdddb4c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -145,5 +145,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 5c73674d3d0..997b6186303 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -354,5 +354,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h index d82ff66c0a2..58a50d908c9 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -545,5 +545,5 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h index 23ba0cc2f6b..e5bb26ef1d5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h @@ -29,7 +29,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x @@ -42,39 +42,39 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index eee436dc44f..a423e8c659f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h index 350f17cc260..74f18438de7 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -199,5 +199,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h index 322f006d44d..4f355760b23 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -808,7 +808,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1171,5 +1171,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h index 45fda531bd7..984af74a998 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h index 2af6d339720..ef250fe77ba 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -723,5 +723,5 @@ # define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h index 5072c16d681..e634ebdb7eb 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index 946408d1916..c1bfd5b1339 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -38,9 +38,9 @@ * (both pclk1 and pclk2) */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define STM32_SPI_CLK_MAX 50000000UL -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_SPI_CLK_MAX 54000000UL #endif diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index c996cd30768..bfefcbffcde 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -29,8 +29,8 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -356,5 +356,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h index dbe7de5cf2f..208693831df 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -585,5 +585,5 @@ #define DMAMAP_QUADSPI_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h index 84e638d078a..c98d3c72aa0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h @@ -29,7 +29,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x @@ -42,53 +42,53 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_I) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G -# undef CONFIG_STM32F7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32F7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256), _K(256), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NPAGES 12 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index 370b090abd1..a63ce45ffc1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h index 1f9e1673df3..b60c2f882c5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -205,5 +205,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h index 82d795a98c0..5ef7ae8ecde 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -916,7 +916,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1330,5 +1330,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h index 54afc5d9d3d..b6d554f765b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h index 7b72de0e625..6a56b4494b5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -756,5 +756,5 @@ # define RCC_DCKCFGR2_DSISEL_PHY (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* DSI PHY sources DSI clock */ # define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h index 11b42882cff..ef63b7dede8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -163,5 +163,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index e875c19c71a..c47336e6df2 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -59,7 +59,7 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F7_ADC +#ifdef CONFIG_STM32_ADC /* This implementation is for the STM32 ADC IP version 1 */ @@ -121,21 +121,21 @@ /* ADC scan mode support */ -#ifndef CONFIG_STM32F7_ADC1_SCAN -# define CONFIG_STM32F7_ADC1_SCAN 0 +#ifndef CONFIG_STM32_ADC1_SCAN +# define CONFIG_STM32_ADC1_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC2_SCAN -# define CONFIG_STM32F7_ADC2_SCAN 0 +#ifndef CONFIG_STM32_ADC2_SCAN +# define CONFIG_STM32_ADC2_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC3_SCAN -# define CONFIG_STM32F7_ADC3_SCAN 0 +#ifndef CONFIG_STM32_ADC3_SCAN +# define CONFIG_STM32_ADC3_SCAN 0 #endif /* We have to support ADC callbacks if default ADC interrupts or * DMA transfer are enabled */ -#if !defined(CONFIG_STM32F7_ADC_NOIRQ) || defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA) # define ADC_HAVE_CB #else # undef ADC_HAVE_CB @@ -184,7 +184,7 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ struct adc_dev_s *dev; /* Upper-half ADC reference */ #endif @@ -210,7 +210,7 @@ struct stm32_dev_s uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif bool scan; /* True: Scan mode */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. * REVISIT: this takes too much space. We need only 3 bits per channel. */ @@ -252,7 +252,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32F7_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -293,10 +293,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev); static int adc123_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -321,7 +321,7 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable); static int adc_timinit(struct stm32_dev_s *priv); #endif -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -346,7 +346,7 @@ static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg); static void adc_dumpregs(struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static int adc_llops_setup(struct stm32_adc_dev_s *dev); static void adc_llops_shutdown(struct stm32_adc_dev_s *dev); static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source); @@ -375,7 +375,7 @@ static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan); static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(struct stm32_adc_dev_s *dev, struct adc_sample_time_s *time_samples); static void adc_sampletime_write(struct stm32_adc_dev_s *dev); @@ -403,7 +403,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .setup = adc_llops_setup, @@ -428,7 +428,7 @@ static const struct stm32_adc_ops_s g_adc_llops = .inj_get = adc_injget, .inj_startconv = adc_llops_inj_startconv, # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -454,27 +454,27 @@ struct adccmn_data_s g_adc123_cmn = /* ADC1 state */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC1CMN_DATA, .intf = 1, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC1_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC1_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, @@ -483,19 +483,19 @@ static struct stm32_dev_s g_adcpriv1 = .jextcfg = ADC1_JEXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC1_SCAN, + .scan = CONFIG_STM32_ADC1_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -513,27 +513,27 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC2CMN_DATA, .intf = 2, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC2_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC2_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, #ifdef ADC2_HAVE_EXTCFG .extcfg = ADC2_EXTCFG_VALUE, @@ -542,19 +542,19 @@ static struct stm32_dev_s g_adcpriv2 = .jextcfg = ADC2_JEXTCFG_VALUE, #endif #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC2_SCAN, + .scan = CONFIG_STM32_ADC2_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -572,27 +572,27 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC3CMN_DATA, .intf = 3, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC3_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC3_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, .base = STM32_ADC3_BASE, #ifdef ADC3_HAVE_EXTCFG .extcfg = ADC3_EXTCFG_VALUE, @@ -601,19 +601,19 @@ static struct stm32_dev_s g_adcpriv3 = .jextcfg = ADC3_JEXTCFG_VALUE, #endif #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC3_SCAN, + .scan = CONFIG_STM32_ADC3_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -1455,7 +1455,7 @@ static void adc_enable(struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -1587,7 +1587,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv); #else struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1673,7 +1673,7 @@ static void adc_dma_start(struct adc_dev_s *dev) priv->dma = stm32_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Start DMA only if standard ADC interrupts used */ stm32_dmasetup(priv->dma, @@ -1853,7 +1853,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1885,7 +1885,7 @@ static int adc_setup(struct adc_dev_s *dev) /* As default conversion is started here */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1909,7 +1909,7 @@ static int adc_setup(struct adc_dev_s *dev) { /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1967,7 +1967,7 @@ static void adc_shutdown(struct adc_dev_s *dev) if (priv->cmn->refcount <= 1) { -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2469,7 +2469,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2570,23 +2570,23 @@ static int adc_interrupt(struct adc_dev_s *dev) static int adc123_interrupt(int irq, void *context, void *arg) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 adc_interrupt(&g_adcdev1); #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 adc_interrupt(&g_adcdev2); #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 adc_interrupt(&g_adcdev3); #endif return OK; } -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_setup @@ -2821,7 +2821,7 @@ static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_write(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; @@ -2911,7 +2911,7 @@ void adc_sampletime_set(struct stm32_adc_dev_s *dev, } } } -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -3017,7 +3017,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) adc_enable(priv, enable); } -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -3085,12 +3085,12 @@ struct adc_dev_s *stm32_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); dev = &g_adcdev1; - cj_channels = CONFIG_STM32F7_ADC1_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3100,14 +3100,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); dev = &g_adcdev2; - cj_channels = CONFIG_STM32F7_ADC2_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3117,14 +3117,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); dev = &g_adcdev3; - cj_channels = CONFIG_STM32F7_ADC3_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3135,7 +3135,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, break; } -#endif /* CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC3 */ default: { @@ -3150,10 +3150,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, /* Configure regular channels */ - DEBUGASSERT(cr_channels <= CONFIG_STM32F7_ADC_MAX_SAMPLES); - if (cr_channels > CONFIG_STM32F7_ADC_MAX_SAMPLES) + DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cr_channels = CONFIG_STM32F7_ADC_MAX_SAMPLES; + cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cr_channels = cr_channels; @@ -3172,14 +3172,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, memcpy(priv->j_chanlist, j_chanlist, cj_channels); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Assign default values for the sample time table */ memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); priv->adc_channels = ADC_CHANNELS_NUMBER; #endif -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* Store reference to the upper-half ADC device */ priv->dev = dev; @@ -3195,4 +3195,4 @@ struct adc_dev_s *stm32_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32F7_ADC */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index b7e65e97588..39616944981 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -63,75 +63,75 @@ * is intended to be used for that purpose. Timers 1-6 and 8 may be used. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_ADC -# undef CONFIG_STM32F7_TIM1_ADC1 -# undef CONFIG_STM32F7_TIM1_ADC2 -# undef CONFIG_STM32F7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_ADC -# undef CONFIG_STM32F7_TIM2_ADC1 -# undef CONFIG_STM32F7_TIM2_ADC2 -# undef CONFIG_STM32F7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_ADC -# undef CONFIG_STM32F7_TIM3_ADC1 -# undef CONFIG_STM32F7_TIM3_ADC2 -# undef CONFIG_STM32F7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_ADC -# undef CONFIG_STM32F7_TIM4_ADC1 -# undef CONFIG_STM32F7_TIM4_ADC2 -# undef CONFIG_STM32F7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_ADC -# undef CONFIG_STM32F7_TIM5_ADC1 -# undef CONFIG_STM32F7_TIM5_ADC2 -# undef CONFIG_STM32F7_TIM5_ADC3 +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_ADC +# undef CONFIG_STM32_TIM5_ADC1 +# undef CONFIG_STM32_TIM5_ADC2 +# undef CONFIG_STM32_TIM5_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM6 -# undef CONFIG_STM32F7_TIM6_ADC -# undef CONFIG_STM32F7_TIM6_ADC1 -# undef CONFIG_STM32F7_TIM6_ADC2 -# undef CONFIG_STM32F7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_ADC -# undef CONFIG_STM32F7_TIM8_ADC1 -# undef CONFIG_STM32F7_TIM8_ADC2 -# undef CONFIG_STM32F7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \ - defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F7_ADC1_DMA) || defined(CONFIG_STM32F7_ADC2_DMA) || \ - defined(CONFIG_STM32F7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -139,9 +139,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32F7_ADC1) && (CONFIG_STM32F7_ADC1_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC2) && (CONFIG_STM32F7_ADC2_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC3) && (CONFIG_STM32F7_ADC3_INJECTED_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -149,31 +149,31 @@ * information about the timer. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC1) +#elif defined(CONFIG_STM32_TIM5_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM5_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -182,40 +182,40 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC1_TIMTRIG -# error "CONFIG_STM32F7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC2) +#elif defined(CONFIG_STM32_TIM5_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -224,36 +224,36 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC2_TIMTRIG -# error "CONFIG_STM32F7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC3) +#elif defined(CONFIG_STM32_TIM5_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -262,11 +262,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC3_TIMTRIG -# error "CONFIG_STM32F7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -413,315 +413,315 @@ * CONFIG_STM32F7_ADCx_EXTSEL option. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -730,7 +730,7 @@ #ifdef ADC1_EXTSEL_VALUE # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_EXTSEL) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE 0 #else @@ -739,7 +739,7 @@ #ifdef ADC2_EXTSEL_VALUE # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_EXTSEL) +#elif defined(CONFIG_STM32_ADC2_EXTSEL) # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE 0 #else @@ -748,7 +748,7 @@ #ifdef ADC3_EXTSEL_VALUE # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_EXTSEL) +#elif defined(CONFIG_STM32_ADC3_EXTSEL) # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE 0 #else @@ -771,7 +771,7 @@ #ifdef ADC1_JEXTSEL_VALUE # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_JEXTSEL) +#elif defined(CONFIG_STM32_ADC1_JEXTSEL) # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE 0 #else @@ -780,7 +780,7 @@ #ifdef ADC2_JEXTSEL_VALUE # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_JEXTSEL) +#elif defined(CONFIG_STM32_ADC2_JEXTSEL) # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE 0 #else @@ -789,7 +789,7 @@ #ifdef ADC3_JEXTSEL_VALUE # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_JEXTSEL) +#elif defined(CONFIG_STM32_ADC3_JEXTSEL) # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE 0 #else @@ -914,9 +914,9 @@ enum stm32_adc_multimode_e ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */ }; -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Channel and sample time pair */ @@ -941,7 +941,7 @@ struct adc_sample_time_s * same value of the sample time */ uint8_t all_ch_sample_time:3; /* Sample time for all channels */ }; -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -1024,7 +1024,7 @@ struct stm32_adc_ops_s void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(struct stm32_adc_dev_s *dev, @@ -1046,7 +1046,7 @@ struct stm32_adc_ops_s void (*enable)(struct stm32_adc_dev_s *dev, bool enable); }; -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -1088,7 +1088,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || - * CONFIG_STM32F7_ADC3 +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 47ac51b14ed..024e37de43c 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -62,7 +62,7 @@ * the FMC. In order to use FMC RAM, the following additional things need * to be present in the NuttX configuration file: * - * CONFIG_STM32F7_FMC=y : Enables the FMC + * CONFIG_STM32_FMC=y : Enables the FMC * CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. * Either of these autoselects * CONFIG_ARCH_HAVE_HEAP2 @@ -94,15 +94,15 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32F7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif /* We can't possibly have FMC external RAM if the FMC is not enabled */ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # ifdef CONFIG_ARCH_HAVE_HEAP2 -# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed? +# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32_FMC! Kconfig flawed? # endif # undef CONFIG_ARCH_HAVE_HEAP2 #endif diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index bdf2060127c..65a5b0e510f 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -51,14 +51,14 @@ #include "stm32_pwr.h" #include "stm32_rtc.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32F7_BKPSRAM) -#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -147,7 +147,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -633,7 +633,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) int ret = -EFBIG; struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; - for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -784,7 +784,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -802,7 +802,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 0eff55b26e1..7d6e8e3608e 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -44,15 +44,15 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif -#if !defined(CONFIG_STM32F7_BBSRAM_FILES) -# define CONFIG_STM32F7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif /* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique @@ -110,8 +110,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES - * CONFIG_STM32F7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -140,7 +140,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c index b51547ebe35..2d571c61b8d 100644 --- a/arch/arm/src/stm32f7/stm32_can.c +++ b/arch/arm/src/stm32f7/stm32_can.c @@ -48,8 +48,8 @@ #include "stm32_gpio.h" #if defined(CONFIG_CAN) && \ - (defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) || \ - defined(CONFIG_STM32F7_CAN3)) + (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) || \ + defined(CONFIG_STM32_CAN3)) /**************************************************************************** * Pre-processor Definitions @@ -63,7 +63,7 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO # undef CONFIG_STM32_CAN_REGDEBUG @@ -179,7 +179,7 @@ static const struct can_ops_s g_canops = .co_txempty = stm32can_txempty, }; -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { .port = 1, @@ -192,7 +192,7 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -202,7 +202,7 @@ static struct can_dev_s g_can1dev = }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { .port = 2, @@ -215,7 +215,7 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; static struct can_dev_s g_can2dev = @@ -225,7 +225,7 @@ static struct can_dev_s g_can2dev = }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { .port = 3, @@ -238,7 +238,7 @@ static struct stm32_can_s g_can3priv = .filter = 0, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; static struct can_dev_s g_can3dev = @@ -582,21 +582,21 @@ static void stm32can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -1789,8 +1789,8 @@ static int stm32can_bittiming(struct stm32_can_s *priv) else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2038,7 +2038,7 @@ static int stm32can_filterinit(struct stm32_can_s *priv) regval |= CAN_FMR_FINIT; stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); -#if defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) if (priv->port == 1 || priv->port == 2) { /* Assign half the filters to CAN1, half to CAN2 */ @@ -2270,7 +2270,7 @@ struct can_dev_s *stm32_caninitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2286,7 +2286,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2302,7 +2302,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index b9377f43389..356500aafb8 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -40,45 +40,45 @@ /* Configuration ************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32F7_CAN1) || \ - defined(CONFIG_STM32F7_CAN2) || defined(CONFIG_STM32F7_CAN3)) +#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || \ + defined(CONFIG_STM32_CAN2) || defined(CONFIG_STM32_CAN3)) /* CAN BAUD */ -#if defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN1_BAUD) -# error "CONFIG_STM32F7_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN2) && !defined(CONFIG_STM32F7_CAN2_BAUD) -# error "CONFIG_STM32F7_CAN2_BAUD is not defined" +#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN3) && !defined(CONFIG_STM32F7_CAN3_BAUD) -# error "CONFIG_STM32F7_CAN3_BAUD is not defined" +#if defined(CONFIG_STM32_CAN3) && !defined(CONFIG_STM32_CAN3_BAUD) +# error "CONFIG_STM32_CAN3_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32F7_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32F7_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32F7_CAN_TSEG1 -# define CONFIG_STM32F7_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32F7_CAN_TSEG1 < 1 || \ - CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +#if CONFIG_STM32_CAN_TSEG1 < 1 || \ + CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX # error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32F7_CAN_TSEG2 -# define CONFIG_STM32F7_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32F7_CAN_TSEG2 < 1 || \ - CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +#if CONFIG_STM32_CAN_TSEG2 < 1 || \ + CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX # error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif @@ -105,7 +105,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -125,7 +125,7 @@ struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index e4e8f68da1d..14f9ccda020 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -63,10 +63,10 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F7_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /* Pool configuration *******************************************************/ @@ -146,7 +146,7 @@ static void stm32can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); static void stm32can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); static void stm32can_dumpmbregs(struct stm32_can_s *priv, @@ -233,7 +233,7 @@ static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { @@ -250,12 +250,12 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { @@ -272,12 +272,12 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { @@ -294,7 +294,7 @@ static struct stm32_can_s g_can3priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; #endif @@ -312,7 +312,7 @@ static struct stm32_can_s g_can3priv = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -398,7 +398,7 @@ static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -451,7 +451,7 @@ static void stm32can_putfreg(struct stm32_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { @@ -497,7 +497,7 @@ static void stm32can_dumpctrlregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { @@ -564,7 +564,7 @@ static void stm32can_dumpmbregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { @@ -1860,15 +1860,15 @@ static int stm32can_bittiming(struct stm32_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32F7_CAN_TSEG1, - * ts2 is CONFIG_STM32F7_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2036,21 +2036,21 @@ static void stm32can_reset(struct stm32_can_s *priv) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -2298,9 +2298,9 @@ static int stm32can_filterinit(struct stm32_can_s *priv) /* Assign half the filters to CAN1, half to CAN2 */ -#if defined(CONFIG_STM32F7_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32F7_STM32F20XX) || \ - defined(CONFIG_STM32F7_STM32F4XXX) +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F4XXX) regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= CAN_FMR_CAN2SB_MASK; regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; @@ -2432,7 +2432,7 @@ int stm32_cansockinitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2448,7 +2448,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2464,7 +2464,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ @@ -2526,15 +2526,15 @@ errout: #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 stm32_cansockinitialize(1); #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 stm32_cansockinitialize(2); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 stm32_cansockinitialize(3); #endif } diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index 6e650a6e849..84efc445174 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -92,18 +92,18 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1_CAP) || \ - defined(CONFIG_STM32F7_TIM2_CAP) || \ - defined(CONFIG_STM32F7_TIM3_CAP) || \ - defined(CONFIG_STM32F7_TIM4_CAP) || \ - defined(CONFIG_STM32F7_TIM5_CAP) || \ - defined(CONFIG_STM32F7_TIM8_CAP) || \ - defined(CONFIG_STM32F7_TIM9_CAP) || \ - defined(CONFIG_STM32F7_TIM10_CAP) || \ - defined(CONFIG_STM32F7_TIM11_CAP) || \ - defined(CONFIG_STM32F7_TIM12_CAP) || \ - defined(CONFIG_STM32F7_TIM13_CAP) || \ - defined(CONFIG_STM32F7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || \ + defined(CONFIG_STM32_TIM2_CAP) || \ + defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || \ + defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM8_CAP) || \ + defined(CONFIG_STM32_TIM9_CAP) || \ + defined(CONFIG_STM32_TIM10_CAP) || \ + defined(CONFIG_STM32_TIM11_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || \ + defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) /**************************************************************************** * Private Types @@ -182,7 +182,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) { switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -209,7 +209,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -236,7 +236,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -263,7 +263,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -290,7 +290,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -320,7 +320,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -348,7 +348,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -376,7 +376,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -404,7 +404,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -432,7 +432,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -460,7 +460,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -488,7 +488,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -528,31 +528,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM5EN; @@ -561,43 +561,43 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM9EN; break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM10EN; break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM11EN; break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM14EN; @@ -1082,7 +1082,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1094,7 +1094,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1106,7 +1106,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1118,7 +1118,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1130,7 +1130,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1144,7 +1144,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1156,7 +1156,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1168,7 +1168,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1180,7 +1180,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1192,7 +1192,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1204,7 +1204,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1216,7 +1216,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1232,54 +1232,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1336,4 +1336,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index c5a0cee3b6d..f4894e9ec7f 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -71,21 +71,21 @@ # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 2 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 3 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 4 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 5 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #endif /* Are any UARTs enabled? */ @@ -93,7 +93,7 @@ #undef HAVE_UART_DEVICE #if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \ defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \ - defined(CONFIG_STM32F7_UART4) + defined(CONFIG_STM32_UART4) # define HAVE_UART_DEVICE 1 #endif @@ -107,29 +107,29 @@ # undef CONFIG_STM32F7_USART0 #endif #ifndef CONFIG_USART1_SERIALDRIVER -# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32_USART1 #endif #ifndef CONFIG_USART2_SERIALDRIVER -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif /* Don't enable USARTs not supported by the chip. */ #if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART0 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 #elif STM32_NUSART < 2 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 #elif STM32_NUSART < 3 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif /* Are any USARTs enabled? */ -#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \ - defined(CONFIG_STM32F7_USART2) +#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # undef HAVE_UART_DEVICE # define HAVE_UART_DEVICE 1 #endif @@ -199,7 +199,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -217,7 +217,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -226,7 +226,7 @@ # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -252,14 +252,14 @@ #if CHIP_NSPI < 1 # undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #elif CHIP_NSPI < 2 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #endif #ifndef CONFIG_STM32F7_HAVE_SPI # undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #endif /* Are any SPI peripherals enabled? */ diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 4b1df56c919..c56d8bdf7c5 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -46,9 +46,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -596,7 +596,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, " ntransfers: %zu scr: %08" PRIx32 "\n", paddr, maddr, ntransfers, scr); -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); #endif @@ -895,7 +895,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; @@ -958,7 +958,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) dmawarn("stm32_dmacapable:" " dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08" PRIx32 "\n", maddr, mend); -#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1121,4 +1121,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, } #endif -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index d858a62c14f..7ad69cd3ec2 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -242,7 +242,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index f8cd2d298bb..cb8cdc15fe6 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -91,7 +91,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_DMA2D_REGDEBUG +#ifdef CONFIG_STM32_DMA2D_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -109,7 +109,7 @@ struct stm32_dma2d_s { struct dma2d_layer_s dma2d; /* Public dma2d interface */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint32_t *clut; /* Color lookup table */ #endif @@ -172,7 +172,7 @@ static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] = STM32_DMA2D_OCOLR }; -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* DMA2D clut memory address register */ static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = @@ -192,7 +192,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); static int stm32_dma2dirq(int irq, void *context, void *arg); static int stm32_dma2d_waitforirq(void); static int stm32_dma2d_start(void); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_loadclut(uintptr_t reg); #endif static uint32_t @@ -212,7 +212,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Public Functions */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap); #endif static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, @@ -239,15 +239,15 @@ static bool g_initialized; /* Allocate clut */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static uint32_t g_clut[STM32_DMA2D_NCLUT * -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY 4 # else 3 # endif / 4]; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The DMA2D mutex that enforces mutually exclusive access */ @@ -270,14 +270,14 @@ static struct stm32_dma2d_s g_dma2ddev = { .dma2d = { -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .setclut = stm32_dma2d_setclut, #endif .fillcolor = stm32_dma2d_fillcolor, .blit = stm32_dma2d_blit, .blend = stm32_dma2d_blend }, -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .clut = g_clut, #endif .lock = &g_lock @@ -344,7 +344,7 @@ static int stm32_dma2dirq(int irq, void *context, void *arg) putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR); priv->error = OK; } -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 else if (regval & DMA2D_ISR_CTCIF) { /* CLUT transfer complete interrupt */ @@ -461,7 +461,7 @@ static int stm32_dma2d_waitforirq(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 static int stm32_dma2d_loadclut(uintptr_t pfcreg) { int ret; @@ -681,7 +681,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, pfccrreg = DMA2D_XGPFCCR_CM(fmt); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (fmt == DMA2D_PF_L8) { struct stm32_dma2d_s *layer = &g_dma2ddev; @@ -692,7 +692,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Set the CLUT color mode */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY pfccrreg |= DMA2D_XGPFCCR_CCM; # endif @@ -708,7 +708,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]); } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Set alpha blend mode */ @@ -744,7 +744,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) { int n; @@ -760,7 +760,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) * blit operation becomes active */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY uint8_t *clut = (uint8_t *)g_dma2ddev.clut; uint16_t offset = 3 * n; @@ -789,7 +789,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) nxmutex_unlock(priv->lock); return OK; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_dma2d_fillcolor @@ -822,7 +822,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (oinfo->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1006,7 +1006,7 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, "barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos, foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (doverlay->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1095,7 +1095,7 @@ int stm32_dma2dinitialize(void) * arch/arm/src/stm32f7/stm32f7xxxx_rcc.c */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Enable dma2d transfer and clut loading interrupts only */ stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE | diff --git a/arch/arm/src/stm32f7/stm32_dma2d.h b/arch/arm/src/stm32f7/stm32_dma2d.h index 0f84a7732bf..06ace50a01d 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.h +++ b/arch/arm/src/stm32f7/stm32_dma2d.h @@ -65,7 +65,7 @@ struct dma2d_layer_s * On error - -EINVAL */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP int (*setclut)(const struct fb_cmap_s * cmap); #endif diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h index 980add5f69f..42997245544 100644 --- a/arch/arm/src/stm32f7/stm32_dtcm.h +++ b/arch/arm/src/stm32f7/stm32_dtcm.h @@ -43,11 +43,11 @@ /* The STM32 F7 have DTCM memory */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20010000 -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20020000 #else @@ -58,7 +58,7 @@ * heap. */ -#ifndef CONFIG_STM32F7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index 45820a0adca..727ac68639a 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -144,5 +144,5 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 668418a15ca..8b281e2f31b 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -66,11 +66,11 @@ #include /* STM32_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -101,76 +101,76 @@ #define ETHWORK LPWORK -#ifndef CONFIG_STM32F7_PHYADDR -# error "CONFIG_STM32F7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32F7_MII) && !defined(CONFIG_STM32F7_RMII) -# warning "Neither CONFIG_STM32F7_MII nor CONFIG_STM32F7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32F7_MII) && defined(CONFIG_STM32F7_RMII) -# error "Both CONFIG_STM32F7_MII and CONFIG_STM32F7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32F7_MII -# if !defined(CONFIG_STM32F7_MII_MCO1) && !defined(CONFIG_STM32F7_MII_MCO2) && \ - !defined(CONFIG_STM32F7_MII_EXTCLK) -# warning "Neither CONFIG_STM32F7_MII_MCO1, CONFIG_STM32F7_MII_MCO2, nor CONFIG_STM32F7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_MII_MCO1) && defined(CONFIG_STM32F7_MII_MCO2) -# error "Both CONFIG_STM32F7_MII_MCO1 and CONFIG_STM32F7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_RMII -# if !defined(CONFIG_STM32F7_RMII_MCO1) && !defined(CONFIG_STM32F7_RMII_MCO2) && \ - !defined(CONFIG_STM32F7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32F7_RMII_MCO1, CONFIG_STM32F7_RMII_MCO2, nor CONFIG_STM32F7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_RMII_MCO1) && defined(CONFIG_STM32F7_RMII_MCO2) -# error "Both CONFIG_STM32F7_RMII_MCO1 and CONFIG_STM32F7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_AUTONEG -# ifndef CONFIG_STM32F7_PHYSR -# error "CONFIG_STM32F7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32F7_PHYSR_ALTMODE -# error "CONFIG_STM32F7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10HD -# error "CONFIG_STM32F7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100HD -# error "CONFIG_STM32F7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10FD -# error "CONFIG_STM32F7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100FD -# error "CONFIG_STM32F7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32F7_PHYSR_SPEED -# error "CONFIG_STM32F7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100MBPS -# error "CONFIG_STM32F7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_MODE -# error "CONFIG_STM32F7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32F7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP -# warning "CONFIG_STM32F7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* This driver does not use enhanced descriptors. Enhanced descriptors must @@ -178,8 +178,8 @@ * supported. */ -#undef CONFIG_STM32F7_ETH_ENHANCEDDESC -#undef CONFIG_STM32F7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_ENHANCEDDESC +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -207,16 +207,16 @@ # warning "You using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32F7_ETH_NRXDESC -# define CONFIG_STM32F7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32F7_ETH_NTXDESC -# define CONFIG_STM32F7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32F7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers use for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -231,7 +231,7 @@ #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) -#ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -243,10 +243,10 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -257,7 +257,7 @@ */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -338,7 +338,7 @@ * ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_RD Retry disable 1 (disabled) * ETH_MACCR_IPCO IPv4 checksum offload Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_ROD Receive own disable 0 (enabled) * ETH_MACCR_CSD Carrier sense disable 0 (enabled) @@ -353,7 +353,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96)) #else @@ -471,13 +471,13 @@ * ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes) * ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush) * ETH_DMAOMR_TSF Transmit store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_DMAOMR_DFRF Disable flushing of 0 (enabled) * received frames * ETH_DMAOMR_RSF Receive store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on - * error frames disable CONFIG_STM32F7_ETH_HWCHECKSUM + * error frames disable CONFIG_STM32_ETH_HWCHECKSUM * * When the checksum offload feature is enabled, we need to enable the Store * and Forward mode: the store and forward guarantee that a whole frame is @@ -485,7 +485,7 @@ * checksum is OK the DMA can handle the frame otherwise the frame is dropped */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define DMAOMR_SET_MASK \ (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ ETH_DMAOMR_TSF | ETH_DMAOMR_RSF) @@ -525,7 +525,7 @@ * ETH_DMABMR_DA DMA Arbitration 0 (round robin) * ETH_DMABMR_DSL Descriptor skip length 0 * ETH_DMABMR_EDFE Enhanced descriptor Depends on - * format enable CONFIG_STM32F7_ETH_ENHANCEDDESC + * format enable CONFIG_STM32_ETH_ENHANCEDDESC * ETH_DMABMR_PBL Programmable burst length 32 beats * ETH_DMABMR_RTPR RX TX priority ratio 2:1 * ETH_DMABMR_FB Fixed burst 1 (enabled) @@ -536,7 +536,7 @@ * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC # define DMABMR_SET_MASK \ (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \ ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) @@ -667,7 +667,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -754,10 +754,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv); /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -787,7 +787,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -859,7 +859,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -886,7 +886,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1210,7 +1210,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * un-stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32F7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMAINT_RI); } @@ -1284,7 +1284,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 || @@ -1353,7 +1353,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && @@ -1582,8 +1582,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is the first segment in the frame */ @@ -2657,7 +2657,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].txdesc; @@ -2681,7 +2681,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NTXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2751,7 +2751,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].rxdesc; @@ -2773,7 +2773,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NRXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2863,7 +2863,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32F7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3070,7 +3070,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3090,7 +3090,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) /* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3128,7 +3128,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3149,7 +3149,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_RESET); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3160,7 +3160,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform any necessary, board-specific PHY initialization */ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT ret = stm32_phy_boardinitialize(0); if (ret < 0) { @@ -3181,12 +3181,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3208,7 +3208,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3219,7 +3219,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3241,7 +3241,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, CONFIG_STM32F7_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3250,38 +3250,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32F7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. - * IF This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that + * IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for example, * with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32F7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32F7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32F7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3294,13 +3294,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32F7_PHYSR_MODE) == - CONFIG_STM32F7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32F7_PHYSR_SPEED) == CONFIG_STM32F7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3309,14 +3309,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, phyval); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3327,10 +3327,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3356,7 +3356,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3381,7 +3381,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3412,7 +3412,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32F7_MII) || defined(CONFIG_STM32F7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ @@ -3421,7 +3421,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the MII interface */ -# if defined(CONFIG_STM32F7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3436,7 +3436,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3444,7 +3444,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3452,7 +3452,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3483,7 +3483,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32F7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3498,7 +3498,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3506,7 +3506,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3514,7 +3514,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3538,7 +3538,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -3861,12 +3861,12 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list: Chain Mode */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32F7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list: Chain Mode */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32F7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Enable normal MAC operation */ @@ -3995,4 +3995,4 @@ void arm_netinitialize(void) } #endif -#endif /* STM32_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index b33dd2a646d..c23f2dcd217 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32F7_PHYINIT is defined in the + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the * configuration then the board specific logic must provide * stm32_phyinitialize(); The STM32 Ethernet driver will call this * function one time before it first uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index 39f3c0a943d..4081d9cba24 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Types @@ -376,4 +376,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_fmc.c b/arch/arm/src/stm32f7/stm32_fmc.c index 03eaea6826d..d5e955133a4 100644 --- a/arch/arm/src/stm32f7/stm32_fmc.c +++ b/arch/arm/src/stm32f7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32F7_FMC) +#if defined(CONFIG_STM32_FMC) #include #include @@ -234,4 +234,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(val, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32F7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index aeaea51aa19..5932b37c80d 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -89,22 +89,22 @@ /* PWM lower-half ops and ADC lower-half ops must be enabled */ -#ifndef CONFIG_STM32F7_PWM_LL_OPS +#ifndef CONFIG_STM32_PWM_LL_OPS # error PWM low-level operations interface must be enabled #endif -#ifndef CONFIG_STM32F7_ADC_LL_OPS +#ifndef CONFIG_STM32_ADC_LL_OPS # error ADC low-level operations interface must be enabled #endif /* We don't want start conversion during ADC setup */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV # error ADC startup conversion must be disabled #endif /* We need interface to change ADC sample-time */ -#ifndef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME # error ADC sample-time configuration interface must be enabled #endif @@ -114,35 +114,35 @@ /* FOC0 always use TIMER1 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# if CONFIG_STM32F7_TIM1_MODE != 2 +# if CONFIG_STM32_TIM1_MODE != 2 # error TIM1 must be configured in center-aligned mode 1 # endif -#endif /* CONFIG_STM32F7_FOC_FOC0 */ +#endif /* CONFIG_STM32_FOC_FOC0 */ /* FOC1 always use TIMER8 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# if CONFIG_STM32F7_TIM8_MODE != 2 +# if CONFIG_STM32_TIM8_MODE != 2 # error TIM8 must be configured in center-aligned mode 1 # endif #endif /* The maximum supported number of phases depends on the ADC trigger */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) # if CONFIG_MOTOR_FOC_PHASES > 3 # error max 3 phases supported # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) # if CONFIG_MOTOR_FOC_PHASES > 4 # error max 4 phases supported # endif @@ -158,7 +158,7 @@ /* Only one ADC trigger must be selected */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) && defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO) # error Invalid ADC trigger configuration #endif @@ -174,7 +174,7 @@ * V0 for CNTR = 0 */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* FOC ADC trigger on CCR4 **************************************************/ @@ -183,12 +183,12 @@ * - 1 channel for ADC injection sequence trigger (CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif @@ -202,10 +202,10 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4) #endif @@ -213,20 +213,20 @@ # define ADC_TRIGGER_OFFSET (1) -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4) # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* FOC ADC trigger on TRGO **************************************************/ /* PWM TRGO support must be enabled */ -# ifndef CONFIG_STM32F7_PWM_TRGO +# ifndef CONFIG_STM32_PWM_TRGO # error PWM TRGO support must be enabled # endif @@ -238,12 +238,12 @@ * - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif @@ -257,17 +257,17 @@ * TIMx TRGO = (ARR) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # error TIM8 and TRGO trigger not supported for ADC IPv1 #endif -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO) # endif @@ -280,28 +280,28 @@ /* Phase current samples for FOC0 */ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 # define FOC0_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 # define FOC0_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 # define FOC0_ADC 3 # endif #endif /* Phase current samples for FOC1 */ -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 # define FOC1_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 # define FOC1_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 # define FOC1_ADC 3 # endif #endif @@ -316,55 +316,55 @@ * 3. ADC software trigger starts only regular conversion. */ -#ifdef CONFIG_STM32F7_FOC_USE_ADC1 -# ifndef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_FOC_USE_ADC1 +# ifndef CONFIG_STM32_ADC1 # error ADC1 not supported ! # endif # ifndef ADC1_HAVE_JEXTCFG # error ADC1 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC1_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC1_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC1 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC2 -# ifndef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_FOC_USE_ADC2 +# ifndef CONFIG_STM32_ADC2 # error ADC2 not supported ! # endif # ifndef ADC2_HAVE_JEXTCFG # error ADC2 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC2_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC2_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC2 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC3 -# ifndef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_FOC_USE_ADC3 +# ifndef CONFIG_STM32_ADC3 # error ADC3 not supported ! # endif # ifndef ADC3_HAVE_JEXTCFG # error ADC3 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC3_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC3_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC3 injected channels # endif #endif /* Combine JEXTSEL with JEXTEN default */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL) #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) #endif @@ -390,39 +390,39 @@ /* FOC ADC configuration ****************************************************/ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 # define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 # define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 # define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 +# ifdef CONFIG_STM32_FOC_FOC0_ADC4 # define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 # define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 # define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 # define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 +# ifdef CONFIG_STM32_FOC_FOC1_ADC4 # define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif @@ -502,7 +502,7 @@ /* Define PWM all outputs */ -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \ STM32_PWM_OUT2N| \ STM32_PWM_OUT3N) @@ -510,7 +510,7 @@ # define PMW_OUTPUTS_ALL_COMP (0) #endif -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) # define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4) #else # define PMW_OUTPUTS_ALL_OUT4 (0) @@ -683,10 +683,10 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state); static int stm32_foc_calibration_start(struct foc_dev_s *dev); static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, uint32_t offset); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, uint8_t rcr); #else @@ -813,7 +813,7 @@ static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY /* Configure deadtime */ PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt); @@ -1015,7 +1015,7 @@ static int stm32_foc_adc_cfg(struct foc_dev_s *dev) return OK; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /**************************************************************************** * Name: stm32_foc_adc_ccr4_trg_set @@ -1047,7 +1047,7 @@ static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset); } -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /**************************************************************************** * Name: stm32_foc_adc_trgo_trg_set @@ -1140,9 +1140,9 @@ static int stm32_foc_configure(struct foc_dev_s *dev, DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq / priv->data.adc_freq) * 2); #else @@ -1156,7 +1156,7 @@ static int stm32_foc_configure(struct foc_dev_s *dev, /* REVISIT: synchronise instances if TRGO trigger selected */ #if (CONFIG_MOTOR_FOC_INST > 1) -# if defined(CONFIG_STM32F7_FOC_ADC_TRGO) +# if defined(CONFIG_STM32_FOC_ADC_TRGO) # error stm32_foc_sync_all breaks TRGO event on V0 vector # endif @@ -1704,9 +1704,9 @@ static int stm32_foc_calibration_start(struct foc_dev_s *dev) DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, 1); #else # error Invalid FOC ADC trigger @@ -2039,7 +2039,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* ADC interrupts frequency is PWM frequency */ priv->data.adc_freq = dev->cfg.pwm_freq; @@ -2048,7 +2048,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) priv->data.notifier_div = (dev->cfg.pwm_freq / freq); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* Call work on every ADC interrupt */ priv->data.notifier_div = 1; @@ -2250,7 +2250,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) switch (inst) { -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 case 0: { pwm_inst = FOC0_PWM; @@ -2264,7 +2264,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) } #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 case 1: { pwm_inst = FOC1_PWM; diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 27455106e85..611cf9987fd 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -502,4 +502,4 @@ void stm32_iocompensation(void) } } -#endif /* CONFIG_STM32F7_STM32F72XX || ... || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F72XX || ... || CONFIG_STM32_STM32F77XX */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index e805129f8e8..4c3dc112a8b 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -155,34 +155,34 @@ * * One of: * - * CONFIG_STM32F7_STM32F72XX - * CONFIG_STM32F7_STM32F73XX - * CONFIG_STM32F7_STM32F74XX - * CONFIG_STM32F7_STM32F75XX - * CONFIG_STM32F7_STM32F76XX - * CONFIG_STM32F7_STM32F77XX + * CONFIG_STM32_STM32F72XX + * CONFIG_STM32_STM32F73XX + * CONFIG_STM32_STM32F74XX + * CONFIG_STM32_STM32F75XX + * CONFIG_STM32_STM32F76XX + * CONFIG_STM32_STM32F77XX * * * and one or more interfaces: * - * CONFIG_STM32F7_I2C1 - * CONFIG_STM32F7_I2C2 - * CONFIG_STM32F7_I2C3 - * CONFIG_STM32F7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32F7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -256,8 +256,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \ - defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -265,25 +265,25 @@ #undef INVALID_CLOCK_SOURCE -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 # if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 # if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 # if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -300,25 +300,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 -# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F7_I2CTIMEOTICKS -# define CONFIG_STM32F7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -482,9 +482,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -534,7 +534,7 @@ static const struct i2c_ops_s stm32_i2c_ops = #endif }; -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -571,7 +571,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -608,7 +608,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -645,7 +645,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -766,7 +766,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -783,7 +783,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -839,12 +839,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -882,10 +882,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2740,22 +2740,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2827,5 +2827,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || \ - * CONFIG_STM32F7_I2C3 || CONFIG_STM32F7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h index e9bb1656b29..4580980d9d4 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.h +++ b/arch/arm/src/stm32f7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO -# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index 53b8e44da21..3bb12864f51 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -76,7 +76,7 @@ #include "stm32_spi.h" #include "stm32_rcc.h" -#if defined(CONFIG_STM32F7_I2S1) || defined(CONFIG_STM32F7_I2S2) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_I2S1) || defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3) /**************************************************************************** * Pre-processor Definitions @@ -92,8 +92,8 @@ # error CONFIG_AUDIO required by this driver #endif -#ifndef CONFIG_STM32F7_I2S_MAXINFLIGHT -# define CONFIG_STM32F7_I2S_MAXINFLIGHT 16 +#ifndef CONFIG_STM32_I2S_MAXINFLIGHT +# define CONFIG_STM32_I2S_MAXINFLIGHT 16 #endif /* Assume no RX/TX support until we learn better */ @@ -103,28 +103,28 @@ /* Check for I2S RX support */ -# if defined(CONFIG_STM32F7_I2S1_RX) +# if defined(CONFIG_STM32_I2S1_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_RX) +# if defined(CONFIG_STM32_I2S2_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_RX) +# if defined(CONFIG_STM32_I2S3_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -132,28 +132,28 @@ /* Check for I2S3 TX support */ -# if defined(CONFIG_STM32F7_I2S1_TX) +# if defined(CONFIG_STM32_I2S1_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_TX) +# if defined(CONFIG_STM32_I2S2_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_TX) +# if defined(CONFIG_STM32_I2S3_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -163,19 +163,19 @@ /* I2S interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven I2S not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -200,7 +200,7 @@ # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /* Debug ********************************************************************/ @@ -209,8 +209,8 @@ */ #ifndef CONFIG_DEBUG_I2S_INFO -# undef CONFIG_STM32F7_I2S_DMADEBUG -# undef CONFIG_STM32F7_I2S_REGDEBUG +# undef CONFIG_STM32_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_REGDEBUG # undef CONFIG_STM32F7_I2S_QDEBUG # undef CONFIG_STM32F7_I2S_DUMPBUFFERS #endif @@ -219,46 +219,46 @@ * logic here is constrained to byte, half-word, and word sizes. */ -#ifndef CONFIG_STM32F7_I2S1_DATALEN -# define CONFIG_STM32F7_I2S1_DATALEN 16 +#ifndef CONFIG_STM32_I2S1_DATALEN +# define CONFIG_STM32_I2S1_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S2_DATALEN -# define CONFIG_STM32F7_I2S2_DATALEN 16 +#ifndef CONFIG_STM32_I2S2_DATALEN +# define CONFIG_STM32_I2S2_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S3_DATALEN -# define CONFIG_STM32F7_I2S3_DATALEN 16 +#ifndef CONFIG_STM32_I2S3_DATALEN +# define CONFIG_STM32_I2S3_DATALEN 16 #endif -#if CONFIG_STM32F7_I2S1_DATALEN == 8 +#if CONFIG_STM32_I2S1_DATALEN == 8 # define STM32_I2S1_DATAMASK 0 -#elif CONFIG_STM32F7_I2S1_DATALEN == 16 +#elif CONFIG_STM32_I2S1_DATALEN == 16 # define STM32_I2S1_DATAMASK 1 -#elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S1_DATALEN +#elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S1_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S2_DATALEN == 8 +#if CONFIG_STM32_I2S2_DATALEN == 8 # define STM32_I2S2_DATAMASK 0 -#elif CONFIG_STM32F7_I2S2_DATALEN == 16 +#elif CONFIG_STM32_I2S2_DATALEN == 16 # define STM32_I2S2_DATAMASK 1 -#elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S2_DATALEN +#elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S2_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S3_DATALEN == 8 +#if CONFIG_STM32_I2S3_DATALEN == 8 # define STM32_I2S3_DATAMASK 0 -#elif CONFIG_STM32F7_I2S3_DATALEN == 16 +#elif CONFIG_STM32_I2S3_DATALEN == 16 # define STM32_I2S3_DATAMASK 1 -#elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S3_DATALEN +#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S3_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S3_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN #endif /* Check if we need to build RX and/or TX support */ @@ -266,7 +266,7 @@ #if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_DMADEBUG #endif #define DMA_INITIAL 0 @@ -309,7 +309,7 @@ struct stm32_transport_s sq_queue_t done; /* A queue of completed transfers */ struct work_s work; /* Supports worker thread operations */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif }; @@ -344,11 +344,11 @@ struct stm32_i2s_s sem_t bufsem; /* Buffer wait semaphore */ struct stm32_buffer_s *freelist; /* A list a free buffer containers */ - struct stm32_buffer_s containers[CONFIG_STM32F7_I2S_MAXINFLIGHT]; + struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT]; /* Debug stuff */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG bool wr; /* Last was a write */ uint32_t regaddr; /* Last address */ uint16_t regval; /* Last value */ @@ -362,7 +362,7 @@ struct stm32_i2s_s /* Register helpers */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr); #else @@ -397,12 +397,12 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) # define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) # define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -414,7 +414,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) # define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) # define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -467,15 +467,15 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv); static int i2s_dma_allocate(struct stm32_i2s_s *priv); static void i2s_dma_free(struct stm32_i2s_s *priv); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv); #endif @@ -520,7 +520,7 @@ static const struct i2s_ops_s g_i2sops = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr) { @@ -579,7 +579,7 @@ static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint32_t regaddr = priv->base + offset; uint16_t regval = getreg16(regaddr); -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, false, regval, regaddr)) { i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval); @@ -610,7 +610,7 @@ static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, { uint32_t regaddr = priv->base + offset; -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, true, regval, regaddr)) { i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval); @@ -759,9 +759,9 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) int i; priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_I2S_MAXINFLIGHT); + nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT); - for (i = 0; i < CONFIG_STM32F7_I2S_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++) { i2s_buf_free(priv, &priv->containers[i]); } @@ -771,7 +771,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * Name: i2s_dma_sampleinit * * Description: - * Initialize sampling of DMA registers (if CONFIG_STM32F7_I2S_DMADEBUG) + * Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG) * * Input Parameters: * priv - I2S state instance @@ -781,7 +781,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) +#if defined(CONFIG_STM32_I2S_DMADEBUG) static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt) { @@ -809,7 +809,7 @@ static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -875,7 +875,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -1145,7 +1145,7 @@ static void i2s_rx_worker(void *arg) if (sq_empty(&priv->rx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); if (bfcontainer) { @@ -1543,7 +1543,7 @@ static void i2s_tx_worker(void *arg) if (sq_empty(&priv->tx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); if (bfcontainer) { @@ -2441,7 +2441,7 @@ static void i2s_dma_free(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2450,7 +2450,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S1_BASE; -#ifdef CONFIG_STM32F7_I2S1_RX +#ifdef CONFIG_STM32_I2S1_RX priv->rxenab = true; if (!priv->initialized) @@ -2463,9 +2463,9 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_RX */ +#endif /* CONFIG_STM32_I2S1_RX */ -#ifdef CONFIG_STM32F7_I2S1_TX +#ifdef CONFIG_STM32_I2S1_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2480,16 +2480,16 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_TX */ +#endif /* CONFIG_STM32_I2S1_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; + priv->datalen = CONFIG_STM32_I2S1_DATALEN; #ifdef CONFIG_DEBUG priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S1 */ +#endif /* CONFIG_STM32_I2S1 */ /**************************************************************************** * Name: i2s2_configure @@ -2506,7 +2506,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2515,7 +2515,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S2_BASE; -#ifdef CONFIG_STM32F7_I2S2_RX +#ifdef CONFIG_STM32_I2S2_RX priv->rxenab = true; if (!priv->initialized) @@ -2528,9 +2528,9 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_RX */ +#endif /* CONFIG_STM32_I2S2_RX */ -#ifdef CONFIG_STM32F7_I2S2_TX +#ifdef CONFIG_STM32_I2S2_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2545,16 +2545,16 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_TX */ +#endif /* CONFIG_STM32_I2S2_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; + priv->datalen = CONFIG_STM32_I2S2_DATALEN; #ifdef CONFIG_DEBUG priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S2 */ +#endif /* CONFIG_STM32_I2S2 */ /**************************************************************************** * Name: i2s3_configure @@ -2571,7 +2571,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2580,7 +2580,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S3_BASE; -#ifdef CONFIG_STM32F7_I2S3_RX +#ifdef CONFIG_STM32_I2S3_RX priv->rxenab = true; if (!priv->initialized) @@ -2593,9 +2593,9 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_RX */ +#endif /* CONFIG_STM32_I2S3_RX */ -#ifdef CONFIG_STM32F7_I2S3_TX +#ifdef CONFIG_STM32_I2S3_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2610,16 +2610,16 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_TX */ +#endif /* CONFIG_STM32_I2S3_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; + priv->datalen = CONFIG_STM32_I2S3_DATALEN; #ifdef CONFIG_DEBUG priv->align = STM32_I2S3_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S3 */ /**************************************************************************** * Public Functions @@ -2677,7 +2677,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 if (port == 1) { /* Select I2S1 */ @@ -2686,7 +2686,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 if (port == 2) { /* Select I2S2 */ @@ -2695,7 +2695,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 if (port == 3) { /* Select I2S3 */ @@ -2736,4 +2736,4 @@ errout_with_alloc: } #endif /* I2S_HAVE_RX || I2S_HAVE_TX */ -#endif /* CONFIG_STM32F7_I2S1 || CONFIG_STM32F7_I2S2 || CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S1 || CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_lse.c b/arch/arm/src/stm32f7/stm32_lse.c index 10846796bba..ecc5b01ca3d 100644 --- a/arch/arm/src/stm32f7/stm32_lse.c +++ b/arch/arm/src/stm32f7/stm32_lse.c @@ -41,16 +41,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -59,7 +59,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -85,7 +85,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -109,17 +109,17 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable on. */ regval &= ~(RCC_BDCR_LSEDRV_MASK); - regval |= CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -153,13 +153,13 @@ void stm32_rcc_enablelse(void) } while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index c7f1aff78d6..2901e7ad46d 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -129,8 +129,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32F7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32F7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -138,23 +138,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32F7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -165,24 +165,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32F7_LTDC_L2 -# if defined(CONFIG_STM32F7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -190,7 +190,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -212,7 +212,7 @@ #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # ifndef CONFIG_STM32F7_LTDC_L2_WIDTH # define CONFIG_STM32F7_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif @@ -256,7 +256,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -271,10 +271,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32F7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32F7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -287,7 +287,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -297,7 +297,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -305,27 +305,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32F7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32F7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32F7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32F7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32F7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -333,63 +333,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32F7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32F7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32F7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32F7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32F7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32F7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32F7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32F7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32F7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32F7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32F7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32F7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32F7_LTDC_L2 -# ifdef CONFIG_STM32F7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32F7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -423,28 +423,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32F7_DMA2D -# if defined(CONFIG_STM32F7_LTDC_L1_L8) || \ - defined(CONFIG_STM32F7_LTDC_L2_L8) -# if !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32F7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32F7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -452,12 +452,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32F7_FB_CMAP -# if defined(CONFIG_STM32F7_DMA2D) && !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -465,7 +465,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -473,7 +473,7 @@ # endif #endif -#ifndef CONFIG_STM32F7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -510,9 +510,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32F7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -520,9 +520,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -530,34 +530,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -579,7 +579,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -612,7 +612,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -637,7 +637,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -645,7 +645,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -693,7 +693,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -702,7 +702,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -725,7 +725,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -795,16 +795,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC mutex that enforces mutually exclusive access */ @@ -836,7 +836,7 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -857,7 +857,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -895,9 +895,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -905,7 +905,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -941,7 +941,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -953,7 +953,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -985,7 +985,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1007,7 +1007,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1017,7 +1017,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1027,7 +1027,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1037,7 +1037,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1047,7 +1047,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1057,7 +1057,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1067,7 +1067,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1077,7 +1077,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1087,7 +1087,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1097,7 +1097,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1109,7 +1109,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1119,7 +1119,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1129,7 +1129,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1139,7 +1139,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1149,7 +1149,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1159,7 +1159,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1169,7 +1169,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1179,7 +1179,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1189,7 +1189,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1199,7 +1199,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1209,22 +1209,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1648,7 +1648,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32F7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1920,7 +1920,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -1990,7 +1990,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { @@ -2095,7 +2095,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2104,7 +2104,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2112,7 +2112,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2155,7 +2155,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2215,7 +2215,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2255,7 +2255,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2291,7 +2291,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2378,7 +2378,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2408,7 +2408,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2478,7 +2478,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2498,7 +2498,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2589,7 +2589,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2636,14 +2636,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2651,7 +2651,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxmutex_lock(layer->lock); -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2671,7 +2671,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxmutex_unlock(layer->lock); return ret; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2699,7 +2699,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2760,7 +2760,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2794,7 +2794,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = @@ -2830,7 +2830,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2892,7 +2892,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3006,7 +3006,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3022,26 +3022,26 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ @@ -3135,7 +3135,7 @@ void stm32_ltdcuninitialize(void) #ifdef CONFIG_STM32F7_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32F7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index a0d54267278..9b146f21e61 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -34,7 +34,7 @@ #include "chip.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS) /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ # define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT #endif -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_USBOTGFS_BASE # define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ @@ -58,7 +58,7 @@ # define STM32_OTG_FIFO_SIZE 1280 #endif -#if defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFSHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_USBOTGHS_BASE # define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ @@ -135,5 +135,5 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 7a1fe72b80c..803438a0dd4 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -52,8 +52,8 @@ #include "stm32_rcc.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \ - defined(CONFIG_STM32F7_OTGFSHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGFSHS)) /**************************************************************************** * Pre-processor Definitions @@ -254,7 +254,7 @@ * present */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS # define OTG_GINT_RC_W1 OTG_GINT_RC_W1_HS # else @@ -373,7 +373,7 @@ /* Maximum packet sizes for full speed endpoints */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define STM32_MAXPACKET (512) /* Max packet size (1-512) */ # else # define STM32_MAXPACKET (64) /* Max packet size (1-64) */ @@ -573,7 +573,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); # else @@ -898,7 +898,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -961,7 +961,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2163,7 +2163,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; @@ -3461,7 +3461,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_GUSBCFG_TRDT(9); # else regval |= OTG_GUSBCFG_TRDT(6); @@ -5345,15 +5345,15 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS -# ifdef CONFIG_STM32F7_NO_ULPI +# ifdef CONFIG_STM32_NO_ULPI regval = stm32_getreg(STM32_OTG_GUSBCFG); regval |= OTG_GUSBCFG_PHYSEL; stm32_putreg(regval, STM32_OTG_GUSBCFG); -# else /* CONFIG_STM32F7_NO_ULPI */ +# else /* CONFIG_STM32_NO_ULPI */ /* Switch off FS transceiver */ @@ -5376,7 +5376,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI); stm32_putreg(regval, STM32_OTG_GUSBCFG); -# ifdef CONFIG_STM32F7_INTERNAL_ULPI +# ifdef CONFIG_STM32_INTERNAL_ULPI /* Select UTMI/ULPI Interface */ @@ -5421,9 +5421,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) up_udelay(2000); -# endif /* CONFIG_STM32F7_INTERNAL_ULPI */ -# endif /* CONFIG_STM32F7_NO_ULPI */ -# endif /* CONFIG_STM32F7_OTGFSHS */ +# endif /* CONFIG_STM32_INTERNAL_ULPI */ +# endif /* CONFIG_STM32_NO_ULPI */ +# endif /* CONFIG_STM32_OTGFSHS */ /* Common USB OTG core initialization */ @@ -5465,7 +5465,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -# if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI)) +# if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_NO_ULPI)) regval |= OTG_GCCFG_PWRDWN; # endif @@ -5509,7 +5509,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_DCFG_DSPD_HS; # else regval |= OTG_DCFG_DSPD_FS; @@ -5652,7 +5652,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -# if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI) +# if defined(CONFIG_STM32_OTGFSHS) && defined(CONFIG_STM32_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done * because if both the ULPI and the FS PHY clock enable bits are set at the * same time, the ARM never awakens from WFI due to some bug / errata in @@ -5747,7 +5747,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5919,7 +5919,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) */ stm32_pullup(&priv->usbdev, true); -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 69681d2479b..8d7565adf60 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -73,8 +73,8 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32F7_SYSCFG_IOCOMPENSATION - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG_IOCOMPENSATION - Needed * * Options: * @@ -87,16 +87,16 @@ * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION -# error "CONFIG_STM32F7_SYSCFG_IOCOMPENSATION is required" +#ifndef CONFIG_STM32_SYSCFG_IOCOMPENSATION +# error "CONFIG_STM32_SYSCFG_IOCOMPENSATION is required" #endif /* Default RxFIFO size */ @@ -126,8 +126,8 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32F7_USBHOST_REGDEBUG -# undef CONFIG_STM32F7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -272,7 +272,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -285,7 +285,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -496,7 +496,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -511,7 +511,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -575,7 +575,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -597,7 +597,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -5407,7 +5407,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5433,4 +5433,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_pulsecount.c b/arch/arm/src/stm32f7/stm32_pulsecount.c index ed0a19ae079..664dd33dabd 100644 --- a/arch/arm/src/stm32f7/stm32_pulsecount.c +++ b/arch/arm/src/stm32f7/stm32_pulsecount.c @@ -173,10 +173,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -203,107 +203,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32F7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32F7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -314,7 +314,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -322,7 +322,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1303,21 +1303,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1390,7 +1390,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1399,7 +1399,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1717,7 +1717,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1727,7 +1727,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index 66f1f90ca68..689d741d4d6 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -42,7 +42,7 @@ #include "stm32_rcc.h" #include "stm32_gpio.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ /* Advanced Timer support */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -157,7 +157,7 @@ /* TRGO/TRGO2 support */ -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif @@ -225,7 +225,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -298,10 +298,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev); #endif @@ -342,7 +342,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -372,16 +372,16 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -396,114 +396,114 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1POL, - .idle = CONFIG_STM32F7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1NPOL, - .idle = CONFIG_STM32F7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM1_CH2MODE, -#ifdef CONFIG_STM32F7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2POL, - .idle = CONFIG_STM32F7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2NPOL, - .idle = CONFIG_STM32F7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM1_CH3MODE, -#ifdef CONFIG_STM32F7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3POL, - .idle = CONFIG_STM32F7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3NPOL, - .idle = CONFIG_STM32F7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM1_CH4MODE, -#ifdef CONFIG_STM32F7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH4POL, - .idle = CONFIG_STM32F7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM1_CH5MODE, -#ifdef CONFIG_STM32F7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH5POL, - .idle = CONFIG_STM32F7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM1_CH6MODE, -#ifdef CONFIG_STM32F7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH6POL, - .idle = CONFIG_STM32F7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -514,18 +514,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F7_TIM1_MODE, - .lock = CONFIG_STM32F7_TIM1_LOCK, - .t_dts = CONFIG_STM32F7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -533,72 +533,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM2_CH1MODE, -#ifdef CONFIG_STM32F7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH1POL, - .idle = CONFIG_STM32F7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM2_CH2MODE, -#ifdef CONFIG_STM32F7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH2POL, - .idle = CONFIG_STM32F7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM2_CH3MODE, -#ifdef CONFIG_STM32F7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH3POL, - .idle = CONFIG_STM32F7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM2_CH4MODE, -#ifdef CONFIG_STM32F7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH4POL, - .idle = CONFIG_STM32F7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -610,14 +610,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -629,72 +629,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32F7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM3_CH1MODE, -#ifdef CONFIG_STM32F7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH1POL, - .idle = CONFIG_STM32F7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM3_CH2MODE, -#ifdef CONFIG_STM32F7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH2POL, - .idle = CONFIG_STM32F7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM3_CH3MODE, -#ifdef CONFIG_STM32F7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH3POL, - .idle = CONFIG_STM32F7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM3_CH4MODE, -#ifdef CONFIG_STM32F7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH4POL, - .idle = CONFIG_STM32F7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -706,14 +706,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -725,72 +725,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32F7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM4_CH1MODE, -#ifdef CONFIG_STM32F7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH1POL, - .idle = CONFIG_STM32F7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM4_CH2MODE, -#ifdef CONFIG_STM32F7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH2POL, - .idle = CONFIG_STM32F7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM4_CH3MODE, -#ifdef CONFIG_STM32F7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH3POL, - .idle = CONFIG_STM32F7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM4_CH4MODE, -#ifdef CONFIG_STM32F7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH4POL, - .idle = CONFIG_STM32F7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -802,14 +802,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32F7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -821,71 +821,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32F7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM5_CH1MODE, -#ifdef CONFIG_STM32F7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH1POL, - .idle = CONFIG_STM32F7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM5_CH2MODE, -#ifdef CONFIG_STM32F7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH2POL, - .idle = CONFIG_STM32F7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM5_CH3MODE, -#ifdef CONFIG_STM32F7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH3POL, - .idle = CONFIG_STM32F7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM5_CH4MODE, -#ifdef CONFIG_STM32F7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH4POL, - .idle = CONFIG_STM32F7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -896,14 +896,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32F7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -915,18 +915,18 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32F7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -941,114 +941,114 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1POL, - .idle = CONFIG_STM32F7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1NPOL, - .idle = CONFIG_STM32F7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM8_CH2MODE, -#ifdef CONFIG_STM32F7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2POL, - .idle = CONFIG_STM32F7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2NPOL, - .idle = CONFIG_STM32F7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM8_CH3MODE, -#ifdef CONFIG_STM32F7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3POL, - .idle = CONFIG_STM32F7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3NPOL, - .idle = CONFIG_STM32F7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM8_CH4MODE, -#ifdef CONFIG_STM32F7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH4POL, - .idle = CONFIG_STM32F7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM8_CH5MODE, -#ifdef CONFIG_STM32F7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH5POL, - .idle = CONFIG_STM32F7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM8_CH6MODE, -#ifdef CONFIG_STM32F7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH6POL, - .idle = CONFIG_STM32F7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1059,18 +1059,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32F7_TIM8_MODE, - .lock = CONFIG_STM32F7_TIM8_LOCK, - .t_dts = CONFIG_STM32F7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1078,40 +1078,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM static struct stm32_pwmchan_s g_pwm9channels[] = { /* TIM9 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM9_CH1MODE, -#ifdef CONFIG_STM32F7_TIM9_CH1OUT + .mode = CONFIG_STM32_TIM9_CH1MODE, +#ifdef CONFIG_STM32_TIM9_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH1POL, - .idle = CONFIG_STM32F7_TIM9_CH1IDLE, + .pol = CONFIG_STM32_TIM9_CH1POL, + .idle = CONFIG_STM32_TIM9_CH1IDLE, .pincfg = PWM_TIM9_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM9_CH2MODE, -#ifdef CONFIG_STM32F7_TIM9_CH2OUT + .mode = CONFIG_STM32_TIM9_CH2MODE, +#ifdef CONFIG_STM32_TIM9_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH2POL, - .idle = CONFIG_STM32F7_TIM9_CH2IDLE, + .pol = CONFIG_STM32_TIM9_CH2POL, + .idle = CONFIG_STM32_TIM9_CH2IDLE, .pincfg = PWM_TIM9_CH2CFG, } #endif @@ -1123,7 +1123,7 @@ static struct stm32_pwmchan_s g_pwm9channels[] = static struct stm32_pwmtimer_s g_pwm9dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 9, @@ -1142,24 +1142,24 @@ static struct stm32_pwmtimer_s g_pwm9dev = .base = STM32_TIM9_BASE, .pclk = TIMCLK_TIM9, }; -#endif /* CONFIG_STM32F7_TIM9_PWM */ +#endif /* CONFIG_STM32_TIM9_PWM */ -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM static struct stm32_pwmchan_s g_pwm10channels[] = { /* TIM10 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM10_CH1MODE, -#ifdef CONFIG_STM32F7_TIM10_CH1OUT + .mode = CONFIG_STM32_TIM10_CH1MODE, +#ifdef CONFIG_STM32_TIM10_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM10_CH1POL, - .idle = CONFIG_STM32F7_TIM10_CH1IDLE, + .pol = CONFIG_STM32_TIM10_CH1POL, + .idle = CONFIG_STM32_TIM10_CH1IDLE, .pincfg = PWM_TIM10_CH1CFG, } #endif @@ -1171,7 +1171,7 @@ static struct stm32_pwmchan_s g_pwm10channels[] = static struct stm32_pwmtimer_s g_pwm10dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 10, @@ -1190,24 +1190,24 @@ static struct stm32_pwmtimer_s g_pwm10dev = .base = STM32_TIM10_BASE, .pclk = TIMCLK_TIM10, }; -#endif /* CONFIG_STM32F7_TIM10_PWM */ +#endif /* CONFIG_STM32_TIM10_PWM */ -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM static struct stm32_pwmchan_s g_pwm11channels[] = { /* TIM11 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM11_CH1MODE, -#ifdef CONFIG_STM32F7_TIM11_CH1OUT + .mode = CONFIG_STM32_TIM11_CH1MODE, +#ifdef CONFIG_STM32_TIM11_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM11_CH1POL, - .idle = CONFIG_STM32F7_TIM11_CH1IDLE, + .pol = CONFIG_STM32_TIM11_CH1POL, + .idle = CONFIG_STM32_TIM11_CH1IDLE, .pincfg = PWM_TIM11_CH1CFG, } #endif @@ -1219,7 +1219,7 @@ static struct stm32_pwmchan_s g_pwm11channels[] = static struct stm32_pwmtimer_s g_pwm11dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 11, @@ -1238,40 +1238,40 @@ static struct stm32_pwmtimer_s g_pwm11dev = .base = STM32_TIM11_BASE, .pclk = TIMCLK_TIM11, }; -#endif /* CONFIG_STM32F7_TIM11_PWM */ +#endif /* CONFIG_STM32_TIM11_PWM */ -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM12_CH1MODE, -#ifdef CONFIG_STM32F7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH1POL, - .idle = CONFIG_STM32F7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM12_CH2MODE, -#ifdef CONFIG_STM32F7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH2POL, - .idle = CONFIG_STM32F7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1283,7 +1283,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1302,24 +1302,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32F7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM13_CH1MODE, -#ifdef CONFIG_STM32F7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM13_CH1POL, - .idle = CONFIG_STM32F7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1331,7 +1331,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1350,24 +1350,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32F7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM14_CH1MODE, -#ifdef CONFIG_STM32F7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM14_CH1POL, - .idle = CONFIG_STM32F7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1379,7 +1379,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1398,7 +1398,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32F7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ /**************************************************************************** * Private Functions @@ -1698,7 +1698,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1753,7 +1753,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -1798,7 +1798,7 @@ static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr) } #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /**************************************************************************** * Name: pwm_rcr_get ****************************************************************************/ @@ -2486,7 +2486,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3033,7 +3033,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3042,7 +3042,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3051,7 +3051,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3060,7 +3060,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3069,7 +3069,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3078,7 +3078,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3087,7 +3087,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { regaddr = TIMRCCEN_TIM9; @@ -3096,7 +3096,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { regaddr = TIMRCCEN_TIM10; @@ -3105,7 +3105,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { regaddr = TIMRCCEN_TIM11; @@ -3114,7 +3114,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3123,7 +3123,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3132,7 +3132,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3520,7 +3520,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3531,7 +3531,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3539,7 +3539,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3547,7 +3547,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3555,7 +3555,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3563,7 +3563,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3574,7 +3574,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { lower = &g_pwm9dev; @@ -3582,7 +3582,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { lower = &g_pwm10dev; @@ -3591,7 +3591,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { lower = &g_pwm11dev; @@ -3599,7 +3599,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3607,7 +3607,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3615,7 +3615,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3635,4 +3635,4 @@ errout: return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 06a7671301a..637833554ea 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -57,41 +57,41 @@ * pulsed output signal generation. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32F7_TIM9 -# undef CONFIG_STM32F7_TIM9_PWM +#ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_PWM #endif -#ifndef CONFIG_STM32F7_TIM10 -# undef CONFIG_STM32F7_TIM10_PWM +#ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_PWM #endif -#ifndef CONFIG_STM32F7_TIM11 -# undef CONFIG_STM32F7_TIM11_PWM +#ifndef CONFIG_STM32_TIM11 +# undef CONFIG_STM32_TIM11_PWM #endif -#ifndef CONFIG_STM32F7_TIM12 -# undef CONFIG_STM32F7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32F7_TIM13 -# undef CONFIG_STM32F7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32F7_TIM14 -# undef CONFIG_STM32F7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output @@ -103,38 +103,38 @@ /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32F7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,59 +269,59 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 # define PWM_TIM9_CHANNEL1 1 #else # define PWM_TIM9_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 # define PWM_TIM9_CHANNEL2 1 #else # define PWM_TIM9_CHANNEL2 0 #endif #define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 # define PWM_TIM10_CHANNEL1 1 #else # define PWM_TIM10_CHANNEL1 0 #endif #define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 # define PWM_TIM11_CHANNEL1 1 #else # define PWM_TIM11_CHANNEL1 0 #endif #define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: @@ -336,410 +336,410 @@ * not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32F7_TIM1_PWM -# if !defined(CONFIG_STM32F7_TIM1_CHANNEL) -# error "CONFIG_STM32F7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM1_CHANNEL == 1 -# define CONFIG_STM32F7_TIM1_CHANNEL1 1 -# define CONFIG_STM32F7_TIM1_CH1MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 2 -# define CONFIG_STM32F7_TIM1_CHANNEL2 1 -# define CONFIG_STM32F7_TIM1_CH2MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 3 -# define CONFIG_STM32F7_TIM1_CHANNEL3 1 -# define CONFIG_STM32F7_TIM1_CH3MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 4 -# define CONFIG_STM32F7_TIM1_CHANNEL4 1 -# define CONFIG_STM32F7_TIM1_CH4MODE CONFIG_STM32F7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM2_PWM -# if !defined(CONFIG_STM32F7_TIM2_CHANNEL) -# error "CONFIG_STM32F7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM2_CHANNEL == 1 -# define CONFIG_STM32F7_TIM2_CHANNEL1 1 -# define CONFIG_STM32F7_TIM2_CH1MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 2 -# define CONFIG_STM32F7_TIM2_CHANNEL2 1 -# define CONFIG_STM32F7_TIM2_CH2MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 3 -# define CONFIG_STM32F7_TIM2_CHANNEL3 1 -# define CONFIG_STM32F7_TIM2_CH3MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 4 -# define CONFIG_STM32F7_TIM2_CHANNEL4 1 -# define CONFIG_STM32F7_TIM2_CH4MODE CONFIG_STM32F7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM3_PWM -# if !defined(CONFIG_STM32F7_TIM3_CHANNEL) -# error "CONFIG_STM32F7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM3_CHANNEL == 1 -# define CONFIG_STM32F7_TIM3_CHANNEL1 1 -# define CONFIG_STM32F7_TIM3_CH1MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 2 -# define CONFIG_STM32F7_TIM3_CHANNEL2 1 -# define CONFIG_STM32F7_TIM3_CH2MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 3 -# define CONFIG_STM32F7_TIM3_CHANNEL3 1 -# define CONFIG_STM32F7_TIM3_CH3MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 4 -# define CONFIG_STM32F7_TIM3_CHANNEL4 1 -# define CONFIG_STM32F7_TIM3_CH4MODE CONFIG_STM32F7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM4_PWM -# if !defined(CONFIG_STM32F7_TIM4_CHANNEL) -# error "CONFIG_STM32F7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM4_CHANNEL == 1 -# define CONFIG_STM32F7_TIM4_CHANNEL1 1 -# define CONFIG_STM32F7_TIM4_CH1MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 2 -# define CONFIG_STM32F7_TIM4_CHANNEL2 1 -# define CONFIG_STM32F7_TIM4_CH2MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 3 -# define CONFIG_STM32F7_TIM4_CHANNEL3 1 -# define CONFIG_STM32F7_TIM4_CH3MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 4 -# define CONFIG_STM32F7_TIM4_CHANNEL4 1 -# define CONFIG_STM32F7_TIM4_CH4MODE CONFIG_STM32F7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM5_PWM -# if !defined(CONFIG_STM32F7_TIM5_CHANNEL) -# error "CONFIG_STM32F7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM5_CHANNEL == 1 -# define CONFIG_STM32F7_TIM5_CHANNEL1 1 -# define CONFIG_STM32F7_TIM5_CH1MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 2 -# define CONFIG_STM32F7_TIM5_CHANNEL2 1 -# define CONFIG_STM32F7_TIM5_CH2MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 3 -# define CONFIG_STM32F7_TIM5_CHANNEL3 1 -# define CONFIG_STM32F7_TIM5_CH3MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 4 -# define CONFIG_STM32F7_TIM5_CHANNEL4 1 -# define CONFIG_STM32F7_TIM5_CH4MODE CONFIG_STM32F7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM8_PWM -# if !defined(CONFIG_STM32F7_TIM8_CHANNEL) -# error "CONFIG_STM32F7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM8_CHANNEL == 1 -# define CONFIG_STM32F7_TIM8_CHANNEL1 1 -# define CONFIG_STM32F7_TIM8_CH1MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 2 -# define CONFIG_STM32F7_TIM8_CHANNEL2 1 -# define CONFIG_STM32F7_TIM8_CH2MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 3 -# define CONFIG_STM32F7_TIM8_CHANNEL3 1 -# define CONFIG_STM32F7_TIM8_CH3MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 4 -# define CONFIG_STM32F7_TIM8_CHANNEL4 1 -# define CONFIG_STM32F7_TIM8_CH4MODE CONFIG_STM32F7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM9_PWM -# if !defined(CONFIG_STM32F7_TIM9_CHANNEL) -# error "CONFIG_STM32F7_TIM9_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM9_CHANNEL == 1 -# define CONFIG_STM32F7_TIM9_CHANNEL1 1 -# define CONFIG_STM32F7_TIM9_CH1MODE CONFIG_STM32F7_TIM9_CHMODE -# elif CONFIG_STM32F7_TIM9_CHANNEL == 2 -# define CONFIG_STM32F7_TIM9_CHANNEL2 1 -# define CONFIG_STM32F7_TIM9_CH2MODE CONFIG_STM32F7_TIM9_CHMODE +#ifdef CONFIG_STM32_TIM9_PWM +# if !defined(CONFIG_STM32_TIM9_CHANNEL) +# error "CONFIG_STM32_TIM9_CHANNEL must be provided" +# elif CONFIG_STM32_TIM9_CHANNEL == 1 +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# elif CONFIG_STM32_TIM9_CHANNEL == 2 +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM9_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" # endif # define PWM_TIM9_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM10_PWM -# if !defined(CONFIG_STM32F7_TIM10_CHANNEL) -# error "CONFIG_STM32F7_TIM10_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM10_CHANNEL == 1 -# define CONFIG_STM32F7_TIM10_CHANNEL1 1 -# define CONFIG_STM32F7_TIM10_CH1MODE CONFIG_STM32F7_TIM10_CHMODE +#ifdef CONFIG_STM32_TIM10_PWM +# if !defined(CONFIG_STM32_TIM10_CHANNEL) +# error "CONFIG_STM32_TIM10_CHANNEL must be provided" +# elif CONFIG_STM32_TIM10_CHANNEL == 1 +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM10_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" # endif # define PWM_TIM10_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM11_PWM -# if !defined(CONFIG_STM32F7_TIM11_CHANNEL) -# error "CONFIG_STM32F7_TIM11_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM11_CHANNEL == 1 -# define CONFIG_STM32F7_TIM11_CHANNEL1 1 -# define CONFIG_STM32F7_TIM11_CH1MODE CONFIG_STM32F7_TIM11_CHMODE +#ifdef CONFIG_STM32_TIM11_PWM +# if !defined(CONFIG_STM32_TIM11_CHANNEL) +# error "CONFIG_STM32_TIM11_CHANNEL must be provided" +# elif CONFIG_STM32_TIM11_CHANNEL == 1 +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM11_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" # endif # define PWM_TIM11_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM12_PWM -# if !defined(CONFIG_STM32F7_TIM12_CHANNEL) -# error "CONFIG_STM32F7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM12_CHANNEL == 1 -# define CONFIG_STM32F7_TIM12_CHANNEL1 1 -# define CONFIG_STM32F7_TIM12_CH1MODE CONFIG_STM32F7_TIM12_CHMODE -# elif CONFIG_STM32F7_TIM12_CHANNEL == 2 -# define CONFIG_STM32F7_TIM12_CHANNEL2 1 -# define CONFIG_STM32F7_TIM12_CH2MODE CONFIG_STM32F7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM13_PWM -# if !defined(CONFIG_STM32F7_TIM13_CHANNEL) -# error "CONFIG_STM32F7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM13_CHANNEL == 1 -# define CONFIG_STM32F7_TIM13_CHANNEL1 1 -# define CONFIG_STM32F7_TIM13_CH1MODE CONFIG_STM32F7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM14_PWM -# if !defined(CONFIG_STM32F7_TIM14_CHANNEL) -# error "CONFIG_STM32F7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM14_CHANNEL == 1 -# define CONFIG_STM32F7_TIM14_CHANNEL1 1 -# define CONFIG_STM32F7_TIM14_CH1MODE CONFIG_STM32F7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#endif /* CONFIG_STM32F7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH1OUT +#ifdef CONFIG_STM32_TIM9_CH1OUT # define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT #else # define PWM_TIM9_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH2OUT +#ifdef CONFIG_STM32_TIM9_CH2OUT # define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT #else # define PWM_TIM9_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM10_CH1OUT +#ifdef CONFIG_STM32_TIM10_CH1OUT # define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT #else # define PWM_TIM10_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM11_CH1OUT +#ifdef CONFIG_STM32_TIM11_CH1OUT # define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT #else # define PWM_TIM11_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 @@ -747,12 +747,12 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined(CONFIG_STM32F7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F7_TIM8_CH1NOUT) || defined(CONFIG_STM32F7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) @@ -761,7 +761,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -786,7 +786,7 @@ (dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr) #define PWM_RCR_GET(dev) \ (dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev) -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define PWM_TRGO_SET(dev, trgo) \ (dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo) #endif @@ -898,7 +898,7 @@ enum stm32_pwm_output_e /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -954,7 +954,7 @@ struct stm32_pwm_ops_s uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev); -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO /* Set TRGO/TRGO2 register */ int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo); @@ -998,7 +998,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1044,5 +1044,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c index c86b70a2474..5fac63ef025 100644 --- a/arch/arm/src/stm32f7/stm32_pwr.c +++ b/arch/arm/src/stm32f7/stm32_pwr.c @@ -35,7 +35,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c index e3afc99eb67..fdf06b3bb0d 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ b/arch/arm/src/stm32f7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32F7_TIM2_QE) || defined(CONFIG_STM32F7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM3_QE) || \ - defined(CONFIG_STM32F7_TIM4_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32F7_QENCODER_FILTER -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32F7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32F7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -943,37 +943,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h index 3531846389c..40b2f6f92e1 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ b/arch/arm/src/stm32f7/stm32_qencoder.h @@ -43,23 +43,23 @@ * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 65e52304863..e67a30f701a 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) && defined(CONFIG_STM32F7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,7 +92,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -104,26 +104,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32F7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32F7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32F7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32F7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -164,14 +164,14 @@ struct stm32f7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -181,11 +181,11 @@ struct stm32f7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32f7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -222,7 +222,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -235,7 +235,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -262,16 +262,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32F7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32f7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32f7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); @@ -281,8 +281,8 @@ static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32F7_QSPI_DMATHRESHOLD -# define CONFIG_STM32F7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -336,13 +336,13 @@ static struct stm32f7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -368,7 +368,7 @@ static struct stm32f7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -420,7 +420,7 @@ static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -443,7 +443,7 @@ static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -625,7 +625,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -831,7 +831,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -962,7 +962,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1086,7 +1086,7 @@ static void qspi_ccrconfig(struct stm32f7_qspidev_s *priv, } } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1313,7 +1313,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1579,7 +1579,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2011,7 +2011,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2192,7 +2192,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2253,11 +2253,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32F7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2419,18 +2419,18 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32F7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32F7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1) + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2451,10 +2451,10 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32F7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32F7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32F7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2560,7 +2560,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2574,7 +2574,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2600,7 +2600,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2608,12 +2608,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2679,7 +2679,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2698,7 +2698,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2744,4 +2744,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index a82c3296e06..5485ac57384 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -127,5 +127,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index 92b4ec75fef..b0c35860a24 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -63,11 +63,11 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "stm32f72xx73xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "stm32f74xx75xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "stm32f76xx77xx_rcc.c" #else # error "Unsupported STM32 F7 chip" @@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configurationfile. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -104,14 +104,14 @@ void stm32_clockconfig(void) rcc_reset(); -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); #endif -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -131,7 +131,7 @@ void stm32_clockconfig(void) rcc_enableperipherals(); -#ifdef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -151,7 +151,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index 9a1d166e96d..2bf57bb9855 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -147,7 +147,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,9 +164,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -216,7 +216,7 @@ void stm32_rcc_enablelsi(void); void stm32_rcc_disablelsi(void); -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Name: stm32_rcc_dsisrcphy * diff --git a/arch/arm/src/stm32f7/stm32_rng.c b/arch/arm/src/stm32f7/stm32_rng.c index 7eeb2d4916c..10bad1e664e 100644 --- a/arch/arm/src/stm32f7/stm32_rng.c +++ b/arch/arm/src/stm32f7/stm32_rng.c @@ -40,7 +40,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32F7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -329,4 +329,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index c5d1cc56096..9e2deaff4a0 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32F7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32F7_PWR -# error "CONFIG_STM32F7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32F7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32F7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32F7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h index 91ce5049523..b6130256949 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.h +++ b/arch/arm/src/stm32f7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32F7_RTC_MAGIC) -# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32F7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_REG) -# define CONFIG_STM32F7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32F7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32F7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32F7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index c05e18fc7fe..75d8e998f4e 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -68,7 +68,7 @@ #include "stm32_sai.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32F7_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -86,11 +86,11 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32F7_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32F7_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif @@ -106,19 +106,19 @@ # define CONFIG_STM32F7_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 #ifndef STM32_SAI1_FREQUENCY # error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 #ifndef STM32_SAI2_FREQUENCY # error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ # if defined(CONFIG_STM32F7_SAI_DMAPRIO) @@ -194,7 +194,7 @@ struct stm32f7_sai_s mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -236,7 +236,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_schedule(struct stm32f7_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -274,19 +274,19 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -295,19 +295,19 @@ static struct stm32f7_sai_s g_sai1a_priv = }; #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -318,19 +318,19 @@ static struct stm32f7_sai_s g_sai1b_priv = /* SAI2 state */ -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -339,19 +339,19 @@ static struct stm32f7_sai_s g_sai2a_priv = }; #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -491,7 +491,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #else /* GCR */ -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 uint32_t gcr = getreg32(STM32_SAI1_GCR); i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else @@ -757,7 +757,7 @@ static void sai_timeout(wdparm_t arg) struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ stm32_dmastop(priv->dma); @@ -787,7 +787,7 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static int sai_dma_setup(struct stm32f7_sai_s *priv) { struct sai_buffer_s *bfcontainer; @@ -959,7 +959,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -1071,7 +1071,7 @@ static void sai_schedule(struct stm32f7_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; @@ -1268,7 +1268,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1368,7 +1368,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1522,7 +1522,7 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) sai_datawidth((struct i2s_dev_s *)priv, CONFIG_STM32F7_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ priv->dma = stm32_dmachannel(priv->dma_ch); @@ -1581,7 +1581,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); @@ -1589,7 +1589,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI1_FS_A); stm32_configgpio(GPIO_SAI1_SCK_A); stm32_configgpio(GPIO_SAI1_MCLK_A); @@ -1598,7 +1598,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); @@ -1606,7 +1606,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI1_FS_B); stm32_configgpio(GPIO_SAI1_SCK_B); stm32_configgpio(GPIO_SAI1_MCLK_B); @@ -1615,7 +1615,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); @@ -1623,7 +1623,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI2_FS_A); stm32_configgpio(GPIO_SAI2_SCK_A); stm32_configgpio(GPIO_SAI2_MCLK_A); @@ -1632,7 +1632,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); @@ -1640,7 +1640,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI2_FS_B); stm32_configgpio(GPIO_SAI2_SCK_B); stm32_configgpio(GPIO_SAI2_MCLK_B); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 1bf6eac7baf..d82877095a1 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -53,7 +53,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -65,7 +65,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32F7_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -74,15 +74,15 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional. + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally optional. * For most usages, SDMMC will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32F7_SDMMC_DMA is enabled. - * CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output. This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * * CONFIG_SDMMC1/2_SDIO_MODE @@ -100,20 +100,20 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#ifndef CONFIG_STM32F7_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# ifndef CONFIG_STM32F7_DMA2 -# error "CONFIG_STM32F7_SDMMC_DMA support requires CONFIG_STM32F7_DMA2" +# ifndef CONFIG_STM32_DMA2 +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32F7_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -121,16 +121,16 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32F7_SDMMC1 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC1_DMAPRIO -# define CONFIG_STM32F7_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC1_CLK UINT32_C(48000000) @@ -139,16 +139,16 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC2 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC2_DMAPRIO -# define CONFIG_STM32F7_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC2_CLK UINT32_C(48000000) @@ -163,7 +163,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32F7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -345,8 +345,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -379,7 +379,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -409,7 +409,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -433,7 +433,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -450,7 +450,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -473,7 +473,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -488,7 +488,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -563,7 +563,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -572,7 +572,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen); static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ /* Initialization/uninitialization/reset ************************************/ @@ -583,7 +583,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -615,7 +615,7 @@ struct stm32_dev_s g_sdmmcdev1 = .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -627,7 +627,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif .dmarecvsetup = stm32_recvsetup, .dmasendsetup = stm32_sendsetup, -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ #endif /* CONFIG_SDIO_DMA*/ }, .base = STM32_SDMMC1_BASE, @@ -636,8 +636,8 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -651,7 +651,7 @@ struct stm32_dev_s g_sdmmcdev1 = }; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -696,8 +696,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -712,7 +712,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -859,7 +859,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -952,7 +952,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -968,7 +968,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -992,12 +992,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -1016,7 +1016,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -1046,12 +1046,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -1070,13 +1070,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -1089,7 +1089,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1107,7 +1107,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1515,7 +1515,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1625,7 +1625,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1664,7 +1664,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1884,7 +1884,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1903,7 +1903,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ priv->rxbuffer = 0; priv->rxend = 0; @@ -1944,7 +1944,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2241,7 +2241,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2298,7 +2298,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2354,7 +2354,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2871,7 +2871,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2968,11 +2968,11 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32F7_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); @@ -3009,7 +3009,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3112,7 +3112,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3315,18 +3315,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; # endif @@ -3356,14 +3356,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; # endif @@ -3398,7 +3398,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ priv->dma = stm32_dmachannel(dmachan); @@ -3499,7 +3499,7 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32F7_SDMMC1 || CONFIG_STM32F7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ #ifdef HAVE_SDMMC_SDIO_MODE void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index c04b5eca680..c73b64b0548 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -78,16 +78,16 @@ */ # if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 # endif # endif # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -135,14 +135,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -172,16 +172,16 @@ */ #if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART6_TXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 transmit DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 transmit DMA requires CONFIG_STM32_DMA2 # endif #endif #if defined(CONFIG_USART2_TXDMA) || defined(CONFIG_USART3_TXDMA) || \ defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) || \ defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32_DMA1 # endif #endif @@ -228,7 +228,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -331,8 +331,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART. @@ -354,7 +354,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -364,13 +364,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -413,7 +413,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32F7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -720,49 +720,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -770,7 +770,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -839,7 +839,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -908,7 +908,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -977,7 +977,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1046,7 +1046,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1115,7 +1115,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1184,7 +1184,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1253,7 +1253,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1324,28 +1324,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1635,7 +1635,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1828,49 +1828,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1ENR_UART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1ENR_UART5EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1ENR_UART7EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1ENR_UART8EN; regaddr = STM32_RCC_APB1ENR; @@ -1938,7 +1938,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2291,8 +2291,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2405,11 +2405,11 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2432,7 +2432,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2499,7 +2499,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2550,7 +2550,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2687,8 +2687,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F7_USART_BREAKS -# ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2907,7 +2907,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3699,7 +3699,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3728,7 +3728,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index 4ddc01a5539..2b43927a3ec 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -73,9 +73,9 @@ #include "stm32_dma.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,39 +135,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32F7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,10 +182,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -231,7 +231,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -291,7 +291,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -336,11 +336,11 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # ifdef SPI1_DMABUFSIZE_ADJUSTED @@ -362,7 +362,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -407,11 +407,11 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -433,7 +433,7 @@ static struct stm32_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -478,11 +478,11 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI3_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -504,7 +504,7 @@ static struct stm32_spidev_s g_spi3dev = }; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -549,11 +549,11 @@ static struct stm32_spidev_s g_spi4dev = }, .spibase = STM32_SPI4_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI4, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI4_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # ifdef SPI4_DMABUFSIZE_ADJUSTED @@ -575,7 +575,7 @@ static struct stm32_spidev_s g_spi4dev = }; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -620,11 +620,11 @@ static struct stm32_spidev_s g_spi5dev = }, .spibase = STM32_SPI5_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI5, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI5_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # ifdef SPI5_DMABUFSIZE_ADJUSTED @@ -646,7 +646,7 @@ static struct stm32_spidev_s g_spi5dev = }; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -691,11 +691,11 @@ static struct stm32_spidev_s g_spi6dev = }, .spibase = STM32_SPI6_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI6, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI6_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # ifdef SPI6_DMABUFSIZE_ADJUSTED @@ -916,7 +916,7 @@ static inline void spi_writebyte(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -949,7 +949,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -982,7 +982,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -997,7 +997,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -1012,7 +1012,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1032,7 +1032,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1052,7 +1052,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -1103,7 +1103,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -1154,7 +1154,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -1170,7 +1170,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1397,7 +1397,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA uint16_t cr2bits; #endif @@ -1440,7 +1440,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_modifycr1(priv, 0, SPI_CR1_SPE); spi_modifycr1(priv, setbits, clrbits); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Enabling SPI causes a spurious received character indication * which confuse the DMA controller so we disable DMA during that * enabling; and flush the SPI RX FIFO before re-enabling DMA. @@ -1461,7 +1461,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_getreg(priv, STM32_SPI_DR_OFFSET); } -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Re-enable DMA (with SPI disabled) */ @@ -1691,9 +1691,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32F7_SPI_DMA) || defined(CONFIG_STM32F7_DMACAPABLE) || \ - defined(CONFIG_STM32F7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32F7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1777,8 +1777,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32F7_SPI_DMA || CONFIG_STM32F7_DMACAPABLE || - * CONFIG_STM32F7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1802,7 +1802,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1816,13 +1816,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32F7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() * do the work. */ - if (nbytes <= CONFIG_STM32F7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1840,7 +1840,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* If this bus uses a in driver DMA aligned buffers we can skip the test */ if ((txbuffer && priv->txbuf == 0 && @@ -1948,7 +1948,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, } } } -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1969,7 +1969,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2173,7 +2173,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the @@ -2235,7 +2235,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2260,7 +2260,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2285,7 +2285,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2310,7 +2310,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2335,7 +2335,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2360,7 +2360,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2393,6 +2393,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F7_SPI1 || CONFIG_STM32F7_SPI2 || CONFIG_STM32F7_SPI3 || - * CONFIG_STM32F7_SPI4 || CONFIG_STM32F7_SPI5 || CONFIG_STM32F7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h index f4adbac6a5e..346af668597 100644 --- a/arch/arm/src/stm32f7/stm32_spi.h +++ b/arch/arm/src/stm32f7/stm32_spi.h @@ -98,42 +98,42 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -161,32 +161,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c index 52ddb0e04bd..d348d93cadb 100644 --- a/arch/arm/src/stm32f7/stm32_tickless.c +++ b/arch/arm/src/stm32f7/stm32_tickless.c @@ -107,18 +107,18 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32F7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32F7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if CONFIG_STM32F7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -426,43 +426,43 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32F7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM1STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM2STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM3STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM4STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM5STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: /* Basic timers not supported by this implementation */ @@ -471,7 +471,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: /* Basic timers not supported by this implementation */ @@ -480,52 +480,52 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM8STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM9STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM10STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM11STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM12STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM13STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM14STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; @@ -534,7 +534,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; @@ -543,7 +543,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; @@ -559,8 +559,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32F7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32F7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1027,10 +1027,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1047,7 +1047,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1068,7 +1068,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index e5ba5829719..622568201c1 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -72,140 +72,140 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined (CONFIG_STM32F7_TIM1_ADC) || \ - defined(CONFIG_STM32F7_TIM1_DAC) || defined(CONFIG_STM32F7_TIM1_QE) -# undef CONFIG_STM32F7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) || defined (CONFIG_STM32F7_TIM2_ADC) || \ - defined(CONFIG_STM32F7_TIM2_DAC) || defined(CONFIG_STM32F7_TIM2_QE) -# undef CONFIG_STM32F7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) || defined (CONFIG_STM32F7_TIM3_ADC) || \ - defined(CONFIG_STM32F7_TIM3_DAC) || defined(CONFIG_STM32F7_TIM3_QE) -# undef CONFIG_STM32F7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) || defined (CONFIG_STM32F7_TIM4_ADC) || \ - defined(CONFIG_STM32F7_TIM4_DAC) || defined(CONFIG_STM32F7_TIM4_QE) -# undef CONFIG_STM32F7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32F7_TIM5_PWM) || defined (CONFIG_STM32F7_TIM5_ADC) || \ - defined(CONFIG_STM32F7_TIM5_DAC) || defined(CONFIG_STM32F7_TIM5_QE) -# undef CONFIG_STM32F7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32F7_TIM6_ADC) || \ - defined(CONFIG_STM32F7_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) -# undef CONFIG_STM32F7_TIM6 +#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \ - defined(CONFIG_STM32F7_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) -# undef CONFIG_STM32F7_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32F7_TIM8_PWM) || defined (CONFIG_STM32F7_TIM8_ADC) || \ - defined(CONFIG_STM32F7_TIM8_DAC) || defined(CONFIG_STM32F7_TIM8_QE) -# undef CONFIG_STM32F7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32F7_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ - defined(CONFIG_STM32F7_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) -# undef CONFIG_STM32F7_TIM9 +#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ + defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) +# undef CONFIG_STM32_TIM9 #endif -#if defined(CONFIG_STM32F7_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ - defined(CONFIG_STM32F7_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) -# undef CONFIG_STM32F7_TIM10 +#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ + defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) +# undef CONFIG_STM32_TIM10 #endif -#if defined(CONFIG_STM32F7_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ - defined(CONFIG_STM32F7_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) -# undef CONFIG_STM32F7_TIM11 +#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ + defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) +# undef CONFIG_STM32_TIM11 #endif -#if defined(CONFIG_STM32F7_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ - defined(CONFIG_STM32F7_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) -# undef CONFIG_STM32F7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32F7_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ - defined(CONFIG_STM32F7_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) -# undef CONFIG_STM32F7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32F7_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ - defined(CONFIG_STM32F7_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) -# undef CONFIG_STM32F7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32F7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM9) +#if defined(CONFIG_STM32_TIM9) # if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) # define HAVE_TIM9_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM10) +#if defined(CONFIG_STM32_TIM10) # if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) # define HAVE_TIM10_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM11) +#if defined(CONFIG_STM32_TIM11) # if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) # define HAVE_TIM11_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) # define HAVE_TIM12_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) # define HAVE_TIM13_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) # define HAVE_TIM14_GPIOCONFIG 1 @@ -216,13 +216,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) /**************************************************************************** * Private Types @@ -326,14 +326,14 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif /* TIM5 is 32-bits on all except F10x lines */ -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -431,72 +431,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -550,72 +550,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: vectorno = STM32_IRQ_TIM9; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: vectorno = STM32_IRQ_TIM10; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: vectorno = STM32_IRQ_TIM11; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; @@ -818,7 +818,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -843,7 +843,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -872,7 +872,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -901,7 +901,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -930,7 +930,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -984,7 +984,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -# ifdef CONFIG_STM32F7_TIM9 +# ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: switch (channel) { @@ -1013,7 +1013,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: switch (channel) { @@ -1042,7 +1042,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: switch (channel) { @@ -1071,7 +1071,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1100,7 +1100,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1240,7 +1240,7 @@ struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -1249,7 +1249,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -1258,7 +1258,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -1267,7 +1267,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -1276,7 +1276,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -1285,7 +1285,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -1294,7 +1294,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -1303,7 +1303,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -1312,7 +1312,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 struct stm32_tim_priv_s stm32_tim9_priv = { .ops = &stm32_tim_ops, @@ -1321,7 +1321,7 @@ struct stm32_tim_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 struct stm32_tim_priv_s stm32_tim10_priv = { .ops = &stm32_tim_ops, @@ -1330,7 +1330,7 @@ struct stm32_tim_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 struct stm32_tim_priv_s stm32_tim11_priv = { .ops = &stm32_tim_ops, @@ -1339,7 +1339,7 @@ struct stm32_tim_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -1348,7 +1348,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -1357,7 +1357,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -1378,85 +1378,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); @@ -1488,72 +1488,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); break; @@ -1569,4 +1569,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM8) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c index f0f5dda38f0..1005d174f75 100644 --- a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c @@ -56,13 +56,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -144,7 +144,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -152,7 +152,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -160,7 +160,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -168,7 +168,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -176,7 +176,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -184,7 +184,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -192,7 +192,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -200,7 +200,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -208,7 +208,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -216,7 +216,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -224,7 +224,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -232,7 +232,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -240,7 +240,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -248,7 +248,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -482,72 +482,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index d65dbe36b2f..e3f555f43ad 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -41,43 +41,43 @@ */ #if STM32_NUART < 4 -# undef CONFIG_STM32F7_UART8 +# undef CONFIG_STM32_UART8 #endif #if STM32_NUART < 3 -# undef CONFIG_STM32F7_UART7 +# undef CONFIG_STM32_UART7 #endif #if STM32_NUART < 2 -# undef CONFIG_STM32F7_UART5 +# undef CONFIG_STM32_UART5 #endif #if STM32_NUART < 1 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #endif #if STM32_NUSART < 4 -# undef CONFIG_STM32F7_USART6 +# undef CONFIG_STM32_USART6 #endif #if STM32_NUSART < 3 -# undef CONFIG_STM32F7_USART3 +# undef CONFIG_STM32_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F7_USART1) || defined(CONFIG_STM32F7_USART2) || \ - defined(CONFIG_STM32F7_USART3) || defined(CONFIG_STM32F7_UART4) || \ - defined(CONFIG_STM32F7_UART5) || defined(CONFIG_STM32F7_USART6) || \ - defined(CONFIG_STM32F7_UART7) || defined(CONFIG_STM32F7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -195,42 +195,42 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F7_USART1 +#ifndef CONFIG_STM32_USART1 # undef CONFIG_USART1_RXDMA # undef CONFIG_USART1_TXDMA #endif -#ifndef CONFIG_STM32F7_USART2 +#ifndef CONFIG_STM32_USART2 # undef CONFIG_USART2_RXDMA # undef CONFIG_USART2_TXDMA #endif -#ifndef CONFIG_STM32F7_USART3 +#ifndef CONFIG_STM32_USART3 # undef CONFIG_USART3_RXDMA # undef CONFIG_USART3_TXDMA #endif -#ifndef CONFIG_STM32F7_UART4 +#ifndef CONFIG_STM32_UART4 # undef CONFIG_UART4_RXDMA # undef CONFIG_UART4_TXDMA #endif -#ifndef CONFIG_STM32F7_UART5 +#ifndef CONFIG_STM32_UART5 # undef CONFIG_UART5_RXDMA # undef CONFIG_UART5_TXDMA #endif -#ifndef CONFIG_STM32F7_USART6 +#ifndef CONFIG_STM32_USART6 # undef CONFIG_USART6_RXDMA # undef CONFIG_USART6_TXDMA #endif -#ifndef CONFIG_STM32F7_UART7 +#ifndef CONFIG_STM32_UART7 # undef CONFIG_UART7_RXDMA # undef CONFIG_UART7_TXDMA #endif -#ifndef CONFIG_STM32F7_UART8 +#ifndef CONFIG_STM32_UART8 # undef CONFIG_UART8_RXDMA # undef CONFIG_UART8_TXDMA #endif @@ -300,42 +300,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h index 7ae4f8e9d25..68eaee020a8 100644 --- a/arch/arm/src/stm32f7/stm32_usbhost.h +++ b/arch/arm/src/stm32f7/stm32_usbhost.h @@ -28,10 +28,10 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32F7_SYSCFG - Needed + * CONFIG_STM32_OTGFSHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * @@ -44,7 +44,7 @@ * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGFSHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 2633267d255..629881f1196 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -167,13 +167,13 @@ static inline void rcc_enableahb1(void) ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -185,31 +185,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -217,9 +217,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -229,7 +229,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -252,31 +252,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -303,13 +303,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -336,151 +336,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -492,19 +492,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -531,67 +531,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -601,56 +601,56 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_OTGFSHS -#ifdef CONFIG_STM32F7_INTERNAL_ULPI +#ifdef CONFIG_STM32_OTGFSHS +#ifdef CONFIG_STM32_INTERNAL_ULPI regval |= RCC_APB2ENR_OTGPHYCEN; #endif @@ -669,7 +669,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -764,7 +764,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -831,7 +831,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -857,7 +857,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) /* Configure PLLSAI */ @@ -865,14 +865,14 @@ static void stm32_stdclockconfig(void) regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_PLLSAICFGR_PLLSAIR_MASK # endif ); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIP | STM32_RCC_PLLSAICFGR_PLLSAIQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_PLLSAICFGR_PLLSAIR # endif ); @@ -881,7 +881,7 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_DCKCFGR1); regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK | RCC_DCKCFGR1_PLLSAIDIVQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_DCKCFGR1_PLLSAIDIVR_MASK # endif | RCC_DCKCFGR1_SAI1SEL_MASK @@ -890,7 +890,7 @@ static void stm32_stdclockconfig(void) regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ | STM32_RCC_DCKCFGR1_PLLSAIDIVQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_DCKCFGR1_PLLSAIDIVR # endif | STM32_RCC_DCKCFGR1_SAI1SRC @@ -919,13 +919,13 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_PLLI2SCFGR); regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_PLLI2SCFGR_PLLI2SP_MASK # endif | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_PLLI2SCFGR_PLLI2SP # endif | STM32_RCC_PLLI2SCFGR_PLLI2SQ @@ -956,7 +956,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_I2C1SEL_MASK | RCC_DCKCFGR2_I2C2SEL_MASK | RCC_DCKCFGR2_I2C3SEL_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_DCKCFGR2_I2C4SEL_MASK | RCC_DCKCFGR2_CECSEL_MASK # endif @@ -975,7 +975,7 @@ static void stm32_stdclockconfig(void) | STM32_RCC_DCKCFGR2_I2C1SRC | STM32_RCC_DCKCFGR2_I2C2SRC | STM32_RCC_DCKCFGR2_I2C3SRC -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_DCKCFGR2_I2C4SRC | STM32_RCC_DCKCFGR2_CECSRC # endif @@ -986,13 +986,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index f2a51b9e306..fa7e56b6c6c 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -169,13 +169,13 @@ static inline void rcc_enableahb1(void) ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -187,31 +187,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -219,9 +219,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -231,7 +231,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -254,31 +254,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -305,13 +305,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -338,151 +338,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -494,19 +494,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -533,67 +533,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -603,49 +603,49 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; @@ -664,7 +664,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -759,7 +759,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -826,7 +826,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -852,7 +852,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) /* Configure PLLSAI */ @@ -961,13 +961,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 070060097d5..e14d7017494 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 -/* If CONFIG_STM32F7_DSIHOST is defined in the board configuration, then +/* If CONFIG_STM32_DSIHOST is defined in the board configuration, then * STM32_RCC_DCKCFGR2_DSISRC must also be defined to select the clock * source. */ @@ -177,13 +177,13 @@ static inline void rcc_enableahb1(void) ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -195,31 +195,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -227,9 +227,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -239,7 +239,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -262,31 +262,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -313,13 +313,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -346,157 +346,157 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#if defined(CONFIG_STM32F7_SPI2) || defined(CONFIG_STM32F7_I2S2) +#if defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_I2S2) /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#if defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_I2S3) /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 /* CAN3 clock enable. */ regval |= (RCC_APB1ENR_CAN3EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -508,19 +508,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -547,67 +547,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -617,55 +617,55 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_DSIHOST +#ifdef CONFIG_STM32_DSIHOST /* LTDC clock enable */ regval |= RCC_APB2ENR_DSIEN; @@ -684,7 +684,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -779,7 +779,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -846,7 +846,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -872,7 +872,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) /* Configure PLLSAI */ @@ -990,13 +990,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/boards/arm/stm32f7/common/Kconfig b/boards/arm/stm32f7/common/Kconfig index 2d926e6634d..8be75fe6173 100644 --- a/boards/arm/stm32f7/common/Kconfig +++ b/boards/arm/stm32f7/common/Kconfig @@ -3,178 +3,178 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -config STM32F7_ROMFS +config STM32_ROMFS bool "Automount baked-in ROMFS image" default n depends on FS_ROMFS ---help--- - Select STM32F7_ROMFS_IMAGEFILE, STM32F7_ROMFS_DEV_MINOR, STM32F7_ROMFS_MOUNTPOINT + Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT -config STM32F7_ROMFS_DEV_MINOR +config STM32_ROMFS_DEV_MINOR int "Minor for the block device backing the data" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default 64 -config STM32F7_ROMFS_MOUNTPOINT +config STM32_ROMFS_MOUNTPOINT string "Mountpoint of the custom romfs image" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default "/rom" -config STM32F7_ROMFS_IMAGEFILE +config STM32_ROMFS_IMAGEFILE string "ROMFS image file to include into build" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default "../../../rom.img" -config STM32F7_SPI_TEST +config STM32_SPI_TEST bool "Enable SPI test" default n ---help--- Enable Spi test - initialize and configure SPI to send - STM32F7_SPI_TEST_MESSAGE text. The text is sent on the + STM32_SPI_TEST_MESSAGE text. The text is sent on the selected SPI Buses with the configured parameters. Note the CS lines will not be asserted. -if STM32F7_SPI_TEST +if STM32_SPI_TEST -config STM32F7_SPI_TEST_MESSAGE +config STM32_SPI_TEST_MESSAGE string "Text to Send on SPI Bus(es)" default "Hello World" - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Text to sent on SPI bus(es) -config STM32F7_SPI1_TEST +config STM32_SPI1_TEST bool "Test SPI bus 1" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 1 -if STM32F7_SPI1_TEST +if STM32_SPI1_TEST -config STM32F7_SPI1_TEST_FREQ +config STM32_SPI1_TEST_FREQ int "SPI 1 Clock Freq in Hz" default 1000000 - depends on STM32F7_SPI1_TEST + depends on STM32_SPI1_TEST ---help--- Sets SPI 1 Clock Freq -config STM32F7_SPI1_TEST_BITS +config STM32_SPI1_TEST_BITS int "SPI 1 number of bits" default 8 - depends on STM32F7_SPI1_TEST + depends on STM32_SPI1_TEST ---help--- Sets SPI 1 bit length choice prompt "SPI BUS 1 Clock Mode" - default STM32F7_SPI1_TEST_MODE3 + default STM32_SPI1_TEST_MODE3 ---help--- Sets SPI 1 clock mode -config STM32F7_SPI1_TEST_MODE0 +config STM32_SPI1_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI1_TEST_MODE1 +config STM32_SPI1_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI1_TEST_MODE2 +config STM32_SPI1_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI1_TEST_MODE3 +config STM32_SPI1_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 1 Clock Mode" -endif # STM32F7_SPI1_TEST +endif # STM32_SPI1_TEST -config STM32F7_SPI2_TEST +config STM32_SPI2_TEST bool "Test SPI bus 2" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 2 -if STM32F7_SPI2_TEST +if STM32_SPI2_TEST -config STM32F7_SPI2_TEST_FREQ +config STM32_SPI2_TEST_FREQ int "SPI 2 Clock Freq in Hz" default 12000000 - depends on STM32F7_SPI2_TEST + depends on STM32_SPI2_TEST ---help--- Sets SPI 2 Clock Freq -config STM32F7_SPI2_TEST_BITS +config STM32_SPI2_TEST_BITS int "SPI 2 number of bits" default 8 - depends on STM32F7_SPI2_TEST + depends on STM32_SPI2_TEST ---help--- Sets SPI 2 bit length choice prompt "SPI BUS 2 Clock Mode" - default STM32F7_SPI2_TEST_MODE3 + default STM32_SPI2_TEST_MODE3 ---help--- Sets SPI 2 clock mode -config STM32F7_SPI2_TEST_MODE0 +config STM32_SPI2_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI2_TEST_MODE1 +config STM32_SPI2_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI2_TEST_MODE2 +config STM32_SPI2_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI2_TEST_MODE3 +config STM32_SPI2_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 2 Clock Mode" -endif # STM32F7_SPI2_TEST +endif # STM32_SPI2_TEST -config STM32F7_SPI3_TEST +config STM32_SPI3_TEST bool "Test SPI bus 3" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 3 -if STM32F7_SPI3_TEST +if STM32_SPI3_TEST -config STM32F7_SPI3_TEST_FREQ +config STM32_SPI3_TEST_FREQ int "SPI 3 Clock Freq in Hz" default 40000000 - depends on STM32F7_SPI3_TEST + depends on STM32_SPI3_TEST ---help--- Sets SPI 3 Clock Freq -config STM32F7_SPI3_TEST_BITS +config STM32_SPI3_TEST_BITS int "SPI 3 number of bits" default 8 - depends on STM32F7_SPI3_TEST + depends on STM32_SPI3_TEST ---help--- Sets SPI 3 bit length choice prompt "SPI BUS 3 Clock Mode" - default STM32F7_SPI3_TEST_MODE3 + default STM32_SPI3_TEST_MODE3 ---help--- Sets SPI 3 clock mode -config STM32F7_SPI3_TEST_MODE0 +config STM32_SPI3_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI3_TEST_MODE1 +config STM32_SPI3_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI3_TEST_MODE2 +config STM32_SPI3_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI3_TEST_MODE3 +config STM32_SPI3_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 3 Clock Mode" -endif # STM32F7_SPI3_TEST -endif # STM32F7_SPI_TEST +endif # STM32_SPI3_TEST +endif # STM32_SPI_TEST diff --git a/boards/arm/stm32f7/common/include/stm32_can_setup.h b/boards/arm/stm32f7/common/include/stm32_can_setup.h index 5361bfe204a..d0632d611df 100644 --- a/boards/arm/stm32f7/common/include/stm32_can_setup.h +++ b/boards/arm/stm32f7/common/include/stm32_can_setup.h @@ -61,7 +61,7 @@ extern "C" * Name: stm32_can_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER int stm32_can_setup(void); #endif diff --git a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h b/boards/arm/stm32f7/common/include/stm32_cansock_setup.h index 971f2216dcb..5dcab9fd7b5 100644 --- a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h +++ b/boards/arm/stm32f7/common/include/stm32_cansock_setup.h @@ -61,7 +61,7 @@ extern "C" * Name: stm32_cansock_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET int stm32_cansock_setup(void); #endif diff --git a/boards/arm/stm32f7/common/include/stm32_romfs.h b/boards/arm/stm32f7/common/include/stm32_romfs.h index 3b52acfa36f..577b3a7f4ff 100644 --- a/boards/arm/stm32f7/common/include/stm32_romfs.h +++ b/boards/arm/stm32f7/common/include/stm32_romfs.h @@ -43,7 +43,7 @@ #include -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /**************************************************************************** * Pre-processor Definitions @@ -72,6 +72,6 @@ int stm32_romfs_initialize(void); -#endif /* CONFIG_STM32F7_ROMFS */ +#endif /* CONFIG_STM32_ROMFS */ #endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_spitest.h b/boards/arm/stm32f7/common/include/stm32_spitest.h index 09605759e1e..860042f9469 100644 --- a/boards/arm/stm32f7/common/include/stm32_spitest.h +++ b/boards/arm/stm32f7/common/include/stm32_spitest.h @@ -62,7 +62,7 @@ extern "C" * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt index f653591bd15..d4b612a0f4b 100644 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ b/boards/arm/stm32f7/common/src/CMakeLists.txt @@ -34,16 +34,16 @@ if(CONFIG_AUDIO_CS4344) list(APPEND SRCS stm32_cs4344.c) endif() -if(CONFIG_STM32F7_CAN) - if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can_setup.c) endif() - if(CONFIG_STM32F7_CAN_SOCKET) + if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_cansock_setup.c) endif() endif() -if(CONFIG_STM32F7_ROMFS) +if(CONFIG_STM32_ROMFS) list(APPEND SRCS stm32_romfs_initialize.c) endif() @@ -51,7 +51,7 @@ if(CONFIG_BOARDCTL_RESET) list(APPEND SRCS stm32_reset.c) endif() -if(CONFIG_STM32F7_SPI_TEST) +if(CONFIG_STM32_SPI_TEST) list(APPEND SRCS stm32_spitest.c) endif() diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs index 04321561a58..0a4f96c20c4 100644 --- a/boards/arm/stm32f7/common/src/Make.defs +++ b/boards/arm/stm32f7/common/src/Make.defs @@ -34,16 +34,16 @@ ifeq ($(CONFIG_AUDIO_CS4344),y) CSRCS += stm32_cs4344.c endif -ifeq ($(CONFIG_STM32F7_CAN),y) -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CSRCS += stm32_can_setup.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CSRCS += stm32_cansock_setup.c endif endif -ifeq ($(CONFIG_STM32F7_ROMFS),y) +ifeq ($(CONFIG_STM32_ROMFS),y) CSRCS += stm32_romfs_initialize.c endif @@ -51,7 +51,7 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += stm32_reset.c endif -ifeq ($(CONFIG_STM32F7_SPI_TEST),y) +ifeq ($(CONFIG_STM32_SPI_TEST),y) CSRCS += stm32_spitest.c endif diff --git a/boards/arm/stm32f7/common/src/stm32_can_setup.c b/boards/arm/stm32f7/common/src/stm32_can_setup.c index 5f62d6da00f..2eedf06992e 100644 --- a/boards/arm/stm32f7/common/src/stm32_can_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_can_setup.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #else # define CAN_PORT 2 @@ -60,7 +60,7 @@ int stm32_can_setup(void) { -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) struct can_dev_s *can; int ret; @@ -85,7 +85,7 @@ int stm32_can_setup(void) return OK; #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; diff --git a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c index 2bb60d2b8bc..58dbf738cfe 100644 --- a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c @@ -36,7 +36,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN2) +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) # error "No CAN is enable. Please enable at least one CAN device" #endif @@ -58,7 +58,7 @@ int stm32_cansock_setup(void) UNUSED(ret); -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(1); @@ -69,7 +69,7 @@ int stm32_cansock_setup(void) } #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(2); diff --git a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c index 53fe0927d43..1d105e29b0e 100644 --- a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c @@ -54,20 +54,20 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_ROMFS -# error "CONFIG_STM32F7_ROMFS must be defined" +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_IMAGEFILE -# error "CONFIG_STM32F7_ROMFS_IMAGEFILE must be defined" +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_DEV_MINOR -# error "CONFIG_STM32F7_ROMFS_DEV_MINOR must be defined" +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_MOUNTPOINT -# error "CONFIG_STM32F7_ROMFS_MOUNTPOINT must be defined" +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" #endif #define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) @@ -76,7 +76,7 @@ #define STR(m) STR2(m) #define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32F7_ROMFS_DEV_MINOR) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) /**************************************************************************** * Private Data @@ -87,7 +87,7 @@ __asm__ ( ".balign 16\n" ".globl romfs_data_begin\n" "romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32F7_ROMFS_IMAGEFILE) "\n"\ + ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ \ ".balign " STR(ROMFS_SECTOR_SIZE) "\n" ".globl romfs_data_end\n" @@ -125,7 +125,7 @@ int stm32_romfs_initialize(void) romfs_data_len = romfs_data_end - romfs_data_begin; - ret = romdisk_register(CONFIG_STM32F7_ROMFS_DEV_MINOR, romfs_data_begin, + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); if (ret < 0) { @@ -136,14 +136,14 @@ int stm32_romfs_initialize(void) /* Mount the file system */ finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, "romfs", MS_RDONLY, NULL); if (ret < 0) { ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); return ret; } diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c index 51bf2d63ca6..5ae8b71833a 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -43,42 +43,42 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1_TEST) -# if defined(CONFIG_STM32F7_SPI1_TEST_MODE0) +#if defined(CONFIG_STM32_SPI1_TEST) +# if defined(CONFIG_STM32_SPI1_TEST_MODE0) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE1) +# elif defined(CONFIG_STM32_SPI1_TEST_MODE1) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE2) +# elif defined(CONFIG_STM32_SPI1_TEST_MODE2) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE3) +# elif defined(CONFIG_STM32_SPI1_TEST_MODE3) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined" # endif #endif -#if defined(CONFIG_STM32F7_SPI2_TEST) -# if defined(CONFIG_STM32F7_SPI2_TEST_MODE0) +#if defined(CONFIG_STM32_SPI2_TEST) +# if defined(CONFIG_STM32_SPI2_TEST_MODE0) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE1) +# elif defined(CONFIG_STM32_SPI2_TEST_MODE1) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE2) +# elif defined(CONFIG_STM32_SPI2_TEST_MODE2) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE3) +# elif defined(CONFIG_STM32_SPI2_TEST_MODE3) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined" # endif #endif -#if defined(CONFIG_STM32F7_SPI3_TEST) -# if defined(CONFIG_STM32F7_SPI3_TEST_MODE0) +#if defined(CONFIG_STM32_SPI3_TEST) +# if defined(CONFIG_STM32_SPI3_TEST_MODE0) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE1) +# elif defined(CONFIG_STM32_SPI3_TEST_MODE1) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE2) +# elif defined(CONFIG_STM32_SPI3_TEST_MODE2) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE3) +# elif defined(CONFIG_STM32_SPI3_TEST_MODE3) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined" @@ -89,13 +89,13 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) struct spi_dev_s *g_spi1; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) struct spi_dev_s *g_spi2; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) struct spi_dev_s *g_spi3; #endif @@ -108,7 +108,7 @@ struct spi_dev_s *g_spi3; * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ @@ -116,9 +116,9 @@ int stm32_spidev_bus_test(void) { /* Configure and test SPI- */ - uint8_t *tx = (uint8_t *)CONFIG_STM32F7_SPI_TEST_MESSAGE; + uint8_t *tx = (uint8_t *)CONFIG_STM32_SPI_TEST_MESSAGE; -#if defined(CONFIG_STM32F7_SPI1_TEST) +#if defined(CONFIG_STM32_SPI1_TEST) g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) @@ -129,14 +129,14 @@ int stm32_spidev_bus_test(void) /* Default SPI1 to STM32_SPI1_FREQ and mode */ - SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); - SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); + SPI_SETFREQUENCY(g_spi1, CONFIG_STM32_SPI1_TEST_FREQ); + SPI_SETBITS(g_spi1, CONFIG_STM32_SPI1_TEST_BITS); SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE); SPI_EXCHANGE(g_spi1, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif -#if defined(CONFIG_STM32F7_SPI2_TEST) +#if defined(CONFIG_STM32_SPI2_TEST) g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) @@ -147,14 +147,14 @@ int stm32_spidev_bus_test(void) /* Default SPI2 to STM32_SPI2_FREQ and mode */ - SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); - SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); + SPI_SETFREQUENCY(g_spi2, CONFIG_STM32_SPI2_TEST_FREQ); + SPI_SETBITS(g_spi2, CONFIG_STM32_SPI2_TEST_BITS); SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE); SPI_EXCHANGE(g_spi2, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif -#if defined(CONFIG_STM32F7_SPI3_TEST) +#if defined(CONFIG_STM32_SPI3_TEST) g_spi3 = stm32_spibus_initialize(3); if (!g_spi3) @@ -165,11 +165,11 @@ int stm32_spidev_bus_test(void) /* Default SPI3 to STM32_SPI3_FREQ and mode */ - SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); - SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); + SPI_SETFREQUENCY(g_spi3, CONFIG_STM32_SPI3_TEST_FREQ); + SPI_SETBITS(g_spi3, CONFIG_STM32_SPI3_TEST_BITS); SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE); SPI_EXCHANGE(g_spi3, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif return OK; diff --git a/boards/arm/stm32f7/nucleo-f722ze/Kconfig b/boards/arm/stm32f7/nucleo-f722ze/Kconfig index 60ec42530ca..884622e3a10 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/Kconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F722ZE_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F722ZE_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F722ZE_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig index 59f5aaad34e..1cb4871af1a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -46,12 +47,12 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig index c03ccde370c..59a299a0093 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_SOCKET=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig index f856c740564..c5ade09840d 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -70,10 +71,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig index 2e7c9a4dabd..d1dd0b02677 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -42,9 +43,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt index f8b17eb732e..030ab2e9850 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs index 084c954afc3..d39777f15f4 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h index 1db1e63552c..4b4039a3e9b 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h +++ b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -263,7 +263,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -295,7 +295,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 96deea3ee98..6f66e59090f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -49,19 +49,19 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index 04b76397fdf..2ed57dfe5f3 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c index 82194ab10bf..16862f9ada7 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c index 7c848385d0c..6339b20c21f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c index 2ab163679c5..20272a1dac8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c index 1adc20c2cae..8614a43c515 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c index c38a390ca09..26f3bf756fd 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c index 57a304d3a3e..1a4e5d2f19e 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f746zg/Kconfig b/boards/arm/stm32f7/nucleo-f746zg/Kconfig index c1d96afcf0b..d59a47ec85b 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/Kconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F746ZG_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F746ZG_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F746ZG_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig index d32e6ac0e4c..95125cef760 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -52,9 +53,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig index 0112b71b52d..0997aceb7ed 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -95,46 +96,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NOTE=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig index ae9b97ca15c..c1b3531bf8a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,10 +44,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_DTCMEXCLUDE=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig index 291c438c26c..fe194da3baf 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig @@ -6,7 +6,7 @@ # modifications. # # CONFIG_NDEBUG is not set -# CONFIG_STM32F7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=16 CONFIG_ANALOG=y @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -91,46 +92,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt index 73a308ecf1c..1c42f137288 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs index 92eaf789e58..78a75d54df0 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h index a71f98a2c34..2a1c8d883b7 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h +++ b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -276,7 +276,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -308,7 +308,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 7f79bebc84d..c1f68f20083 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -49,19 +49,19 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index 7834ac832df..ab415b60f99 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c index adab9af41bb..da3915eacc6 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c index 39d379e5c8d..f7cc0a58d81 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c index bb3c0cfae36..983a1bddb56 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c index a2de94884cc..8100783be19 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c index ee391eb04ad..417e00c2ae1 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c index 1e3c23c0ad7..fe457155c2a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f767zi/Kconfig b/boards/arm/stm32f7/nucleo-f767zi/Kconfig index e8eb80d5fab..e01d882951f 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/Kconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F767ZI_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F767ZI_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F767ZI_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig index 3baad155b05..93030ce7258 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -55,10 +56,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig index 6ddfdc06852..240cfc4a2e9 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,15 +63,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig index bc43b47e6f8..c78a21c59fa 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt index 28d7f560bef..b9e35dee705 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs index b4c24d64fec..77197f80a79 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h index 60c9ab458c9..2816cc143d2 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h +++ b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h @@ -126,7 +126,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -137,7 +137,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -179,9 +179,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -205,11 +205,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -301,7 +301,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -333,7 +333,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index bf7d56c0c6b..7c871a67cd2 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -49,19 +49,19 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index 31431f9d53d..f443aaca0aa 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c index c6bf11bbf24..b1bdae2f12b 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c index 4213f82a5a2..8f705ee31e1 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -112,14 +112,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -154,7 +154,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -167,7 +167,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -203,7 +203,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -215,7 +215,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -227,7 +227,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -239,7 +239,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -253,7 +253,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -262,7 +262,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -270,7 +270,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c index 9ddb4938292..b6619c43310 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c index 800b70d45d0..9dbd545ea85 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c index 3b19fd2fa66..788b0c1963c 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c index 1e4c86e2623..f153ccd2c64 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/steval-eth001v1/Kconfig b/boards/arm/stm32f7/steval-eth001v1/Kconfig index 6d1513de7bc..64f4caa11eb 100644 --- a/boards/arm/stm32f7/steval-eth001v1/Kconfig +++ b/boards/arm/stm32f7/steval-eth001v1/Kconfig @@ -5,12 +5,12 @@ if ARCH_BOARD_STEVAL_ETH001V1 -if STM32F7_FOC +if STM32_FOC config BOARD_STM32F7_STEVALETH001V1_FOC_VBUS bool "STEVAL-ETH001V1 board VBUS sense" default n -endif # STM32F7_FOC +endif # STM32_FOC endif # ARCH_BOARD_STEVAL_ETH001V1 diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig index 89261567704..04b8ea48f2c 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig index 2d3229bf10e..244c71c100b 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig index cf898372ae8..4e4dea5daa4 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt index 0082f8f9499..fb3a6271dbe 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt +++ b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs index ace68763fc4..6d4a16a40b5 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs +++ b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CSRCS += stm32_foc.c endif diff --git a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h index 22026d5156f..caf25dc1ae0 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h +++ b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h @@ -72,7 +72,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC int stm32_foc_setup(void); #endif diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c index 1ef16e93ce0..b69d7f74819 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c @@ -65,7 +65,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC /* Initialize and register the FOC device - must be before ADC setup */ ret = stm32_foc_setup(); diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c index 9a27e7bc948..93d7ec8bd1e 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c @@ -54,33 +54,33 @@ * 2. PWM complementary channels must have positive polarity */ -#ifndef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # error #endif -#if CONFIG_STM32F7_TIM1_CH1POL != 0 +#if CONFIG_STM32_TIM1_CH1POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2POL != 0 +#if CONFIG_STM32_TIM1_CH2POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3POL != 0 +#if CONFIG_STM32_TIM1_CH3POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH1NPOL != 0 +#if CONFIG_STM32_TIM1_CH1NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2NPOL != 0 +#if CONFIG_STM32_TIM1_CH2NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3NPOL != 0 +#if CONFIG_STM32_TIM1_CH3NPOL != 0 # error #endif /* Aux ADC needs DMA enabled */ #ifdef CONFIG_ADC -# ifndef CONFIG_STM32F7_ADC1_DMA +# ifndef CONFIG_STM32_ADC1_DMA # error # endif #endif @@ -122,7 +122,7 @@ #define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS # define STEVALETH001V1_FOC_VBUS 1 #else # define STEVALETH001V1_FOC_VBUS 0 @@ -133,11 +133,11 @@ /* Check ADC1 configuration */ -#if ADC1_INJECTED != CONFIG_STM32F7_ADC1_INJECTED_CHAN +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN # error #endif -#if CONFIG_STM32F7_ADC1_RESOLUTION != 0 +#if CONFIG_STM32_ADC1_RESOLUTION != 0 # error #endif @@ -186,7 +186,7 @@ static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); static uint8_t g_adc1_chan[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS 14, /* ADC1 REG - VBUS */ #endif 15, /* ADC1 INJ1 - PHASE 1 */ @@ -196,7 +196,7 @@ static uint8_t g_adc1_chan[] = static uint32_t g_adc1_pins[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS GPIO_ADC1_IN14, #endif GPIO_ADC1_IN15, @@ -208,7 +208,7 @@ static uint32_t g_adc1_pins[] = static adc_channel_t g_adc1_stime[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS { .channel = 14, .sample_time = VBUS_SAMPLE_TIME diff --git a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig index 378ee084c7f..30bf96e0d37 100644 --- a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746-ws" CONFIG_ARCH_BOARD_STM32F746_WS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746IG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_INTERRUPTSTACK=2600 @@ -75,15 +76,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_DMACAPABLE=y -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SDMMC1=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_SPI1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt index 973faf1d304..00b881c28cf 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt @@ -22,11 +22,11 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_dma_alloc.c) -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs index 80e52803544..67df23791a9 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs @@ -24,11 +24,11 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_spi.c stm32_dma_alloc.c -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c index eb4801aefb4..16dc06038d0 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c @@ -86,9 +86,9 @@ static void stm32_i2ctool(void) void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -127,7 +127,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* Initialize the SDIO block driver */ int ret = OK; diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c index 9d86414318e..17ca34d8bfa 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746-ws.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -195,42 +195,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -238,4 +238,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI6 */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c index b4a9bf9f192..4625864a28b 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32_gpio.h" #include "stm32f746-ws.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -330,4 +330,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h index 80532801ade..bed84b94caf 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h @@ -108,7 +108,7 @@ void weak_function stm32_spidev_initialize(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC1) int stm32_sdio_initialize(void); #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/Kconfig b/boards/arm/stm32f7/stm32f746g-disco/Kconfig index f43ffe7e876..15c51d8a03e 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/Kconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/Kconfig @@ -12,7 +12,7 @@ config STM32F746GDISCO_FLASH select MTD_N25QXXX select MTD_SMART select FS_SMARTFS - select STM32F7_QSPI + select STM32_QSPI select MTD_BYTE_WRITE ---help--- Configures an MTD device for use with the onboard flash diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig index 0205e65dc25..59a85748ed6 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_SAI2=y -CONFIG_STM32F7_SAI2_A=y -CONFIG_STM32F7_SAI2_B=y -CONFIG_STM32F7_SAI2_B_SYNC_WITH_A=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_SAI2=y +CONFIG_STM32_SAI2_A=y +CONFIG_STM32_SAI2_B=y +CONFIG_STM32_SAI2_B_SYNC_WITH_A=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig index 1a6201d978f..f437e6b8e71 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig @@ -8,13 +8,14 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,11 +49,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index cb454fadbe6..4783972604f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -9,13 +9,14 @@ # CONFIG_LV_BUILD_EXAMPLES is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,13 +62,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STM32F746GDISCO_TOUCHSCREEN_SWAPXY=y -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig index a72895966d0..ea305fd8164 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,16 +62,16 @@ CONFIG_RR_INTERVAL=20 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig index b7d6e8247b1..870f454c806 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig index bef22e03840..3ac4ed78996 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig @@ -9,13 +9,14 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,11 +58,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig index b1d0a835575..59395d2b919 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig @@ -10,13 +10,14 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -50,11 +51,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index 0cd3f2c5624..35a9e14961f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -90,7 +90,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* Highest SYSCLK with USB OTG FS clock = 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_RNG) /* Highest SYSCLK with USB OTG FS clock <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -528,7 +528,7 @@ /* SAI2 pinset */ -#if defined(CONFIG_STM32F7_SAI2) && defined(CONFIG_STM32F7_SAI2_A) +#if defined(CONFIG_STM32_SAI2) && defined(CONFIG_STM32_SAI2_A) # define GPIO_SAI2_SD_A (GPIO_SAI2_SD_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_FS_A (GPIO_SAI2_FS_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_SCK_A (GPIO_SAI2_SCK_A_2|GPIO_SPEED_100MHz) diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt index fa3921f051c..3b1baaf5cb3 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() @@ -56,13 +56,13 @@ if(CONFIG_MTD_N25QXXX) list(APPEND SRCS stm32_n25q.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs index ddc33cdca5b..bfa456fb8a5 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs @@ -42,11 +42,11 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif @@ -58,13 +58,13 @@ ifeq ($(CONFIG_MTD_N25QXXX),y) CSRCS += stm32_n25q.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c index db7cfae7827..374703bb0cb 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c @@ -36,11 +36,11 @@ #include "stm32_gpio.h" #include "stm32_adc.h" -#ifndef CONFIG_STM32F7_ADC3 +#ifndef CONFIG_STM32_ADC3 # error "Only ADC3 channels are available on the arduino header of the board" #endif -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -104,7 +104,7 @@ static const uint32_t g_pinlist[6] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -150,4 +150,4 @@ int stm32_adc_setup(void) #endif } -#endif /* (CONFIG_ADC) && (CONFIG_STM32F7_ADC3) */ +#endif /* (CONFIG_ADC) && (CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c index 3992542c13f..32938e7d4c3 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. @@ -81,13 +81,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_enablefmc(); #endif } diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 666181b3eb8..bd6e034d810 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -57,7 +57,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c index cef610f4c3d..c353723e5d0 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c @@ -40,7 +40,7 @@ #include "stm32_gpio.h" #include "stm32_ltdc.h" -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c index 66c889a5c92..9ebe6730adc 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746g-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c index cb7c130d8cb..627dd0b399a 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32F7_I2C3 -# error "FT5x06 support requires CONFIG_STM32F7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c index 8d556b459ec..7df40f874e3 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f746g-disco.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -334,4 +334,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h index 1bbf837dd78..fec4ada12bd 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h @@ -43,7 +43,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32F7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -84,7 +84,7 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC +#ifdef CONFIG_STM32_SDMMC #define HAVE_SDIO #else #undef HAVE_SDIO @@ -212,7 +212,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_enablefmc(void); #endif @@ -224,7 +224,7 @@ void stm32_enablefmc(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_disablefmc(void); #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index 74e1fa7b568..a6feb52f19f 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,25 +58,25 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_BKPSRAM=y -CONFIG_STM32F7_CEC=y -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_I2C4=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x18 -CONFIG_STM32F7_PHYSR_100HD=0x8 -CONFIG_STM32F7_PHYSR_10FD=0x14 -CONFIG_STM32F7_PHYSR_10HD=0x4 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x1C -CONFIG_STM32F7_RNG=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_BKPSRAM=y +CONFIG_STM32_CEC=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x18 +CONFIG_STM32_PHYSR_100HD=0x8 +CONFIG_STM32_PHYSR_10FD=0x14 +CONFIG_STM32_PHYSR_10HD=0x4 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x1C +CONFIG_STM32_RNG=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index 0f40ae30525..df8d9cd8a84 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,7 +39,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index 028b29b0023..ad56c12a473 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt index b41627ab518..1c726649844 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt @@ -40,7 +40,7 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs index 82a79440d22..dacf581a7a2 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs @@ -42,7 +42,7 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c index 1ba49ec977e..42880e2706d 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c @@ -59,9 +59,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -87,7 +87,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index f0c45df93e3..a74c94d43f0 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -43,7 +43,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c index 4f36938bb58..ef0f7aef17d 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f769i-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h index 5c2ad841e97..5daf2597d97 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h @@ -158,7 +158,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig index cf9cf1cb87d..104b3eec356 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -45,8 +46,8 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig index 23b69992c3e..5be0771023d 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,14 +63,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_SDMMC2_SDIO_MODE=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig index bd8641a4643..62cd75915ad 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -88,14 +89,14 @@ CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_I2S2=y -CONFIG_STM32F7_I2S2_MCK=y -CONFIG_STM32F7_I2S2_TX=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2S2=y +CONFIG_STM32_I2S2_MCK=y +CONFIG_STM32_I2S2_TX=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_DEFAULT=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" CONFIG_SYSLOG_MAX_CHANNELS=2 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig index 8f9a71be404..b5f1c6d5b17 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,8 +49,8 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 CONFIG_USBDEV=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig index b63aa4ec89f..290478e8ab3 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -36,7 +37,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig index 9df11e1e0fc..70331b5896e 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -64,10 +65,10 @@ CONFIG_SENSORS_BMI270=y CONFIG_SENSORS_BMI270_I2C=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig index 26e856613c8..aac213c9285 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,9 +39,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig index 1b453b93181..e06beff8f4c 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -54,9 +55,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 2b1cfc1a9f9..29719bff24c 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt index a22e8a9afed..a1c6ad74cb7 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt @@ -44,13 +44,13 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs index 8d6ef41b3a6..8b662918a3f 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs @@ -47,13 +47,13 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif @@ -65,7 +65,7 @@ ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32F7_SDMMC2),y) +ifeq ($(CONFIG_STM32_SDMMC2),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index adae2fb2067..bbf5cd536c1 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -36,7 +36,7 @@ #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI # include "stm32_qspi.h" # ifdef CONFIG_FS_FAT @@ -74,9 +74,9 @@ extern struct qspi_dev_s *stm32_qspi_initialize(int intf); void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -102,7 +102,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } @@ -124,7 +124,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI struct qspi_dev_s *qspi; struct mtd_dev_s *mtd; diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index 25d4604116b..e2a62c396a9 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -43,7 +43,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c index fec4e8256a6..0d4fb153ceb 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f777zit6-meadow.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -117,7 +117,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -131,7 +131,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -145,7 +145,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -183,35 +183,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -219,4 +219,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c index 49a5b7310f7..be5332f7f44 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); # ifdef CONFIG_USBHOST stm32_configgpio(GPIO_OTGFS_PWRON); @@ -339,4 +339,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h index 827959faa57..6fd24bd22f0 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h @@ -47,7 +47,7 @@ /* SDCard validation */ -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -165,7 +165,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); void stm32_disablefmc(void); #endif @@ -178,7 +178,7 @@ void stm32_disablefmc(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC2) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC2) int stm32_sdio_initialize(void); #endif