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!arch/stm32h5: use common STM32 Kconfig symbols

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BREAKING CHANGE: STM32H5 Kconfig symbols were renamed from CONFIG_STM32H5_* to CONFIG_STM32_*.
Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names.
The custom clock option is a special breaking case that does not follow the family-to-common pattern:
CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl 2026-05-28 14:28:38 +02:00 • committed by Alan C. Assis
parent c306e4129d
commit ed0c96334c
84 changed files with 2117 additions and 8186 deletions
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8
Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst
View file

@ -182,7 +182,7 @@ This configuration enables USB Host support with the Mass Storage Class
USB mass-storage device (e.g. a USB flash drive) to the board's USB-C
connector. Key options enabled:
- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller
- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller
- ``CONFIG_USBHOST_MSC`` — USB Mass Storage Class host driver
- ``CONFIG_USBHOST_HUB`` — USB hub support
- ``CONFIG_FS_FAT`` — FAT filesystem for mounting the storage device
@ -196,7 +196,7 @@ configured in this build.
USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough
for reliable USB operation, so this configuration uses the external
high-speed oscillator (HSE) as the USB clock source
(``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board
(``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board
HSE is not connected by default; to enable it you must:
- **Connect** solder bridges **SB3** and **SB4**
@ -214,7 +214,7 @@ full networking support and the CDC-ECM USB Ethernet host driver. It is
intended to test USB Host operation with a USB-to-Ethernet adapter that
uses the CDC-ECM (Ethernet Control Model) protocol. Key options enabled:
- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller
- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller
- ``CONFIG_USBHOST_CDCECM`` — USB CDC-ECM Ethernet host driver
- ``CONFIG_USBHOST_COMPOSITE`` — composite USB device support
- ``CONFIG_USBHOST_HUB`` — USB hub support
@ -233,7 +233,7 @@ verify network connectivity.
USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough
for reliable USB operation, so this configuration uses the external
high-speed oscillator (HSE) as the USB clock source
(``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board
(``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board
HSE is not connected by default; to enable it you must:
- **Connect** solder bridges **SB3** and **SB4**

2
Documentation/platforms/arm/stm32h5/index.rst
View file

@ -95,7 +95,7 @@ capable of operating as a device or host.
Pre-requisites:
- CONFIG_USBHOST - Enable USB host support
- CONFIG_STM32H5_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode
- CONFIG_STM32_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode
USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE.
HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode.

1
arch/arm/Kconfig
View file

@ -669,6 +669,7 @@ config ARCH_CHIP_STM32L4
config ARCH_CHIP_STM32H5
bool "STMicro STM32 H5"
select ARCH_CHIP_STM32
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP

10
arch/arm/include/stm32h5/chip.h
View file

@ -37,7 +37,7 @@
# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
@ -54,7 +54,7 @@
#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
#define STM32_NRNG (1) /* Random number generator (RNG) */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
@ -66,7 +66,7 @@
#define STM32_QSPI (0) /* No QuadSPI1 */
#define STM32_OCTOSPI (1) /* OCTOSPI1*/
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_NSPI (6) /* SPI1-SPI6 */
# define STM32_NI2C (4) /* I2C1-4 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
@ -80,7 +80,7 @@
#define STM32_NCAN (2) /* CAN1 */
#define STM32_NSAI (2) /* SAI1-2 */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_NSDMMC (2) /* SDMMC interface */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32_NSDMMC (1) /* SDMMC interface */
@ -103,7 +103,7 @@
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#if defined(CONFIG_STM32H5_HAVE_ETHERNET)
#if defined(CONFIG_STM32_HAVE_ETHERNET)
# define STM32_NETHERNET 1 /* Ethernet MAC */
#else
# define STM32_NETHERNET 0 /* No Ethernet MAC */

2
arch/arm/include/stm32h5/irq.h
View file

@ -66,7 +66,7 @@
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include <arch/stm32h5/stm32h5xx_irq.h>
#else
# error "Unsupported STM32 H5 chip"

18
arch/arm/include/stm32h5/stm32h5xx_irq.h
View file

@ -119,7 +119,7 @@
# define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */
# define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */
# define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */
# define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */
#endif
@ -132,12 +132,12 @@
# define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */
# define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */
# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */
# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */
#endif
# define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 85) /* 85: USART6 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 86) /* 86: USART10 global interrupt */
# define STM32_IRQ_USART11 (STM32_IRQ_FIRST + 87) /* 87: USART11 global interrupt */
# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */
@ -151,7 +151,7 @@
# define STM32_IRQ_GPDMA2_CH5 (STM32_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */
# define STM32_IRQ_GPDMA2_CH6 (STM32_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */
# define STM32_IRQ_GPDMA2_CH7 (STM32_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 98) /* 98: UART7 global interrupt */
# define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 99) /* 99: UART8 global interrupt */
# define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 100) /* 100: UART9 global interrupt */
@ -161,14 +161,14 @@
# define STM32_IRQ_FPU (STM32_IRQ_FIRST + 103) /* 103: FPU global interrupt */
# define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */
# define STM32_IRQ_DCACHE (STM32_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_ETH (STM32_IRQ_FIRST + 106) /* 106: ETH global interrupt */
# define STM32_IRQ_ETH_WKUP (STM32_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */
#endif
# define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */
# define STM32_IRQ_FDCAN2_IT0 (STM32_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */
# define STM32_IRQ_FDCAN2_IT1 (STM32_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */
# define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 112) /* 112: FMAC global interrupt */
#endif
@ -180,13 +180,13 @@
# define STM32_IRQ_PKA (STM32_IRQ_FIRST + 118) /* 118: PKA global interrupt */
# define STM32_IRQ_CEC (STM32_IRQ_FIRST + 119) /* 119: CEC global interrupt */
# define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */
# define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */
#endif
# define STM32_IRQ_I3C1_EV (STM32_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */
# define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */
# define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */
# define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */
@ -199,7 +199,7 @@
# define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 132) /* 132: I3C2_ER global interrupt */
#endif
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_NEXTINTS 131
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32_IRQ_NEXTINTS 133

34
arch/arm/src/stm32h5/CMakeLists.txt
View file

@ -24,7 +24,7 @@ set(SRCS)
# Common ARM and Cortex-M33 files
if(CONFIG_STM32H5_PROGMEM)
if(CONFIG_STM32_PROGMEM)
list(APPEND SRCS stm32_flash.c)
endif()
@ -44,7 +44,7 @@ list(
stm32_lsi.c
stm32_uid.c)
if(CONFIG_STM32H5_USART)
if(CONFIG_STM32_USART)
list(APPEND SRCS stm32_serial.c)
endif()
@ -56,7 +56,7 @@ if(CONFIG_TIMER)
list(APPEND SRCS stm32_tim_lowerhalf.c)
endif()
if(CONFIG_STM32H5_I2C)
if(CONFIG_STM32_I2C)
list(APPEND SRCS stm32_i2c.c)
endif()
@ -64,55 +64,55 @@ if(CONFIG_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_STM32H5_FDCAN_CHARDRIVER)
if(CONFIG_STM32_FDCAN_CHARDRIVER)
list(APPEND SRCS stm32_fdcan.c)
endif()
if(CONFIG_STM32H5_RNG)
if(CONFIG_STM32_RNG)
list(APPEND SRCS stm32_rng.c)
endif()
if(CONFIG_STM32H5_ICACHE)
if(CONFIG_STM32_ICACHE)
list(APPEND SRCS stm32_icache.c)
endif()
if(CONFIG_STM32H5_SPI)
if(CONFIG_STM32_SPI)
list(APPEND SRCS stm32_spi.c)
endif()
if(CONFIG_STM32H5_QSPI1)
if(CONFIG_STM32_QSPI1)
list(APPEND SRCS stm32_qspi.c)
endif()
if(CONFIG_STM32H5_TIM)
if(CONFIG_STM32_TIM)
list(APPEND SRCS stm32_tim.c)
endif()
if(CONFIG_STM32H5_HAVE_HSI48)
if(CONFIG_STM32_HAVE_HSI48)
list(APPEND SRCS stm32_hsi48.c)
endif()
if(CONFIG_STM32H5_USBFS)
if(CONFIG_STM32_USBFS)
list(APPEND SRCS stm32_usbfs.c)
endif()
if(CONFIG_STM32H5_USBFS_HOST)
if(CONFIG_STM32_USBFS_HOST)
list(APPEND SRCS stm32_usbdrdhost.c)
endif()
if(CONFIG_STM32H5_ETHMAC)
if(CONFIG_STM32_ETHMAC)
list(APPEND SRCS stm32_ethernet.c)
endif()
if(CONFIG_STM32H5_DMA)
if(CONFIG_STM32_DMA)
list(APPEND SRCS stm32_dma.c)
endif()
if(CONFIG_STM32H5_DTS)
if(CONFIG_STM32_DTS)
list(APPEND SRCS stm32_dts.c)
endif()
if(CONFIG_STM32H5_PWM)
if(CONFIG_STM32_PWM)
list(APPEND SRCS stm32_pwm.c)
endif()
@ -122,7 +122,7 @@ endif()
# Required chip type specific files
if(CONFIG_STM32H5_STM32H5XXXX)
if(CONFIG_STM32_STM32H5XXXX)
list(APPEND SRCS stm32h5xx_rcc.c)
endif()

6238
arch/arm/src/stm32h5/Kconfig
View file

File diff suppressed because it is too large Load diff

36
arch/arm/src/stm32h5/Make.defs
View file

@ -29,7 +29,7 @@ HEAD_ASRC =
include armv8-m/Make.defs
ifeq ($(CONFIG_STM32H5_PROGMEM),y)
ifeq ($(CONFIG_STM32_PROGMEM),y)
CHIP_CSRCS += stm32_flash.c
endif
@ -44,7 +44,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle.c
endif
ifeq ($(CONFIG_STM32H5_USART),y)
ifeq ($(CONFIG_STM32_USART),y)
CHIP_CSRCS += stm32_serial.c
endif
@ -52,7 +52,7 @@ ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
endif
ifeq ($(CONFIG_STM32H5_I2C),y)
ifeq ($(CONFIG_STM32_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
@ -60,64 +60,64 @@ ifeq ($(CONFIG_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32H5_FDCAN_CHARDRIVER),y)
ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y)
CHIP_CSRCS += stm32_fdcan.c
endif
ifeq ($(CONFIG_STM32H5_RNG),y)
ifeq ($(CONFIG_STM32_RNG),y)
CHIP_CSRCS += stm32_rng.c
endif
ifeq ($(CONFIG_STM32H5_ICACHE),y)
ifeq ($(CONFIG_STM32_ICACHE),y)
CHIP_CSRCS += stm32_icache.c
endif
ifeq ($(CONFIG_STM32H5_SPI),y)
ifeq ($(CONFIG_STM32_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32H5_QSPI1),y)
ifeq ($(CONFIG_STM32_QSPI1),y)
CHIP_CSRCS += stm32_qspi.c
endif
ifeq ($(CONFIG_STM32H5_TIM),y)
ifeq ($(CONFIG_STM32_TIM),y)
CHIP_CSRCS += stm32_tim.c
endif
ifeq ($(CONFIG_STM32H5_HAVE_HSI48),y)
ifeq ($(CONFIG_STM32_HAVE_HSI48),y)
CHIP_CSRCS += stm32_hsi48.c
endif
ifeq ($(CONFIG_STM32H5_USBFS),y)
ifeq ($(CONFIG_STM32_USBFS),y)
CHIP_CSRCS += stm32_usbfs.c
endif
ifeq ($(CONFIG_STM32H5_USBFS_HOST),y)
ifeq ($(CONFIG_STM32_USBFS_HOST),y)
CHIP_CSRCS += stm32_usbdrdhost.c
endif
ifeq ($(CONFIG_STM32H5_ETHMAC),y)
ifeq ($(CONFIG_STM32_ETHMAC),y)
CHIP_CSRCS += stm32_ethernet.c
endif
ifeq ($(CONFIG_STM32H5_DMA),y)
ifeq ($(CONFIG_STM32_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
ifeq ($(CONFIG_STM32H5_DTS),y)
ifeq ($(CONFIG_STM32_DTS),y)
CHIP_CSRCS += stm32_dts.c
endif
ifeq ($(CONFIG_STM32H5_PWM),y)
ifeq ($(CONFIG_STM32_PWM),y)
CHIP_CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32H5_PULSECOUNT),y)
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
CHIP_CSRCS += stm32_pulsecount.c
endif
# Required chip type specific files
ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
ifeq ($(CONFIG_STM32_STM32H5XXXX),y)
CHIP_CSRCS += stm32h5xx_rcc.c
endif

4
arch/arm/src/stm32h5/hardware/stm32_ethernet.h
View file

@ -33,7 +33,7 @@
/* Ethernet support only on STM32H563/573 chips. */
#if defined(CONFIG_STM32H5_STM32H56XXX)
#if defined(CONFIG_STM32_STM32H56XXX)
/****************************************************************************
* Pre-processor Definitions
@ -681,5 +681,5 @@ struct eth_desc_s
****************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H5_STM32H56XXX */
#endif /* CONFIG_STM32_STM32H56XXX */
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_ETHERNET_H */

2
arch/arm/src/stm32h5/hardware/stm32_flash.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H56XXX)
#if defined(CONFIG_STM32_STM32H56XXX)
# include "hardware/stm32h5xxx_flash.h"
#else
# error "Unsupported STM32 H5 flash"

2
arch/arm/src/stm32h5/hardware/stm32_gpdma.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "stm32h56x_dmasigmap.h"
#else
# error "Unsupported STM32 H5 DMA map"

2
arch/arm/src/stm32h5/hardware/stm32_gpio.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_gpio.h"
#else
# error "Unsupported STM32 H5 PWR"

2
arch/arm/src/stm32h5/hardware/stm32_i2c.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_i2c.h"
#else
# error "Unsupported STM32 H5 I2C"

2
arch/arm/src/stm32h5/hardware/stm32_memorymap.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_memorymap.h"
#else
# error "Unsupported STM32 H5 memory map"

2
arch/arm/src/stm32h5/hardware/stm32_pinmap.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H56XXX)
#if defined(CONFIG_STM32_STM32H56XXX)
# include "hardware/stm32h56xxx_pinmap.h"
#else
# error "Unsupported STM32 H5 pin map"

2
arch/arm/src/stm32h5/hardware/stm32_pwr.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_pwr.h"
#else
# error "Unsupported STM32 H5 PWR"

2
arch/arm/src/stm32h5/hardware/stm32_rcc.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_rcc.h"
#else
# error "Unsupported STM32 H5 rcc"

2
arch/arm/src/stm32h5/hardware/stm32_sbs.h
View file

@ -32,7 +32,7 @@
#if !defined(CONFIG_STM32H5_STM32H52XXX) && \
!defined(CONFIG_STM32H5_STM32H53XXX) && \
!defined(CONFIG_STM32H5_STM32H56XXX) && \
!defined(CONFIG_STM32_STM32H56XXX) && \
!defined(CONFIG_STM32H5_STM32H57XXX)
# warning "SBS not verified on STM32H50x variants."
#endif

2
arch/arm/src/stm32h5/hardware/stm32_uart.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \
defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# include "hardware/stm32h5xxx_uart.h"
#else
# error "Unsupported STM32 H5 uart"

4
arch/arm/src/stm32h5/hardware/stm32_usbfs.h
View file

@ -30,7 +30,7 @@
#include <nuttx/config.h>
#include <chip.h>
#ifdef CONFIG_STM32H5_HAVE_USBFS
#ifdef CONFIG_STM32_HAVE_USBFS
/****************************************************************************
* Pre-processor Definitions
@ -331,5 +331,5 @@
#define USB_COUNT_RX_SHIFT (16) /* Bits 25-16: Reception Byte Count */
#define USB_COUNT_RX_MASK (0x3ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32H5_HAVE_USBFS */
#endif /* CONFIG_STM32_HAVE_USBFS */
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H */

4
arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32H5_STM32H563XX) || \
#if defined(CONFIG_STM32_STM32H563XX) || \
defined(CONFIG_STM32H5_STM32H562XX)
/****************************************************************************
* Pre-processor Definitions
@ -786,5 +786,5 @@
#define GPIO_ADC2_INN18_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
#define GPIO_ADC2_INP19_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
#endif /* CONFIG_STM32H5_STM32H563XX*/
#endif /* CONFIG_STM32_STM32H563XX*/
#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H */

14
arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h
View file

@ -481,7 +481,7 @@
#define FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT (0)
#define FLASH_SECWM1R_CUR_SECWM1_END_SHIFT (16)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT)
# define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT)
#endif
@ -496,7 +496,7 @@
#define FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT (0)
#define FLASH_SECWM1R_PRG_SECWM1_END_SHIFT (16)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT)
# define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT)
#endif
@ -527,7 +527,7 @@
#define FLASH_HDP1R_CUR_HDP1_STRT_SHIFT (0)
#define FLASH_HDP1R_CUR_HDP1_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT)
# define FLASH_HDP1R_CUR_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT)
#endif
@ -542,7 +542,7 @@
#define FLASH_HDP1R_PRG_HDP1_STRT_SHIFT (0)
#define FLASH_HDP1R_PRG_HDP1_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT)
# define FLASH_HDP1R_PRG_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT)
#endif
@ -587,7 +587,7 @@
#define FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT (0)
#define FLASH_SECWM2R_PRG_SECWM2_END_SHIFT (16)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT)
# define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT)
#endif
@ -618,7 +618,7 @@
#define FLASH_HDP2R_CUR_HDP2_STRT_SHIFT (0)
#define FLASH_HDP2R_CUR_HDP2_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT)
# define FLASH_HDP2R_CUR_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT)
#endif
@ -633,7 +633,7 @@
#define FLASH_HDP2R_PRG_HDP2_STRT_SHIFT (0)
#define FLASH_HDP2R_PRG_HDP2_END_SHIFT (0)
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT)
# define FLASH_HDP2R_PRG_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT)
#endif

2
arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32H5_STM32H5XXXX)
#if defined(CONFIG_STM32_STM32H5XXXX)
/****************************************************************************
* Pre-processor Definitions

2
arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32H5_STM32H5XXXX)
#if defined(CONFIG_STM32_STM32H5XXXX)
/****************************************************************************
* Pre-processor Definitions

99
arch/arm/src/stm32h5/stm32_adc.c
View file

@ -53,7 +53,7 @@
#ifdef CONFIG_ADC
#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
/****************************************************************************
* Pre-processor Definitions
@ -168,7 +168,7 @@ struct stm32_dev_s
/* List of selected ADC channels to sample */
uint8_t chanlist[CONFIG_STM32H5_ADC_MAX_SAMPLES];
uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES];
};
/****************************************************************************
@ -260,7 +260,7 @@ static const struct adc_ops_s g_adcops =
/* ADC1 state */
#ifdef CONFIG_STM32H5_ADC1
#ifdef CONFIG_STM32_ADC1
/* Double the size of the buffer in circular mode
* Circular mode utilizes half-transfer DMA interrupts and a 2x buffer
@ -269,10 +269,10 @@ static const struct adc_ops_s g_adcops =
*/
#ifdef ADC1_HAVE_DMA
# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\
CONFIG_STM32H5_ADC1_DMA_BATCH)
# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\
CONFIG_STM32_ADC1_DMA_BATCH)
# ifdef CONFIG_STM32H5_ADC1_DMA_CFG
# if CONFIG_STM32_ADC1_DMA_CFG == 1
# define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE * 2)
# else
# define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE)
@ -290,18 +290,18 @@ static struct stm32_dev_s g_adcpriv1 =
.irq = STM32_IRQ_ADC1,
.isr = adc12_interrupt,
.intf = 1,
.resolution = CONFIG_STM32H5_ADC1_RESOLUTION,
.resolution = CONFIG_STM32_ADC1_RESOLUTION,
.base = STM32_ADC1_BASE,
.mbase = STM32_ADC1_BASE,
.initialized = false,
#ifdef ADC1_HAVE_TIMER
.trigger = CONFIG_STM32H5_ADC1_TIMTRIG,
.trigger = CONFIG_STM32_ADC1_TIMTRIG,
.tbase = ADC1_TIMER_BASE,
.trcc_enr = ADC1_TIMER_RCC_ENR,
.trcc_en = ADC1_TIMER_RCC_EN,
.extsel = ADC1_EXTSEL_VALUE,
.pclck = ADC1_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
#endif
#ifdef BOARD_ADC1_DIFSEL
@ -326,8 +326,8 @@ static struct stm32_dev_s g_adcpriv1 =
.hasdma = true,
.r_chanbuffer = g_adc1_chanbuffer,
.r_dmabuffer = g_adc1_dmabuffer,
.dmabatch = CONFIG_STM32H5_ADC1_DMA_BATCH,
# ifdef CONFIG_STM32H5_ADC1_DMA_CFG
.dmabatch = CONFIG_STM32_ADC1_DMA_BATCH,
# if CONFIG_STM32_ADC1_DMA_CFG == 1
.circular = true,
# else
.circular = false,
@ -338,25 +338,25 @@ static struct stm32_dev_s g_adcpriv1 =
#ifdef ADC1_HAVE_OVERSAMPLE
.oversample = true,
# ifdef CONFIG_STM32H5_ADC1_TROVS
# ifdef CONFIG_STM32_ADC1_TROVS
.trovs = true,
# else
.trovs = false,
# endif
.ovsr = CONFIG_STM32H5_ADC1_OVSR,
.ovss = CONFIG_STM32H5_ADC1_OVSS,
.ovsr = CONFIG_STM32_ADC1_OVSR,
.ovss = CONFIG_STM32_ADC1_OVSS,
#else
.oversample = false,
#endif
#ifdef CONFIG_STM32H5_ADC1_WDG1
#ifdef CONFIG_STM32_ADC1_WDG1
.wdg1_enable = true,
.wdg1_flt = CONFIG_STM32H5_ADC1_WDG1_FLT,
.wdg1_low_thresh = CONFIG_STM32H5_ADC1_WDG1_LOWTHRESH,
.wdg1_high_thresh = CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH,
# ifdef CONFIG_STM32H5_ADC1_WDG1_SGL
.wdg1_flt = CONFIG_STM32_ADC1_WDG1_FLT,
.wdg1_low_thresh = CONFIG_STM32_ADC1_WDG1_LOWTHRESH,
.wdg1_high_thresh = CONFIG_STM32_ADC1_WDG1_HIGHTHRESH,
# ifdef CONFIG_STM32_ADC1_WDG1_SGL
.wdg1_single_chan = true,
.wdg1_chan = CONFIG_STM32H5_ADC1_WDG1_CHAN,
.wdg1_chan = CONFIG_STM32_ADC1_WDG1_CHAN,
# else
.wdg1_single_chan = false,
.wdg1_chan = 0,
@ -375,13 +375,13 @@ static struct adc_dev_s g_adcdev1 =
/* ADC2 state */
#ifdef CONFIG_STM32H5_ADC2
#ifdef CONFIG_STM32_ADC2
#ifdef ADC2_HAVE_DMA
# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\
CONFIG_STM32H5_ADC2_DMA_BATCH)
# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\
CONFIG_STM32_ADC2_DMA_BATCH)
# ifdef CONFIG_STM32H5_ADC2_DMA_CFG
# ifdef CONFIG_STM32_ADC2_DMA_CFG
# define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE * 2)
# else
# define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE)
@ -399,18 +399,18 @@ static struct stm32_dev_s g_adcpriv2 =
.irq = STM32_IRQ_ADC2,
.isr = adc12_interrupt,
.intf = 2,
.resolution = CONFIG_STM32H5_ADC2_RESOLUTION,
.resolution = CONFIG_STM32_ADC2_RESOLUTION,
.base = STM32_ADC2_BASE,
.mbase = STM32_ADC2_BASE,
.initialized = false,
#ifdef ADC2_HAVE_TIMER
.trigger = CONFIG_STM32H5_ADC2_TIMTRIG,
.trigger = CONFIG_STM32_ADC2_TIMTRIG,
.tbase = ADC2_TIMER_BASE,
.trcc_enr = ADC2_TIMER_RCC_ENR,
.trcc_en = ADC2_TIMER_RCC_EN,
.extsel = ADC2_EXTSEL_VALUE,
.pclck = ADC2_TIMER_PCLK_FREQUENCY,
.freq = CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY,
.freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY,
#endif
#ifdef BOARD_ADC2_DIFSEL
@ -435,8 +435,8 @@ static struct stm32_dev_s g_adcpriv2 =
.hasdma = true,
.r_chanbuffer = g_adc2_chanbuffer,
.r_dmabuffer = g_adc2_dmabuffer,
.dmabatch = CONFIG_STM32H5_ADC2_DMA_BATCH,
# ifdef CONFIG_STM32H5_ADC2_DMA_CFG
.dmabatch = CONFIG_STM32_ADC2_DMA_BATCH,
# ifdef CONFIG_STM32_ADC2_DMA_CFG
.circular = true,
# else
.circular = false,
@ -447,25 +447,25 @@ static struct stm32_dev_s g_adcpriv2 =
#ifdef ADC2_HAVE_OVERSAMPLE
.oversample = true,
# ifdef CONFIG_STM32H5_ADC2_TROVS
# ifdef CONFIG_STM32_ADC2_TROVS
.trovs = true,
# else
.trovs = false,
# endif
.ovsr = CONFIG_STM32H5_ADC2_OVSR,
.ovss = CONFIG_STM32H5_ADC2_OVSS,
.ovsr = CONFIG_STM32_ADC2_OVSR,
.ovss = CONFIG_STM32_ADC2_OVSS,
#else
.oversample = false,
#endif
#ifdef CONFIG_STM32H5_ADC2_WDG1
#ifdef CONFIG_STM32_ADC2_WDG1
.wdg1_enable = true,
.wdg1_flt = CONFIG_STM32H5_ADC2_WDG1_FLT,
.wdg1_low_thresh = CONFIG_STM32H5_ADC2_WDG1_LOWTHRESH,
.wdg1_high_thresh = CONFIG_STM32H5_ADC2_WDG1_HIGHTHRESH,
# ifdef CONFIG_STM32H5_ADC2_WDG1_SGL
.wdg1_flt = CONFIG_STM32_ADC2_WDG1_FLT,
.wdg1_low_thresh = CONFIG_STM32_ADC2_WDG1_LOWTHRESH,
.wdg1_high_thresh = CONFIG_STM32_ADC2_WDG1_HIGHTHRESH,
# ifdef CONFIG_STM32_ADC2_WDG1_SGL
.wdg1_single_chan = true,
.wdg1_chan = CONFIG_STM32H5_ADC2_WDG1_CHAN,
.wdg1_chan = CONFIG_STM32_ADC2_WDG1_CHAN,
# else
.wdg1_single_chan = false,
.wdg1_chan = 0,
@ -1409,7 +1409,7 @@ static int adc_setup(struct adc_dev_s *dev)
* ADC1 and ADC2 are enabled.)
*/
#if defined(CONFIG_STM32H5_ADC1) && defined(CONFIG_STM32H5_ADC2)
#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)
if ((dev == &g_adcdev1 &&
!((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) ||
(dev == &g_adcdev2 &&
@ -1687,7 +1687,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch)
priv->rnchannels = 1;
}
DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES);
DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES);
bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST,
ADC_SQR4_SQ_OFFSET);
@ -2033,13 +2033,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
*
****************************************************************************/
#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
static int adc12_interrupt(int irq, void *context, void *arg)
{
uint32_t regval;
uint32_t pending;
#ifdef CONFIG_STM32H5_ADC1
#ifdef CONFIG_STM32_ADC1
regval = getreg32(STM32_ADC1_ISR);
pending = regval & ADC_INT_MASK;
if (pending != 0)
@ -2048,7 +2048,7 @@ static int adc12_interrupt(int irq, void *context, void *arg)
}
#endif
#ifdef CONFIG_STM32H5_ADC2
#ifdef CONFIG_STM32_ADC2
regval = getreg32(STM32_ADC2_ISR);
pending = regval & ADC_INT_MASK;
if (pending != 0)
@ -2598,13 +2598,13 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
switch (intf)
{
#ifdef CONFIG_STM32H5_ADC1
#ifdef CONFIG_STM32_ADC1
case 1:
ainfo("ADC1 selected\n");
dev = &g_adcdev1;
break;
#endif
#ifdef CONFIG_STM32H5_ADC2
#ifdef CONFIG_STM32_ADC2
case 2:
ainfo("ADC2 selected\n");
dev = &g_adcdev2;
@ -2620,10 +2620,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
priv = (struct stm32_dev_s *)dev->ad_priv;
priv->cb = NULL;
DEBUGASSERT(cchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES);
if (cchannels > CONFIG_STM32H5_ADC_MAX_SAMPLES)
DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES);
if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES)
{
cchannels = CONFIG_STM32H5_ADC_MAX_SAMPLES;
cchannels = CONFIG_STM32_ADC_MAX_SAMPLES;
}
priv->cchannels = cchannels;
@ -2639,6 +2639,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
return dev;
}
#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */
#endif /* CONFIG_ADC */

448
arch/arm/src/stm32h5/stm32_adc.h
View file

@ -36,7 +36,7 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
/* Configuration ************************************************************/
@ -46,75 +46,75 @@
* is intended to be used for that purpose.
*/
#ifndef CONFIG_STM32H5_TIM1
# undef CONFIG_STM32H5_TIM1_ADC
# undef CONFIG_STM32H5_TIM1_ADC1
# undef CONFIG_STM32H5_TIM1_ADC2
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_ADC
# undef CONFIG_STM32_TIM1_ADC1
# undef CONFIG_STM32_TIM1_ADC2
#endif
#ifndef CONFIG_STM32H5_TIM2
# undef CONFIG_STM32H5_TIM2_ADC
# undef CONFIG_STM32H5_TIM2_ADC1
# undef CONFIG_STM32H5_TIM2_ADC2
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_ADC
# undef CONFIG_STM32_TIM2_ADC1
# undef CONFIG_STM32_TIM2_ADC2
#endif
#ifndef CONFIG_STM32H5_TIM3
# undef CONFIG_STM32H5_TIM3_ADC
# undef CONFIG_STM32H5_TIM3_ADC1
# undef CONFIG_STM32H5_TIM3_ADC2
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_ADC
# undef CONFIG_STM32_TIM3_ADC1
# undef CONFIG_STM32_TIM3_ADC2
#endif
#ifndef CONFIG_STM32H5_TIM4
# undef CONFIG_STM32H5_TIM4_ADC
# undef CONFIG_STM32H5_TIM4_ADC1
# undef CONFIG_STM32H5_TIM4_ADC2
#ifndef CONFIG_STM32_TIM4
# undef CONFIG_STM32_TIM4_ADC
# undef CONFIG_STM32_TIM4_ADC1
# undef CONFIG_STM32_TIM4_ADC2
#endif
#ifndef CONFIG_STM32H5_TIM6
# undef CONFIG_STM32H5_TIM6_ADC
# undef CONFIG_STM32H5_TIM6_ADC1
# undef CONFIG_STM32H5_TIM6_ADC2
#ifndef CONFIG_STM32_TIM6
# undef CONFIG_STM32_TIM6_ADC
# undef CONFIG_STM32_TIM6_ADC1
# undef CONFIG_STM32_TIM6_ADC2
#endif
#ifndef CONFIG_STM32H5_TIM8
# undef CONFIG_STM32H5_TIM8_ADC
# undef CONFIG_STM32H5_TIM8_ADC1
# undef CONFIG_STM32H5_TIM8_ADC2
#ifndef CONFIG_STM32_TIM8
# undef CONFIG_STM32_TIM8_ADC
# undef CONFIG_STM32_TIM8_ADC1
# undef CONFIG_STM32_TIM8_ADC2
#endif
#ifndef CONFIG_STM32H5_TIM15
# undef CONFIG_STM32H5_TIM15_ADC
# undef CONFIG_STM32H5_TIM15_ADC1
# undef CONFIG_STM32H5_TIM15_ADC2
#ifndef CONFIG_STM32_TIM15
# undef CONFIG_STM32_TIM15_ADC
# undef CONFIG_STM32_TIM15_ADC1
# undef CONFIG_STM32_TIM15_ADC2
#endif
/* DMA support */
#undef ADC_HAVE_DMA
#if defined(CONFIG_STM32H5_ADC1_DMA) || defined(CONFIG_STM32H5_ADC2_DMA)
#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA)
# define ADC_HAVE_DMA 1
#endif
#if defined(CONFIG_STM32H5_ADC1_DMA)
#if defined(CONFIG_STM32_ADC1_DMA)
# define ADC1_HAVE_DMA 1
#endif
#if defined(CONFIG_STM32H5_ADC2_DMA)
#if defined(CONFIG_STM32_ADC2_DMA)
# define ADC2_HAVE_DMA 1
#endif
/* Oversampling support */
#undef ADC_HAVE_OVERSAMPLE
#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) || \
defined(CONFIG_STM32H5_ADC2_OVERSAMPLE)
#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) || \
defined(CONFIG_STM32_ADC2_OVERSAMPLE)
# define ADC_HAVE_OVERSAMPLE 1
#endif
#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE)
#if defined(CONFIG_STM32_ADC1_OVERSAMPLE)
# define ADC1_HAVE_OVERSAMPLE 1
#endif
#if defined(CONFIG_STM32H5_ADC2_OVERSAMPLE)
#if defined(CONFIG_STM32_ADC2_OVERSAMPLE)
# define ADC2_HAVE_OVERSAMPLE 1
#endif
#undef ADC_HAVE_WDG1
#if defined(CONFIG_STM32H5_ADC1_WDG1) || defined(CONFIG_STM32H5_ADC2_WDG1)
#if defined(CONFIG_STM32_ADC1_WDG1) || defined(CONFIG_STM32_ADC2_WDG1)
# define ADC_HAVE_WDG1 1
#endif
@ -136,43 +136,43 @@
* information about the timer.
*/
#if defined(CONFIG_STM32H5_TIM1_ADC1)
#if defined(CONFIG_STM32_TIM1_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM1_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN
#elif defined(CONFIG_STM32H5_TIM2_ADC1)
#elif defined(CONFIG_STM32_TIM2_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM2_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN
#elif defined(CONFIG_STM32H5_TIM3_ADC1)
#elif defined(CONFIG_STM32_TIM3_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM3_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN
#elif defined(CONFIG_STM32H5_TIM4_ADC1)
#elif defined(CONFIG_STM32_TIM4_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM4_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN
#elif defined(CONFIG_STM32H5_TIM6_ADC1)
#elif defined(CONFIG_STM32_TIM6_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM6_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN
#elif defined(CONFIG_STM32H5_TIM8_ADC1)
#elif defined(CONFIG_STM32_TIM8_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM8_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN
#elif defined(CONFIG_STM32H5_TIM15_ADC1)
#elif defined(CONFIG_STM32_TIM15_ADC1)
# define ADC1_HAVE_TIMER 1
# define ADC1_TIMER_BASE STM32_TIM15_BASE
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
@ -183,52 +183,52 @@
#endif
#ifdef ADC1_HAVE_TIMER
# ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined"
# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY
# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32H5_ADC1_TIMTRIG
# error "CONFIG_STM32H5_ADC1_TIMTRIG not defined"
# ifndef CONFIG_STM32_ADC1_TIMTRIG
# error "CONFIG_STM32_ADC1_TIMTRIG not defined"
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
# endif
#endif
#if defined(CONFIG_STM32H5_TIM1_ADC2)
#if defined(CONFIG_STM32_TIM1_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM1_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN
#elif defined(CONFIG_STM32H5_TIM2_ADC2)
#elif defined(CONFIG_STM32_TIM2_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM2_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN
#elif defined(CONFIG_STM32H5_TIM3_ADC2)
#elif defined(CONFIG_STM32_TIM3_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM3_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN
#elif defined(CONFIG_STM32H5_TIM4_ADC2)
#elif defined(CONFIG_STM32_TIM4_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM4_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN
#elif defined(CONFIG_STM32H5_TIM6_ADC2)
#elif defined(CONFIG_STM32_TIM6_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM6_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN
#elif defined(CONFIG_STM32H5_TIM8_ADC2)
#elif defined(CONFIG_STM32_TIM8_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM8_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN
#elif defined(CONFIG_STM32H5_TIM15_ADC2)
#elif defined(CONFIG_STM32_TIM15_ADC2)
# define ADC2_HAVE_TIMER 1
# define ADC2_TIMER_BASE STM32_TIM15_BASE
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
@ -239,11 +239,11 @@
#endif
#ifdef ADC2_HAVE_TIMER
# ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY
# error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined"
# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY
# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined"
# endif
# ifndef CONFIG_STM32H5_ADC2_TIMTRIG
# error "CONFIG_STM32H5_ADC2_TIMTRIG not defined"
# ifndef CONFIG_STM32_ADC2_TIMTRIG
# error "CONFIG_STM32_ADC2_TIMTRIG not defined"
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
# endif
#endif
@ -254,231 +254,231 @@
# undef ADC_HAVE_TIMER
#endif
#if defined(CONFIG_STM32H5_TIM1_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
#if defined(CONFIG_STM32_TIM1_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# define ADC1_EXTSEL_VALUE ADC_CFGR__EXTSEL_T1CC3
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM1)"
# endif
#elif defined(CONFIG_STM32H5_TIM2_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
#elif defined(CONFIG_STM32_TIM2_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)"
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM2)"
# endif
#elif defined(CONFIG_STM32H5_TIM3_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
#elif defined(CONFIG_STM32_TIM3_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)"
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM3)"
# endif
#elif defined(CONFIG_STM32H5_TIM4_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
#elif defined(CONFIG_STM32_TIM4_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CRFT_EXTSEL_T4TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)"
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM4)"
# endif
#elif defined(CONFIG_STM32H5_TIM6_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM6_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)"
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM6)"
# endif
#elif defined(CONFIG_STM32H5_TIM8_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM8_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM8)"
# endif
#elif defined(CONFIG_STM32H5_TIM15_ADC1)
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM15_ADC1)
# if CONFIG_STM32_ADC1_TIMTRIG == 0
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
# define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC1_TIMTRIG == 5
# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)"
# else
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)"
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM15)"
# endif
#endif
#if defined(CONFIG_STM32H5_TIM1_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
#if defined(CONFIG_STM32_TIM1_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC3
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM1)"
# endif
#elif defined(CONFIG_STM32H5_TIM2_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
#elif defined(CONFIG_STM32_TIM2_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)"
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM2)"
# endif
#elif defined(CONFIG_STM32H5_TIM3_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
#elif defined(CONFIG_STM32_TIM3_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)"
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM3)"
# endif
#elif defined(CONFIG_STM32H5_TIM4_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
#elif defined(CONFIG_STM32_TIM4_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)"
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM4)"
# endif
#elif defined(CONFIG_STM32H5_TIM6_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM6_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)"
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM6)"
# endif
#elif defined(CONFIG_STM32H5_TIM8_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM8_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM8)"
# endif
#elif defined(CONFIG_STM32H5_TIM15_ADC2)
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
#elif defined(CONFIG_STM32_TIM15_ADC2)
# if CONFIG_STM32_ADC2_TIMTRIG == 0
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
# define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
# elif CONFIG_STM32_ADC2_TIMTRIG == 5
# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)"
# else
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)"
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM15)"
# endif
#endif
@ -524,5 +524,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist,
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2*/
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2*/
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_ADC_H */

2
arch/arm/src/stm32h5/stm32_dbgmcu.h
View file

@ -31,7 +31,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H5XXXX)
#if defined(CONFIG_STM32_STM32H5XXXX)
# include "hardware/stm32_dbgmcu.h"
#else
# error "Unsupported STM32H5 chip"

6
arch/arm/src/stm32h5/stm32_dma.c
View file

@ -118,7 +118,7 @@ static int gpdma_dmainterrupt(int irq, void *context, void *arg);
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H5_DMA1
#ifdef CONFIG_STM32_DMA1
static struct gpdma_ch_s g_chan[] =
{
{
@ -150,7 +150,7 @@ static struct gpdma_ch_s g_chan[] =
.base = STM32_DMA1_BASE + CH_BASE_OFFSET(3)
},
#endif
#ifdef CONFIG_STM32H5_DMA2
#ifdef CONFIG_STM32_DMA2
{
.dma_instance = 2,
.channel = 0,
@ -703,7 +703,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
return (size_t)(br1 & GPDMA_CXBR1_BNDT_MASK);
}
#ifdef CONFIG_STM32H5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
/****************************************************************************
* Name: stm32_dmacapable
*

8
arch/arm/src/stm32h5/stm32_dma.h
View file

@ -39,9 +39,9 @@
# undef CONFIG_DEBUG_DMA_INFO
#endif
#ifdef CONFIG_STM32H5_DMACAPABLE
# error "CONFIG_STM32H5_DMACAPABLE not yet implemented."
# undef CONFIG_STM32H5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
# error "CONFIG_STM32_DMACAPABLE not yet implemented."
# undef CONFIG_STM32_DMACAPABLE
#endif
/****************************************************************************
@ -319,7 +319,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
*
****************************************************************************/
#ifdef CONFIG_STM32H5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
bool stm32_dmacapable(DMA_HANDLE handle, struct stm32_gpdma_cfg_s *cfg);
#else
# define stm32_dmacapable(handle, cfg) (true)

30
arch/arm/src/stm32h5/stm32_dts.c
View file

@ -59,7 +59,7 @@ static int stm32_dts_set_interval (struct sensor_lowerhalf_s *lower,
struct file *filep,
uint32_t *period_us);
#if CONFIG_STM32H5_DTS_TRIGGER == 0
#if CONFIG_STM32_DTS_TRIGGER == 0
static ssize_t stm32_dts_fetch (struct sensor_lowerhalf_s *lower,
struct file *filep,
char *buffer, size_t buflen);
@ -75,7 +75,7 @@ static int stm32_dts_isr (int irq, void *context, void *arg);
* Pre-processor Definitions
****************************************************************************/
#if CONFIG_STM32H5_DTS_TRIGGER != 0
#if CONFIG_STM32_DTS_TRIGGER != 0
# error "Hardware triggers not implemented. Need LP Timers first."
#endif
@ -112,7 +112,7 @@ static const struct sensor_ops_s g_dts_ops =
.activate = stm32_dts_activate,
.set_interval = stm32_dts_set_interval,
.batch = NULL,
#if CONFIG_STM32H5_DTS_TRIGGER == 0
#if CONFIG_STM32_DTS_TRIGGER == 0
.fetch = stm32_dts_fetch,
#else
.fetch = NULL,
@ -230,7 +230,7 @@ static void dts_configure_cfgr1(void)
{
/* Compute PCLK prescaler <= 1MHz */
#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE)
#if !defined(CONFIG_STM32_DTS_REFCLK_LSE)
uint32_t div = (STM32_PCLK1_FREQUENCY + 1000000 - 1) / 1000000;
if (div > 127)
@ -245,13 +245,13 @@ static void dts_configure_cfgr1(void)
uint32_t cfgr1 =
DTS_CFGR1_TS1_EN
| DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32H5_DTS_SMP_TIME)
#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE)
| DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32_DTS_SMP_TIME)
#if !defined(CONFIG_STM32_DTS_REFCLK_LSE)
| DTS_CFGR1_HSREF_CLK_DIV_RATIO(div)
#else
| DTS_CFGR1_REFCLK_SEL
#endif
| DTS_CFGR1_TS1_INTRIG(CONFIG_STM32H5_DTS_TRIGGER);
| DTS_CFGR1_TS1_INTRIG(CONFIG_STM32_DTS_TRIGGER);
putreg32(cfgr1, STM32_DTS_CFGR1);
}
@ -295,7 +295,7 @@ static void dts_get_cfg_data(void)
{
uint32_t cfgr1 = getreg32(STM32_DTS_CFGR1);
#if defined(CONFIG_STM32H5_DTS_REFCLK_LSE)
#if defined(CONFIG_STM32_DTS_REFCLK_LSE)
g_dts_cfg.lse = true;
#else
g_dts_cfg.lse = false;
@ -324,23 +324,23 @@ static void dts_configure_interrupts(struct sensor_lowerhalf_s *lower)
{
uint32_t itenr = 0;
#ifdef CONFIG_STM32H5_DTS_ITEN_ITEF
#ifdef CONFIG_STM32_DTS_ITEN_ITEF
itenr |= DTS_ITENR_ITEEN;
#endif
#ifdef CONFIG_STM32H5_DTS_ITEN_ITLF
#ifdef CONFIG_STM32_DTS_ITEN_ITLF
itenr |= DTS_ITENR_ITLEN;
#endif
#ifdef CONFIG_STM32H5_DTS_ITEN_ITHF
#ifdef CONFIG_STM32_DTS_ITEN_ITHF
itenr |= DTS_ITENR_ITHEN;
#endif
#ifdef CONFIG_STM32H5_DTS_AITEN_AITEF
#ifdef CONFIG_STM32_DTS_AITEN_AITEF
itenr |= DTS_ITENR_AITEEN;
#endif
#ifdef CONFIG_STM32H5_DTS_AITEN_AITLF
#ifdef CONFIG_STM32_DTS_AITEN_AITLF
itenr |= DTS_ITENR_AITLEN;
#endif
#ifdef CONFIG_STM32H5_DTS_AITEN_AITHF
#ifdef CONFIG_STM32_DTS_AITEN_AITHF
itenr |= DTS_ITENR_AITHEN;
#endif
@ -392,7 +392,7 @@ static int stm32_dts_activate(struct sensor_lowerhalf_s *lower,
return OK;
}
#if CONFIG_STM32H5_DTS_TRIGGER == 0
#if CONFIG_STM32_DTS_TRIGGER == 0
/****************************************************************************
* Name: stm32_dts_fetch
*

270
arch/arm/src/stm32h5/stm32_ethernet.c
View file

@ -67,11 +67,11 @@
#include <arch/board/board.h>
/* STM32_NETHERNET determines the number of physical interfaces that can
* be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if
* be supported by the hardware. CONFIG_STM32_ETHMAC will defined if
* any STM32H5 Ethernet support is enabled in the configuration.
*/
#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC)
#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC)
/****************************************************************************
* Pre-processor Definitions
@ -102,76 +102,76 @@
# endif
#endif
#ifndef CONFIG_STM32H5_PHYADDR
# error "CONFIG_STM32H5_PHYADDR must be defined in the NuttX configuration"
#ifndef CONFIG_STM32_PHYADDR
# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration"
#endif
#if !defined(CONFIG_STM32H5_MII) && !defined(CONFIG_STM32H5_RMII)
# warning "Neither CONFIG_STM32H5_MII nor CONFIG_STM32H5_RMII defined"
#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII)
# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined"
#endif
#if defined(CONFIG_STM32H5_MII) && defined(CONFIG_STM32H5_RMII)
# error "Both CONFIG_STM32H5_MII and CONFIG_STM32H5_RMII defined"
#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII)
# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined"
#endif
#ifdef CONFIG_STM32H5_MII
# if !defined(CONFIG_STM32H5_MII_MCO1) && !defined(CONFIG_STM32H5_MII_MCO2) && \
!defined(CONFIG_STM32H5_MII_EXTCLK)
# warning "Neither CONFIG_STM32H5_MII_MCO1, CONFIG_STM32H5_MII_MCO2, nor CONFIG_STM32H5_MII_EXTCLK defined"
#ifdef CONFIG_STM32_MII
# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \
!defined(CONFIG_STM32_MII_EXTCLK)
# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined"
# endif
# if defined(CONFIG_STM32H5_MII_MCO1) && defined(CONFIG_STM32H5_MII_MCO2)
# error "Both CONFIG_STM32H5_MII_MCO1 and CONFIG_STM32H5_MII_MCO2 defined"
# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2)
# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined"
# endif
#endif
#ifdef CONFIG_STM32H5_RMII
# if !defined(CONFIG_STM32H5_RMII_MCO1) && !defined(CONFIG_STM32H5_RMII_MCO2) && \
!defined(CONFIG_STM32H5_RMII_EXTCLK)
# warning "Neither CONFIG_STM32H5_RMII_MCO1, CONFIG_STM32H5_RMII_MCO2, nor CONFIG_STM32H5_RMII_EXTCLK defined"
#ifdef CONFIG_STM32_RMII
# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \
!defined(CONFIG_STM32_RMII_EXTCLK)
# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined"
# endif
# if defined(CONFIG_STM32H5_RMII_MCO1) && defined(CONFIG_STM32H5_RMII_MCO2)
# error "Both CONFIG_STM32H5_RMII_MCO1 and CONFIG_STM32H5_RMII_MCO2 defined"
# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2)
# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined"
# endif
#endif
#ifdef CONFIG_STM32H5_AUTONEG
# ifndef CONFIG_STM32H5_PHYSR
# error "CONFIG_STM32H5_PHYSR must be defined in the NuttX configuration"
#ifdef CONFIG_STM32_AUTONEG
# ifndef CONFIG_STM32_PHYSR
# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration"
# endif
# ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG
# ifndef CONFIG_STM32H5_PHYSR_ALTMODE
# error "CONFIG_STM32H5_PHYSR_ALTMODE must be defined in the NuttX configuration"
# ifdef CONFIG_STM32_PHYSR_ALTCONFIG
# ifndef CONFIG_STM32_PHYSR_ALTMODE
# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_10HD
# error "CONFIG_STM32H5_PHYSR_10HD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_10HD
# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_100HD
# error "CONFIG_STM32H5_PHYSR_100HD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_100HD
# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_10FD
# error "CONFIG_STM32H5_PHYSR_10FD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_10FD
# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_100FD
# error "CONFIG_STM32H5_PHYSR_100FD must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_100FD
# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration"
# endif
# else
# ifndef CONFIG_STM32H5_PHYSR_SPEED
# error "CONFIG_STM32H5_PHYSR_SPEED must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_SPEED
# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_100MBPS
# error "CONFIG_STM32H5_PHYSR_100MBPS must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_100MBPS
# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_MODE
# error "CONFIG_STM32H5_PHYSR_MODE must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_MODE
# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration"
# endif
# ifndef CONFIG_STM32H5_PHYSR_FULLDUPLEX
# error "CONFIG_STM32H5_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX
# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
# endif
# endif
#endif
#ifdef CONFIG_STM32H5_ETH_PTP
# warning "CONFIG_STM32H5_ETH_PTP is not yet supported"
#ifdef CONFIG_STM32_ETH_PTP
# warning "CONFIG_STM32_ETH_PTP is not yet supported"
#endif
/* Add 4 to the configured buffer size to account for the 2 byte checksum
@ -200,16 +200,16 @@
# warning "You are using an incomplete/untested configuration"
#endif
#ifndef CONFIG_STM32H5_ETH_NRXDESC
# define CONFIG_STM32H5_ETH_NRXDESC 8
#ifndef CONFIG_STM32_ETH_NRXDESC
# define CONFIG_STM32_ETH_NRXDESC 8
#endif
#ifndef CONFIG_STM32H5_ETH_NTXDESC
# define CONFIG_STM32H5_ETH_NTXDESC 4
#ifndef CONFIG_STM32_ETH_NTXDESC
# define CONFIG_STM32_ETH_NTXDESC 4
#endif
/* We need at least one more free buffer than transmit buffers */
#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H5_ETH_NTXDESC+1)
#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1)
/* Buffers used for DMA access must begin on an address aligned with the
* D-Cache line and must be an even multiple of the D-Cache line size.
@ -227,10 +227,10 @@
#define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE)
#define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE)
#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC)
#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC)
#define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE)
#define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE)
@ -241,7 +241,7 @@
*/
#ifndef CONFIG_DEBUG_NET_INFO
# undef CONFIG_STM32H5_ETHMAC_REGDEBUG
# undef CONFIG_STM32_ETHMAC_REGDEBUG
#endif
/* Clocking *****************************************************************/
@ -332,7 +332,7 @@
* ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled)
* ETH_MACCR_DR Retry disable 1 (disabled)
* ETH_MACCR_IPC IPv4 checksum offload
* Depends on CONFIG_STM32H5_ETH_HWCHECKSUM
* Depends on CONFIG_STM32_ETH_HWCHECKSUM
* ETH_MACCR_LM Loopback mode 0 (disabled)
* ETH_MACCR_DO Receive own disable 0 (enabled)
* ETH_MACCR_DCRS Carrier sense disable 0 (enabled)
@ -347,7 +347,7 @@
* ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100
*/
#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
# define MACCR_SET_BITS \
(ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96))
#else
@ -661,7 +661,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET];
/* Register operations ******************************************************/
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint32_t val, uint32_t addr);
static void stm32_checksetup(void);
@ -733,7 +733,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
union stm32_desc_u *rxtable, uint8_t *rxbuffer);
/* PHY Initialization */
#ifndef CONFIG_STM32H5_NO_PHY
#ifndef CONFIG_STM32_NO_PHY
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int stm32_phyintenable(struct stm32_ethmac_s *priv);
#endif
@ -745,17 +745,17 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
static inline int stm32_dm9161(struct stm32_ethmac_s *priv);
#endif
static int stm32_phyinit(struct stm32_ethmac_s *priv);
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_phyregdump(void);
#endif
#endif
/* MAC/DMA Initialization */
#ifdef CONFIG_STM32H5_MII
#ifdef CONFIG_STM32_MII
static inline void stm32_selectmii(void);
#endif
#ifdef CONFIG_STM32H5_RMII
#ifdef CONFIG_STM32_RMII
static inline void stm32_selectrmii(void);
#endif
static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv);
@ -785,7 +785,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv);
*
****************************************************************************/
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -857,7 +857,7 @@ static uint32_t stm32_getreg(uint32_t addr)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
@ -884,7 +884,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_checksetup(void)
{
}
@ -1026,10 +1026,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv,
struct eth_desc_s * curr)
{
union stm32_desc_u *first =
&g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC];
&g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC];
union stm32_desc_u *last =
&g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC +
CONFIG_STM32H5_ETH_NTXDESC - 1];
&g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC +
CONFIG_STM32_ETH_NTXDESC - 1];
union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1;
if (next > last)
@ -1113,7 +1113,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* pseudo-header checksum will be computed.
*/
#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
txdesc->des3 = ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL;
#else
txdesc->des3 = ETH_TDES3_RD_FD;
@ -1207,7 +1207,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* pseudo-header checksum will be computed.
*/
#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
txdesc->des3 = (ETH_TDES3_RD_OWN | ETH_TDES3_RD_LD | ETH_TDES3_RD_FD |
ETH_TDES3_RD_CIC_ALL);
#else
@ -1259,7 +1259,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv)
* stoppable transmit events.
*/
if (priv->inflight >= CONFIG_STM32H5_ETH_NTXDESC)
if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC)
{
stm32_disableint(priv, ETH_DMACIER_RIE);
}
@ -1325,7 +1325,7 @@ static int stm32_txpoll(struct net_driver_s *dev)
* In a race condition, ETH_TDES3_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
* nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC).
* nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC).
*/
if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 ||
@ -1398,7 +1398,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv)
* In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still
* not available because stm32_freeframe() has not yet run. If
* stm32_freeframe() has run, the buffer1 pointer (des0) will be
* nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC).
* nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC).
*/
if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 &&
@ -1524,10 +1524,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv,
struct eth_desc_s * curr)
{
union stm32_desc_u *first =
&g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC];
&g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC];
union stm32_desc_u *last =
&g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC +
CONFIG_STM32H5_ETH_NRXDESC - 1];
&g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC +
CONFIG_STM32_ETH_NRXDESC - 1];
union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1;
if (next > last)
@ -1678,8 +1678,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
for (i = 0;
(rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 &&
i < CONFIG_STM32H5_ETH_NRXDESC &&
priv->inflight < CONFIG_STM32H5_ETH_NTXDESC;
i < CONFIG_STM32_ETH_NRXDESC &&
priv->inflight < CONFIG_STM32_ETH_NTXDESC;
i++)
{
/* Check if this is a normal descriptor */
@ -1724,7 +1724,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv)
ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
/* Check if any errors are reported in the frame.
* If hardware checksum is enabled, check if:
* - RDES1 is valid
@ -2796,7 +2796,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
/* Initialize each TX descriptor */
for (i = 0; i < CONFIG_STM32H5_ETH_NTXDESC; i++)
for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++)
{
txdesc = &txtable[i].desc;
@ -2832,7 +2832,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv,
* properly but the DMACCATXDR advances to outside the descriptor ring
*/
stm32_putreg(CONFIG_STM32H5_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR);
stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR);
/* Set Transmit Descriptor List Address Register */
@ -2885,7 +2885,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
/* Initialize each RX descriptor */
for (i = 0; i < CONFIG_STM32H5_ETH_NRXDESC; i++)
for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++)
{
rxdesc = &rxtable[i].desc;
@ -2918,7 +2918,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
* properly but the DMACCARXDR advances to outside the descriptor ring
*/
stm32_putreg(CONFIG_STM32H5_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR);
stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR);
/* Set Receive Descriptor List Address Register */
@ -2926,7 +2926,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
/* Set Receive Descriptor Tail pointer Address */
stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H5_ETH_NRXDESC - 1].desc,
stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc,
STM32_ETH_DMACRXDTPR);
}
@ -2962,7 +2962,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
#ifdef CONFIG_NETDEV_PHY_IOCTL
static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
#ifndef CONFIG_STM32H5_NO_PHY
#ifndef CONFIG_STM32_NO_PHY
#ifdef CONFIG_ARCH_PHY_INTERRUPT
struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
#endif
@ -2992,7 +2992,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
req->phy_id = CONFIG_STM32H5_PHYADDR;
req->phy_id = CONFIG_STM32_PHYADDR;
ret = OK;
}
break;
@ -3026,7 +3026,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
}
#endif /* CONFIG_NETDEV_PHY_IOCTL */
#ifndef CONFIG_STM32H5_NO_PHY
#ifndef CONFIG_STM32_NO_PHY
/****************************************************************************
* Function: stm32_phyintenable
*
@ -3224,7 +3224,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
* indication that check if the DM9161 PHY CHIP is not ready.
*/
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_PHYID1, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY ID1: %d\n", ret);
@ -3246,7 +3246,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
* Register 16
*/
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, 16, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret);
@ -3280,7 +3280,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
static void stm32_phyregdump()
{
uint16_t phyval;
@ -3289,7 +3289,7 @@ static void stm32_phyregdump()
for (i = 0; i < 0x20; i++)
{
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, i, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, i, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read reg: 0%2x\n", i);
@ -3320,7 +3320,7 @@ static void stm32_phyregdump()
static int stm32_phyinit(struct stm32_ethmac_s *priv)
{
#ifdef CONFIG_STM32H5_AUTONEG
#ifdef CONFIG_STM32_AUTONEG
volatile uint32_t timeout;
#endif
uint32_t regval;
@ -3342,7 +3342,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Put the PHY in reset mode */
ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_RESET,
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET,
MII_MCR_RESET);
if (ret < 0)
{
@ -3355,7 +3355,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
{
up_mdelay(10);
to -= 10;
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MCR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MCR, &phyval);
}
while (phyval & MII_MCR_RESET && to > 0);
@ -3369,7 +3369,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
ninfo("Phy reset in %d ms\n", PHY_RESET_DELAY - to);
}
#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG
#ifdef CONFIG_STM32_ETHMAC_REGDEBUG
stm32_phyregdump();
#endif
@ -3385,12 +3385,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Perform auto-negotiation if so configured */
#ifdef CONFIG_STM32H5_AUTONEG
#ifdef CONFIG_STM32_AUTONEG
/* Wait for link status */
for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
{
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
@ -3412,7 +3412,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Enable auto-negotiation */
ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_ANENABLE,
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE,
MII_MCR_ANENABLE);
if (ret < 0)
{
@ -3424,7 +3424,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
{
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
@ -3446,7 +3446,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Read the result of the auto-negotiation from the PHY-specific register */
ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, CONFIG_STM32H5_PHYSR, &phyval);
ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval);
if (ret < 0)
{
nerr("ERROR: Failed to read PHY status register\n");
@ -3455,38 +3455,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Remember the selected speed and duplex modes */
ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H5_PHYSR, phyval);
ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval);
/* Different PHYs present speed and mode information in different ways. IF
* This CONFIG_STM32H5_PHYSR_ALTCONFIG is selected, this indicates that
* This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that
* the PHY represents speed and mode information are combined, for
* example, with separate bits for 10HD, 100HD, 10FD and 100FD.
*/
#ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG
switch (phyval & CONFIG_STM32H5_PHYSR_ALTMODE)
#ifdef CONFIG_STM32_PHYSR_ALTCONFIG
switch (phyval & CONFIG_STM32_PHYSR_ALTMODE)
{
default:
nerr("ERROR: Unrecognized PHY status setting\n");
/* Falls through */
case CONFIG_STM32H5_PHYSR_10HD:
case CONFIG_STM32_PHYSR_10HD:
priv->fduplex = 0;
priv->mbps100 = 0;
break;
case CONFIG_STM32H5_PHYSR_100HD:
case CONFIG_STM32_PHYSR_100HD:
priv->fduplex = 0;
priv->mbps100 = 1;
break;
case CONFIG_STM32H5_PHYSR_10FD:
case CONFIG_STM32_PHYSR_10FD:
priv->fduplex = 1;
priv->mbps100 = 0;
break;
case CONFIG_STM32H5_PHYSR_100FD:
case CONFIG_STM32_PHYSR_100FD:
priv->fduplex = 1;
priv->mbps100 = 1;
break;
@ -3499,13 +3499,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
*/
#else
if ((phyval & CONFIG_STM32H5_PHYSR_MODE) ==
CONFIG_STM32H5_PHYSR_FULLDUPLEX)
if ((phyval & CONFIG_STM32_PHYSR_MODE) ==
CONFIG_STM32_PHYSR_FULLDUPLEX)
{
priv->fduplex = 1;
}
if ((phyval & CONFIG_STM32H5_PHYSR_SPEED) == CONFIG_STM32H5_PHYSR_100MBPS)
if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS)
{
priv->mbps100 = 1;
}
@ -3514,14 +3514,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
#else /* Auto-negotiation not selected */
phyval = 0;
#ifdef CONFIG_STM32H5_ETHFD
#ifdef CONFIG_STM32_ETHFD
phyval |= MII_MCR_FULLDPLX;
#endif
#ifdef CONFIG_STM32H5_ETH100MBPS
#ifdef CONFIG_STM32_ETH100MBPS
phyval |= MII_MCR_SPEED100;
#endif
ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, phyval, 0xffff);
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff);
if (ret < 0)
{
nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
@ -3532,10 +3532,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
/* Remember the selected speed and duplex modes */
#ifdef CONFIG_STM32H5_ETHFD
#ifdef CONFIG_STM32_ETHFD
priv->fduplex = 1;
#endif
#ifdef CONFIG_STM32H5_ETH100MBPS
#ifdef CONFIG_STM32_ETH100MBPS
priv->mbps100 = 1;
#endif
#endif
@ -3563,7 +3563,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_MII
#ifdef CONFIG_STM32_MII
#pragma message "If TrustZone is enabled, MII will fail to select."
static inline void stm32_selectmii(void)
{
@ -3590,7 +3590,7 @@ static inline void stm32_selectmii(void)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_RMII
#ifdef CONFIG_STM32_RMII
#pragma message "If TrustZone is enabled, RMII will fail to select."
static inline void stm32_selectrmii(void)
{
@ -3623,17 +3623,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
{
/* Configure GPIO pins to support Ethernet */
#if defined(CONFIG_STM32H5_MII) || defined(CONFIG_STM32H5_RMII)
#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII)
/* MDC and MDIO are common to both modes */
# ifndef CONFIG_STM32H5_NO_PHY
# ifndef CONFIG_STM32_NO_PHY
stm32_configgpio(GPIO_ETH_MDC);
stm32_configgpio(GPIO_ETH_MDIO);
# endif
/* Set up the MII interface */
# if defined(CONFIG_STM32H5_MII)
# if defined(CONFIG_STM32_MII)
/* Select the MII interface */
@ -3648,7 +3648,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_STM32H5_MII_MCO1)
# if defined(CONFIG_STM32_MII_MCO1)
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
* info.
*/
@ -3656,7 +3656,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO1);
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
# elif defined(CONFIG_STM32H5_MII_MCO2)
# elif defined(CONFIG_STM32_MII_MCO2)
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
* info.
*/
@ -3664,7 +3664,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO2);
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
# elif defined(CONFIG_STM32H5_MII_MCO)
# elif defined(CONFIG_STM32_MII_MCO)
/* Setup MCO pin for alternative usage */
stm32_configgpio(GPIO_MCO);
@ -3695,7 +3695,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the RMII interface. */
# elif defined(CONFIG_STM32H5_RMII)
# elif defined(CONFIG_STM32_RMII)
/* Select the RMII interface */
@ -3710,7 +3710,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_STM32H5_RMII_MCO1)
# if defined(CONFIG_STM32_RMII_MCO1)
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
* info.
*/
@ -3718,7 +3718,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO1);
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
# elif defined(CONFIG_STM32H5_RMII_MCO2)
# elif defined(CONFIG_STM32_RMII_MCO2)
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
* info.
*/
@ -3726,7 +3726,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO2);
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
# elif defined(CONFIG_STM32H5_RMII_MCO)
# elif defined(CONFIG_STM32_RMII_MCO)
/* Setup MCO pin for alternative usage */
stm32_configgpio(GPIO_MCO);
@ -3749,7 +3749,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
# endif
#endif
#ifdef CONFIG_STM32H5_ETH_PTP
#ifdef CONFIG_STM32_ETH_PTP
/* Enable pulse-per-second (PPS) output signal */
stm32_configgpio(GPIO_ETH_PPS_OUT);
@ -4088,7 +4088,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
* sequence in stm32_rcc.c.
*/
#ifdef CONFIG_STM32H5_PHYINIT
#ifdef CONFIG_STM32_PHYINIT
/* Perform any necessary, board-specific PHY initialization */
ret = stm32_phy_boardinitialize(0);
@ -4111,24 +4111,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
/* Initialize TX Descriptors list */
stm32_txdescinit(priv,
&g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]);
&g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]);
/* Initialize RX Descriptors list */
stm32_rxdescinit(priv,
&g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC],
&g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC],
&g_rxbuffer[priv->intf * RXBUFFER_SIZE]);
/* Initialize the PHY */
#ifdef CONFIG_STM32H5_NO_PHY
#ifdef CONFIG_STM32_NO_PHY
ninfo("MAC without PHY\n");
#ifdef CONFIG_STM32H5_ETHFD
#ifdef CONFIG_STM32_ETHFD
priv->fduplex = 1;
#else
priv->fduplex = 0;
#endif
#ifdef CONFIG_STM32H5_ETH100MBPS
#ifdef CONFIG_STM32_ETH100MBPS
priv->mbps100 = 1;
#else
priv->mbps100 = 0;
@ -4242,7 +4242,7 @@ static inline int stm32_ethinitialize(int intf)
return -EAGAIN;
}
#ifdef CONFIG_STM32H5_PHYINIT
#ifdef CONFIG_STM32_PHYINIT
/* Perform any necessary, board-specific PHY initialization */
ret = stm32_phy_boardinitialize(0);
@ -4290,4 +4290,4 @@ void arm_netinitialize(void)
}
#endif
#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */
#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */

4
arch/arm/src/stm32h5/stm32_ethernet.h
View file

@ -75,7 +75,7 @@ int stm32_ethinitialize(int intf);
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_STM32H5_PHYINIT is defined in the configuration
* the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration
* then the board specific logic must provide stm32_phyinitialize(); The
* STM32 Ethernet driver will call this function one time before it first
* uses the PHY.
@ -90,7 +90,7 @@ int stm32_ethinitialize(int intf);
*
****************************************************************************/
#ifdef CONFIG_STM32H5_PHYINIT
#ifdef CONFIG_STM32_PHYINIT
int stm32_phy_boardinitialize(int intf);
#endif

130
arch/arm/src/stm32h5/stm32_fdcan.c
View file

@ -75,7 +75,7 @@
# define STM32_CANRAM1_BASE (STM32_FDCAN_SRAM_BASE + 0x0000)
# define STM32_CANRAM2_BASE (STM32_FDCAN_SRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4))
# ifdef CONFIG_STM32H5_FDCAN1
# ifdef CONFIG_STM32_FDCAN1
# define FDCAN1_STDFILTER_SIZE (28)
# define FDCAN1_EXTFILTER_SIZE (8)
# define FDCAN1_RXFIFO0_SIZE (3)
@ -90,7 +90,7 @@
# define FDCAN1_TXEVENTFIFO_WORDS (6)
# define FDCAN1_TXFIFIOQ_WORDS (54)
# endif
# ifdef CONFIG_STM32H5_FDCAN2
# ifdef CONFIG_STM32_FDCAN2
# define FDCAN2_STDFILTER_SIZE (28)
# define FDCAN2_EXTFILTER_SIZE (8)
# define FDCAN2_RXFIFO0_SIZE (3)
@ -108,18 +108,18 @@
/* FDCAN1 Configuration *****************************************************/
#ifdef CONFIG_STM32H5_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Bit timing */
# ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING
# ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING
# define FDCAN1_NTSEG1 (CONFIG_STM32H5_FDCAN1_NTSEG1 - 1)
# define FDCAN1_NTSEG2 (CONFIG_STM32H5_FDCAN1_NTSEG2 - 1)
# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1)
# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1)
# define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \
((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \
CONFIG_STM32H5_FDCAN1_BITRATE)) - 1)
# define FDCAN1_NSJW (CONFIG_STM32H5_FDCAN1_NSJW - 1)
CONFIG_STM32_FDCAN1_BITRATE)) - 1)
# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1)
# if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX
# error Invalid FDCAN1 NTSEG1
@ -134,13 +134,13 @@
# error Invalid FDCAN1 NBRP
# endif
# ifdef CONFIG_STM32H5_FDCAN1_FD_BRS
# define FDCAN1_DTSEG1 (CONFIG_STM32H5_FDCAN1_DTSEG1 - 1)
# define FDCAN1_DTSEG2 (CONFIG_STM32H5_FDCAN1_DTSEG2 - 1)
# ifdef CONFIG_STM32_FDCAN1_FD_BRS
# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1)
# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1)
# define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \
((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \
CONFIG_STM32H5_FDCAN1_DBITRATE)) - 1)
# define FDCAN1_DSJW (CONFIG_STM32H5_FDCAN1_DSJW - 1)
CONFIG_STM32_FDCAN1_DBITRATE)) - 1)
# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1)
# else
# define FDCAN1_DTSEG1 1
# define FDCAN1_DTSEG2 1
@ -174,22 +174,22 @@
# define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS)
# define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS)
#endif /* CONFIG_STM32H5_FDCAN1 */
#endif /* CONFIG_STM32_FDCAN1 */
/* FDCAN2 Configuration *****************************************************/
#ifdef CONFIG_STM32H5_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
/* Bit timing */
# ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING
# ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING
# define FDCAN2_NTSEG1 (CONFIG_STM32H5_FDCAN2_NTSEG1 - 1)
# define FDCAN2_NTSEG2 (CONFIG_STM32H5_FDCAN2_NTSEG2 - 1)
# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1)
# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1)
# define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \
((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \
CONFIG_STM32H5_FDCAN2_BITRATE)) - 1))
# define FDCAN2_NSJW (CONFIG_STM32H5_FDCAN2_NSJW - 1)
CONFIG_STM32_FDCAN2_BITRATE)) - 1))
# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1)
# if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX
# error Invalid FDCAN2 NTSEG1
@ -204,13 +204,13 @@
# error Invalid FDCAN1 NBRP
# endif
# ifdef CONFIG_STM32H5_FDCAN2_FD_BRS
# define FDCAN2_DTSEG1 (CONFIG_STM32H5_FDCAN2_DTSEG1 - 1)
# define FDCAN2_DTSEG2 (CONFIG_STM32H5_FDCAN2_DTSEG2 - 1)
# ifdef CONFIG_STM32_FDCAN2_FD_BRS
# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1)
# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1)
# define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \
((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \
CONFIG_STM32H5_FDCAN2_DBITRATE)) - 1))
# define FDCAN2_DSJW (CONFIG_STM32H5_FDCAN2_DSJW - 1)
CONFIG_STM32_FDCAN2_DBITRATE)) - 1))
# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1)
# else
# define FDCAN2_DTSEG1 1
# define FDCAN2_DTSEG2 1
@ -245,7 +245,7 @@
# define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS)
# define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS)
#endif /* CONFIG_STM32H5_FDCAN2 */
#endif /* CONFIG_STM32_FDCAN2 */
/* Interrupts ***************************************************************/
@ -325,12 +325,12 @@
/* Debug configurations that may be enabled just for testing FDCAN */
#ifndef CONFIG_DEBUG_CAN_INFO
# undef CONFIG_STM32H5_FDCAN_REGDEBUG
# undef CONFIG_STM32_FDCAN_REGDEBUG
#endif
#undef STM32_FDCAN_LOOPBACK
#if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \
defined(CONFIG_STM32H5_FDCAN2_LOOPBACK)
#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \
defined(CONFIG_STM32_FDCAN2_LOOPBACK)
# define STM32_FDCAN_LOOPBACK 1
#endif
@ -435,7 +435,7 @@ struct stm32_fdcan_s
#endif
uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
uintptr_t regaddr; /* Last register address read */
uint32_t regval; /* Last value read from the register */
unsigned int count; /* Number of times that the value was read */
@ -460,7 +460,7 @@ struct fdcan_bitseg
static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset);
static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
uint32_t regval);
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
const char *msg);
static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
@ -537,7 +537,7 @@ static const struct can_ops_s g_fdcanops =
.co_txempty = fdcan_txempty,
};
#ifdef CONFIG_STM32H5_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
/* Message RAM allocation */
/* Constant configuration */
@ -547,11 +547,11 @@ static const struct stm32_config_s g_fdcan1const =
.rxpinset = GPIO_FDCAN1_RX,
.txpinset = GPIO_FDCAN1_TX,
.base = STM32_FDCAN1_BASE,
.baud = CONFIG_STM32H5_FDCAN1_BITRATE,
#if defined(CONFIG_STM32H5_FDCAN1_FD_BRS)
.data_baud = CONFIG_STM32H5_FDCAN1_DBITRATE,
.baud = CONFIG_STM32_FDCAN1_BITRATE,
#if defined(CONFIG_STM32_FDCAN1_FD_BRS)
.data_baud = CONFIG_STM32_FDCAN1_DBITRATE,
#endif
#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING
#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING
.nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) |
FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) |
FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) |
@ -564,14 +564,14 @@ static const struct stm32_config_s g_fdcan1const =
.port = 1,
.irq0 = STM32_IRQ_FDCAN1_IT0,
.irq1 = STM32_IRQ_FDCAN1_IT1,
#if defined(CONFIG_STM32H5_FDCAN1_CLASSIC)
#if defined(CONFIG_STM32_FDCAN1_CLASSIC)
.mode = FDCAN_CLASSIC_MODE,
#elif defined(CONFIG_STM32H5_FDCAN1_FD)
#elif defined(CONFIG_STM32_FDCAN1_FD)
.mode = FDCAN_FD_MODE,
#else
.mode = FDCAN_FD_BRS_MODE,
#endif
#if defined(CONFIG_STM32H5_FDCAN1_NONISO_FORMAT)
#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT)
.format = FDCAN_NONISO_BOSCH_V1_FORMAT,
#else
.format = FDCAN_ISO11898_1_FORMAT,
@ -587,7 +587,7 @@ static const struct stm32_config_s g_fdcan1const =
.txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE),
.txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE),
#ifdef CONFIG_STM32H5_FDCAN1_LOOPBACK
#ifdef CONFIG_STM32_FDCAN1_LOOPBACK
.loopback = true,
#endif
@ -609,9 +609,9 @@ static const struct stm32_config_s g_fdcan1const =
static struct stm32_fdcan_s g_fdcan1priv;
static struct can_dev_s g_fdcan1dev;
#endif /* CONFIG_STM32H5_FDCAN1 */
#endif /* CONFIG_STM32_FDCAN1 */
#ifdef CONFIG_STM32H5_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
/* FDCAN2 message RAM allocation */
/* FDCAN2 constant configuration */
@ -621,11 +621,11 @@ static const struct stm32_config_s g_fdcan2const =
.rxpinset = GPIO_FDCAN2_RX,
.txpinset = GPIO_FDCAN2_TX,
.base = STM32_FDCAN2_BASE,
.baud = CONFIG_STM32H5_FDCAN2_BITRATE,
#if defined(CONFIG_STM32H5_FDCAN2_FD_BRS)
.data_baud = CONFIG_STM32H5_FDCAN2_DBITRATE,
.baud = CONFIG_STM32_FDCAN2_BITRATE,
#if defined(CONFIG_STM32_FDCAN2_FD_BRS)
.data_baud = CONFIG_STM32_FDCAN2_DBITRATE,
#endif
#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING
#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING
.nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) |
FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) |
FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) |
@ -638,14 +638,14 @@ static const struct stm32_config_s g_fdcan2const =
.port = 2,
.irq0 = STM32_IRQ_FDCAN2_IT0,
.irq1 = STM32_IRQ_FDCAN2_IT1,
#if defined(CONFIG_STM32H5_FDCAN2_CLASSIC)
#if defined(CONFIG_STM32_FDCAN2_CLASSIC)
.mode = FDCAN_CLASSIC_MODE,
#elif defined(CONFIG_STM32H5_FDCAN2_FD)
#elif defined(CONFIG_STM32_FDCAN2_FD)
.mode = FDCAN_FD_MODE,
#else
.mode = FDCAN_FD_BRS_MODE,
#endif
#if defined(CONFIG_STM32H5_FDCAN2_NONISO_FORMAT)
#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT)
.format = FDCAN_NONISO_BOSCH_V1_FORMAT,
#else
.format = FDCAN_ISO11898_1_FORMAT,
@ -661,7 +661,7 @@ static const struct stm32_config_s g_fdcan2const =
.txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE),
.txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE),
#ifdef CONFIG_STM32H5_FDCAN2_LOOPBACK
#ifdef CONFIG_STM32_FDCAN2_LOOPBACK
.loopback = true,
#endif
@ -683,7 +683,7 @@ static const struct stm32_config_s g_fdcan2const =
static struct stm32_fdcan_s g_fdcan2priv;
static struct can_dev_s g_fdcan2dev;
#endif /* CONFIG_STM32H5_FDCAN2 */
#endif /* CONFIG_STM32_FDCAN2 */
/****************************************************************************
* Private Functions
@ -703,7 +703,7 @@ static struct can_dev_s g_fdcan2dev;
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset)
{
const struct stm32_config_s *config = priv->config;
@ -783,7 +783,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
uint32_t regval)
{
@ -823,7 +823,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -869,7 +869,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -912,7 +912,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumptxregs(struct stm32_fdcan_s *priv,
const char *msg)
{
@ -961,7 +961,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv)
{
const struct stm32_config_s *config = priv->config;
@ -2406,7 +2406,7 @@ static bool fdcan_txempty(struct can_dev_s *dev)
{
struct stm32_fdcan_s *priv = dev->cd_priv;
uint32_t regval = 0;
#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE
#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE
int tffl = 0;
bool empty = false;
#endif
@ -2426,7 +2426,7 @@ static bool fdcan_txempty(struct can_dev_s *dev)
/* Tx FIFO Free Level */
#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE
#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE
tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT;
empty = (tffl >= priv->config->ntxfifoq);
return empty;
@ -3275,7 +3275,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv)
/* Enable FIFO/Queue mode */
regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET);
#ifdef CONFIG_STM32H5_FDCAN_QUEUE_MODE
#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE
regval |= FDCAN_TXBC_TFQM;
#else
regval &= ~FDCAN_TXBC_TFQM;
@ -3461,7 +3461,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing)
return 3; /* Solution not found */
}
#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG
#ifdef CONFIG_STM32_FDCAN_REGDEBUG
ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d"
", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1,
bs2 - 1);
@ -3506,7 +3506,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port)
/* Select FDCAN peripheral to be initialized */
#ifdef CONFIG_STM32H5_FDCAN1
#ifdef CONFIG_STM32_FDCAN1
if (port == FDCAN1)
{
/* Select the FDCAN1 device structure */
@ -3514,13 +3514,13 @@ struct can_dev_s *stm32_fdcaninitialize(int port)
dev = &g_fdcan1dev;
priv = &g_fdcan1priv;
config = &g_fdcan1const;
#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING
#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING
auto_bit_timing = false;
#endif
}
else
#endif
#ifdef CONFIG_STM32H5_FDCAN2
#ifdef CONFIG_STM32_FDCAN2
if (port == FDCAN2)
{
/* Select the FDCAN2 device structure */
@ -3528,7 +3528,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port)
dev = &g_fdcan2dev;
priv = &g_fdcan2priv;
config = &g_fdcan2const;
#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING
#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING
auto_bit_timing = false;
#endif
}

4
arch/arm/src/stm32h5/stm32_fdcan.h
View file

@ -64,7 +64,7 @@ extern "C"
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER
#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
/****************************************************************************
* Name: stm32_fdcaninitialize
@ -83,7 +83,7 @@ extern "C"
struct can_dev_s *stm32_fdcaninitialize(int port);
#endif
#ifdef CONFIG_STM32H5_FDCAN_SOCKET
#ifdef CONFIG_STM32_FDCAN_SOCKET
/****************************************************************************
* Name: stm32_fdcansockinitialize

2
arch/arm/src/stm32h5/stm32_flash.c
View file

@ -26,7 +26,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32H5_STM32H563XX)
#if defined(CONFIG_STM32_STM32H563XX)
# include "stm32h563xx_flash.c"
#else
# error "Unsupported STM32 H5 chip"

2
arch/arm/src/stm32h5/stm32_gpio.h
View file

@ -39,7 +39,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H5XXXX)
#if defined(CONFIG_STM32_STM32H5XXXX)
# include "hardware/stm32_gpio.h"
#else
# error "Unsupported STM32H5 chip"

4
arch/arm/src/stm32h5/stm32_hsi48.c
View file

@ -37,7 +37,7 @@
* Public Functions
****************************************************************************/
#ifdef CONFIG_STM32H5_HAVE_HSI48
#ifdef CONFIG_STM32_HAVE_HSI48
/****************************************************************************
* Name: stm32_enable_hsi48
*
@ -168,4 +168,4 @@ void stm32_disable_hsi48(void)
putreg32(regval, STM32_CRS_CR);
}
#endif /* CONFIG_STM32H5_HAVE_HSI48 */
#endif /* CONFIG_STM32_HAVE_HSI48 */

4
arch/arm/src/stm32h5/stm32_hsi48.h
View file

@ -29,7 +29,7 @@
#include <nuttx/config.h>
#ifdef CONFIG_STM32H5_HAVE_HSI48
#ifdef CONFIG_STM32_HAVE_HSI48
/****************************************************************************
* Public Types
@ -92,5 +92,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc);
void stm32_disable_hsi48(void);
#endif /* CONFIG_STM32H5_HAVE_HSI48 */
#endif /* CONFIG_STM32_HAVE_HSI48 */
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */

196
arch/arm/src/stm32h5/stm32_i2c.c
View file

@ -162,24 +162,24 @@
*
* and one or more interfaces:
*
* CONFIG_STM32H5_I2C1
* CONFIG_STM32H5_I2C2
* CONFIG_STM32H5_I2C3
* CONFIG_STM32H5_I2C4
* CONFIG_STM32_I2C1
* CONFIG_STM32_I2C2
* CONFIG_STM32_I2C3
* CONFIG_STM32_I2C4
*
* To configure the ISR timeout using fixed values
* (CONFIG_STM32H5_I2C_DYNTIMEO=n):
* (CONFIG_STM32_I2C_DYNTIMEO=n):
*
* CONFIG_STM32H5_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32H5_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32H5_I2CTIMEOTICKS (Timeout in ticks)
* CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds)
* CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds)
* CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks)
*
* To configure the ISR timeout using dynamic values
* (CONFIG_STM32H5_I2C_DYNTIMEO=y):
* (CONFIG_STM32_I2C_DYNTIMEO=y):
*
* CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE
* CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE
* (Timeout in microseconds per byte)
* CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP
* CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
* (Timeout for start/stop in msec)
*
* Debugging output enabled with:
@ -227,8 +227,8 @@
/* At least one I2C peripheral must be enabled */
#if defined(CONFIG_STM32H5_I2C1) || defined(CONFIG_STM32H5_I2C2) || \
defined(CONFIG_STM32H5_I2C3) || defined(CONFIG_STM32H5_I2C4)
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4)
/****************************************************************************
* Pre-processor Definitions
@ -246,25 +246,25 @@
/* Interrupt wait timeout in seconds and milliseconds */
#if !defined(CONFIG_STM32H5_I2CTIMEOSEC) && !defined(CONFIG_STM32H5_I2CTIMEOMS)
# define CONFIG_STM32H5_I2CTIMEOSEC 0
# define CONFIG_STM32H5_I2CTIMEOMS 500 /* Default is 500 milliseconds */
#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOSEC 0
# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */
# warning "Using Default 500 Ms Timeout"
#elif !defined(CONFIG_STM32H5_I2CTIMEOSEC)
# define CONFIG_STM32H5_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32H5_I2CTIMEOMS)
# define CONFIG_STM32H5_I2CTIMEOMS 0 /* User provided seconds */
#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */
#elif !defined(CONFIG_STM32_I2CTIMEOMS)
# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */
#endif
/* Interrupt wait time timeout in system timer ticks */
#ifndef CONFIG_STM32H5_I2CTIMEOTICKS
# define CONFIG_STM32H5_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32H5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H5_I2CTIMEOMS))
#ifndef CONFIG_STM32_I2CTIMEOTICKS
# define CONFIG_STM32_I2CTIMEOTICKS \
(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
#endif
#ifndef CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H5_I2CTIMEOTICKS)
#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
#endif
/* Macros to convert a I2C pin to a GPIO output */
@ -443,9 +443,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv,
static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
uint8_t offset, uint32_t clearbits,
uint32_t setbits);
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs);
#endif /* CONFIG_STM32H5_I2C_DYNTIMEO */
#endif /* CONFIG_STM32_I2C_DYNTIMEO */
static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv);
#ifdef CONFIG_I2C_TRACE
@ -485,7 +485,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H5_I2C1
#ifdef CONFIG_STM32_I2C1
static const struct stm32_i2c_config_s stm32_i2c1_config =
{
.base = STM32_I2C1_BASE,
@ -523,7 +523,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv =
};
#endif
#ifdef CONFIG_STM32H5_I2C2
#ifdef CONFIG_STM32_I2C2
static const struct stm32_i2c_config_s stm32_i2c2_config =
{
.base = STM32_I2C2_BASE,
@ -561,7 +561,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
};
#endif
#ifdef CONFIG_STM32H5_I2C3
#ifdef CONFIG_STM32_I2C3
static const struct stm32_i2c_config_s stm32_i2c3_config =
{
.base = STM32_I2C3_BASE,
@ -599,7 +599,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
};
#endif
#ifdef CONFIG_STM32H5_I2C4
#ifdef CONFIG_STM32_I2C4
static const struct stm32_i2c_config_s stm32_i2c4_config =
{
.base = STM32_I2C4_BASE,
@ -731,7 +731,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
{
size_t bytecount = 0;
@ -748,7 +748,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
* factor.
*/
return USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE * bytecount);
return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
}
#endif
@ -804,12 +804,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
{
/* Wait until either the transfer is complete or the timeout expires */
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
stm32_i2c_toticks(priv->msgc, priv->msgv));
#else
ret = nxsem_tickwait_uninterruptible(&priv->sem_isr,
CONFIG_STM32H5_I2CTIMEOTICKS);
CONFIG_STM32_I2CTIMEOTICKS);
#endif
if (ret < 0)
{
@ -847,10 +847,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv)
/* Get the timeout value */
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = stm32_i2c_toticks(priv->msgc, priv->msgv);
#else
timeout = CONFIG_STM32H5_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Signal the interrupt handler that we are waiting. NOTE: Interrupts
@ -988,10 +988,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv)
/* Select a timeout */
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP);
#ifdef CONFIG_STM32_I2C_DYNTIMEO
timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
#else
timeout = CONFIG_STM32H5_I2CTIMEOTICKS;
timeout = CONFIG_STM32_I2CTIMEOTICKS;
#endif
/* Wait as stop might still be in progress */
@ -1283,82 +1283,82 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv,
switch (priv->config->base)
{
#ifdef CONFIG_STM32H5_I2C1
#ifdef CONFIG_STM32_I2C1
case STM32_I2C1_BASE:
# if defined(CONFIG_STM32H5_I2C1_CLK_HSI)
# if defined(CONFIG_STM32_I2C1_CLK_HSI)
i2c_ker_ck = STM32_HSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI)
# elif defined(CONFIG_STM32_I2C1_CLK_CSI)
i2c_ker_ck = STM32_CSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1)
# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1)
i2c_ker_ck = STM32_PCLK1_FREQUENCY;
# else
i2c_ker_ck = STM32_PLL3R_FREQUENCY;
# endif
anfoff = CONFIG_STM32H5_I2C1_ANFOFF;
dnf = CONFIG_STM32H5_I2C1_DNF;
# ifdef CONFIG_STM32H5_I2C1_RF_OVERRIDE
tr_max = CONFIG_STM32H5_I2C1_RISE;
tf_max = CONFIG_STM32H5_I2C1_FALL;
anfoff = CONFIG_STM32_I2C1_ANFOFF;
dnf = CONFIG_STM32_I2C1_DNF;
# ifdef CONFIG_STM32_I2C1_RF_OVERRIDE
tr_max = CONFIG_STM32_I2C1_RISE;
tf_max = CONFIG_STM32_I2C1_FALL;
rf_override = true;
# endif
break;
#endif
#ifdef CONFIG_STM32H5_I2C2
#ifdef CONFIG_STM32_I2C2
case STM32_I2C2_BASE:
# if defined(CONFIG_STM32H5_I2C2_CLK_HSI)
# if defined(CONFIG_STM32_I2C2_CLK_HSI)
i2c_ker_ck = STM32_HSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI)
# elif defined(CONFIG_STM32_I2C2_CLK_CSI)
i2c_ker_ck = STM32_CSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1)
# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1)
i2c_ker_ck = STM32_PCLK1_FREQUENCY;
# else
i2c_ker_ck = STM32_PLL3R_FREQUENCY;
# endif
anfoff = CONFIG_STM32H5_I2C2_ANFOFF;
dnf = CONFIG_STM32H5_I2C2_DNF;
# ifdef CONFIG_STM32H5_I2C2_RF_OVERRIDE
tr_max = CONFIG_STM32H5_I2C2_RISE;
tf_max = CONFIG_STM32H5_I2C2_FALL;
anfoff = CONFIG_STM32_I2C2_ANFOFF;
dnf = CONFIG_STM32_I2C2_DNF;
# ifdef CONFIG_STM32_I2C2_RF_OVERRIDE
tr_max = CONFIG_STM32_I2C2_RISE;
tf_max = CONFIG_STM32_I2C2_FALL;
rf_override = true;
# endif
break;
#endif
#ifdef CONFIG_STM32H5_I2C3
#ifdef CONFIG_STM32_I2C3
case STM32_I2C3_BASE:
# if defined(CONFIG_STM32H5_I2C3_CLK_HSI)
# if defined(CONFIG_STM32_I2C3_CLK_HSI)
i2c_ker_ck = STM32_HSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI)
# elif defined(CONFIG_STM32_I2C3_CLK_CSI)
i2c_ker_ck = STM32_CSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3)
# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3)
i2c_ker_ck = STM32_PCLK3_FREQUENCY;
# else
i2c_ker_ck = STM32_PLL3R_FREQUENCY;
# endif
anfoff = CONFIG_STM32H5_I2C3_ANFOFF;
dnf = CONFIG_STM32H5_I2C3_DNF;
# ifdef CONFIG_STM32H5_I2C3_RF_OVERRIDE
tr_max = CONFIG_STM32H5_I2C3_RISE;
tf_max = CONFIG_STM32H5_I2C3_FALL;
anfoff = CONFIG_STM32_I2C3_ANFOFF;
dnf = CONFIG_STM32_I2C3_DNF;
# ifdef CONFIG_STM32_I2C3_RF_OVERRIDE
tr_max = CONFIG_STM32_I2C3_RISE;
tf_max = CONFIG_STM32_I2C3_FALL;
rf_override = true;
# endif
break;
#endif
#ifdef CONFIG_STM32H5_I2C4
#ifdef CONFIG_STM32_I2C4
case STM32_I2C4_BASE:
# if defined(CONFIG_STM32H5_I2C4_CLK_HSI)
# if defined(CONFIG_STM32_I2C4_CLK_HSI)
i2c_ker_ck = STM32_HSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI)
# elif defined(CONFIG_STM32_I2C4_CLK_CSI)
i2c_ker_ck = STM32_CSI_FREQUENCY;
# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3)
# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3)
i2c_ker_ck = STM32_PCLK3_FREQUENCY;
# else
i2c_ker_ck = STM32_PLL3R_FREQUENCY;
# endif
anfoff = CONFIG_STM32H5_I2C4_ANFOFF;
dnf = CONFIG_STM32H5_I2C4_DNF;
# ifdef CONFIG_STM32H5_I2C4_RF_OVERRIDE
tr_max = CONFIG_STM32H5_I2C4_RISE;
tf_max = CONFIG_STM32H5_I2C4_FALL;
anfoff = CONFIG_STM32_I2C4_ANFOFF;
dnf = CONFIG_STM32_I2C4_DNF;
# ifdef CONFIG_STM32_I2C4_RF_OVERRIDE
tr_max = CONFIG_STM32_I2C4_RISE;
tf_max = CONFIG_STM32_I2C4_FALL;
rf_override = true;
# endif
break;
@ -2387,17 +2387,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv)
switch (priv->config->base)
{
#ifdef CONFIG_STM32H5_I2C1
#ifdef CONFIG_STM32_I2C1
case STM32_I2C1_BASE:
# if defined(CONFIG_STM32H5_I2C1_CLK_HSI)
# if defined(CONFIG_STM32_I2C1_CLK_HSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C1SEL_MASK,
RCC_CCIPR4_I2C1SEL_HSIKERCK);
# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI)
# elif defined(CONFIG_STM32_I2C1_CLK_CSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C1SEL_MASK,
RCC_CCIPR4_I2C1SEL_CSIKERCK);
# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1)
# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C1SEL_MASK,
RCC_CCIPR4_I2C1SEL_RCCPCLK1);
@ -2408,17 +2408,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv)
# endif
break;
#endif
#ifdef CONFIG_STM32H5_I2C2
#ifdef CONFIG_STM32_I2C2
case STM32_I2C2_BASE:
# if defined(CONFIG_STM32H5_I2C2_CLK_HSI)
# if defined(CONFIG_STM32_I2C2_CLK_HSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C2SEL_MASK,
RCC_CCIPR4_I2C2SEL_HSIKERCK);
# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI)
# elif defined(CONFIG_STM32_I2C2_CLK_CSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C2SEL_MASK,
RCC_CCIPR4_I2C2SEL_CSIKERCK);
# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1)
# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C2SEL_MASK,
RCC_CCIPR4_I2C2SEL_PCLK1);
@ -2429,17 +2429,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv)
# endif
break;
#endif
#ifdef CONFIG_STM32H5_I2C3
#ifdef CONFIG_STM32_I2C3
case STM32_I2C3_BASE:
# if defined(CONFIG_STM32H5_I2C3_CLK_HSI)
# if defined(CONFIG_STM32_I2C3_CLK_HSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C3SEL_MASK,
RCC_CCIPR4_I2C3SEL_HSIKERCK);
# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI)
# elif defined(CONFIG_STM32_I2C3_CLK_CSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C3SEL_MASK,
RCC_CCIPR4_I2C3SEL_CSIKERCK);
# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3)
# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C3SEL_MASK,
RCC_CCIPR4_I2C3SEL_PCLK3);
@ -2450,17 +2450,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv)
# endif
break;
#endif
#ifdef CONFIG_STM32H5_I2C4
#ifdef CONFIG_STM32_I2C4
case STM32_I2C4_BASE:
# if defined(CONFIG_STM32H5_I2C4_CLK_HSI)
# if defined(CONFIG_STM32_I2C4_CLK_HSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C4SEL_MASK,
RCC_CCIPR4_I2C4SEL_HSIKERCK);
# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI)
# elif defined(CONFIG_STM32_I2C4_CLK_CSI)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C4SEL_MASK,
RCC_CCIPR4_I2C4SEL_CSIKERCK);
# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3)
# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3)
modifyreg32(STM32_RCC_CCIPR4,
RCC_CCIPR4_I2C4SEL_MASK,
RCC_CCIPR4_I2C4SEL_PCLK3);
@ -3016,22 +3016,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port)
switch (port)
{
#ifdef CONFIG_STM32H5_I2C1
#ifdef CONFIG_STM32_I2C1
case 1:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
break;
#endif
#ifdef CONFIG_STM32H5_I2C2
#ifdef CONFIG_STM32_I2C2
case 2:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
break;
#endif
#ifdef CONFIG_STM32H5_I2C3
#ifdef CONFIG_STM32_I2C3
case 3:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
break;
#endif
#ifdef CONFIG_STM32H5_I2C4
#ifdef CONFIG_STM32_I2C4
case 4:
priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
break;
@ -3117,5 +3117,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev)
return OK;
}
#endif /* CONFIG_STM32H5_I2C1 || CONFIG_STM32H5_I2C2 || \
* CONFIG_STM32H5_I2C3 || CONFIG_STM32H5_I2C4 */
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \
* CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */

8
arch/arm/src/stm32h5/stm32_i2c.h
View file

@ -41,10 +41,10 @@
* seconds per byte value must be provided as well.
*/
#ifdef CONFIG_STM32H5_I2C_DYNTIMEO
# if CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32H5_I2C_DYNTIMEO because of CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32H5_I2C_DYNTIMEO
#ifdef CONFIG_STM32_I2C_DYNTIMEO
# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1
# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE"
# undef CONFIG_STM32_I2C_DYNTIMEO
# endif
#endif

70
arch/arm/src/stm32h5/stm32_icache.c
View file

@ -40,8 +40,8 @@
* Pre-processor Definitions
****************************************************************************/
#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\
defined(CONFIG_STM32H5_ICACHE_ERR_INT))
#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32_ICACHE_INV_INT) ||\
defined(CONFIG_STM32_ICACHE_ERR_INT))
/****************************************************************************
* Private Types
@ -82,51 +82,51 @@ static struct stm32_icache_s icache1 =
.lock = SP_UNLOCKED,
};
#ifdef CONFIG_STM32H5_ICACHE_REGION0
#ifdef CONFIG_STM32_ICACHE_REGION0
static struct stm32_icache_region region0 =
{
.num = 0,
.baseaddr = CONFIG_STM32H5_ICACHE_REGION0_BADDR,
.rsize = CONFIG_STM32H5_ICACHE_REGION0_RSIZE,
.remapaddr = CONFIG_STM32H5_ICACHE_REGION0_REMAPADDR,
.mstsel = CONFIG_STM32H5_ICACHE_REGION0_MSTSEL,
.hburst = CONFIG_STM32H5_ICACHE_REGION0_HBURST,
.baseaddr = CONFIG_STM32_ICACHE_REGION0_BADDR,
.rsize = CONFIG_STM32_ICACHE_REGION0_RSIZE,
.remapaddr = CONFIG_STM32_ICACHE_REGION0_REMAPADDR,
.mstsel = CONFIG_STM32_ICACHE_REGION0_MSTSEL,
.hburst = CONFIG_STM32_ICACHE_REGION0_HBURST,
};
#endif
#ifdef CONFIG_STM32H5_ICACHE_REGION1
#ifdef CONFIG_STM32_ICACHE_REGION1
static struct stm32_icache_region region1 =
{
.num = 1,
.baseaddr = CONFIG_STM32H5_ICACHE_REGION1_BADDR,
.rsize = CONFIG_STM32H5_ICACHE_REGION1_RSIZE,
.remapaddr = CONFIG_STM32H5_ICACHE_REGION1_REMAPADDR,
.mstsel = CONFIG_STM32H5_ICACHE_REGION1_MSTSEL,
.hburst = CONFIG_STM32H5_ICACHE_REGION1_HBURST,
.baseaddr = CONFIG_STM32_ICACHE_REGION1_BADDR,
.rsize = CONFIG_STM32_ICACHE_REGION1_RSIZE,
.remapaddr = CONFIG_STM32_ICACHE_REGION1_REMAPADDR,
.mstsel = CONFIG_STM32_ICACHE_REGION1_MSTSEL,
.hburst = CONFIG_STM32_ICACHE_REGION1_HBURST,
};
#endif
#ifdef CONFIG_STM32H5_ICACHE_REGION2
#ifdef CONFIG_STM32_ICACHE_REGION2
static struct stm32_icache_region region2 =
{
.num = 2,
.baseaddr = CONFIG_STM32H5_ICACHE_REGION2_BADDR,
.rsize = CONFIG_STM32H5_ICACHE_REGION2_RSIZE,
.remapaddr = CONFIG_STM32H5_ICACHE_REGION2_REMAPADDR,
.mstsel = CONFIG_STM32H5_ICACHE_REGION2_MSTSEL,
.hburst = CONFIG_STM32H5_ICACHE_REGION2_HBURST,
.baseaddr = CONFIG_STM32_ICACHE_REGION2_BADDR,
.rsize = CONFIG_STM32_ICACHE_REGION2_RSIZE,
.remapaddr = CONFIG_STM32_ICACHE_REGION2_REMAPADDR,
.mstsel = CONFIG_STM32_ICACHE_REGION2_MSTSEL,
.hburst = CONFIG_STM32_ICACHE_REGION2_HBURST,
};
#endif
#ifdef CONFIG_STM32H5_ICACHE_REGION3
#ifdef CONFIG_STM32_ICACHE_REGION3
static struct stm32_icache_region region3 =
{
.num = 3,
.baseaddr = CONFIG_STM32H5_ICACHE_REGION3_BADDR,
.rsize = CONFIG_STM32H5_ICACHE_REGION3_RSIZE,
.remapaddr = CONFIG_STM32H5_ICACHE_REGION3_REMAPADDR,
.mstsel = CONFIG_STM32H5_ICACHE_REGION3_MSTSEL,
.hburst = CONFIG_STM32H5_ICACHE_REGION3_HBURST,
.baseaddr = CONFIG_STM32_ICACHE_REGION3_BADDR,
.rsize = CONFIG_STM32_ICACHE_REGION3_RSIZE,
.remapaddr = CONFIG_STM32_ICACHE_REGION3_REMAPADDR,
.mstsel = CONFIG_STM32_ICACHE_REGION3_MSTSEL,
.hburst = CONFIG_STM32_ICACHE_REGION3_HBURST,
};
#endif
@ -235,7 +235,7 @@ void stm32_icache_initialize(void)
/* Set associativity */
#ifdef CONFIG_STM32H5_ICACHE_DIRECT
#ifdef CONFIG_STM32_ICACHE_DIRECT
regval = getreg32(STM32_ICACHE_CR);
regval &= ~(ICACHE_CR_WAYSEL);
putreg32(regval, STM32_ICACHE_CR);
@ -246,23 +246,23 @@ void stm32_icache_initialize(void)
* Reset Monitors on Initialization
*/
#ifdef CONFIG_STM32H5_ICACHE_MONITOR_EN
#ifdef CONFIG_STM32_ICACHE_MONITOR_EN
stm32_icache_enable_monitors();
stm32_icache_reset_monitors();
#endif
/* Set up region configuration registers */
#ifdef CONFIG_STM32H5_ICACHE_REGION0
#ifdef CONFIG_STM32_ICACHE_REGION0
stm32_icache_setup_region(region0);
#endif
#ifdef CONFIG_STM32H5_ICACHE_REGION1
#ifdef CONFIG_STM32_ICACHE_REGION1
stm32_icache_setup_region(region1);
#endif
#ifdef CONFIG_STM32H5_ICACHE_REGION2
#ifdef CONFIG_STM32_ICACHE_REGION2
stm32_icache_setup_region(region2);
#endif
#ifdef CONFIG_STM32H5_ICACHE_REGION3
#ifdef CONFIG_STM32_ICACHE_REGION3
stm32_icache_setup_region(region3);
#endif
@ -278,10 +278,10 @@ void stm32_icache_initialize(void)
if (ret == OK)
{
regval = 0;
# ifdef CONFIG_STM32H5_ICACHE_INV_INT
# ifdef CONFIG_STM32_ICACHE_INV_INT
regval |= ICACHE_IER_BSYENDIE;
# endif
# ifdef CONFIG_STM32H5_ICACHE_ERR_INT
# ifdef CONFIG_STM32_ICACHE_ERR_INT
regval |= ICACHE_IER_ERRIE;
# endif
stm32_icache_set_ier(regval);
@ -358,7 +358,7 @@ void stm32_invalidate_icache(void)
regval |= ICACHE_CR_CACHEINV;
putreg32(regval, STM32_ICACHE_CR);
#if defined(CONFIG_STM32H5_ICACHE_INV_INT)
#if defined(CONFIG_STM32_ICACHE_INV_INT)
stm32_icache_invf_interrupt();
#else
stm32_icache_invf_poll();

2
arch/arm/src/stm32h5/stm32_idle.c
View file

@ -92,7 +92,7 @@ void up_idle(void)
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();

20
arch/arm/src/stm32h5/stm32_lse.c
View file

@ -41,9 +41,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
@ -79,7 +79,7 @@ void stm32_rcc_enablelse(void)
bool writable;
uint32_t regval;
volatile int32_t timeout;
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
volatile int32_t drive = 0;
#endif
@ -105,19 +105,19 @@ void stm32_rcc_enablelse(void)
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. LSE must be OFF
* to change drive strength.
*/
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
regval |= CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
regval |= RCC_BDCR_LSEON;
#endif
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
do
{
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void)
}
}
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
if (timeout != 0)
{
break;
@ -154,7 +154,7 @@ void stm32_rcc_enablelse(void)
while (drive < sizeof(drives) / sizeof(drives[0]));
#endif
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */

92
arch/arm/src/stm32h5/stm32_pulsecount.c
View file

@ -182,10 +182,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev);
static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
const struct pulsecount_info_s *info);
static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev);
# ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
# ifdef CONFIG_STM32_TIM1_PULSECOUNT
static int pulsecount_tim1interrupt(int irq, void *context, void *arg);
# endif
# ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
# ifdef CONFIG_STM32_TIM8_PULSECOUNT
static int pulsecount_tim8interrupt(int irq, void *context, void *arg);
# endif
static uint8_t pulsecount_count(uint32_t count);
@ -212,107 +212,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static struct stm32_tim_s g_pulsecount1dev =
{
.channel =
{
.channel = CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL,
#if CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 1
.channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL,
#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH1OUT,
},
#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 2
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH2OUT,
},
#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 3
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH3OUT,
},
#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 4
#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM1_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM1_CH4OUT,
},
#endif
},
.timid = 1,
.timtype = TIMTYPE_TIM1,
.t_dts = CONFIG_STM32H5_TIM1_PULSECOUNT_TDTS,
.t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS,
.irq = STM32_IRQ_TIM1_UP,
.base = STM32_TIM1_BASE,
.pclk = TIMCLK_TIM1,
};
#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */
#endif /* CONFIG_STM32_TIM1_PULSECOUNT */
#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
static struct stm32_tim_s g_pulsecount8dev =
{
.channel =
{
.channel = CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL,
#if CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 1
.channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL,
#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH1OUT,
},
#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 2
#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH2OUT,
},
#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 3
#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH3OUT,
},
#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 4
#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4
.out1 =
{
.in_use = 1,
.pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE,
.pol = CONFIG_STM32_TIM8_PULSECOUNT_POL,
.idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE,
.pincfg = GPIO_TIM8_CH4OUT,
},
#endif
},
.timid = 8,
.timtype = TIMTYPE_TIM8,
.t_dts = CONFIG_STM32H5_TIM8_PULSECOUNT_TDTS,
.t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS,
.irq = STM32_IRQ_TIM8_UP,
.base = STM32_TIM8_BASE,
.pclk = TIMCLK_TIM8,
};
#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */
#endif /* CONFIG_STM32_TIM8_PULSECOUNT */
static const struct pulsecount_ops_s g_pulsecountops =
{
@ -323,7 +323,7 @@ static const struct pulsecount_ops_s g_pulsecountops =
.ioctl = pulsecount_ioctl,
};
#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static struct stm32_pulsecount_s g_pulsecount1lower =
{
.ops = &g_pulsecountops,
@ -331,7 +331,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower =
};
#endif
#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
static struct stm32_pulsecount_s g_pulsecount8lower =
{
.ops = &g_pulsecountops,
@ -1321,21 +1321,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
static int pulsecount_tim1interrupt(int irq, void *context, void *arg)
{
return pulsecount_interrupt((struct pulsecount_lowerhalf_s *)
&g_pulsecount1dev);
}
#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */
#endif /* CONFIG_STM32_TIM1_PULSECOUNT */
#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
static int pulsecount_tim8interrupt(int irq, void *context, void *arg)
{
return pulsecount_interrupt((struct pulsecount_lowerhalf_s *)
&g_pulsecount8dev);
}
#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */
#endif /* CONFIG_STM32_TIM8_PULSECOUNT */
/****************************************************************************
* Name: pulsecount_count
@ -1408,7 +1408,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on)
switch (priv->timid)
{
#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
{
regaddr = TIMRCCEN_TIM1;
@ -1417,7 +1417,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on)
}
#endif
#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
case 8:
{
regaddr = TIMRCCEN_TIM8;
@ -1600,7 +1600,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev)
switch (priv->timid)
{
#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
{
regaddr = TIMRCCRST_TIM1;
@ -1609,7 +1609,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev)
}
#endif
#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
case 8:
{
regaddr = TIMRCCRST_TIM8;
@ -1761,7 +1761,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer)
switch (timer)
{
#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT
#ifdef CONFIG_STM32_TIM1_PULSECOUNT
case 1:
{
lower = &g_pulsecount1lower;
@ -1771,7 +1771,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer)
}
#endif
#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT
#ifdef CONFIG_STM32_TIM8_PULSECOUNT
case 8:
{
lower = &g_pulsecount8lower;

614
arch/arm/src/stm32h5/stm32_pwm.c
View file

File diff suppressed because it is too large Load diff

522
arch/arm/src/stm32h5/stm32_pwm.h
View file

@ -39,7 +39,7 @@
#include "chip.h"
#ifdef CONFIG_STM32H5_PWM
#ifdef CONFIG_STM32_PWM
# include <arch/board/board.h>
# include "hardware/stm32_tim.h"
#endif
@ -57,41 +57,41 @@
* pulsed output signal generation.
*/
#ifndef CONFIG_STM32H5_TIM1
# undef CONFIG_STM32H5_TIM1_PWM
#ifndef CONFIG_STM32_TIM1
# undef CONFIG_STM32_TIM1_PWM
#endif
#ifndef CONFIG_STM32H5_TIM2
# undef CONFIG_STM32H5_TIM2_PWM
#ifndef CONFIG_STM32_TIM2
# undef CONFIG_STM32_TIM2_PWM
#endif
#ifndef CONFIG_STM32H5_TIM3
# undef CONFIG_STM32H5_TIM3_PWM
#ifndef CONFIG_STM32_TIM3
# undef CONFIG_STM32_TIM3_PWM
#endif
#ifndef CONFIG_STM32H5_TIM4
# undef CONFIG_STM32H5_TIM4_PWM
#ifndef CONFIG_STM32_TIM4
# undef CONFIG_STM32_TIM4_PWM
#endif
#ifndef CONFIG_STM32H5_TIM5
# undef CONFIG_STM32H5_TIM5_PWM
#ifndef CONFIG_STM32_TIM5
# undef CONFIG_STM32_TIM5_PWM
#endif
#ifndef CONFIG_STM32H5_TIM8
# undef CONFIG_STM32H5_TIM8_PWM
#ifndef CONFIG_STM32_TIM8
# undef CONFIG_STM32_TIM8_PWM
#endif
#ifndef CONFIG_STM32H5_TIM12
# undef CONFIG_STM32H5_TIM12_PWM
#ifndef CONFIG_STM32_TIM12
# undef CONFIG_STM32_TIM12_PWM
#endif
#ifndef CONFIG_STM32H5_TIM13
# undef CONFIG_STM32H5_TIM13_PWM
#ifndef CONFIG_STM32_TIM13
# undef CONFIG_STM32_TIM13_PWM
#endif
#ifndef CONFIG_STM32H5_TIM14
# undef CONFIG_STM32H5_TIM14_PWM
#ifndef CONFIG_STM32_TIM14
# undef CONFIG_STM32_TIM14_PWM
#endif
#ifndef CONFIG_STM32H5_TIM15
# undef CONFIG_STM32H5_TIM15_PWM
#ifndef CONFIG_STM32_TIM15
# undef CONFIG_STM32_TIM15_PWM
#endif
#ifndef CONFIG_STM32H5_TIM16
# undef CONFIG_STM32H5_TIM16_PWM
#ifndef CONFIG_STM32_TIM16
# undef CONFIG_STM32_TIM16_PWM
#endif
#ifndef CONFIG_STM32H5_TIM17
# undef CONFIG_STM32H5_TIM17_PWM
#ifndef CONFIG_STM32_TIM17
# undef CONFIG_STM32_TIM17_PWM
#endif
/* The basic timers (timer 6 and 7) are not capable of generating output
@ -103,38 +103,38 @@
/* Check if PWM support for any channel is enabled. */
#ifdef CONFIG_STM32H5_PWM
#ifdef CONFIG_STM32_PWM
/* PWM driver channels configuration */
#ifdef CONFIG_STM32H5_PWM_MULTICHAN
#ifdef CONFIG_STM32_PWM_MULTICHAN
#ifdef CONFIG_STM32H5_TIM1_CHANNEL1
#ifdef CONFIG_STM32_TIM1_CHANNEL1
# define PWM_TIM1_CHANNEL1 1
#else
# define PWM_TIM1_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CHANNEL2
#ifdef CONFIG_STM32_TIM1_CHANNEL2
# define PWM_TIM1_CHANNEL2 1
#else
# define PWM_TIM1_CHANNEL2 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CHANNEL3
#ifdef CONFIG_STM32_TIM1_CHANNEL3
# define PWM_TIM1_CHANNEL3 1
#else
# define PWM_TIM1_CHANNEL3 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CHANNEL4
#ifdef CONFIG_STM32_TIM1_CHANNEL4
# define PWM_TIM1_CHANNEL4 1
#else
# define PWM_TIM1_CHANNEL4 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CHANNEL5
#ifdef CONFIG_STM32_TIM1_CHANNEL5
# define PWM_TIM1_CHANNEL5 1
#else
# define PWM_TIM1_CHANNEL5 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CHANNEL6
#ifdef CONFIG_STM32_TIM1_CHANNEL6
# define PWM_TIM1_CHANNEL6 1
#else
# define PWM_TIM1_CHANNEL6 0
@ -143,22 +143,22 @@
PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \
PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6)
#ifdef CONFIG_STM32H5_TIM2_CHANNEL1
#ifdef CONFIG_STM32_TIM2_CHANNEL1
# define PWM_TIM2_CHANNEL1 1
#else
# define PWM_TIM2_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CHANNEL2
#ifdef CONFIG_STM32_TIM2_CHANNEL2
# define PWM_TIM2_CHANNEL2 1
#else
# define PWM_TIM2_CHANNEL2 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CHANNEL3
#ifdef CONFIG_STM32_TIM2_CHANNEL3
# define PWM_TIM2_CHANNEL3 1
#else
# define PWM_TIM2_CHANNEL3 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CHANNEL4
#ifdef CONFIG_STM32_TIM2_CHANNEL4
# define PWM_TIM2_CHANNEL4 1
#else
# define PWM_TIM2_CHANNEL4 0
@ -166,22 +166,22 @@
#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
#ifdef CONFIG_STM32H5_TIM3_CHANNEL1
#ifdef CONFIG_STM32_TIM3_CHANNEL1
# define PWM_TIM3_CHANNEL1 1
#else
# define PWM_TIM3_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CHANNEL2
#ifdef CONFIG_STM32_TIM3_CHANNEL2
# define PWM_TIM3_CHANNEL2 1
#else
# define PWM_TIM3_CHANNEL2 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CHANNEL3
#ifdef CONFIG_STM32_TIM3_CHANNEL3
# define PWM_TIM3_CHANNEL3 1
#else
# define PWM_TIM3_CHANNEL3 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CHANNEL4
#ifdef CONFIG_STM32_TIM3_CHANNEL4
# define PWM_TIM3_CHANNEL4 1
#else
# define PWM_TIM3_CHANNEL4 0
@ -189,22 +189,22 @@
#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
#ifdef CONFIG_STM32H5_TIM4_CHANNEL1
#ifdef CONFIG_STM32_TIM4_CHANNEL1
# define PWM_TIM4_CHANNEL1 1
#else
# define PWM_TIM4_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CHANNEL2
#ifdef CONFIG_STM32_TIM4_CHANNEL2
# define PWM_TIM4_CHANNEL2 1
#else
# define PWM_TIM4_CHANNEL2 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CHANNEL3
#ifdef CONFIG_STM32_TIM4_CHANNEL3
# define PWM_TIM4_CHANNEL3 1
#else
# define PWM_TIM4_CHANNEL3 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CHANNEL4
#ifdef CONFIG_STM32_TIM4_CHANNEL4
# define PWM_TIM4_CHANNEL4 1
#else
# define PWM_TIM4_CHANNEL4 0
@ -212,22 +212,22 @@
#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
#ifdef CONFIG_STM32H5_TIM5_CHANNEL1
#ifdef CONFIG_STM32_TIM5_CHANNEL1
# define PWM_TIM5_CHANNEL1 1
#else
# define PWM_TIM5_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CHANNEL2
#ifdef CONFIG_STM32_TIM5_CHANNEL2
# define PWM_TIM5_CHANNEL2 1
#else
# define PWM_TIM5_CHANNEL2 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CHANNEL3
#ifdef CONFIG_STM32_TIM5_CHANNEL3
# define PWM_TIM5_CHANNEL3 1
#else
# define PWM_TIM5_CHANNEL3 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CHANNEL4
#ifdef CONFIG_STM32_TIM5_CHANNEL4
# define PWM_TIM5_CHANNEL4 1
#else
# define PWM_TIM5_CHANNEL4 0
@ -235,32 +235,32 @@
#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
#ifdef CONFIG_STM32H5_TIM8_CHANNEL1
#ifdef CONFIG_STM32_TIM8_CHANNEL1
# define PWM_TIM8_CHANNEL1 1
#else
# define PWM_TIM8_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CHANNEL2
#ifdef CONFIG_STM32_TIM8_CHANNEL2
# define PWM_TIM8_CHANNEL2 1
#else
# define PWM_TIM8_CHANNEL2 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CHANNEL3
#ifdef CONFIG_STM32_TIM8_CHANNEL3
# define PWM_TIM8_CHANNEL3 1
#else
# define PWM_TIM8_CHANNEL3 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CHANNEL4
#ifdef CONFIG_STM32_TIM8_CHANNEL4
# define PWM_TIM8_CHANNEL4 1
#else
# define PWM_TIM8_CHANNEL4 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CHANNEL5
#ifdef CONFIG_STM32_TIM8_CHANNEL5
# define PWM_TIM8_CHANNEL5 1
#else
# define PWM_TIM8_CHANNEL5 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CHANNEL6
#ifdef CONFIG_STM32_TIM8_CHANNEL6
# define PWM_TIM8_CHANNEL6 1
#else
# define PWM_TIM8_CHANNEL6 0
@ -269,59 +269,59 @@
PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \
PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6)
#ifdef CONFIG_STM32H5_TIM12_CHANNEL1
#ifdef CONFIG_STM32_TIM12_CHANNEL1
# define PWM_TIM12_CHANNEL1 1
#else
# define PWM_TIM12_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM12_CHANNEL2
#ifdef CONFIG_STM32_TIM12_CHANNEL2
# define PWM_TIM12_CHANNEL2 1
#else
# define PWM_TIM12_CHANNEL2 0
#endif
#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2)
#ifdef CONFIG_STM32H5_TIM13_CHANNEL1
#ifdef CONFIG_STM32_TIM13_CHANNEL1
# define PWM_TIM13_CHANNEL1 1
#else
# define PWM_TIM13_CHANNEL1 0
#endif
#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1)
#ifdef CONFIG_STM32H5_TIM14_CHANNEL1
#ifdef CONFIG_STM32_TIM14_CHANNEL1
# define PWM_TIM14_CHANNEL1 1
#else
# define PWM_TIM14_CHANNEL1 0
#endif
#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1)
#ifdef CONFIG_STM32H5_TIM15_CHANNEL1
#ifdef CONFIG_STM32_TIM15_CHANNEL1
# define PWM_TIM15_CHANNEL1 1
#else
# define PWM_TIM15_CHANNEL1 0
#endif
#ifdef CONFIG_STM32H5_TIM15_CHANNEL2
#ifdef CONFIG_STM32_TIM15_CHANNEL2
# define PWM_TIM15_CHANNEL2 1
#else
# define PWM_TIM15_CHANNEL2 0
#endif
#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
#ifdef CONFIG_STM32H5_TIM16_CHANNEL1
#ifdef CONFIG_STM32_TIM16_CHANNEL1
# define PWM_TIM16_CHANNEL1 1
#else
# define PWM_TIM16_CHANNEL1 0
#endif
#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
#ifdef CONFIG_STM32H5_TIM17_CHANNEL1
#ifdef CONFIG_STM32_TIM17_CHANNEL1
# define PWM_TIM17_CHANNEL1 1
#else
# define PWM_TIM17_CHANNEL1 0
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#else /* !CONFIG_STM32H5_PWM_MULTICHAN */
#else /* !CONFIG_STM32_PWM_MULTICHAN */
/* For each timer that is enabled for PWM usage, we need the following
* additional configuration settings:
@ -338,425 +338,425 @@
* is not supported by this driver: Only one output channel per timer.
*/
#ifdef CONFIG_STM32H5_TIM1_PWM
# if !defined(CONFIG_STM32H5_TIM1_CHANNEL)
# error "CONFIG_STM32H5_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM1_CHANNEL == 1
# define CONFIG_STM32H5_TIM1_CHANNEL1 1
# define CONFIG_STM32H5_TIM1_CH1MODE CONFIG_STM32H5_TIM1_CHMODE
# elif CONFIG_STM32H5_TIM1_CHANNEL == 2
# define CONFIG_STM32H5_TIM1_CHANNEL2 1
# define CONFIG_STM32H5_TIM1_CH2MODE CONFIG_STM32H5_TIM1_CHMODE
# elif CONFIG_STM32H5_TIM1_CHANNEL == 3
# define CONFIG_STM32H5_TIM1_CHANNEL3 1
# define CONFIG_STM32H5_TIM1_CH3MODE CONFIG_STM32H5_TIM1_CHMODE
# elif CONFIG_STM32H5_TIM1_CHANNEL == 4
# define CONFIG_STM32H5_TIM1_CHANNEL4 1
# define CONFIG_STM32H5_TIM1_CH4MODE CONFIG_STM32H5_TIM1_CHMODE
#ifdef CONFIG_STM32_TIM1_PWM
# if !defined(CONFIG_STM32_TIM1_CHANNEL)
# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32_TIM1_CHANNEL == 1
# define CONFIG_STM32_TIM1_CHANNEL1 1
# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE
# elif CONFIG_STM32_TIM1_CHANNEL == 2
# define CONFIG_STM32_TIM1_CHANNEL2 1
# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE
# elif CONFIG_STM32_TIM1_CHANNEL == 3
# define CONFIG_STM32_TIM1_CHANNEL3 1
# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE
# elif CONFIG_STM32_TIM1_CHANNEL == 4
# define CONFIG_STM32_TIM1_CHANNEL4 1
# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM1_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
# endif
# define PWM_TIM1_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM2_PWM
# if !defined(CONFIG_STM32H5_TIM2_CHANNEL)
# error "CONFIG_STM32H5_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM2_CHANNEL == 1
# define CONFIG_STM32H5_TIM2_CHANNEL1 1
# define CONFIG_STM32H5_TIM2_CH1MODE CONFIG_STM32H5_TIM2_CHMODE
# elif CONFIG_STM32H5_TIM2_CHANNEL == 2
# define CONFIG_STM32H5_TIM2_CHANNEL2 1
# define CONFIG_STM32H5_TIM2_CH2MODE CONFIG_STM32H5_TIM2_CHMODE
# elif CONFIG_STM32H5_TIM2_CHANNEL == 3
# define CONFIG_STM32H5_TIM2_CHANNEL3 1
# define CONFIG_STM32H5_TIM2_CH3MODE CONFIG_STM32H5_TIM2_CHMODE
# elif CONFIG_STM32H5_TIM2_CHANNEL == 4
# define CONFIG_STM32H5_TIM2_CHANNEL4 1
# define CONFIG_STM32H5_TIM2_CH4MODE CONFIG_STM32H5_TIM2_CHMODE
#ifdef CONFIG_STM32_TIM2_PWM
# if !defined(CONFIG_STM32_TIM2_CHANNEL)
# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32_TIM2_CHANNEL == 1
# define CONFIG_STM32_TIM2_CHANNEL1 1
# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE
# elif CONFIG_STM32_TIM2_CHANNEL == 2
# define CONFIG_STM32_TIM2_CHANNEL2 1
# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE
# elif CONFIG_STM32_TIM2_CHANNEL == 3
# define CONFIG_STM32_TIM2_CHANNEL3 1
# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE
# elif CONFIG_STM32_TIM2_CHANNEL == 4
# define CONFIG_STM32_TIM2_CHANNEL4 1
# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM2_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
# endif
# define PWM_TIM2_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM3_PWM
# if !defined(CONFIG_STM32H5_TIM3_CHANNEL)
# error "CONFIG_STM32H5_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM3_CHANNEL == 1
# define CONFIG_STM32H5_TIM3_CHANNEL1 1
# define CONFIG_STM32H5_TIM3_CH1MODE CONFIG_STM32H5_TIM3_CHMODE
# elif CONFIG_STM32H5_TIM3_CHANNEL == 2
# define CONFIG_STM32H5_TIM3_CHANNEL2 1
# define CONFIG_STM32H5_TIM3_CH2MODE CONFIG_STM32H5_TIM3_CHMODE
# elif CONFIG_STM32H5_TIM3_CHANNEL == 3
# define CONFIG_STM32H5_TIM3_CHANNEL3 1
# define CONFIG_STM32H5_TIM3_CH3MODE CONFIG_STM32H5_TIM3_CHMODE
# elif CONFIG_STM32H5_TIM3_CHANNEL == 4
# define CONFIG_STM32H5_TIM3_CHANNEL4 1
# define CONFIG_STM32H5_TIM3_CH4MODE CONFIG_STM32H5_TIM3_CHMODE
#ifdef CONFIG_STM32_TIM3_PWM
# if !defined(CONFIG_STM32_TIM3_CHANNEL)
# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32_TIM3_CHANNEL == 1
# define CONFIG_STM32_TIM3_CHANNEL1 1
# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE
# elif CONFIG_STM32_TIM3_CHANNEL == 2
# define CONFIG_STM32_TIM3_CHANNEL2 1
# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE
# elif CONFIG_STM32_TIM3_CHANNEL == 3
# define CONFIG_STM32_TIM3_CHANNEL3 1
# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE
# elif CONFIG_STM32_TIM3_CHANNEL == 4
# define CONFIG_STM32_TIM3_CHANNEL4 1
# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM3_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
# endif
# define PWM_TIM3_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM4_PWM
# if !defined(CONFIG_STM32H5_TIM4_CHANNEL)
# error "CONFIG_STM32H5_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM4_CHANNEL == 1
# define CONFIG_STM32H5_TIM4_CHANNEL1 1
# define CONFIG_STM32H5_TIM4_CH1MODE CONFIG_STM32H5_TIM4_CHMODE
# elif CONFIG_STM32H5_TIM4_CHANNEL == 2
# define CONFIG_STM32H5_TIM4_CHANNEL2 1
# define CONFIG_STM32H5_TIM4_CH2MODE CONFIG_STM32H5_TIM4_CHMODE
# elif CONFIG_STM32H5_TIM4_CHANNEL == 3
# define CONFIG_STM32H5_TIM4_CHANNEL3 1
# define CONFIG_STM32H5_TIM4_CH3MODE CONFIG_STM32H5_TIM4_CHMODE
# elif CONFIG_STM32H5_TIM4_CHANNEL == 4
# define CONFIG_STM32H5_TIM4_CHANNEL4 1
# define CONFIG_STM32H5_TIM4_CH4MODE CONFIG_STM32H5_TIM4_CHMODE
#ifdef CONFIG_STM32_TIM4_PWM
# if !defined(CONFIG_STM32_TIM4_CHANNEL)
# error "CONFIG_STM32_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32_TIM4_CHANNEL == 1
# define CONFIG_STM32_TIM4_CHANNEL1 1
# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE
# elif CONFIG_STM32_TIM4_CHANNEL == 2
# define CONFIG_STM32_TIM4_CHANNEL2 1
# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE
# elif CONFIG_STM32_TIM4_CHANNEL == 3
# define CONFIG_STM32_TIM4_CHANNEL3 1
# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE
# elif CONFIG_STM32_TIM4_CHANNEL == 4
# define CONFIG_STM32_TIM4_CHANNEL4 1
# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM4_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL"
# endif
# define PWM_TIM4_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM5_PWM
# if !defined(CONFIG_STM32H5_TIM5_CHANNEL)
# error "CONFIG_STM32H5_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM5_CHANNEL == 1
# define CONFIG_STM32H5_TIM5_CHANNEL1 1
# define CONFIG_STM32H5_TIM5_CH1MODE CONFIG_STM32H5_TIM5_CHMODE
# elif CONFIG_STM32H5_TIM5_CHANNEL == 2
# define CONFIG_STM32H5_TIM5_CHANNEL2 1
# define CONFIG_STM32H5_TIM5_CH2MODE CONFIG_STM32H5_TIM5_CHMODE
# elif CONFIG_STM32H5_TIM5_CHANNEL == 3
# define CONFIG_STM32H5_TIM5_CHANNEL3 1
# define CONFIG_STM32H5_TIM5_CH3MODE CONFIG_STM32H5_TIM5_CHMODE
# elif CONFIG_STM32H5_TIM5_CHANNEL == 4
# define CONFIG_STM32H5_TIM5_CHANNEL4 1
# define CONFIG_STM32H5_TIM5_CH4MODE CONFIG_STM32H5_TIM5_CHMODE
#ifdef CONFIG_STM32_TIM5_PWM
# if !defined(CONFIG_STM32_TIM5_CHANNEL)
# error "CONFIG_STM32_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32_TIM5_CHANNEL == 1
# define CONFIG_STM32_TIM5_CHANNEL1 1
# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE
# elif CONFIG_STM32_TIM5_CHANNEL == 2
# define CONFIG_STM32_TIM5_CHANNEL2 1
# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE
# elif CONFIG_STM32_TIM5_CHANNEL == 3
# define CONFIG_STM32_TIM5_CHANNEL3 1
# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE
# elif CONFIG_STM32_TIM5_CHANNEL == 4
# define CONFIG_STM32_TIM5_CHANNEL4 1
# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM5_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL"
# endif
# define PWM_TIM5_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM8_PWM
# if !defined(CONFIG_STM32H5_TIM8_CHANNEL)
# error "CONFIG_STM32H5_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM8_CHANNEL == 1
# define CONFIG_STM32H5_TIM8_CHANNEL1 1
# define CONFIG_STM32H5_TIM8_CH1MODE CONFIG_STM32H5_TIM8_CHMODE
# elif CONFIG_STM32H5_TIM8_CHANNEL == 2
# define CONFIG_STM32H5_TIM8_CHANNEL2 1
# define CONFIG_STM32H5_TIM8_CH2MODE CONFIG_STM32H5_TIM8_CHMODE
# elif CONFIG_STM32H5_TIM8_CHANNEL == 3
# define CONFIG_STM32H5_TIM8_CHANNEL3 1
# define CONFIG_STM32H5_TIM8_CH3MODE CONFIG_STM32H5_TIM8_CHMODE
# elif CONFIG_STM32H5_TIM8_CHANNEL == 4
# define CONFIG_STM32H5_TIM8_CHANNEL4 1
# define CONFIG_STM32H5_TIM8_CH4MODE CONFIG_STM32H5_TIM8_CHMODE
#ifdef CONFIG_STM32_TIM8_PWM
# if !defined(CONFIG_STM32_TIM8_CHANNEL)
# error "CONFIG_STM32_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32_TIM8_CHANNEL == 1
# define CONFIG_STM32_TIM8_CHANNEL1 1
# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE
# elif CONFIG_STM32_TIM8_CHANNEL == 2
# define CONFIG_STM32_TIM8_CHANNEL2 1
# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE
# elif CONFIG_STM32_TIM8_CHANNEL == 3
# define CONFIG_STM32_TIM8_CHANNEL3 1
# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE
# elif CONFIG_STM32_TIM8_CHANNEL == 4
# define CONFIG_STM32_TIM8_CHANNEL4 1
# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM8_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL"
# endif
# define PWM_TIM8_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM12_PWM
# if !defined(CONFIG_STM32H5_TIM12_CHANNEL)
# error "CONFIG_STM32H5_TIM12_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM12_CHANNEL == 1
# define CONFIG_STM32H5_TIM12_CHANNEL1 1
# define CONFIG_STM32H5_TIM12_CH1MODE CONFIG_STM32H5_TIM12_CHMODE
# elif CONFIG_STM32H5_TIM12_CHANNEL == 2
# define CONFIG_STM32H5_TIM12_CHANNEL2 1
# define CONFIG_STM32H5_TIM12_CH2MODE CONFIG_STM32H5_TIM12_CHMODE
#ifdef CONFIG_STM32_TIM12_PWM
# if !defined(CONFIG_STM32_TIM12_CHANNEL)
# error "CONFIG_STM32_TIM12_CHANNEL must be provided"
# elif CONFIG_STM32_TIM12_CHANNEL == 1
# define CONFIG_STM32_TIM12_CHANNEL1 1
# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE
# elif CONFIG_STM32_TIM12_CHANNEL == 2
# define CONFIG_STM32_TIM12_CHANNEL2 1
# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM12_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL"
# endif
# define PWM_TIM12_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM13_PWM
# if !defined(CONFIG_STM32H5_TIM13_CHANNEL)
# error "CONFIG_STM32H5_TIM13_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM13_CHANNEL == 1
# define CONFIG_STM32H5_TIM13_CHANNEL1 1
# define CONFIG_STM32H5_TIM13_CH1MODE CONFIG_STM32H5_TIM13_CHMODE
#ifdef CONFIG_STM32_TIM13_PWM
# if !defined(CONFIG_STM32_TIM13_CHANNEL)
# error "CONFIG_STM32_TIM13_CHANNEL must be provided"
# elif CONFIG_STM32_TIM13_CHANNEL == 1
# define CONFIG_STM32_TIM13_CHANNEL1 1
# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM13_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL"
# endif
# define PWM_TIM13_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM14_PWM
# if !defined(CONFIG_STM32H5_TIM14_CHANNEL)
# error "CONFIG_STM32H5_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM14_CHANNEL == 1
# define CONFIG_STM32H5_TIM14_CHANNEL1 1
# define CONFIG_STM32H5_TIM14_CH1MODE CONFIG_STM32H5_TIM14_CHMODE
#ifdef CONFIG_STM32_TIM14_PWM
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32_TIM14_CHANNEL == 1
# define CONFIG_STM32_TIM14_CHANNEL1 1
# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM14_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
# endif
# define PWM_TIM14_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM15_PWM
# if !defined(CONFIG_STM32H5_TIM15_CHANNEL)
# error "CONFIG_STM32H5_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM15_CHANNEL == 1
# define CONFIG_STM32H5_TIM15_CHANNEL1 1
# define CONFIG_STM32H5_TIM15_CH1MODE CONFIG_STM32H5_TIM15_CHMODE
# elif CONFIG_STM32H5_TIM15_CHANNEL == 2
# define CONFIG_STM32H5_TIM15_CHANNEL2 1
# define CONFIG_STM32H5_TIM15_CH2MODE CONFIG_STM32H5_TIM15_CHMODE
#ifdef CONFIG_STM32_TIM15_PWM
# if !defined(CONFIG_STM32_TIM15_CHANNEL)
# error "CONFIG_STM32_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32_TIM15_CHANNEL == 1
# define CONFIG_STM32_TIM15_CHANNEL1 1
# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE
# elif CONFIG_STM32_TIM15_CHANNEL == 2
# define CONFIG_STM32_TIM15_CHANNEL2 1
# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM15_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL"
# endif
# define PWM_TIM15_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM16_PWM
# if !defined(CONFIG_STM32H5_TIM16_CHANNEL)
# error "CONFIG_STM32H5_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM16_CHANNEL == 1
# define CONFIG_STM32H5_TIM16_CHANNEL1 1
# define CONFIG_STM32H5_TIM16_CH1MODE CONFIG_STM32H5_TIM16_CHMODE
#ifdef CONFIG_STM32_TIM16_PWM
# if !defined(CONFIG_STM32_TIM16_CHANNEL)
# error "CONFIG_STM32_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32_TIM16_CHANNEL == 1
# define CONFIG_STM32_TIM16_CHANNEL1 1
# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM16_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL"
# endif
# define PWM_TIM16_NCHANNELS 1
#endif
#ifdef CONFIG_STM32H5_TIM17_PWM
# if !defined(CONFIG_STM32H5_TIM17_CHANNEL)
# error "CONFIG_STM32H5_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32H5_TIM17_CHANNEL == 1
# define CONFIG_STM32H5_TIM17_CHANNEL1 1
# define CONFIG_STM32H5_TIM17_CH1MODE CONFIG_STM32H5_TIM17_CHMODE
#ifdef CONFIG_STM32_TIM17_PWM
# if !defined(CONFIG_STM32_TIM17_CHANNEL)
# error "CONFIG_STM32_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32_TIM17_CHANNEL == 1
# define CONFIG_STM32_TIM17_CHANNEL1 1
# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE
# else
# error "Unsupported value of CONFIG_STM32H5_TIM17_CHANNEL"
# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL"
# endif
# define PWM_TIM17_NCHANNELS 1
#endif
#endif /* CONFIG_STM32H5_PWM_MULTICHAN */
#endif /* CONFIG_STM32_PWM_MULTICHAN */
#ifdef CONFIG_STM32H5_TIM1_CH1OUT
#ifdef CONFIG_STM32_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
#else
# define PWM_TIM1_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CH1NOUT
#ifdef CONFIG_STM32_TIM1_CH1NOUT
# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT
#else
# define PWM_TIM1_CH1NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CH2OUT
#ifdef CONFIG_STM32_TIM1_CH2OUT
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
#else
# define PWM_TIM1_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CH2NOUT
#ifdef CONFIG_STM32_TIM1_CH2NOUT
# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT
#else
# define PWM_TIM1_CH2NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CH3OUT
#ifdef CONFIG_STM32_TIM1_CH3OUT
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
#else
# define PWM_TIM1_CH3CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CH3NOUT
#ifdef CONFIG_STM32_TIM1_CH3NOUT
# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT
#else
# define PWM_TIM1_CH3NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM1_CH4OUT
#ifdef CONFIG_STM32_TIM1_CH4OUT
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
#else
# define PWM_TIM1_CH4CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CH1OUT
#ifdef CONFIG_STM32_TIM2_CH1OUT
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
#else
# define PWM_TIM2_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CH2OUT
#ifdef CONFIG_STM32_TIM2_CH2OUT
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
#else
# define PWM_TIM2_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CH3OUT
#ifdef CONFIG_STM32_TIM2_CH3OUT
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
#else
# define PWM_TIM2_CH3CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM2_CH4OUT
#ifdef CONFIG_STM32_TIM2_CH4OUT
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
#else
# define PWM_TIM2_CH4CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CH1OUT
#ifdef CONFIG_STM32_TIM3_CH1OUT
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
#else
# define PWM_TIM3_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CH2OUT
#ifdef CONFIG_STM32_TIM3_CH2OUT
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
#else
# define PWM_TIM3_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CH3OUT
#ifdef CONFIG_STM32_TIM3_CH3OUT
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
#else
# define PWM_TIM3_CH3CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM3_CH4OUT
#ifdef CONFIG_STM32_TIM3_CH4OUT
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
#else
# define PWM_TIM3_CH4CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CH1OUT
#ifdef CONFIG_STM32_TIM4_CH1OUT
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
#else
# define PWM_TIM4_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CH2OUT
#ifdef CONFIG_STM32_TIM4_CH2OUT
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
#else
# define PWM_TIM4_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CH3OUT
#ifdef CONFIG_STM32_TIM4_CH3OUT
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
#else
# define PWM_TIM4_CH3CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM4_CH4OUT
#ifdef CONFIG_STM32_TIM4_CH4OUT
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
#else
# define PWM_TIM4_CH4CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CH1OUT
#ifdef CONFIG_STM32_TIM5_CH1OUT
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
#else
# define PWM_TIM5_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CH2OUT
#ifdef CONFIG_STM32_TIM5_CH2OUT
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
#else
# define PWM_TIM5_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CH3OUT
#ifdef CONFIG_STM32_TIM5_CH3OUT
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
#else
# define PWM_TIM5_CH3CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM5_CH4OUT
#ifdef CONFIG_STM32_TIM5_CH4OUT
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
#else
# define PWM_TIM5_CH4CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH1OUT
#ifdef CONFIG_STM32_TIM8_CH1OUT
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
#else
# define PWM_TIM8_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH1NOUT
#ifdef CONFIG_STM32_TIM8_CH1NOUT
# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT
#else
# define PWM_TIM8_CH1NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH2OUT
#ifdef CONFIG_STM32_TIM8_CH2OUT
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
#else
# define PWM_TIM8_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH2NOUT
#ifdef CONFIG_STM32_TIM8_CH2NOUT
# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT
#else
# define PWM_TIM8_CH2NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH3OUT
#ifdef CONFIG_STM32_TIM8_CH3OUT
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
#else
# define PWM_TIM8_CH3CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH3NOUT
#ifdef CONFIG_STM32_TIM8_CH3NOUT
# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT
#else
# define PWM_TIM8_CH3NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM8_CH4OUT
#ifdef CONFIG_STM32_TIM8_CH4OUT
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
#else
# define PWM_TIM8_CH4CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM12_CH1OUT
#ifdef CONFIG_STM32_TIM12_CH1OUT
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
#else
# define PWM_TIM12_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM12_CH2OUT
#ifdef CONFIG_STM32_TIM12_CH2OUT
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
#else
# define PWM_TIM12_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM13_CH1OUT
#ifdef CONFIG_STM32_TIM13_CH1OUT
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
#else
# define PWM_TIM13_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM14_CH1OUT
#ifdef CONFIG_STM32_TIM14_CH1OUT
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
#else
# define PWM_TIM14_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM15_CH1OUT
#ifdef CONFIG_STM32_TIM15_CH1OUT
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
#else
# define PWM_TIM15_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM15_CH1NOUT
#ifdef CONFIG_STM32_TIM15_CH1NOUT
# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT
#else
# define PWM_TIM15_CH1NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM15_CH2OUT
#ifdef CONFIG_STM32_TIM15_CH2OUT
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
#else
# define PWM_TIM15_CH2CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM16_CH1OUT
#ifdef CONFIG_STM32_TIM16_CH1OUT
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
#else
# define PWM_TIM16_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM16_CH1NOUT
#ifdef CONFIG_STM32_TIM16_CH1NOUT
# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT
#else
# define PWM_TIM16_CH1NCFG 0
#endif
#ifdef CONFIG_STM32H5_TIM17_CH1OUT
#ifdef CONFIG_STM32_TIM17_CH1OUT
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
#else
# define PWM_TIM17_CH1CFG 0
#endif
#ifdef CONFIG_STM32H5_TIM17_CH1NOUT
#ifdef CONFIG_STM32_TIM17_CH1NOUT
# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT
#else
# define PWM_TIM17_CH1NCFG 0
@ -764,21 +764,21 @@
/* Complementary outputs support */
#if defined(CONFIG_STM32H5_TIM1_CH1NOUT) || defined(CONFIG_STM32H5_TIM1_CH2NOUT) || \
defined(CONFIG_STM32H5_TIM1_CH3NOUT)
#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \
defined(CONFIG_STM32_TIM1_CH3NOUT)
# define HAVE_TIM1_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32H5_TIM8_CH1NOUT) || defined(CONFIG_STM32H5_TIM8_CH2NOUT) || \
defined(CONFIG_STM32H5_TIM8_CH3NOUT)
#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \
defined(CONFIG_STM32_TIM8_CH3NOUT)
# define HAVE_TIM8_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32H5_TIM15_CH1NOUT)
#if defined(CONFIG_STM32_TIM15_CH1NOUT)
# define HAVE_TIM15_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32H5_TIM16_CH1NOUT)
#if defined(CONFIG_STM32_TIM16_CH1NOUT)
# define HAVE_TIM16_COMPLEMENTARY
#endif
#if defined(CONFIG_STM32H5_TIM17_CH1NOUT)
#if defined(CONFIG_STM32_TIM17_CH1NOUT)
# define HAVE_TIM17_COMPLEMENTARY
#endif
#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \
@ -789,7 +789,7 @@
/* Low-level ops helpers ****************************************************/
#ifdef CONFIG_STM32H5_PWM_LL_OPS
#ifdef CONFIG_STM32_PWM_LL_OPS
/* NOTE:
* low-level ops accept pwm_lowerhalf_s as first argument, but llops access
@ -925,7 +925,7 @@ enum stm32_pwm_output_e
#endif
};
#ifdef CONFIG_STM32H5_PWM_LL_OPS
#ifdef CONFIG_STM32_PWM_LL_OPS
/* This structure provides the publicly visible representation of the
* "lower-half" PWM driver structure.
@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s
#endif
};
#endif /* CONFIG_STM32H5_PWM_LL_OPS */
#endif /* CONFIG_STM32_PWM_LL_OPS */
/****************************************************************************
* Public Data
@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H5_PWM */
#endif /* CONFIG_STM32_PWM */
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_PWM_H */

108
arch/arm/src/stm32h5/stm32_qspi.c
View file

@ -55,11 +55,11 @@
#include "stm32_rcc.h"
#include "hardware/stm32_qspi.h"
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
#include "stm32_dma.h"
#endif
#ifdef CONFIG_STM32H5_QSPI1
#ifdef CONFIG_STM32_QSPI1
/****************************************************************************
* Pre-processor Definitions
@ -70,7 +70,7 @@
/* Check if QSPI debug is enabled */
#ifndef CONFIG_DEBUG_DMA
# undef CONFIG_STM32H5_QSPI_DMADEBUG
# undef CONFIG_STM32_QSPI_DMADEBUG
#endif
#define DMA_INITIAL 0
@ -83,7 +83,7 @@
/* Can't have both interrupt-driven QSPI and DMA QSPI */
#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) && defined(CONFIG_STM32H5_QSPI_DMA)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for QSPI"
#endif
@ -95,7 +95,7 @@
GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h
#endif
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
# ifdef DMAMAP_QUADSPI
@ -107,26 +107,26 @@
# define DMACHAN_QUADSPI DMAMAP_QUADSPI
# endif
# if defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_LOW)
# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW)
# define QSPI_DMA_PRIO DMA_SCR_PRILO
# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_MEDIUM)
# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM)
# define QSPI_DMA_PRIO DMA_SCR_PRIMED
# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_HIGH)
# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH)
# define QSPI_DMA_PRIO DMA_SCR_PRIHI
# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_VERYHIGH)
# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH)
# define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI
# else
# define QSPI_DMA_PRIO DMA_SCR_PRIMED
# endif
#endif /* CONFIG_STM32H5_QSPI_DMA */
#endif /* CONFIG_STM32_QSPI_DMA */
#ifndef STM32_SYSCLK_FREQUENCY
# error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY
#endif
#if !defined(CONFIG_STM32H5_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H5_QSPI_FLASH_SIZE
# error you must specify a positive flash size via CONFIG_STM32H5_QSPI_FLASH_SIZE
#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE
# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE
#endif
/* DMA timeout. The value is not critical; we just don't want the system to
@ -144,11 +144,11 @@
* QUADSPI clock defaults to HCLK.
*/
#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL)
#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL)
# error your board.h needs to define STM32_RCC_CCIPR4_OCTOSPI1SEL
#endif
#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_QSPI_FREQUENCY)
#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_QSPI_FREQUENCY)
# error your board.h needs to defined STM32_QSPI_FREQUENCY
#else
# define QSPI_CLK_FREQUENCY STM32_QSPI_FREQUENCY
@ -183,14 +183,14 @@ struct stm32_qspidev_s
mutex_t lock; /* Assures mutually exclusive access to QSPI */
bool memmap; /* TRUE: Controller is in memory mapped mode */
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
xcpt_t handler; /* Interrupt handler */
uint8_t irq; /* Interrupt number */
sem_t op_sem; /* Block until complete */
struct qspi_xctnspec_s *xctn; /* context of transaction in progress */
#endif
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
bool candma; /* DMA is supported */
sem_t dmawait; /* Used to wait for DMA completion */
int result; /* DMA result */
@ -200,11 +200,11 @@ struct stm32_qspidev_s
/* Debug stuff */
#ifdef CONFIG_STM32H5_QSPI_DMADEBUG
#ifdef CONFIG_STM32_QSPI_DMADEBUG
struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES];
#endif
#ifdef CONFIG_STM32H5_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
bool wrlast; /* Last was a write */
uint32_t addresslast; /* Last address */
uint32_t valuelast; /* Last value */
@ -240,7 +240,7 @@ struct qspi_xctnspec_s
uint8_t isddr; /* true if 'double data rate' */
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
uint8_t function; /* functional mode; to distinguish a read or write */
int8_t disposition; /* how it all turned out */
uint32_t idxnow; /* index into databuffer of current byte in transfer */
@ -253,7 +253,7 @@ struct qspi_xctnspec_s
/* Helpers */
#ifdef CONFIG_STM32H5_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr,
uint32_t value, uint32_t address);
#else
@ -280,16 +280,16 @@ static void qspi_dumpgpioconfig(const char *msg);
/* Interrupts */
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
static int qspi0_interrupt(int irq, void *context, void *arg);
#endif
/* DMA support */
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
# ifdef CONFIG_STM32H5_QSPI_DMADEBUG
# ifdef CONFIG_STM32_QSPI_DMADEBUG
# define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i])
static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv);
static void qspi_dma_sampledone(struct stm32_qspidev_s *priv);
@ -299,8 +299,8 @@ static void qspi_dma_sampledone(struct stm32_qspidev_s *priv);
# define qspi_dma_sampledone(s)
# endif
# ifndef CONFIG_STM32H5_QSPI_DMATHRESHOLD
# define CONFIG_STM32H5_QSPI_DMATHRESHOLD 4
# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD
# define CONFIG_STM32_QSPI_DMATHRESHOLD 4
# endif
#endif
@ -354,13 +354,13 @@ static struct stm32_qspidev_s g_qspi0dev =
},
.base = STM32_OCTOSPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
.handler = qspi0_interrupt,
.irq = STM32_IRQ_OCTOSPI1,
.op_sem = SEM_INITIALIZER(0),
#endif
.intf = 0,
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
.candma = true,
.dmawait = SEM_INITIALIZER(0),
#endif
@ -386,7 +386,7 @@ static struct stm32_qspidev_s g_qspi0dev =
*
****************************************************************************/
#ifdef CONFIG_STM32H5_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr,
uint32_t value, uint32_t address)
{
@ -438,7 +438,7 @@ static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv,
uint32_t address = priv->base + offset;
uint32_t value = getreg32(address);
#ifdef CONFIG_STM32H5_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
if (qspi_checkreg(priv, false, value, address))
{
spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value);
@ -461,7 +461,7 @@ static inline void qspi_putreg(struct stm32_qspidev_s *priv,
{
uint32_t address = priv->base + offset;
#ifdef CONFIG_STM32H5_QSPI_REGDEBUG
#ifdef CONFIG_STM32_QSPI_REGDEBUG
if (qspi_checkreg(priv, true, value, address))
{
spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value);
@ -583,7 +583,7 @@ static void qspi_dumpgpioconfig(const char *msg)
}
#endif
#ifdef CONFIG_STM32H5_QSPI_DMADEBUG
#ifdef CONFIG_STM32_QSPI_DMADEBUG
/****************************************************************************
* Name: qspi_dma_sampleinit
*
@ -797,7 +797,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
xctn->isddr = 0;
}
#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS)
xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CR_FMODE_INDWR :
CR_FMODE_INDRD;
xctn->disposition = - EIO;
@ -936,7 +936,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
xctn->isddr = 0;
#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS)
xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CR_FMODE_INDWR :
CR_FMODE_INDRD;
xctn->disposition = - EIO;
@ -1075,7 +1075,7 @@ static void qspi_ccrconfig(struct stm32_qspidev_s *priv,
}
}
#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS)
#if defined(CONFIG_STM32_QSPI_INTERRUPTS)
/****************************************************************************
* Name: qspi0_interrupt
*
@ -1298,7 +1298,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
return OK;
}
#elif defined(CONFIG_STM32H5_QSPI_DMA)
#elif defined(CONFIG_STM32_QSPI_DMA)
/****************************************************************************
* Name: qspi_dma_timeout
*
@ -1571,7 +1571,7 @@ static int qspi_memory_dma(struct stm32_qspidev_s *priv,
}
#endif
#if !defined(CONFIG_STM32H5_QSPI_INTERRUPTS)
#if !defined(CONFIG_STM32_QSPI_INTERRUPTS)
/****************************************************************************
* Name: qspi_receive_blocking
*
@ -2017,7 +2017,7 @@ static int qspi_command(struct qspi_dev_s *dev,
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
STM32_QUADSPI_FCR_OFFSET);
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* interrupt mode will need access to the transaction context */
priv->xctn = &xctn;
@ -2198,7 +2198,7 @@ static int qspi_memory(struct qspi_dev_s *dev,
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
STM32_QUADSPI_FCR_OFFSET);
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* interrupt mode will need access to the transaction context */
priv->xctn = &xctn;
@ -2257,11 +2257,11 @@ static int qspi_memory(struct qspi_dev_s *dev,
ret = xctn.disposition;
#elif defined(CONFIG_STM32H5_QSPI_DMA)
#elif defined(CONFIG_STM32_QSPI_DMA)
/* Can we perform DMA? Should we perform DMA? */
if (priv->candma &&
meminfo->buflen > CONFIG_STM32H5_QSPI_DMATHRESHOLD &&
meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD &&
IS_ALIGNED((uintptr_t)meminfo->buffer, 4) &&
IS_ALIGNED(meminfo->buflen, 4))
{
@ -2423,18 +2423,18 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv)
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE |
QSPI_CR_TOIE | QSPI_CR_MSEL | QSPI_CR_DMM);
#if defined(CONFIG_STM32H5_QSPI_MODE_BANK2)
#if defined(CONFIG_STM32_QSPI_MODE_BANK2)
regval |= QSPI_CR_MSEL;
#endif
#if defined(CONFIG_STM32H5_QSPI_MODE_DUAL)
#if defined(CONFIG_STM32_QSPI_MODE_DUAL)
regval |= QSPI_CR_DMM;
#endif
/* Configure QSPI FIFO Threshold */
regval &= ~(QSPI_CR_FTHRES_MASK);
regval |= ((CONFIG_STM32H5_QSPI_FIFO_THESHOLD - 1) <<
regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) <<
QSPI_CR_FTHRES_SHIFT);
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
@ -2460,10 +2460,10 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv)
QSPI_DCR1_CSHT_MASK |
QSPI_DCR1_DEVSIZE_MASK);
regval |= ((CONFIG_STM32H5_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT);
if (0 != CONFIG_STM32H5_QSPI_FLASH_SIZE)
regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT);
if (0 != CONFIG_STM32_QSPI_FLASH_SIZE)
{
unsigned int nsize = CONFIG_STM32H5_QSPI_FLASH_SIZE;
unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE;
int nlog2size = 31;
while ((nsize & 0x80000000) == 0)
@ -2569,7 +2569,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
{
/* Now perform one time initialization. */
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
/* Pre-allocate DMA channels. */
if (priv->candma)
@ -2583,7 +2583,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
}
#endif
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* Attach the interrupt handler */
ret = irq_attach(priv->irq, priv->handler, NULL);
@ -2609,7 +2609,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
priv->initialized = true;
priv->memmap = false;
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
up_enable_irq(priv->irq);
#endif
}
@ -2617,12 +2617,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf)
return &priv->qspi;
errout_with_irq:
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
irq_detach(priv->irq);
errout_with_dmach:
#endif
#ifdef CONFIG_STM32H5_QSPI_DMA
#ifdef CONFIG_STM32_QSPI_DMA
if (priv->dmach)
{
stm32_dmafree(priv->dmach);
@ -2688,7 +2688,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev,
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET);
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
/* Enable Timeout interrupt */
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
@ -2707,7 +2707,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev,
qspi_setupxctnfrommem(&xctn, meminfo);
#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS
#ifdef CONFIG_STM32_QSPI_INTERRUPTS
priv->xctn = NULL;
#endif
@ -2753,4 +2753,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev)
qspi_lock(dev, false);
}
#endif /* CONFIG_STM32H5_QSPI */
#endif /* CONFIG_STM32_QSPI */

4
arch/arm/src/stm32h5/stm32_qspi.h
View file

@ -33,7 +33,7 @@
#include "chip.h"
#ifdef CONFIG_STM32H5_QSPI1
#ifdef CONFIG_STM32_QSPI1
/****************************************************************************
* Pre-processor Definitions
@ -125,5 +125,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev);
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H5_QSPI */
#endif /* CONFIG_STM32_QSPI */
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_QSPI_H */

18
arch/arm/src/stm32h5/stm32_rcc.c
View file

@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
# endif
#endif
@ -66,7 +66,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
@ -101,7 +101,7 @@ static const uint32_t drives[4] =
*
****************************************************************************/
#if defined(CONFIG_STM32H5_PWR) && defined(CONFIG_STM32H5_RTC)
#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC)
static inline void rcc_resetbkp(void)
{
bool init_stat;
@ -166,7 +166,7 @@ static inline void rcc_resetbkp(void)
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -189,7 +189,7 @@ void stm32_clockconfig(void)
rcc_resetbkp();
#endif
#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
@ -223,7 +223,7 @@ void stm32_clockconfig(void)
* stm32_clockconfig()
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -238,7 +238,7 @@ void stm32_clockconfig(void)
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */

10
arch/arm/src/stm32h5/stm32_rcc.h
View file

@ -32,7 +32,7 @@
#include "arm_internal.h"
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H5XXXX)
#if defined(CONFIG_STM32_STM32H5XXXX)
# include "hardware/stm32_rcc.h"
#else
# error "Unsupported STM32H5 chip"
@ -126,7 +126,7 @@ static inline void stm32_mco2config(uint32_t source)
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
@ -149,7 +149,7 @@ void stm32_clockconfig(void);
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
@ -164,7 +164,7 @@ void stm32_board_clockconfig(void);
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void);
#endif
@ -181,7 +181,7 @@ void stm32_stdclockconfig(void);
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*

116
arch/arm/src/stm32h5/stm32_serial.c
View file

@ -84,7 +84,7 @@
/* Verify that DMA has been enabled and the DMA channel has been defined.
*/
#if !defined(CONFIG_STM32H5_DMA1) && !defined(CONFIG_STM32H5_DMA2)
#if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2)
# error STM32H5 Serial DMA requires one of DMA1 or DMA2 to be enabled
#endif
@ -110,19 +110,19 @@
* can be individually invalidated.
*/
# if !defined(CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE == 0
# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0
# define RXDMA_BUFFER_SIZE 32
# else
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# endif
#endif
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32H5_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32H5_PM_SERIAL_ACTIVITY 10
#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10
#endif
/* USART Unconfigure bits */
@ -142,7 +142,7 @@
* See stm32serial_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
@ -331,7 +331,7 @@ static const struct uart_ops_s g_uart_dma_ops =
/* I/O buffers */
#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE];
static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE];
# ifdef CONFIG_LPUART1_RXDMA
@ -339,7 +339,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_USART1_RXDMA
@ -347,7 +347,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_USART2_RXDMA
@ -355,7 +355,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
# ifdef CONFIG_USART3_RXDMA
@ -363,7 +363,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_UART4_RXDMA
@ -371,7 +371,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
# ifdef CONFIG_UART5_RXDMA
@ -379,7 +379,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER
#ifdef CONFIG_STM32_USART6_SERIALDRIVER
static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE];
static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE];
# ifdef CONFIG_USART6_RXDMA
@ -387,7 +387,7 @@ static char g_usart6rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H7_UART7_SERIALDRIVER
#ifdef CONFIG_STM32_UART7_SERIALDRIVER
static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE];
static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE];
# ifdef CONFIG_UART7_RXDMA
@ -419,7 +419,7 @@ static char g_usart11rxfifo[RXDMA_BUFFER_SIZE];
# endif
#endif
#ifdef CONFIG_STM32H12_UART12_SERIALDRIVER
#ifdef CONFIG_STM32_UART12_SERIALDRIVER
static char g_uart12rxbuffer[CONFIG_UART12_RXBUFSIZE];
static char g_uart12txbuffer[CONFIG_UART12_TXBUFSIZE];
# ifdef CONFIG_UART12_RXDMA
@ -429,7 +429,7 @@ static char g_uart12rxfifo[RXDMA_BUFFER_SIZE];
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
static struct stm32_serial_s g_lpuart1priv =
{
.dev =
@ -504,7 +504,7 @@ static struct stm32_serial_s g_lpuart1priv =
};
#endif
#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
static struct stm32_serial_s g_usart1priv =
{
.dev =
@ -581,7 +581,7 @@ static struct stm32_serial_s g_usart1priv =
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
static struct stm32_serial_s g_usart2priv =
{
.dev =
@ -658,7 +658,7 @@ static struct stm32_serial_s g_usart2priv =
/* This describes the state of the STM32 USART3 port. */
#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
static struct stm32_serial_s g_usart3priv =
{
.dev =
@ -735,7 +735,7 @@ static struct stm32_serial_s g_usart3priv =
/* This describes the state of the STM32 UART4 port. */
#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
static struct stm32_serial_s g_uart4priv =
{
.dev =
@ -812,7 +812,7 @@ static struct stm32_serial_s g_uart4priv =
/* This describes the state of the STM32 UART5 port. */
#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
static struct stm32_serial_s g_uart5priv =
{
.dev =
@ -889,7 +889,7 @@ static struct stm32_serial_s g_uart5priv =
/* This describes the state of the STM32 USART6 port. */
#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER
#ifdef CONFIG_STM32_USART6_SERIALDRIVER
static struct stm32_serial_s g_usart6priv =
{
.dev =
@ -966,7 +966,7 @@ static struct stm32_serial_s g_usart6priv =
/* This describes the state of the STM32 UART7 port. */
#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER
#ifdef CONFIG_STM32_UART7_SERIALDRIVER
static struct stm32_serial_s g_uart7priv =
{
.dev =
@ -1043,7 +1043,7 @@ static struct stm32_serial_s g_uart7priv =
/* This describes the state of the STM32 UART8 port. */
#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER
#ifdef CONFIG_STM32_UART8_SERIALDRIVER
static struct stm32_serial_s g_uart8priv =
{
.dev =
@ -1431,31 +1431,31 @@ static struct stm32_serial_s g_uart12priv =
static struct stm32_serial_s * const
g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] =
{
#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
[0] = &g_lpuart1priv,
#endif
#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
[1] = &g_usart1priv,
#endif
#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
[2] = &g_usart2priv,
#endif
#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
[3] = &g_usart3priv,
#endif
#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
[4] = &g_uart4priv,
#endif
#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
[5] = &g_uart5priv,
#endif
#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER
#ifdef CONFIG_STM32_USART6_SERIALDRIVER
[6] = &g_usart6priv,
#endif
#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER
#ifdef CONFIG_STM32_UART7_SERIALDRIVER
[7] = &g_uart7priv,
#endif
#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER
#ifdef CONFIG_STM32_UART8_SERIALDRIVER
[8] = &g_uart8priv,
#endif
#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER
@ -1652,7 +1652,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev)
/* This first implementation is for U[S]ARTs that support oversampling
* by 8 in additional to the standard oversampling by 16.
*/
#ifdef CONFIG_STM32H5_LPUART1
#ifdef CONFIG_STM32_LPUART1
if (priv->islpuart == true)
{
/* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */
@ -1738,7 +1738,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev)
priv->baud;
}
else
#endif /* CONFIG_STM32H5_LPUART1 */
#endif /* CONFIG_STM32_LPUART1 */
{
uint32_t usartdiv8;
@ -1847,7 +1847,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev)
regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
regval |= USART_CR3_RTSE;
@ -2051,55 +2051,55 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on)
{
default:
return;
#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER
#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER
case STM32_LPUART1_BASE:
rcc_en = RCC_APB3ENR_LPUART1EN ;
regaddr = STM32_RCC_APB3ENR;
break;
#endif
#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER
#ifdef CONFIG_STM32_USART1_SERIALDRIVER
case STM32_USART1_BASE:
rcc_en = RCC_APB2ENR_USART1EN ;
regaddr = STM32_RCC_APB2ENR;
break;
#endif
#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER
#ifdef CONFIG_STM32_USART2_SERIALDRIVER
case STM32_USART2_BASE:
rcc_en = RCC_APB1LENR_USART2EN;
regaddr = STM32_RCC_APB1LENR;
break;
#endif
#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER
#ifdef CONFIG_STM32_USART3_SERIALDRIVER
case STM32_USART3_BASE:
rcc_en = RCC_APB1LENR_USART3EN;
regaddr = STM32_RCC_APB1LENR;
break;
#endif
#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER
#ifdef CONFIG_STM32_UART4_SERIALDRIVER
case STM32_UART4_BASE:
rcc_en = RCC_APB1LENR_UART4EN;
regaddr = STM32_RCC_APB1LENR;
break;
#endif
#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER
#ifdef CONFIG_STM32_UART5_SERIALDRIVER
case STM32_UART5_BASE:
rcc_en = RCC_APB1LENR_UART5EN;
regaddr = STM32_RCC_APB1LENR;
break;
#endif
#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER
#ifdef CONFIG_STM32_USART6_SERIALDRIVER
case STM32_USART6_BASE:
rcc_en = RCC_APB1LENR_USART6EN;
regaddr = STM32_RCC_APB1LENR;
break;
#endif
#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER
#ifdef CONFIG_STM32_UART7_SERIALDRIVER
case STM32_UART7_BASE:
rcc_en = RCC_APB1LENR_UART7EN;
regaddr = STM32_RCC_APB1LENR;
break;
#endif
#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER
#ifdef CONFIG_STM32_UART8_SERIALDRIVER
case STM32_UART8_BASE:
rcc_en = RCC_APB1LENR_UART8EN;
regaddr = STM32_RCC_APB1LENR;
@ -2193,7 +2193,7 @@ static int stm32serial_setup(struct uart_dev_s *dev)
{
uint32_t config = priv->rts_gpio;
#ifdef CONFIG_STM32H5_FLOWCONTROL_BROKEN
#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN
/* Instead of letting hw manage this pin, we will bitbang */
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@ -2584,8 +2584,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg)
/* Report serial activity to the power management logic */
#if defined(CONFIG_PM) && CONFIG_STM32H5_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H5_PM_SERIAL_ACTIVITY);
#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0
pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY);
#endif
/* Loop until there are no characters to be transferred or,
@ -2834,7 +2834,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32H5_USART_SINGLEWIRE
#ifdef CONFIG_STM32_USART_SINGLEWIRE
case TIOCSSINGLEWIRE:
{
uint32_t cr1;
@ -2912,7 +2912,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32H5_USART_INVERT
#ifdef CONFIG_STM32_USART_INVERT
case TIOCSINVERT:
{
uint32_t cr1;
@ -2963,7 +2963,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif
#ifdef CONFIG_STM32H5_USART_SWAP
#ifdef CONFIG_STM32_USART_SWAP
case TIOCSSWAP:
{
uint32_t cr1;
@ -3100,8 +3100,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd,
break;
#endif /* CONFIG_SERIAL_TERMIOS */
#ifdef CONFIG_STM32H5_USART_BREAKS
# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT
#ifdef CONFIG_STM32_USART_BREAKS
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
{
irqstate_t flags;
@ -3343,7 +3343,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev,
(struct stm32_serial_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN)
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
{
/* Assert/de-assert nRTS set it high resume/stop sending */
@ -3699,7 +3699,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable)
}
# endif
# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT
# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
{
leave_critical_section(flags);
@ -4049,7 +4049,7 @@ void arm_serialinit(void)
#if CONSOLE_UART > 0
uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev);
#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* If not disabled, register the console UART to ttyS0 and exclude
* it from initializing it further down
*/
@ -4078,7 +4078,7 @@ void arm_serialinit(void)
continue;
}
#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING
#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING
/* Don't create a device for the console - we did that above */
if (g_uart_devs[i]->dev.isconsole)

184
arch/arm/src/stm32h5/stm32_spi.c
View file

@ -72,7 +72,7 @@
#include "stm32_gpio.h"
#include "stm32_spi.h"
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
#include "stm32_dma.h"
#endif
@ -82,9 +82,9 @@
# define SPI_MAX_KER_CK 125000000
#endif
#if defined(CONFIG_STM32H5_SPI1) || defined(CONFIG_STM32H5_SPI2) || \
defined(CONFIG_STM32H5_SPI3) || defined(CONFIG_STM32H5_SPI4) || \
defined(CONFIG_STM32H5_SPI5) || defined(CONFIG_STM32H5_SPI6)
#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \
defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \
defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6)
/****************************************************************************
* Pre-processor Definitions
@ -94,18 +94,18 @@
/* SPI interrupts */
#ifdef CONFIG_STM32H5_SPI_INTERRUPTS
#ifdef CONFIG_STM32_SPI_INTERRUPTS
# error "Interrupt driven SPI not yet supported"
#endif
/* Can't have both interrupt driven SPI and SPI DMA */
#if defined(CONFIG_STM32H5_SPI_INTERRUPTS) && defined(CONFIG_STM32H5_SPI_DMA)
#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA)
# error "Cannot enable both interrupt mode and DMA mode for SPI"
#endif
/* SPI DMA priority */
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
# if defined(CONFIG_SPI_DMAPRIO)
# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO
@ -142,39 +142,39 @@
# define SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32H5_SPI1_DMA_BUFFER) && \
CONFIG_STM32H5_SPI1_DMA_BUFFER > 0
# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI1_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \
CONFIG_STM32_SPI1_DMA_BUFFER > 0
# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER)
# define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32H5_SPI2_DMA_BUFFER) && \
CONFIG_STM32H5_SPI2_DMA_BUFFER > 0
# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI2_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \
CONFIG_STM32_SPI2_DMA_BUFFER > 0
# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER)
# define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32H5_SPI3_DMA_BUFFER) && \
CONFIG_STM32H5_SPI3_DMA_BUFFER > 0
# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI3_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \
CONFIG_STM32_SPI3_DMA_BUFFER > 0
# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER)
# define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32H5_SPI4_DMA_BUFFER) && \
CONFIG_STM32H5_SPI4_DMA_BUFFER > 0
# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI4_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \
CONFIG_STM32_SPI4_DMA_BUFFER > 0
# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER)
# define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
# if defined(CONFIG_STM32H5_SPI5_DMA_BUFFER) && \
CONFIG_STM32H5_SPI5_DMA_BUFFER > 0
# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI5_DMA_BUFFER)
# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \
CONFIG_STM32_SPI5_DMA_BUFFER > 0
# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER)
# define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
#if defined(CONFIG_STM32H5_SPI6_DMA_BUFFER) && \
CONFIG_STM32H5_SPI6_DMA_BUFFER > 0
# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI6_DMA_BUFFER)
#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \
CONFIG_STM32_SPI6_DMA_BUFFER > 0
# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER)
# define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN
# endif
@ -182,7 +182,7 @@
/* Kernel clock configuration */
#if defined(CONFIG_STM32H5_SPI1)
#if defined(CONFIG_STM32_SPI1)
# ifndef STM32_SPI1_FREQUENCY
# error Must define STM32_SPI1_FREQUENCY in board.h
# else
@ -195,7 +195,7 @@
# endif
#endif /* SPI1 */
#if defined(CONFIG_STM32H5_SPI2)
#if defined(CONFIG_STM32_SPI2)
# ifndef STM32_SPI2_FREQUENCY
# error Must define STM32_SPI2_FREQUENCY in board.h
# else
@ -208,7 +208,7 @@
# endif
#endif /* SPI2 */
#if defined(CONFIG_STM32H5_SPI3)
#if defined(CONFIG_STM32_SPI3)
# ifndef STM32_SPI3_FREQUENCY
# error Must define STM32_SPI3_FREQUENCY in board.h
# else
@ -221,7 +221,7 @@
# endif
#endif /* SPI3 */
#if defined(CONFIG_STM32H5_SPI1)
#if defined(CONFIG_STM32_SPI1)
# ifndef STM32_SPI1_FREQUENCY
# error Must define STM32_SPI1_FREQUENCY in board.h
# else
@ -234,7 +234,7 @@
# endif
#endif /* SPI1 */
#if defined(CONFIG_STM32H5_SPI5)
#if defined(CONFIG_STM32_SPI5)
# ifndef STM32_SPI5_FREQUENCY
# error Must define STM32_SPI5_FREQUENCY in board.h
# else
@ -247,7 +247,7 @@
# endif
#endif /* SPI5 */
#if defined(CONFIG_STM32H5_SPI6)
#if defined(CONFIG_STM32_SPI6)
# ifndef STM32_SPI6_FREQUENCY
# error Must define STM32_SPI6_FREQUENCY in board.h
# else
@ -278,7 +278,7 @@ struct stm32_spidev_s
uint32_t spibase; /* SPIn base address */
uint32_t spiclock; /* Clocking for the SPI module */
uint8_t spiirq; /* SPI IRQ number */
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
volatile uint8_t rxresult; /* Result of the RX DMA */
volatile uint8_t txresult; /* Result of the RX DMA */
#ifdef CONFIG_SPI_TRIGGER
@ -328,7 +328,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv);
/* DMA support */
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv);
static int spi_dmatxwait(struct stm32_spidev_s *priv);
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv);
@ -394,7 +394,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain,
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI1
#ifdef CONFIG_STM32_SPI1
static const struct spi_ops_s g_sp1iops =
{
.lock = spi_lock,
@ -443,7 +443,7 @@ static struct stm32_spidev_s g_spi1dev =
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_SPI1_FREQUENCY,
.spiirq = STM32_IRQ_SPI1,
#ifdef CONFIG_STM32H5_SPI1_DMA
#ifdef CONFIG_STM32_SPI1_DMA
.rxch = DMAMAP_SPI1_RX,
.txch = DMAMAP_SPI1_TX,
# if defined(SPI1_DMABUFSIZE_ADJUSTED)
@ -458,15 +458,15 @@ static struct stm32_spidev_s g_spi1dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32H5_SPI1_COMMTYPE
.config = CONFIG_STM32H5_SPI1_COMMTYPE,
#ifdef CONFIG_STM32_SPI1_COMMTYPE
.config = CONFIG_STM32_SPI1_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32H5_SPI1 */
#endif /* CONFIG_STM32_SPI1 */
#ifdef CONFIG_STM32H5_SPI2
#ifdef CONFIG_STM32_SPI2
static const struct spi_ops_s g_sp2iops =
{
.lock = spi_lock,
@ -515,7 +515,7 @@ static struct stm32_spidev_s g_spi2dev =
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_SPI2_FREQUENCY,
.spiirq = STM32_IRQ_SPI2,
#ifdef CONFIG_STM32H5_SPI2_DMA
#ifdef CONFIG_STM32_SPI2_DMA
.rxch = DMAMAP_SPI2_RX,
.txch = DMAMAP_SPI2_TX,
# if defined(SPI2_DMABUFSIZE_ADJUSTED)
@ -530,15 +530,15 @@ static struct stm32_spidev_s g_spi2dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32H5_SPI2_COMMTYPE
.config = CONFIG_STM32H5_SPI2_COMMTYPE,
#ifdef CONFIG_STM32_SPI2_COMMTYPE
.config = CONFIG_STM32_SPI2_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32H5_SPI2 */
#endif /* CONFIG_STM32_SPI2 */
#ifdef CONFIG_STM32H5_SPI3
#ifdef CONFIG_STM32_SPI3
static const struct spi_ops_s g_sp3iops =
{
.lock = spi_lock,
@ -587,7 +587,7 @@ static struct stm32_spidev_s g_spi3dev =
.spibase = STM32_SPI3_BASE,
.spiclock = STM32_SPI3_FREQUENCY,
.spiirq = STM32_IRQ_SPI3,
#ifdef CONFIG_STM32H5_SPI3_DMA
#ifdef CONFIG_STM32_SPI3_DMA
.rxch = DMAMAP_SPI3_RX,
.txch = DMAMAP_SPI3_TX,
# if defined(SPI3_DMABUFSIZE_ADJUSTED)
@ -602,15 +602,15 @@ static struct stm32_spidev_s g_spi3dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32H5_SPI3_COMMTYPE
.config = CONFIG_STM32H5_SPI3_COMMTYPE,
#ifdef CONFIG_STM32_SPI3_COMMTYPE
.config = CONFIG_STM32_SPI3_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32H5_SPI3 */
#endif /* CONFIG_STM32_SPI3 */
#ifdef CONFIG_STM32H5_SPI4
#ifdef CONFIG_STM32_SPI4
static const struct spi_ops_s g_sp4iops =
{
.lock = spi_lock,
@ -659,7 +659,7 @@ static struct stm32_spidev_s g_spi4dev =
.spibase = STM32_SPI4_BASE,
.spiclock = STM32_SPI4_FREQUENCY,
.spiirq = STM32_IRQ_SPI4,
#ifdef CONFIG_STM32H5_SPI4_DMA
#ifdef CONFIG_STM32_SPI4_DMA
.rxch = DMAMAP_SPI4_RX,
.txch = DMAMAP_SPI4_TX,
# if defined(SPI4_DMABUFSIZE_ADJUSTED)
@ -674,15 +674,15 @@ static struct stm32_spidev_s g_spi4dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32H5_SPI4_COMMTYPE
.config = CONFIG_STM32H5_SPI4_COMMTYPE,
#ifdef CONFIG_STM32_SPI4_COMMTYPE
.config = CONFIG_STM32_SPI4_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32H5_SPI4 */
#endif /* CONFIG_STM32_SPI4 */
#ifdef CONFIG_STM32H5_SPI5
#ifdef CONFIG_STM32_SPI5
static const struct spi_ops_s g_sp5iops =
{
.lock = spi_lock,
@ -731,7 +731,7 @@ static struct stm32_spidev_s g_spi5dev =
.spibase = STM32_SPI5_BASE,
.spiclock = STM32_SPI5_FREQUENCY,
.spiirq = STM32_IRQ_SPI5,
#ifdef CONFIG_STM32H5_SPI5_DMA
#ifdef CONFIG_STM32_SPI5_DMA
.rxch = DMAMAP_SPI5_RX,
.txch = DMAMAP_SPI5_TX,
# if defined(SPI5_DMABUFSIZE_ADJUSTED)
@ -746,15 +746,15 @@ static struct stm32_spidev_s g_spi5dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32H5_SPI5_COMMTYPE
.config = CONFIG_STM32H5_SPI5_COMMTYPE,
#ifdef CONFIG_STM32_SPI5_COMMTYPE
.config = CONFIG_STM32_SPI5_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32H5_SPI5 */
#endif /* CONFIG_STM32_SPI5 */
#ifdef CONFIG_STM32H5_SPI6
#ifdef CONFIG_STM32_SPI6
static const struct spi_ops_s g_sp6iops =
{
.lock = spi_lock,
@ -804,7 +804,7 @@ static struct stm32_spidev_s g_spi6dev =
.spibase = STM32_SPI6_BASE,
.spiclock = STM32_SPI6_FREQUENCY,
.spiirq = STM32_IRQ_SPI6,
#ifdef CONFIG_STM32H5_SPI6_DMA
#ifdef CONFIG_STM32_SPI6_DMA
.rxch = DMAMAP_SPI6_RX,
.txch = DMAMAP_SPI6_TX,
# if defined(SPI6_DMABUFSIZE_ADJUSTED)
@ -819,13 +819,13 @@ static struct stm32_spidev_s g_spi6dev =
#ifdef CONFIG_PM
.pm_cb.prepare = spi_pm_prepare,
#endif
#ifdef CONFIG_STM32H5_SPI6_COMMTYPE
.config = CONFIG_STM32H5_SPI6_COMMTYPE,
#ifdef CONFIG_STM32_SPI6_COMMTYPE
.config = CONFIG_STM32_SPI6_COMMTYPE,
#else
.config = FULL_DUPLEX,
#endif
};
#endif /* CONFIG_STM32H5_SPI6 */
#endif /* CONFIG_STM32_SPI6 */
/****************************************************************************
* Private Functions
@ -1147,7 +1147,7 @@ static int spi_interrupt(int irq, void *context, void *arg)
spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0);
/* Set result and release wait semaphore */
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
priv->txresult = 0x80;
nxsem_post(&priv->txsem);
#endif
@ -1164,7 +1164,7 @@ static int spi_interrupt(int irq, void *context, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmarxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -1204,7 +1204,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static int spi_dmatxwait(struct stm32_spidev_s *priv)
{
int ret;
@ -1253,7 +1253,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
{
nxsem_post(&priv->rxsem);
@ -1268,7 +1268,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg;
@ -1288,7 +1288,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxsetup(struct stm32_spidev_s *priv,
void *rxbuffer, void *rxdummy,
size_t nwords, stm32_dmacfg_t *dmacfg)
@ -1350,7 +1350,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxsetup(struct stm32_spidev_s *priv,
const void *txbuffer, const void *txdummy,
size_t nwords, stm32_dmacfg_t *dmacfg)
@ -1410,7 +1410,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmarxstart(struct stm32_spidev_s *priv)
{
/* Can't receive in tx only mode */
@ -1434,7 +1434,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv)
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_dmatxstart(struct stm32_spidev_s *priv)
{
/* Can't transmit in rx only mode */
@ -1991,9 +1991,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
*
****************************************************************************/
#if !defined(CONFIG_STM32H5_SPI_DMA) || defined(CONFIG_STM32H5_DMACAPABLE) || \
defined(CONFIG_STM32H5_SPI_DMATHRESHOLD)
#if !defined(CONFIG_STM32H5_SPI_DMA)
#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \
defined(CONFIG_STM32_SPI_DMATHRESHOLD)
#if !defined(CONFIG_STM32_SPI_DMA)
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
#else
@ -2082,8 +2082,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
}
}
#endif /* !CONFIG_STM32H5_SPI_DMA || CONFIG_STM32H5_DMACAPABLE ||
* CONFIG_STM32H5_SPI_DMATHRESHOLD
#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE ||
* CONFIG_STM32_SPI_DMATHRESHOLD
*/
/****************************************************************************
@ -2107,7 +2107,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
@ -2125,12 +2125,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords;
#ifdef CONFIG_STM32H5_SPI_DMATHRESHOLD
#ifdef CONFIG_STM32_SPI_DMATHRESHOLD
/* If this is a small SPI transfer, then let spi_exchange_nodma() do the
* work.
*/
if (nbytes <= CONFIG_STM32H5_SPI_DMATHRESHOLD)
if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD)
{
spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords);
return;
@ -2194,7 +2194,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg);
spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg);
#ifdef CONFIG_STM32H5_DMACAPABLE
#ifdef CONFIG_STM32_DMACAPABLE
/* Test for DMA capability of only callers buffers, internal buffers are
* guaranteed capable.
@ -2324,7 +2324,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
priv->trigarmed = false;
#endif
}
#endif /* CONFIG_STM32H5_SPI_DMA */
#endif /* CONFIG_STM32_SPI_DMA */
/****************************************************************************
* Name: spi_trigger
@ -2345,7 +2345,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
#ifdef CONFIG_SPI_TRIGGER
static int spi_trigger(struct spi_dev_s *dev)
{
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
if (!priv->trigarmed)
@ -2579,7 +2579,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv)
spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7);
#ifdef CONFIG_STM32H5_SPI_DMA
#ifdef CONFIG_STM32_SPI_DMA
/* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA
* channel. If the channel is not available, then stm32_dmachannel() will
* block and wait until the channel becomes available. WARNING: If you
@ -2661,7 +2661,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
struct stm32_spidev_s *priv = NULL;
irqstate_t flags = enter_critical_section();
#ifdef CONFIG_STM32H5_SPI1
#ifdef CONFIG_STM32_SPI1
if (bus == 1)
{
/* Select SPI1 */
@ -2686,7 +2686,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32H5_SPI2
#ifdef CONFIG_STM32_SPI2
if (bus == 2)
{
/* Select SPI2 */
@ -2711,7 +2711,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32H5_SPI3
#ifdef CONFIG_STM32_SPI3
if (bus == 3)
{
/* Select SPI3 */
@ -2736,7 +2736,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32H5_SPI4
#ifdef CONFIG_STM32_SPI4
if (bus == 4)
{
/* Select SPI4 */
@ -2761,7 +2761,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32H5_SPI5
#ifdef CONFIG_STM32_SPI5
if (bus == 5)
{
/* Select SPI5 */
@ -2786,7 +2786,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
else
#endif
#ifdef CONFIG_STM32H5_SPI6
#ifdef CONFIG_STM32_SPI6
if (bus == 6)
{
/* Select SPI6 */
@ -2819,6 +2819,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
return (struct spi_dev_s *)priv;
}
#endif /* CONFIG_STM32H5_SPI1 || CONFIG_STM32H5_SPI2 || CONFIG_STM32H5_SPI3 ||
* CONFIG_STM32H5_SPI4 || CONFIG_STM32H5_SPI5 || CONFIG_STM32H5_SPI6
#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 ||
* CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6
*/

24
arch/arm/src/stm32h5/stm32_spi.h
View file

@ -112,42 +112,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus);
*
****************************************************************************/
#ifdef CONFIG_STM32H5_SPI1
#ifdef CONFIG_STM32_SPI1
void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32H5_SPI2
#ifdef CONFIG_STM32_SPI2
void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32H5_SPI3
#ifdef CONFIG_STM32_SPI3
void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32H5_SPI4
#ifdef CONFIG_STM32_SPI4
void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32H5_SPI5
#ifdef CONFIG_STM32_SPI5
void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32H5_SPI6
#ifdef CONFIG_STM32_SPI6
void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid);
@ -175,32 +175,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32H5_SPI1
#ifdef CONFIG_STM32_SPI1
int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32H5_SPI2
#ifdef CONFIG_STM32_SPI2
int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32H5_SPI3
#ifdef CONFIG_STM32_SPI3
int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32H5_SPI4
#ifdef CONFIG_STM32_SPI4
int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32H5_SPI5
#ifdef CONFIG_STM32_SPI5
int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_STM32H5_SPI6
#ifdef CONFIG_STM32_SPI6
int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif

4
arch/arm/src/stm32h5/stm32_start.c
View file

@ -176,7 +176,7 @@ void __start(void)
*dest++ = *src++;
}
#ifdef CONFIG_STM32H5_SRAM2_INIT
#ifdef CONFIG_STM32_SRAM2_INIT
/* NOTE: this is optional because this may be inappropriate, especially
* if the memory is being used for it's battery backed purpose. In that
* case, the first-time initialization needs to be performed by the board
@ -225,7 +225,7 @@ void __start(void)
stm32_board_initialize();
showprogress('C');
#ifdef CONFIG_STM32H5_ICACHE
#ifdef CONFIG_STM32_ICACHE
stm32_enable_icache();
#endif
showprogress('G');

284
arch/arm/src/stm32h5/stm32_tim.c
View file

@ -72,77 +72,77 @@
* In any of these cases, the timer will not be used by this timer module.
*/
#if defined(CONFIG_STM32H5_TIM1_PWM) || defined (CONFIG_STM32H5_TIM1_ADC) || \
defined(CONFIG_STM32H5_TIM1_DAC) || defined(CONFIG_STM32H5_TIM1_QE)
# undef CONFIG_STM32H5_TIM1
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \
defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE)
# undef CONFIG_STM32_TIM1
#endif
#if defined(CONFIG_STM32H5_TIM2_PWM) || defined (CONFIG_STM32H5_TIM2_ADC) || \
defined(CONFIG_STM32H5_TIM2_DAC) || defined(CONFIG_STM32H5_TIM2_QE)
# undef CONFIG_STM32H5_TIM2
#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \
defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE)
# undef CONFIG_STM32_TIM2
#endif
#if defined(CONFIG_STM32H5_TIM3_PWM) || defined (CONFIG_STM32H5_TIM3_ADC) || \
defined(CONFIG_STM32H5_TIM3_DAC) || defined(CONFIG_STM32H5_TIM3_QE)
# undef CONFIG_STM32H5_TIM3
#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \
defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE)
# undef CONFIG_STM32_TIM3
#endif
#if defined(CONFIG_STM32H5_TIM4_PWM) || defined (CONFIG_STM32H5_TIM4_ADC) || \
defined(CONFIG_STM32H5_TIM4_DAC) || defined(CONFIG_STM32H5_TIM4_QE)
# undef CONFIG_STM32H5_TIM4
#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \
defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE)
# undef CONFIG_STM32_TIM4
#endif
#if defined(CONFIG_STM32H5_TIM5_PWM) || defined (CONFIG_STM32H5_TIM5_ADC) || \
defined(CONFIG_STM32H5_TIM5_DAC) || defined(CONFIG_STM32H5_TIM5_QE)
# undef CONFIG_STM32H5_TIM5
#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \
defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE)
# undef CONFIG_STM32_TIM5
#endif
#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32H5_TIM6_ADC) || \
defined(CONFIG_STM32H5_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE)
# undef CONFIG_STM32H5_TIM6
#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \
defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE)
# undef CONFIG_STM32_TIM6
#endif
#if defined(CONFIG_STM32H5_TIM7_PWM) || defined (CONFIG_STM32H5_TIM7_ADC) || \
defined(CONFIG_STM32H5_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE)
# undef CONFIG_STM32H5_TIM7
defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE)
# undef CONFIG_STM32_TIM7
#endif
#if defined(CONFIG_STM32H5_TIM8_PWM) || defined (CONFIG_STM32H5_TIM8_ADC) || \
defined(CONFIG_STM32H5_TIM8_DAC) || defined(CONFIG_STM32H5_TIM8_QE)
# undef CONFIG_STM32H5_TIM8
#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \
defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE)
# undef CONFIG_STM32_TIM8
#endif
#if defined(CONFIG_STM32H5_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \
defined(CONFIG_STM32H5_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE)
# undef CONFIG_STM32H5_TIM12
#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \
defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE)
# undef CONFIG_STM32_TIM12
#endif
#if defined(CONFIG_STM32H5_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \
defined(CONFIG_STM32H5_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE)
# undef CONFIG_STM32H5_TIM13
#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \
defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE)
# undef CONFIG_STM32_TIM13
#endif
#if defined(CONFIG_STM32H5_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \
defined(CONFIG_STM32H5_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE)
# undef CONFIG_STM32H5_TIM14
#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \
defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE)
# undef CONFIG_STM32_TIM14
#endif
#if defined(CONFIG_STM32H5_TIM15_PWM) || defined (CONFIG_STM32H5_TIM15_ADC) || \
#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \
defined(CONFIG_STM32H5_TIM15_DAC) || defined(CONFIG_STM32H5_TIM15_QE)
# undef CONFIG_STM32H5_TIM15
# undef CONFIG_STM32_TIM15
#endif
#if defined(CONFIG_STM32H5_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \
#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \
defined(CONFIG_STM32H5_TIM16_DAC) || defined(CONFIG_STM32H5_TIM16_QE)
# undef CONFIG_STM32H5_TIM16
# undef CONFIG_STM32_TIM16
#endif
#if defined(CONFIG_STM32H5_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \
#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \
defined(CONFIG_STM32H5_TIM17_DAC) || defined(CONFIG_STM32H5_TIM17_QE)
# undef CONFIG_STM32H5_TIM17
# undef CONFIG_STM32_TIM17
#endif
#if defined(CONFIG_STM32H5_TIM1)
#if defined(CONFIG_STM32_TIM1)
# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\
defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT)
@ -150,35 +150,35 @@
# endif
#endif
#if defined(CONFIG_STM32H5_TIM2)
#if defined(CONFIG_STM32_TIM2)
# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
# define HAVE_TIM2_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM3)
#if defined(CONFIG_STM32_TIM3)
# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
# define HAVE_TIM3_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM4)
#if defined(CONFIG_STM32_TIM4)
# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
# define HAVE_TIM4_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM5)
#if defined(CONFIG_STM32_TIM5)
# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
# define HAVE_TIM5_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM8)
#if defined(CONFIG_STM32_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\
defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT)
@ -186,37 +186,37 @@
# endif
#endif
#if defined(CONFIG_STM32H5_TIM12)
#if defined(CONFIG_STM32_TIM12)
# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)
# define HAVE_TIM12_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM13)
#if defined(CONFIG_STM32_TIM13)
# if defined(GPIO_TIM13_CH1OUT)
# define HAVE_TIM13_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM14)
#if defined(CONFIG_STM32_TIM14)
# if defined(GPIO_TIM14_CH1OUT)
# define HAVE_TIM14_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM15)
#if defined(CONFIG_STM32_TIM15)
# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)
# define HAVE_TIM15_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM16)
#if defined(CONFIG_STM32_TIM16)
# if defined(GPIO_TIM16_CH1OUT)
# define HAVE_TIM16_GPIOCONFIG 1
# endif
#endif
#if defined(CONFIG_STM32H5_TIM17)
#if defined(CONFIG_STM32_TIM17)
# if defined(GPIO_TIM17_CH1OUT)
# define HAVE_TIM17_GPIOCONFIG 1
# endif
@ -226,13 +226,13 @@
* intended for some other purpose.
*/
#if defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \
defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \
defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \
defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \
defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \
defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \
defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17)
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \
defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \
defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)
/****************************************************************************
* Private Types
@ -307,7 +307,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops =
.checkint = &stm32_tim_checkint,
};
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
struct stm32_tim_priv_s stm32_tim1_priv =
{
.ops = &stm32_tim_ops,
@ -315,7 +315,7 @@ struct stm32_tim_priv_s stm32_tim1_priv =
.base = STM32_TIM1_BASE,
};
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
.ops = &stm32_tim_ops,
@ -324,7 +324,7 @@ struct stm32_tim_priv_s stm32_tim2_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv =
{
.ops = &stm32_tim_ops,
@ -333,7 +333,7 @@ struct stm32_tim_priv_s stm32_tim3_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv =
{
.ops = &stm32_tim_ops,
@ -342,7 +342,7 @@ struct stm32_tim_priv_s stm32_tim4_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv =
{
.ops = &stm32_tim_ops,
@ -351,7 +351,7 @@ struct stm32_tim_priv_s stm32_tim5_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
.ops = &stm32_tim_ops,
@ -360,7 +360,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
.ops = &stm32_tim_ops,
@ -369,7 +369,7 @@ struct stm32_tim_priv_s stm32_tim7_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv =
{
.ops = &stm32_tim_ops,
@ -378,7 +378,7 @@ struct stm32_tim_priv_s stm32_tim8_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
struct stm32_tim_priv_s stm32_tim12_priv =
{
.ops = &stm32_tim_ops,
@ -387,7 +387,7 @@ struct stm32_tim_priv_s stm32_tim12_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
struct stm32_tim_priv_s stm32_tim13_priv =
{
.ops = &stm32_tim_ops,
@ -396,7 +396,7 @@ struct stm32_tim_priv_s stm32_tim13_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
struct stm32_tim_priv_s stm32_tim14_priv =
{
.ops = &stm32_tim_ops,
@ -405,7 +405,7 @@ struct stm32_tim_priv_s stm32_tim14_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
struct stm32_tim_priv_s stm32_tim15_priv =
{
.ops = &stm32_tim_ops,
@ -414,7 +414,7 @@ struct stm32_tim_priv_s stm32_tim15_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
struct stm32_tim_priv_s stm32_tim16_priv =
{
.ops = &stm32_tim_ops,
@ -423,7 +423,7 @@ struct stm32_tim_priv_s stm32_tim16_priv =
};
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
struct stm32_tim_priv_s stm32_tim17_priv =
{
.ops = &stm32_tim_ops,
@ -514,12 +514,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if defined(CONFIG_STM32H5_TIM2)
#if defined(CONFIG_STM32_TIM2)
case STM32_TIM2_BASE:
return 32;
#endif
#if defined(CONFIG_STM32H5_TIM5)
#if defined(CONFIG_STM32_TIM5)
case STM32_TIM5_BASE:
return 32;
#endif
@ -621,72 +621,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
freqin = STM32_APB2_TIM1_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
freqin = STM32_APB1_TIM2_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
freqin = STM32_APB1_TIM3_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
freqin = STM32_APB1_TIM4_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
freqin = STM32_APB1_TIM5_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
freqin = STM32_APB1_TIM6_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
freqin = STM32_APB1_TIM7_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
freqin = STM32_APB2_TIM8_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
case STM32_TIM12_BASE:
freqin = STM32_APB1_TIM12_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
freqin = STM32_APB1_TIM13_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
freqin = STM32_APB1_TIM14_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
freqin = STM32_APB2_TIM15_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
freqin = STM32_APB2_TIM16_CLKIN;
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
freqin = STM32_APB2_TIM17_CLKIN;
break;
@ -740,72 +740,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1_UP;
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
vectorno = STM32_IRQ_TIM4;
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
vectorno = STM32_IRQ_TIM5;
break;
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8_UP;
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
case STM32_TIM12_BASE:
vectorno = STM32_IRQ_TIM12;
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
vectorno = STM32_IRQ_TIM13;
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
vectorno = STM32_IRQ_TIM14;
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
vectorno = STM32_IRQ_TIM15;
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
vectorno = STM32_IRQ_TIM16;
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
vectorno = STM32_IRQ_TIM17;
break;
@ -1011,7 +1011,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
@ -1044,7 +1044,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
@ -1073,7 +1073,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
@ -1102,7 +1102,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
@ -1131,7 +1131,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
@ -1160,7 +1160,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
@ -1194,7 +1194,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
case STM32_TIM12_BASE:
switch (channel)
{
@ -1213,7 +1213,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
switch (channel)
{
@ -1227,7 +1227,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
switch (channel)
{
@ -1242,7 +1242,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
switch (channel)
{
@ -1261,7 +1261,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
switch (channel)
{
@ -1275,7 +1275,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
switch (channel)
{
@ -1359,85 +1359,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
case 12:
dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
case 13:
dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
case 14:
dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
@ -1469,72 +1469,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
case STM32_TIM12_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
case STM32_TIM13_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
case STM32_TIM14_BASE:
modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
case STM32_TIM15_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
case STM32_TIM16_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
case STM32_TIM17_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
break;
@ -1550,4 +1550,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev)
return OK;
}
#endif /* defined(CONFIG_STM32H5_TIM1 || ... || TIM17) */
#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */

70
arch/arm/src/stm32h5/stm32_tim_lowerhalf.c
View file

@ -58,13 +58,13 @@
#include "stm32_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \
defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \
defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \
defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \
defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \
defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \
defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17))
(defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \
defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \
defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \
defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \
defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \
defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17))
/****************************************************************************
* Pre-processor Definitions
@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops =
.ioctl = NULL,
};
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
static struct stm32_lowerhalf_s g_tim12_lowerhalf =
{
.ops = &g_timer_ops,
@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
static struct stm32_lowerhalf_s g_tim13_lowerhalf =
{
.ops = &g_timer_ops,
@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
static struct stm32_lowerhalf_s g_tim14_lowerhalf =
{
.ops = &g_timer_ops,
@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf =
};
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
@ -473,75 +473,75 @@ int stm32_timer_initialize(const char *devpath, int timer)
switch (timer)
{
#ifdef CONFIG_STM32H5_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
#ifdef CONFIG_STM32_TIM12
case 12:
lower = &g_tim12_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
#ifdef CONFIG_STM32_TIM13
case 13:
lower = &g_tim13_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
#ifdef CONFIG_STM32_TIM14
case 14:
lower = &g_tim14_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
#ifdef CONFIG_STM32_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
#ifdef CONFIG_STM32_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
#ifdef CONFIG_STM32_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;

182
arch/arm/src/stm32h5/stm32_uart.h
View file

@ -32,7 +32,7 @@
#include "chip.h"
#if defined(CONFIG_STM32H5_STM32H5XXXX)
#if defined(CONFIG_STM32_STM32H5XXXX)
# include "hardware/stm32_uart.h"
#else
# error "Unsupported STM32H5 chip"
@ -46,116 +46,116 @@
* device.
*/
#if !defined(CONFIG_STM32H5_HAVE_UART12)
# undef CONFIG_STM32H5_UART12
#if !defined(CONFIG_STM32_HAVE_UART12)
# undef CONFIG_STM32_UART12
#endif
#if !defined(CONFIG_STM32H5_HAVE_USART11)
# undef CONFIG_STM32H5_USART11
#if !defined(CONFIG_STM32_HAVE_USART11)
# undef CONFIG_STM32_USART11
#endif
#if !defined(CONFIG_STM32H5_HAVE_USART10)
# undef CONFIG_STM32H5_USART10
#if !defined(CONFIG_STM32_HAVE_USART10)
# undef CONFIG_STM32_USART10
#endif
#if !defined(CONFIG_STM32H5_HAVE_UART9)
# undef CONFIG_STM32H5_UART9
#if !defined(CONFIG_STM32_HAVE_UART9)
# undef CONFIG_STM32_UART9
#endif
#if !defined(CONFIG_STM32H5_HAVE_UART8)
# undef CONFIG_STM32H5_UART8
#if !defined(CONFIG_STM32_HAVE_UART8)
# undef CONFIG_STM32_UART8
#endif
#if !defined(CONFIG_STM32H5_HAVE_UART7)
# undef CONFIG_STM32H5_UART7
#if !defined(CONFIG_STM32_HAVE_UART7)
# undef CONFIG_STM32_UART7
#endif
#if !defined(CONFIG_STM32H5_HAVE_USART6)
# undef CONFIG_STM32H5_USART6
#if !defined(CONFIG_STM32_HAVE_USART6)
# undef CONFIG_STM32_USART6
#endif
#if !defined(CONFIG_STM32H5_HAVE_UART5)
# undef CONFIG_STM32H5_UART5
#if !defined(CONFIG_STM32_HAVE_UART5)
# undef CONFIG_STM32_UART5
#endif
#if !defined(CONFIG_STM32H5_HAVE_UART4)
# undef CONFIG_STM32H5_UART4
#if !defined(CONFIG_STM32_HAVE_UART4)
# undef CONFIG_STM32_UART4
#endif
#if !defined(CONFIG_STM32H5_HAVE_USART3)
# undef CONFIG_STM32H5_USART3
#if !defined(CONFIG_STM32_HAVE_USART3)
# undef CONFIG_STM32_USART3
#endif
#if !defined(CONFIG_STM32H5_HAVE_USART2)
# undef CONFIG_STM32H5_USART2
#if !defined(CONFIG_STM32_HAVE_USART2)
# undef CONFIG_STM32_USART2
#endif
#if !defined(CONFIG_STM32H5_HAVE_USART1)
# undef CONFIG_STM32H5_USART1
#if !defined(CONFIG_STM32_HAVE_USART1)
# undef CONFIG_STM32_USART1
#endif
#if !defined(CONFIG_STM32H5_HAVE_LPUART1)
# undef CONFIG_STM32H5_LPUART1
#if !defined(CONFIG_STM32_HAVE_LPUART1)
# undef CONFIG_STM32_LPUART1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32H5_LPUART1)
# undef CONFIG_STM32H5_LPUART1_SERIALDRIVER
# undef CONFIG_STM32H5_LPUART1_1WIREDRIVER
#if !defined(CONFIG_STM32_LPUART1)
# undef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_STM32_LPUART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_USART1)
# undef CONFIG_STM32H5_USART1_SERIALDRIVER
# undef CONFIG_STM32H5_USART1_1WIREDRIVER
#if !defined(CONFIG_STM32_USART1)
# undef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_STM32_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_USART2)
# undef CONFIG_STM32H5_USART2_SERIALDRIVER
# undef CONFIG_STM32H5_USART2_1WIREDRIVER
#if !defined(CONFIG_STM32_USART2)
# undef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_STM32_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_USART3)
# undef CONFIG_STM32H5_USART3_SERIALDRIVER
# undef CONFIG_STM32H5_USART3_1WIREDRIVER
#if !defined(CONFIG_STM32_USART3)
# undef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_STM32_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_UART4)
# undef CONFIG_STM32H5_UART4_SERIALDRIVER
# undef CONFIG_STM32H5_UART4_1WIREDRIVER
#if !defined(CONFIG_STM32_UART4)
# undef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_STM32_UART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_UART5)
# undef CONFIG_STM32H5_UART5_SERIALDRIVER
# undef CONFIG_STM32H5_UART5_1WIREDRIVER
#if !defined(CONFIG_STM32_UART5)
# undef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_STM32_UART5_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_USART6)
# undef CONFIG_STM32H5_USART6_SERIALDRIVER
# undef CONFIG_STM32H5_USART6_1WIREDRIVER
#if !defined(CONFIG_STM32_USART6)
# undef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_STM32_USART6_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_UART7)
# undef CONFIG_STM32H5_UART7_SERIALDRIVER
# undef CONFIG_STM32H5_UART7_1WIREDRIVER
#if !defined(CONFIG_STM32_UART7)
# undef CONFIG_STM32_UART7_SERIALDRIVER
# undef CONFIG_STM32_UART7_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_UART8)
# undef CONFIG_STM32H5_UART8_SERIALDRIVER
# undef CONFIG_STM32H5_UART8_1WIREDRIVER
#if !defined(CONFIG_STM32_UART8)
# undef CONFIG_STM32_UART8_SERIALDRIVER
# undef CONFIG_STM32_UART8_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_UART9)
#if !defined(CONFIG_STM32_UART9)
# undef CONFIG_STM32H5_UART9_SERIALDRIVER
# undef CONFIG_STM32H5_UART9_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_USART10)
#if !defined(CONFIG_STM32_USART10)
# undef CONFIG_STM32H5_USART10_SERIALDRIVER
# undef CONFIG_STM32H5_USART10_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_USART11)
#if !defined(CONFIG_STM32_USART11)
# undef CONFIG_STM32H5_USART11_SERIALDRIVER
# undef CONFIG_STM32H5_USART11_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32H5_UART12)
#if !defined(CONFIG_STM32_UART12)
# undef CONFIG_STM32H5_UART12_SERIALDRIVER
# undef CONFIG_STM32H5_UART12_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32H5_LPUART1) || defined(CONFIG_STM32H5_USART1) || \
defined(CONFIG_STM32H5_USART2) || defined(CONFIG_STM32H5_USART3) || \
defined(CONFIG_STM32H5_UART4) || defined(CONFIG_STM32H5_UART5) || \
defined(CONFIG_STM32H5_USART6) || defined(CONFIG_STM32H5_UART7) || \
defined(CONFIG_STM32H5_UART8) || defined(CONFIG_STM32H5_UART9) || \
defined(CONFIG_STM32H5_USART10) || defined(CONFIG_STM32H5_USART11) || \
#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \
defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) || \
defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \
defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \
defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \
defined(CONFIG_STM32H5_USART12)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER)
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -170,7 +170,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART1_SERIALDRIVER)
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -185,7 +185,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART2_SERIALDRIVER)
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
@ -200,7 +200,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART3_SERIALDRIVER)
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -215,7 +215,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART4_SERIALDRIVER)
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -230,7 +230,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART5_SERIALDRIVER)
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -245,7 +245,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 6
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART6_SERIALDRIVER)
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -260,7 +260,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 7
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART7_SERIALDRIVER)
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -275,7 +275,7 @@
# undef CONFIG_UART12_SERIAL_CONSOLE
# define CONSOLE_UART 8
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART8_SERIALDRIVER)
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
@ -381,39 +381,39 @@
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32H5_LPUART1_SERIALDRIVER
#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER
# undef CONFIG_LPUART1_RXDMA
#endif
#ifndef CONFIG_STM32H5_USART1_SERIALDRIVER
#ifndef CONFIG_STM32_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32H5_USART2_SERIALDRIVER
#ifndef CONFIG_STM32_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32H5_USART3_SERIALDRIVER
#ifndef CONFIG_STM32_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32H5_UART4_SERIALDRIVER
#ifndef CONFIG_STM32_UART4_SERIALDRIVER
# undef CONFIG_UART4_RXDMA
#endif
#ifndef CONFIG_STM32H5_UART5_SERIALDRIVER
#ifndef CONFIG_STM32_UART5_SERIALDRIVER
# undef CONFIG_UART5_RXDMA
#endif
#ifndef CONFIG_STM32H5_USART6_SERIALDRIVER
#ifndef CONFIG_STM32_USART6_SERIALDRIVER
# undef CONFIG_USART6_RXDMA
#endif
#ifndef CONFIG_STM32H5_UART7_SERIALDRIVER
#ifndef CONFIG_STM32_UART7_SERIALDRIVER
# undef CONFIG_UART7_RXDMA
#endif
#ifndef CONFIG_STM32H5_UART8_SERIALDRIVER
#ifndef CONFIG_STM32_UART8_SERIALDRIVER
# undef CONFIG_UART8_RXDMA
#endif
@ -480,23 +480,23 @@
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA)
#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA)
#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32H5_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA

18
arch/arm/src/stm32h5/stm32_usbdrdhost.c
View file

@ -62,7 +62,7 @@
#include "hardware/stm32h5xxx_pwr.h"
#include "stm32_usbdrdhost.h"
#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H5_USBFS_HOST)
#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_USBFS_HOST)
/****************************************************************************
* Pre-processor Definitions
@ -70,12 +70,12 @@
/* Configuration */
#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS
# define CONFIG_STM32H5_USBDRD_NCHANNELS 8
#ifndef CONFIG_STM32_USBDRD_NCHANNELS
# define CONFIG_STM32_USBDRD_NCHANNELS 8
#endif
#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE
# define CONFIG_STM32H5_USBDRD_DESCSIZE 128
#ifndef CONFIG_STM32_USBDRD_DESCSIZE
# define CONFIG_STM32_USBDRD_DESCSIZE 128
#endif
#ifndef CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT
@ -84,7 +84,7 @@
/* Hardware definitions */
#define STM32_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS
#define STM32_NHOST_CHANNELS CONFIG_STM32_USBDRD_NCHANNELS
#define STM32_EP0_MAX_PACKET_SIZE 64
#define STM32_RETRY_COUNT 3 /* Control transfer retries */
@ -2176,14 +2176,14 @@ static int stm32_alloc(struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr && buffer && maxlen);
alloc = kmm_malloc(CONFIG_STM32H5_USBDRD_DESCSIZE);
alloc = kmm_malloc(CONFIG_STM32_USBDRD_DESCSIZE);
if (!alloc)
{
return -ENOMEM;
}
*buffer = alloc;
*maxlen = CONFIG_STM32H5_USBDRD_DESCSIZE;
*maxlen = CONFIG_STM32_USBDRD_DESCSIZE;
return OK;
}
@ -2890,4 +2890,4 @@ void stm32_usbdrdhost_vbusdrive(int port, bool enable)
uinfo("VBUS drive port=%d enable=%d (default - no-op)\n", port, enable);
}
#endif /* CONFIG_USBHOST && CONFIG_STM32H5_USBFS_HOST */
#endif /* CONFIG_USBHOST && CONFIG_STM32_USBFS_HOST */

12
arch/arm/src/stm32h5/stm32_usbdrdhost.h
View file

@ -39,20 +39,20 @@
/* Pre-requisites */
#if !defined(CONFIG_STM32H5_USBFS_HOST)
# error "CONFIG_STM32H5_USBFS_HOST is required"
#if !defined(CONFIG_STM32_USBFS_HOST)
# error "CONFIG_STM32_USBFS_HOST is required"
#endif
/* USB DRD Host Driver Configuration */
#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS
# define CONFIG_STM32H5_USBDRD_NCHANNELS 8
#ifndef CONFIG_STM32_USBDRD_NCHANNELS
# define CONFIG_STM32_USBDRD_NCHANNELS 8
#endif
/* Default descriptor buffer size */
#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE
# define CONFIG_STM32H5_USBDRD_DESCSIZE 128
#ifndef CONFIG_STM32_USBDRD_DESCSIZE
# define CONFIG_STM32_USBDRD_DESCSIZE 128
#endif
/****************************************************************************

16
arch/arm/src/stm32h5/stm32_usbfs.c
View file

@ -49,7 +49,7 @@
#include "stm32_gpio.h"
#include "stm32_usbfs.h"
#if defined(CONFIG_STM32H5_USBFS)
#if defined(CONFIG_STM32_USBFS)
/****************************************************************************
* Pre-processor Definitions
@ -70,7 +70,7 @@
*/
#ifndef CONFIG_DEBUG_USB_INFO
# undef CONFIG_STM32H5_USBFS_REGDEBUG
# undef CONFIG_STM32_USBFS_REGDEBUG
#endif
/* Initial interrupt mask: Reset + Suspend + Correct Transfer */
@ -345,7 +345,7 @@ struct stm32_usbdev_s
/* Register operations ******************************************************/
#ifdef CONFIG_STM32H5_USBFS_REGDEBUG
#ifdef CONFIG_STM32_USBFS_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr);
static void stm32_putreg(uint16_t val, uint32_t addr);
static void stm32_checksetup(void);
@ -609,7 +609,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
* Name: stm32_getreg
****************************************************************************/
#ifdef CONFIG_STM32H5_USBFS_REGDEBUG
#ifdef CONFIG_STM32_USBFS_REGDEBUG
static uint32_t stm32_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;
@ -668,7 +668,7 @@ static uint32_t stm32_getreg(uint32_t addr)
* Name: stm32_putreg
****************************************************************************/
#ifdef CONFIG_STM32H5_USBFS_REGDEBUG
#ifdef CONFIG_STM32_USBFS_REGDEBUG
static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
@ -685,7 +685,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
* Name: stm32_dumpep
****************************************************************************/
#ifdef CONFIG_STM32H5_USBFS_REGDEBUG
#ifdef CONFIG_STM32_USBFS_REGDEBUG
static void stm32_dumpep(int epno)
{
uint32_t addr;
@ -723,7 +723,7 @@ static void stm32_dumpep(int epno)
* Name: stm32_checksetup
****************************************************************************/
#ifdef CONFIG_STM32H5_USBFS_REGDEBUG
#ifdef CONFIG_STM32_USBFS_REGDEBUG
static void stm32_checksetup(void)
{
uint32_t cfgr = getreg32(STM32_RCC_CFGR);
@ -3950,4 +3950,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
return OK;
}
#endif /* CONFIG_STM32H5_USBFS */
#endif /* CONFIG_STM32_USBFS */

48
arch/arm/src/stm32h5/stm32h563xx_flash.c
View file

@ -58,42 +58,42 @@
#define FLASH_BLOCK_SIZE _K(8)
#define FLASH_PAGE_SIZE 16
#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \
!defined(CONFIG_STM32H5_FLASH_CONFIG_I)
# define CONFIG_STM32H5_FLASH_OVERRIDE_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \
!defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \
!defined(CONFIG_STM32_FLASH_CONFIG_B) && \
!defined(CONFIG_STM32_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32_FLASH_CONFIG_E) && \
!defined(CONFIG_STM32_FLASH_CONFIG_G) && \
!defined(CONFIG_STM32_FLASH_CONFIG_I)
# define CONFIG_STM32_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32H5_FLASH_CONFIG_C
# undef CONFIG_STM32H5_FLASH_CONFIG_E
# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C)
# define CONFIG_STM32H5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E)
# define CONFIG_STM32H5_FLASH_CONFIG_E
#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32_FLASH_CONFIG_C
# undef CONFIG_STM32_FLASH_CONFIG_E
# if defined(CONFIG_STM32_FLASH_OVERRIDE_C)
# define CONFIG_STM32_FLASH_CONFIG_C
# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E)
# define CONFIG_STM32_FLASH_CONFIG_E
# endif
#endif
#if defined(CONFIG_STM32H5_FLASH_CONFIG_I)
#if defined(CONFIG_STM32_FLASH_CONFIG_I)
# define H5_FLASH_BANK_NBLOCKS 128
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G)
#elif defined(CONFIG_STM32_FLASH_CONFIG_G)
# define H5_FLASH_BANK_NBLOCKS 64
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E)
#elif defined(CONFIG_STM32_FLASH_CONFIG_E)
# define H5_FLASH_BANK_NBLOCKS 32
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C)
#elif defined(CONFIG_STM32_FLASH_CONFIG_C)
# define H5_FLASH_BANK_NBLOCKS 16
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_B)
#elif defined(CONFIG_STM32_FLASH_CONFIG_B)
# define H5_FLASH_BANK_NBLOCKS 8
#else
# warning "No valid STM32_FLASH_CONFIG_x defined."

128
arch/arm/src/stm32h5/stm32h5xx_rcc.c
View file

@ -62,7 +62,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32_USE_CLK48)
#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if defined(STM32_CLKUSB_SEL)
# if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK)
# define STM32_USE_HSI48 1
@ -101,13 +101,13 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
#ifdef CONFIG_STM32H5_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHB1ENR_GPDMA1EN;
#endif
#ifdef CONFIG_STM32H5_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHB1ENR_GPDMA2EN;
@ -119,31 +119,31 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_FLASHEN;
#endif
#ifdef CONFIG_STM32H5_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32H5_CORDIC
#ifdef CONFIG_STM32_CORDIC
/* CORDIC clock enable */
regval |= RCC_AHB1ENR_CORDICEN;
#endif
#ifdef CONFIG_STM32H5_FMAC
#ifdef CONFIG_STM32_FMAC
/* FMAC clock enable */
regval |= RCC_AHB1ENR_FMACEN;
#endif
#ifdef CONFIG_STM32H5_RAMCFG
#ifdef CONFIG_STM32_RAMCFG
/* RAMCFG clock enable */
regval |= RCC_AHB1ENR_RAMCFGEN;
#endif
#ifdef CONFIG_STM32H5_ETHMAC
#ifdef CONFIG_STM32_ETHMAC
/* ETH clock enable */
regval |= RCC_AHB1ENR_ETHEN;
@ -174,7 +174,7 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_DCACHEEN;
#endif
#ifdef CONFIG_STM32H5_SRAM1
#ifdef CONFIG_STM32_SRAM1
/* ETH clock enable */
regval |= RCC_AHB1ENR_SRAM1EN;
@ -233,61 +233,61 @@ static inline void rcc_enableahb2(void)
);
#endif
#if defined(CONFIG_STM32H5_ADC)
#if defined(CONFIG_STM32_ADC)
/* ADC clock enable */
regval |= RCC_AHB2ENR_ADCEN;
#endif
#ifdef CONFIG_STM32H5_DAC1
#ifdef CONFIG_STM32_DAC1
/* DAC1 clock enable */
regval |= RCC_AHB2ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32H5_DCMI_PSSI
#ifdef CONFIG_STM32_DCMI_PSSI
/* Digital Camera Interface clock enable */
regval |= RCC_AHB2ENR_DCMI_PSSIEN;
#endif
#ifdef CONFIG_STM32H5_AES
#ifdef CONFIG_STM32_AES
/* Cryptographic modules clock enable */
regval |= RCC_AHB2ENR_AESEN;
#endif
#ifdef CONFIG_STM32H5_HASH
#ifdef CONFIG_STM32_HASH
/* Hash module enable */
regval |= RCC_AHB2ENR_HASHEN
#endif
#ifdef CONFIG_STM32H5_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
#endif
#ifdef CONFIG_STM32H5_PKA
#ifdef CONFIG_STM32_PKA
/* Public Key Accelerator clock enable */
regval |= RCC_AHB2ENR_PKAEN;
#endif
#ifdef CONFIG_STM32H5_SAES
#ifdef CONFIG_STM32_SAES
/* Secure AES coprocessor clock enable */
regval |= RCC_AHB2ENR_SAESEN;
#endif
#ifdef CONFIG_STM32H5_SRAM2
#ifdef CONFIG_STM32_SRAM2
/* SRAM2 clock enable */
regval |= RCC_AHB2ENR_SRAM2EN;
#endif
#ifdef CONFIG_STM32H5_SRAM3
#ifdef CONFIG_STM32_SRAM3
/* SRAM2 clock enable */
regval |= RCC_AHB2ENR_SRAM3EN;
@ -320,25 +320,25 @@ static inline void rcc_enableahb4(void)
regval |= RCC_AHB4ENR_OTFDEC1EN;
#endif
#ifdef CONFIG_STM32H5_SDMMC1
#ifdef CONFIG_STM32_SDMMC1
/* SDMMC1 clock enable */
regval |= RCC_AHB4ENR_SDMMC1EN;
#endif
#ifdef CONFIG_STM32H5_SDMMC2
#ifdef CONFIG_STM32_SDMMC2
/* SDMMC1 clock enable */
regval |= RCC_AHB4ENR_SDMMC2EN;
#endif
#ifdef CONFIG_STM32H5_FMC
#ifdef CONFIG_STM32_FMC
/* Flexible memory controller clock enable */
regval |= RCC_AHB4ENR_FMCEN;
#endif
#ifdef CONFIG_STM32H5_OCTOSPI1
#ifdef CONFIG_STM32_OCTOSPI1
/* OCTOSPI1 module clock enable */
regval |= RCC_AHB4ENR_OSPI1EN;
@ -365,49 +365,49 @@ static inline void rcc_enableapb1l(void)
regval = getreg32(STM32_RCC_APB1LENR);
#ifdef CONFIG_STM32H5_SPI2
#ifdef CONFIG_STM32_SPI2
/* Bit 14: SPI2 clock enable */
regval |= RCC_APB1LENR_SPI2EN;
#endif
#ifdef CONFIG_STM32H5_SPI3
#ifdef CONFIG_STM32_SPI3
/* Bit 15: SPI3 clock enable */
regval |= RCC_APB1LENR_SPI3EN;
#endif
#ifdef CONFIG_STM32H5_USART2
#ifdef CONFIG_STM32_USART2
/* Bit 17: USART2 clock enable */
regval |= RCC_APB1LENR_USART2EN;
#endif
#ifdef CONFIG_STM32H5_USART3
#ifdef CONFIG_STM32_USART3
/* Bit 18: USART3 clock enable */
regval |= RCC_APB1LENR_USART3EN;
#endif
#ifdef CONFIG_STM32H5_UART4
#ifdef CONFIG_STM32_UART4
/* Bit 19: UART4 clock enable */
regval |= RCC_APB1LENR_UART4EN;
#endif
#ifdef CONFIG_STM32H5_UART5
#ifdef CONFIG_STM32_UART5
/* Bit 20: UART5 clock enable */
regval |= RCC_APB1LENR_UART5EN;
#endif
#ifdef CONFIG_STM32H5_I2C1
#ifdef CONFIG_STM32_I2C1
/* Bit 21: I2C1 clock enable */
regval |= RCC_APB1LENR_I2C1EN;
#endif
#ifdef CONFIG_STM32H5_I2C2
#ifdef CONFIG_STM32_I2C2
/* Bit 22: I2C2 clock enable */
regval |= RCC_APB1LENR_I2C2EN;
@ -428,37 +428,37 @@ static inline void rcc_enableapb1l(void)
}
#endif
#ifdef CONFIG_STM32H5_USART6
#ifdef CONFIG_STM32_USART6
/* Bit 25: USART6 clock enable */
regval |= RCC_APB1LENR_USART6EN;
#endif
#ifdef CONFIG_STM32H5_USART10
#ifdef CONFIG_STM32_USART10
/* Bit 26: USART10 clock enable */
regval |= RCC_APB1LENR_USART10EN;
#endif
#ifdef CONFIG_STM32H5_USART11
#ifdef CONFIG_STM32_USART11
/* Bit 27: USART11 clock enable */
regval |= RCC_APB1LENR_USART11EN;
#endif
#ifdef CONFIG_STM32H5_CEC
#ifdef CONFIG_STM32_CEC
/* Bit 28: CEC clock enable */
regval |= RCC_APB1LENR_CECEN;
#endif
#ifdef CONFIG_STM32H5_UART7
#ifdef CONFIG_STM32_UART7
/* Bit 30: UART7 clock enable */
regval |= RCC_APB1LENR_UART7EN;
#endif
#ifdef CONFIG_STM32H5_UART8
#ifdef CONFIG_STM32_UART8
/* Bit 31: UART8 clock enable */
regval |= RCC_APB1LENR_UART8EN;
@ -485,37 +485,37 @@ static inline void rcc_enableapb1h(void)
regval = getreg32(STM32_RCC_APB1HENR);
#ifdef CONFIG_STM32H5_UART9
#ifdef CONFIG_STM32_UART9
/* Bit 0: UART9 clock enable */
regval |= RCC_APB1HENR_UART9EN;
#endif
#ifdef CONFIG_STM32H5_UART12
#ifdef CONFIG_STM32_UART12
/* Bit 1: UART12 clock enable */
regval |= RCC_APB1HENR_UART12EN;
#endif
#ifdef CONFIG_STM32H5_DTS
#ifdef CONFIG_STM32_DTS
/* Bit 3: DTS clock enable */
regval |= RCC_APB1HENR_DTSEN;
#endif
#ifdef CONFIG_STM32H5_LPTIM2
#ifdef CONFIG_STM32_LPTIM2
/* Bit 5: Low-power Timer 2 clock enable */
regval |= RCC_APB1HENR_LPTIM2EN;
#endif
#ifdef CONFIG_STM32H5_FDCAN
#ifdef CONFIG_STM32_FDCAN
/* Bit 9: FDCAN clock enable */
regval |= RCC_APB1HENR_FDCANEN;
#endif
#ifdef CONFIG_STM32H5_UCPD1
#ifdef CONFIG_STM32_UCPD1
/* Bit 23: UCPD1 clock enable */
regval |= RCC_APB1HENR_UCPD1EN;
@ -544,43 +544,43 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32H5_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32H5_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32H5_SPI4
#ifdef CONFIG_STM32_SPI4
/* SPI4 clock enable */
regval |= RCC_APB2ENR_SPI4EN;
#endif
#ifdef CONFIG_STM32H5_SPI6
#ifdef CONFIG_STM32_SPI6
/* SPI6 clock enable */
regval |= RCC_APB2ENR_SPI6EN;
#endif
#ifdef CONFIG_STM32H5_SAI1
#ifdef CONFIG_STM32_SAI1
/* SAI1 clock enable */
regval |= RCC_APB2ENR_SAI1EN;
#endif
#ifdef CONFIG_STM32H5_SAI2
#ifdef CONFIG_STM32_SAI2
/* SAI2 clock enable */
regval |= RCC_APB2ENR_SAI2EN;
#endif
#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_USBFS_HOST)
#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_USBFS_HOST)
/* USB clock enable */
regval |= RCC_APB2ENR_USBEN;
@ -607,31 +607,31 @@ static inline void rcc_enableapb3(void)
regval = getreg32(STM32_RCC_APB3ENR);
#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32H5_ETHMAC)
#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32_ETHMAC)
/* Bit 1: SBS clock enable */
regval |= RCC_APB3ENR_SBSEN;
#endif
#ifdef CONFIG_STM32H5_SPI5
#ifdef CONFIG_STM32_SPI5
/* Bit 5: SPI5 clock enable */
regval |= RCC_APB3ENR_SPI5EN;
#endif
#ifdef CONFIG_STM32H5_LPUART1
#ifdef CONFIG_STM32_LPUART1
/* Bit 6: LPUART1 clock enable */
regval |= RCC_APB3ENR_LPUART1EN;
#endif
#ifdef CONFIG_STM32H5_I2C3
#ifdef CONFIG_STM32_I2C3
/* Bit 7: I2C3 clock enable */
regval |= RCC_APB3ENR_I2C3EN;
#endif
#ifdef CONFIG_STM32H5_I2C4
#ifdef CONFIG_STM32_I2C4
/* Bit 8: I2C4 clock enable */
regval |= RCC_APB3ENR_I2C4EN;
@ -643,25 +643,25 @@ static inline void rcc_enableapb3(void)
regval |= RCC_APB3ENR_I3C2EN;
#endif
#ifdef CONFIG_STM32H5_LPTIM1
#ifdef CONFIG_STM32_LPTIM1
/* Bit 11: LPTIM1 clock enable */
regval |= RCC_APB3ENR_LPTIM1EN;
#endif
#ifdef CONFIG_STM32H5_LPTIM3
#ifdef CONFIG_STM32_LPTIM3
/* Bit 12: LPTIM3 clock enable */
regval |= RCC_APB3ENR_LPTIM3EN;
#endif
#ifdef CONFIG_STM32H5_LPTIM4
#ifdef CONFIG_STM32_LPTIM4
/* Bit 13: LPTIM4 clock enable */
regval |= RCC_APB3ENR_LPTIM4EN;
#endif
#ifdef CONFIG_STM32H5_LPTIM5
#ifdef CONFIG_STM32_LPTIM5
/* Bit 14: LPTIM5 clock enable */
regval |= RCC_APB3ENR_LPTIM5EN;
@ -673,13 +673,13 @@ static inline void rcc_enableapb3(void)
regval |= RCC_APB3ENR_LPTIM6EN;
#endif
#ifdef CONFIG_STM32H5_VREF
#ifdef CONFIG_STM32_VREF
/* Bit 20: VREF clock enable */
regval |= RCC_APB3ENR_VREFEN;
#endif
#ifdef CONFIG_STM32H5_RTCAPB
#ifdef CONFIG_STM32_RTCAPB
/* Bit 21: RTCABP clock enable */
regval |= RCC_APB3ENR_RTCAPBEN;
@ -859,7 +859,7 @@ void stm32_rcc_enableperipherals(void)
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void)
{
uint32_t regval;
@ -995,7 +995,7 @@ void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_CFGR2);
#ifdef CONFIG_STM32H5_RTC_HSECLOCK
#ifdef CONFIG_STM32_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR1);
@ -1096,7 +1096,7 @@ void stm32_stdclockconfig(void)
{
}
#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) || \
defined(STM32_USE_LSCO_LSI)
/* Low speed internal clock source LSI */

2
boards/arm/stm32h5/nucleo-h563zi/Kconfig
View file

@ -5,7 +5,7 @@
if ARCH_BOARD_NUCLEO_H563ZI
config STM32H5_USE_HSE
config STM32_USE_HSE
bool "Use on-board HSE"
default n
---help---

5
boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig
View file

@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -48,8 +49,8 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_ADC1=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32_ADC1=y
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART3_SERIAL_CONSOLE=y

15
boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig
View file

@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -49,13 +50,13 @@ CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_ADC1=y
CONFIG_STM32H5_ADC1_DMA=y
CONFIG_STM32H5_ADC1_DMA_CFG=y
CONFIG_STM32H5_ADC1_WDG1=y
CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH=2048
CONFIG_STM32H5_DMA1=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32_ADC1=y
CONFIG_STM32_ADC1_DMA=y
CONFIG_STM32_ADC1_DMA_CFG=1
CONFIG_STM32_ADC1_WDG1=y
CONFIG_STM32_ADC1_WDG1_HIGHTHRESH=2048
CONFIG_STM32_DMA1=y
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART3_SERIAL_CONSOLE=y

7
boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -43,9 +44,9 @@ CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SENSORS=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_DTS=y
CONFIG_STM32H5_DTS_SMP_TIME=15
CONFIG_STM32H5_USART3=y
CONFIG_STM32_DTS=y
CONFIG_STM32_DTS_SMP_TIME=15
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SENSORTEST=y
CONFIG_TASK_NAME_SIZE=0

9
boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_FDCAN1=y
CONFIG_STM32H5_FDCAN1_FD=y
CONFIG_STM32H5_FDCAN1_LOOPBACK=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32_FDCAN1=y
CONFIG_STM32_FDCAN1_FD=y
CONFIG_STM32_FDCAN1_LOOPBACK=y
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART3_SERIAL_CONSOLE=y

3
boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -42,7 +43,7 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART3_SERIAL_CONSOLE=y

7
boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -58,9 +59,9 @@ CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_LPWORKSTACKSIZE=4096
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32H5_USBFS_HOST=y
CONFIG_STM32H5_USE_HSE=y
CONFIG_STM32_USART3=y
CONFIG_STM32_USBFS_HOST=y
CONFIG_STM32_USE_HSE=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING=y
CONFIG_TASK_NAME_SIZE=0

9
boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_TIM1=y
CONFIG_STM32H5_TIM1_CH1OUT=y
CONFIG_STM32H5_TIM1_PWM=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32_TIM1=y
CONFIG_STM32_TIM1_CH1OUT=y
CONFIG_STM32_TIM1_PWM=y
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TIMER=y

7
boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig
View file

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=2048
@ -47,9 +48,9 @@ CONFIG_RR_INTERVAL=200
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32H5_USBFS_HOST=y
CONFIG_STM32H5_USE_HSE=y
CONFIG_STM32_USART3=y
CONFIG_STM32_USBFS_HOST=y
CONFIG_STM32_USE_HSE=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_USART3_SERIAL_CONSOLE=y

5
boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig
View file

@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi"
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="stm32h5"
CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32H563ZI=y
CONFIG_ARCH_CHIP_STM32H5=y
CONFIG_ARCH_INTERRUPTSTACK=4096
@ -48,7 +49,7 @@ CONFIG_READLINE_TABCOMPLETION=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_STM32H5_USART3=y
CONFIG_STM32H5_USBFS=y
CONFIG_STM32_USART3=y
CONFIG_STM32_USBFS=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0

16
boards/arm/stm32h5/nucleo-h563zi/include/board.h
View file

@ -36,7 +36,7 @@
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_STM32H5_USBFS_HOST) && !defined(CONFIG_STM32H5_USE_HSE)
#if defined(CONFIG_STM32_USBFS_HOST) && !defined(CONFIG_STM32_USE_HSE)
#error "This board config requires HSE to use the USB HOST."
"HSI48 is not stable enough to use as a host."
"To use HSE on the nucleo-H563ZI,"
@ -65,7 +65,7 @@
#define STM32_LSI_FREQUENCY 32000
#define STM32_LSE_FREQUENCY 32768
#ifdef CONFIG_STM32H5_USE_HSE
#ifdef CONFIG_STM32_USE_HSE
#define STM32_HSE_FREQUENCY 25000000ul
#define STM32_BOARD_USEHSE
@ -108,7 +108,7 @@
#define STM32_VCO2_FRQ ((STM32_HSE_FREQUENCY / 5) * 60)
#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4)
#if defined(CONFIG_STM32H5_USBFS_HOST)
#if defined(CONFIG_STM32_USBFS_HOST)
/* PLL3 config: Generate 48 MHz for USB from 25 MHz HSE.
* VCO input = 25 MHz / 5 = 5 MHz
* VCO output = 5 MHz * 96 = 480 MHz
@ -134,7 +134,7 @@
/* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */
#define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK
#endif /* CONFIG_STM32H5_USBFS_HOST */
#endif /* CONFIG_STM32_USBFS_HOST */
#else
@ -181,22 +181,22 @@
#define STM32_VCO2_FRQ ((STM32_HSI_FREQUENCY / 8) * 75)
#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4)
#endif /* CONFIG_STM32H5_USE_HSE*/
#endif /* CONFIG_STM32_USE_HSE*/
/* Enable CLK48; get it from HSI48 */
#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)
#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG)
# define STM32_USE_CLK48 1
#endif
#if defined(CONFIG_STM32H5_USBFS)
#if defined(CONFIG_STM32_USBFS)
# define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK
# define STM32_HSI48_SYNCSRC SYNCSRC_USB
#else
# define STM32_HSI48_SYNCSRC SYNCSRC_NONE
#endif
#if defined(CONFIG_STM32H5_RNG)
#if defined(CONFIG_STM32_RNG)
# define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK
#endif

6
boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt
View file

@ -36,15 +36,15 @@ if(CONFIG_ADC)
list(APPEND SRCS stm32_adc.c)
endif()
if(CONFIG_STM32H5_DTS)
if(CONFIG_STM32_DTS)
list(APPEND SRCS stm32_dts.c)
endif()
if(CONFIG_STM32H5_FDCAN)
if(CONFIG_STM32_FDCAN)
list(APPEND SRCS stm32_can.c)
endif()
if(CONFIG_STM32H5_USBFS_HOST)
if(CONFIG_STM32_USBFS_HOST)
list(APPEND SRCS stm32_usb.c)
endif()

8
boards/arm/stm32h5/nucleo-h563zi/src/Makefile
View file

@ -39,19 +39,19 @@ ifeq ($(CONFIG_ADC),y)
CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32H5_DTS),y)
ifeq ($(CONFIG_STM32_DTS),y)
CSRCS += stm32_dts.c
endif
ifeq ($(CONFIG_STM32H5_FDCAN),y)
ifeq ($(CONFIG_STM32_FDCAN),y)
CSRCS += stm32_can.c
endif
ifeq ($(CONFIG_STM32H5_PWM),y)
ifeq ($(CONFIG_STM32_PWM),y)
CSRCS += stm32_pwm.c
endif
ifeq ($(CONFIG_STM32H5_USBFS_HOST),y)
ifeq ($(CONFIG_STM32_USBFS_HOST),y)
CSRCS += stm32_usb.c
endif

4
boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h
View file

@ -126,7 +126,7 @@ int stm32_bringup(void);
int stm32_adc_setup(void);
#endif
#ifdef CONFIG_STM32H5_DTS
#ifdef CONFIG_STM32_DTS
int stm32_dts_setup(int devno);
#endif
@ -138,7 +138,7 @@ int stm32_dts_setup(int devno);
*
****************************************************************************/
#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER
#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
int stm32_can_setup(uint8_t port);
#endif

14
boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c
View file

@ -37,7 +37,7 @@
#include "stm32.h"
#if defined(CONFIG_ADC)
#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
/****************************************************************************
* Pre-processor Definitions
@ -67,7 +67,7 @@
/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
#ifdef CONFIG_STM32H5_ADC1
#ifdef CONFIG_STM32_ADC1
static const uint8_t g_chanlist1[ADC1_NCHANNELS] =
{
@ -101,10 +101,10 @@ static uint32_t g_pinlist1[ADC1_NPINS] =
int stm32_adc_setup(void)
{
static bool initialized = false;
#ifdef CONFIG_STM32H5_ADC1
#ifdef CONFIG_STM32_ADC1
struct adc_dev_s *adc1;
#endif
#ifdef CONFIG_STM32H5_ADC2
#ifdef CONFIG_STM32_ADC2
struct adc_dev_s *adc2;
#endif
int ret;
@ -116,7 +116,7 @@ int stm32_adc_setup(void)
{
/* Configure the pins as analog inputs for the selected channels */
#ifdef CONFIG_STM32H5_ADC1
#ifdef CONFIG_STM32_ADC1
for (i = 0; i < ADC1_NCHANNELS; i++)
{
stm32_configgpio(g_pinlist1[i]);
@ -139,7 +139,7 @@ int stm32_adc_setup(void)
}
#endif
#ifdef CONFIG_STM32H5_ADC2
#ifdef CONFIG_STM32_ADC2
for (i = 0; i < ADC2_NCHANNELS; i++)
{
stm32_configgpio(g_pinlist2[i]);
@ -168,5 +168,5 @@ int stm32_adc_setup(void)
return OK;
}
#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */
#endif /* CONFIG_ADC */

8
boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c
View file

@ -107,7 +107,7 @@ int stm32_bringup(void)
}
#endif /* CONFIG_ADC*/
#ifdef CONFIG_STM32H5_DTS
#ifdef CONFIG_STM32_DTS
/* devno == 0 creates /dev/sensor_temp0 */
ret = stm32_dts_setup(0);
@ -117,9 +117,9 @@ int stm32_bringup(void)
}
#endif
#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER
#ifdef CONFIG_STM32_FDCAN_CHARDRIVER
/* Initialize CAN and register the CAN driver. */
# ifdef CONFIG_STM32H5_FDCAN1
# ifdef CONFIG_STM32_FDCAN1
ret = stm32_can_setup(1);
if (ret < 0)
{
@ -127,7 +127,7 @@ int stm32_bringup(void)
}
# endif
# ifdef CONFIG_STM32H5_FDCAN2
# ifdef CONFIG_STM32_FDCAN2
ret = stm32_can_setup(2);
if (ret < 0)
{

2
boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c
View file

@ -46,7 +46,7 @@
/* Configuration ************************************************************/
#if !defined(CONFIG_STM32H5_FDCAN1) && !defined(CONFIG_STM32H5_FDCAN2)
#if !defined(CONFIG_STM32_FDCAN1) && !defined(CONFIG_STM32_FDCAN2)
# error "No CAN device is enabled. Please enable at least one CAN device"
#endif

4
boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c
View file

@ -37,13 +37,13 @@
* Currently the NUCLEO-H563ZI board support is restricted to running NuttX
* in the Non-Secure domain together with TrustedFirmware-M (TFM). In this
* setup the clock configuration is done by TFM, not by NuttX. Thus, the
* board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
* board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
* to avoid the standard clock config logic to run and instead do just
* nothing in this function.
*
****************************************************************************/
#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG)
#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
void stm32_board_clockconfig(void)
{
}

2
boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c
View file

@ -34,7 +34,7 @@
#include "stm32.h"
#if defined(CONFIG_STM32H5_DTS)
#if defined(CONFIG_STM32_DTS)
/****************************************************************************
* Pre-processor Definitions

4
boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c
View file

@ -49,11 +49,11 @@
# undef HAVE_PWM
#endif
#ifndef CONFIG_STM32H5_TIM1
#ifndef CONFIG_STM32_TIM1
# undef HAVE_PWM
#endif
#ifndef CONFIG_STM32H5_TIM1_PWM
#ifndef CONFIG_STM32_TIM1_PWM
# undef HAVE_PWM
#endif

4
boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c
View file

@ -42,7 +42,7 @@
#include "stm32.h"
#include "stm32_usbdrdhost.h"
#ifdef CONFIG_STM32H5_USBFS_HOST
#ifdef CONFIG_STM32_USBFS_HOST
/****************************************************************************
* Pre-processor Definitions
@ -265,4 +265,4 @@ int board_usbhost_select_configuration(FAR struct usbhost_hubport_s *hport,
}
#endif
#endif /* CONFIG_STM32H5_USBFS_HOST */
#endif /* CONFIG_STM32_USBFS_HOST */