Pre-existing violations in this file, reported by checkpatch because the
preceding commit touches it:
nrf53_gpiote.c:185: Missing blank line after declarations
nrf53_gpiote.c:213: Bad alignment
nrf53_gpiote.c:216: Bad alignment
nrf53_gpiote.c:259: Bad right brace alignment
Add the blank line after the declarations in the channel-callback block,
indent the two `break;` statements into their case bodies, and align the
brace closing the per-port `for` loop with its opening at line 209 (it
sat at seven spaces, so neither the loop's eight nor anything else).
Whitespace only — no functional change, brace count unchanged.
Signed-off-by: AlmAck <gluca86@gmail.com>
The driver presents a single channel space of GPIOTE_CHANNELS entries
across the application core's two GPIOTE peripherals, and splits it:
inst = (channel < GPIOTE_PER_CHANNEL) ? 0 : 1;
rchan = (inst == 1) ? channel : (channel - GPIOTE_PER_CHANNEL);
rchan is the channel index within the selected instance, used to build
the per-channel register offsets, so it must be
rchan = channel - GPIOTE_PER_CHANNEL * inst
The ternary has the two arms the other way round: a channel on instance
0 gets rchan = channel - GPIOTE_PER_CHANNEL, which is negative, and a
channel on instance 1 gets an index still offset by a full instance.
The interrupt handler in this same file already applies that mapping in
the opposite direction, converting a per-instance channel back to the
global one:
off = i + GPIOTE_PER_CHANNEL * inst;
so the two were inconsistent, and it is the rchan sites that were wrong.
Per the nRF5340 Product Specification, 'GPIOTE - GPIO tasks and
events', the application core has two GPIOTE instances, GPIOTE0 (secure,
base 0x5000D000) and GPIOTE1 (non-secure, base 0x4002F000), each with
eight channels and its own CONFIG[n] array at offset 0x510 + 4n for
n = 0..7. This matches GPIOTE_PER_CHANNEL == 8, the two base addresses
in hardware/nrf53_memorymap_cpuapp.h, and NRF53_GPIOTE_CONFIG_OFFSET()
in hardware/nrf53_gpiote.h, so rchan is required to be in 0..7 and a
negative value cannot address a CONFIG register.
With a negative rchan the CONFIG register write for a channel on
instance 0 lands below the instance base instead of in CONFIG[n], so the
channel is never configured and its GPIOTE interrupt is never enabled.
On nrf5340-dk this makes the board buttons dead.
Both call sites are corrected.
Signed-off-by: AlmAck <gluca86@gmail.com>
STM32_NGPIO_PORTS is (N+15)>>4. 81 (the real pin count) yields six
ports A-F, so PH0/PH1 cannot be configured. 113 matches the F40x
100-pin entries and gives A-H.
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Fixed all the issues reported by checkpatch.sh in stm32_eth_m3m4_v1.c,
stm32f7/stm32_ethernet.c, stm32h5/stm32_ethernet.c, stm32h7/stm32_ethernet.c
Signed-off-by: alexcekay <alexander@auterion.com>
The STM32 Ethernet MAC drivers hard-code a 60-second TX watchdog
timeout. While this is a reasonable general default, certain board
designs and use-cases require a shorter or longer value.
Introduce CONFIG_STM32_ETH_TXTIMEOUT via the shared Kconfig.eth
with a #ifndef fallback. The default is kept at 60 seconds
to preserve existing behavior.
Assisted-by: Claude Code:claude-sonnet-5
Signed-off-by: alexcekay <alexander@auterion.com>
This commit introduces EDID reading and parsing to the JZ4780 display
driver, replacing hardcoded resolution limits with dynamic mode selection
based on the connected display's capabilities.
Specific changes include:
- Implemented I2C DDC master communication for the HDMI controller to
read EDID blocks from monitors.
- Added dynamic mode selection to calculate bandwidth and pick the best
supported resolution, prioritizing the EDID preferred mode.
- Dynamically allocated framebuffer bounds (g_planeinfo and g_videoinfo)
based on parsed EDID dimensions.
- Configured GPIO pin multiplexing for HDMI power, DDC, and control pins
(POWER_EN, CEC, SCL, SDA) to enable display power and communication
on the CI20 board.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Wire the RTL8721F (amebagreen2) into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x4080AD80,
CPU0_NS_WDG IRQ 69, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Wire the RTL8720F into the shared Ameba watchdog driver
(arch/arm/src/common/ameba/ameba_wdg.c), registered as /dev/watchdog0.
Only the per-chip base address and IRQ differ, so this adds a small
ameba_wdg_chip.h (WDG2 non-secure system watchdog at 0x40801D80,
KM4TZ_NS_WDG IRQ 52, verified against the SoC hal_platform.h and
ameba_vector_table.h) plus the Make.defs/CMakeLists build hooks, the
board bring-up registration, and a wdg defconfig. The shared driver is
unchanged.
Also corrects the RTL8720F row in the rtl8721dx chip-header reference
table (the non-secure system WDG IRQ is KM4TZ_NS_WDG = 52).
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Add a NuttX watchdog lower-half for the Ameba KM4 non-secure system
watchdog (WDG2), registered as /dev/watchdog0. The fwlib WDG API is
ROM-resident, so no board.mk change is needed.
The hardware cannot be stopped once enabled, so stop() is emulated via
the early interrupt (EI) auto-refreshing the counter, and capture()
delivers a pre-timeout callback through the same EI. The EI has a
three-part timing contract, all handled here: it must be armed with
EIMOD=ENABLE at WDG_Init, its EIE gate only takes effect after
WDG_Enable, and -- because the EI is level-based -- a pure capture path
must mask EIE after the one-shot callback to avoid re-entrant storming
while the reset is pending. The EI flag is cleared twice per the slow
WDG clock.
Per-chip base address and IRQ live in ameba_wdg_chip.h so the shared
driver needs no change to port to another Ameba IC.
Verified on pke8721daf: timeout reset (BOOT REASON WDG2), stop()
suppressing the reset, and capture() firing ~EICNT ms before the reset.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Xtensa selected neither fork primitive, so vfork() was simply absent. This
wires it onto the two-primitive semantics.
There is no assembly entry point and none is needed. Every exception entry
already runs SPILL_ALL_WINDOWS, so the whole context of the calling thread is
in its exception frame and copying its stack copies a complete frame chain.
A flat build reaches that frame through SYS_save_context, issued inline so
that the recorded stack pointer belongs to a frame that stays alive for the
whole operation; a build with syscalls reaches it through xcp.sregs, recorded
by xtensa_swint() for the duration of the call.
The stack copy needs more than a relocated stack pointer here. A windowed
ABI stores each frame's caller stack pointer absolutely, in the base save
area below the frame, so a copy taken at a different address still names the
parent throughout and the child's first retw would underflow onto the
parent's stack. xtensa_fork_rebase() walks that chain and adds the
relocation offset to each link. The copy also starts one base save area
below the stack pointer rather than at it, because the frame the child
resumes into keeps its caller's spilled a0-a3 there.
Ported from the per-architecture work, reduced to the two primitives.
Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
The nuttx link target only listed libarch.a, board lib, arch objects and
nuttx-names.dat as prerequisites, so rebuilding an app or system library
(staging/libapps.a etc.) did not trigger a relink and the change never
reached the binary.
Add the staging libraries passed in via LINKLIBS to the prerequisite
list, matching the pattern used by arch/arm/src/Makefile.
Signed-off-by: rongbaichuan <rongbaichuan1027@163.com>
Implement PM STANDBY. Loosely based on stm32h7 with
simpler registers.
Implement PM STOP. Using a similar parameter to stm32h7's
LPDS mode bool. There is no LPDS on stm32h5 but there is
the same lower-power voltage scaling value, so rename the parameter
for stm32h5 and use SVOS5 without LPDS present.
Add arm_pminitialize implementation with default
pm subsystem initialization.
Co-authored-by: Austin.Chen <Austin.Chen@wnc.com.tw>
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Add missing blank lines after declarations and fix one bad alignment
in hostfs/rpmsgfs-related files. These are pre-existing style issues
flagged by CI's whole-file nxstyle check when our PR touches these
files. No logic change (git diff -w is blank-line-only additions).
Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
The SDK ships no bare RTL8721F.rdev profile (unlike RTL8721Dx /
RTL8720F); it splits by flash type into RTL8721F_NOR.rdev /
RTL8721F_NAND.rdev. The default (AMEBA_PY_SOC = RTL8721F) therefore
failed the cmake `flash` target with "profile not found:
RTL8721F.rdev".
Override AMEBA_FLASH_PROFILE to RTL8721F_NOR to match the EVB flash
type and boards/arm/rtl8721f/rtl8721f_evb/scripts/Make.defs.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
ameba_setup_env.sh resolved the system interpreter via `command -v
python3`. Once a previous run put $SHIMBIN at the front of PATH, that
lookup returned $SHIMBIN/python3 and `ln -sf shim shim` created a
self-referential symlink, breaking every subsequent cmake reconfigure
with "Too many levels of symbolic links".
Scan PATH for the first python3 that is not inside $SHIMBIN and
canonicalise it with readlink -f, so the shim always points at a real
interpreter. Idempotent across reconfigures.
Assisted-by: Claude <noreply@anthropic.com>
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
The shared CMake build hardcoded a single ROM symbol linker script
(ameba_rom_symbol_acut_s.ld), so a CMake build of rtl8721f failed to
link: __rom_bss_start_ns__ / __rom_bss_end_ns__ and the rtw_* WiFi ROM
symbols were left undefined. The make build already appends rtl8721f's
four ROM symbol scripts (secure + wifi + os + NS) in
arch/arm/src/rtl8721f/ameba_board.mk; the CMake path did not.
Make the ROM symbol script set per-IC:
- ameba_gen_ldscript.sh now takes one or more ROM ld files as trailing
arguments and cat's them in order (was a single fixed argument).
- ameba_board.cmake keeps the previous single-script default and lets an
arch CMakeLists override it via AMEBA_ROM_LDS; the list is resolved to
full paths and passed to the generator.
- rtl8721f/CMakeLists.txt sets AMEBA_ROM_LDS to its four ROM symbol
scripts, matching its ameba_board.mk cat order.
rtl8721dx and rtl8720f are unchanged (still the single default script).
Verified on rtl8721f: the nsh CMake build now links the nuttx ELF
cleanly with no undefined NS-BSS or rtw_* symbols.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
The generic ARMv7-M user SRAM helper marks memory shareable. STM32H7
Protected user data and heaps can reside in cacheable AXI or D2 SRAM, where
userspace synchronization needs LDREX/STREX to use the CPU-local exclusive
monitor.
Map protected user SRAM as Normal, cacheable, and non-shareable. Dual-core
RPTUN SRAM remains unaffected because it is mapped separately with explicit
shareable attributes.
Tested by booting a Protected image and running user and kernel work-queue
stress tests on an STM32H7 PX4 FMUv6C.
Assisted-by: Codex:GPT-5
Signed-off-by: DuoYuWang <thirteenking.wang@gmail.com>
up_allocate_heap() calculates the available user heap from SRAM_END but
previously placed the aligned region relative to SRAM123_END. That mixes
the selected primary SRAM with a fixed D2 SRAM boundary and leaves
SRAM123_END undefined for dual-core M7 and M4 configurations.
Place the user heap relative to SRAM_END so its size, MPU alignment, and
location all refer to the SRAM region selected by the chip configuration.
Tested by building and booting a Protected image on an STM32H7 PX4 FMUv6C.
Assisted-by: Codex:GPT-5
Signed-off-by: DuoYuWang <thirteenking.wang@gmail.com>
The unique ID on STM32 Cortex-M33 parts is stored in flash information
memory, which cannot be accessed while the instruction cache is enabled.
Add an ICACHE state helper, temporarily disable the instruction cache
while reading the UID using 32-bit accesses, and restore it only when it
was originally enabled. This preserves the caller's cache state and
prevents a bus fault during UID access.
Assisted-by: Codex:gpt-5
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
Add WWDG driver support for STM32H5.
Enable the WWDG peripheral clock when WWDG is enabled.
It's based on STM32H7. This contribution has been
reduced to the minimum number of changes from the
H7 version.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Co-authored-by: Liam Howatt <liamhowatt@geotab.com>
Implement atomic_lock/atomic_unlock using hwspinlock when
CONFIG_LIBC_ATOMIC_HWSPINLOCK is selected, and using up_irq_save/
up_irq_restore when CONFIG_LIBC_ATOMIC_IRQ is selected. Rename
arch_atomic_irq.c to arch_atomic.c.
The 64-bit atomic operations use spinlock (spin_lock_irqsave)
regardless of the selected backend, ensuring multi-core safety.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add hardware spinlock driver implementations for cxd56, rp2040, and
lc823450 chips. These drivers provide the hwspinlock_ops_s interface
used by the atomic hwspinlock backend.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8721F (amebagreen2). The driver is chip-agnostic and reads only
per-chip macros from ameba_rtc_chip.h; RTL8721F differs from amebadplus
only in the RTC interrupt vector (RTL8721F_IRQ_RTC, vector 41). The
APBPeriph_RTC masks and RTC_BASE_YEAR (1900) are identical across all
current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8721f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba RTC driver (arch/arm/src/common/ameba/ameba_rtc.c)
into RTL8720F. The driver is chip-agnostic and reads only per-chip macros
from ameba_rtc_chip.h; RTL8720F differs from amebadplus only in the RTC
interrupt vector (RTL8720F_IRQ_RTC, vector 33). The APBPeriph_RTC masks
and RTC_BASE_YEAR (1900) are identical across all current Ameba chips.
- ameba_rtc_chip.h: per-chip RTC IRQ / clock masks / base year
- Make.defs, ameba_board.mk: compile ameba_rtc.c and the fwlib RAM
RTC source when CONFIG_AMEBA_RTC=y
- board: rtl8720f_rtc.c registers /dev/rtc0 from bringup
- configs/rtc: examples/alarm profile
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Expose the Ameba on-chip RTC as a NuttX date/time RTC at /dev/rtc0
(rdtime/settime) with a single one-shot alarm (setalarm/rdalarm/
cancelalarm/setrelative) that fires the RTC interrupt and the upper-half
callback. The same hardware also backs the arch date/time RTC hooks
(up_rtc_initialize/getdatetime/settime, g_rtc_enabled) so the NuttX
system time is seeded from it.
The driver sits on the SDK fwlib RTC API (mirrored structures + local
externs, no vendor headers pulled into the NuttX include world). The
fwlib RTC API lives in the RAM source ameba_rtc.c, so it is added to the
board fwlib build under CONFIG_AMEBA_RTC. The hardware keeps a year plus
a day-of-year (no month/day register); the driver bridges that to the
NuttX month/day calendar with the libc UTC routines (timegm/gmtime_r),
which is exact and reversible.
The only per-chip fact -- the RTC interrupt vector -- lives in the
per-chip ameba_rtc_chip.h; the shared driver is never edited for a new
Ameba chip. A configs/rtc profile (examples/alarm) is added for
verification.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Replace the enumerated STM32U3/U5 chip conditions in the common M33
source lists and the RCC dispatch header with a single STM32_COMMON_M33
symbol, following the existing STM32_COMMON_* convention.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3 and U5 family-local Cortex-M33 RCC headers to
stm32_rcc_m33.h and dispatch to that private name for the two families
in the common RCC header.
This lets the shared M33 USART implementation use one include name
while RCC registers and clock definitions remain family-local. Extend
the stm32_ports.rst naming rules with the M33 header, source, and
Kconfig symbol conventions.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the shared U3/U5 heap allocator to stm32_allocateheap_m33_v1.c
and keep its direct family selection in Make and CMake.
Size the primary region from a now-mandatory STM32_PRIMARY_SRAM_SIZE,
provided by the U5 chip header as the SRAM1 size, and drop the
U5-specific SRAM bank descriptions so the allocator carries no family
conditionals.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the shared U3/U5 reset handler to stm32_start_m33_v1.c and keep
its direct family selection in Make and CMake.
Include stm32_userspace.h only under CONFIG_BUILD_PROTECTED and define
the SRAM2 span only when CONFIG_STM32_SRAM2_INIT requests the parity
initialization, so families without SRAM2 parity or userspace support
can use the file unchanged.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the shared U3/U5 USART sources to stm32_serial_m33_v3.c and
stm32_lowputc_usart_m33_v3.c and gate them with a new
STM32_HAVE_IP_USART_M33_V3 symbol selected by the U3 and U5 peripheral
options. Rename the USART hardware header to stm32_uart_m33_v3.h with
its register map unchanged.
Store each port's RCC enable register and bit in the serial
descriptor, provided by the family RCC headers as
STM32_<port>_FREQUENCY, _RCC_REG and _RCC_EN, so common clock control
needs no family-specific switch. Correct the LPUART1 RX DMA map name
to DMAMAP_LPUART1_RX.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3/U5 GPIO and EXTI sources to stm32_gpio_m33_v1.c and
stm32_exti_gpio_m33_v1.c and gate them with new
STM32_HAVE_IP_GPIO_M33_V1 and STM32_HAVE_IP_EXTI_M33_V1 symbols
selected by the U3 and U5 peripheral options.
Rename the GPIO and EXTI hardware headers to stm32_gpio_m33_v1.h and
stm32_exti_m33_v1.h with their register maps unchanged, dispatch to
them from the common GPIO and EXTI hardware headers by the new IP
symbols, and widen STM32_EXTI_EXTICR_PORT_MASK to the full 8-bit
EXTICR port-select field.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Remove the disabled CONFIG_STM32_SYSTICK_HCLKd8 reload path and the
non-functional clock-source write. SysTick always runs from HCLK on
these devices, so compute the reload value from STM32_HCLK_FREQUENCY
only.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Iterate the NVIC interrupt enable and priority registers from
STM32_IRQ_NEXTINTS instead of dumping a hardcoded U3/U5 register list,
so the helper works unchanged for any interrupt count.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Rename the U3/U5 idle, NVIC, and SysTick sources to the Cortex-M33 v1
naming convention: stm32_idle_m33_v1.c, stm32_irq_m33_v1.c, and
stm32_timerisr_m33_v1.c, and move them into their own Make and CMake
block, still selected by the direct U3/U5 family condition.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Blank lines only; `git diff --ignore-blank-lines` against the parent is empty.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
MAXMB resets to 0x0f, so OR-ing the intended value into MCR can only ever
raise it. Every configuration with fewer than 16 mailboxes therefore runs with
MAXMB = 15 and FlexCAN arbitrates over mailboxes the driver never initialised:
with the classic payload layout MB14 and MB15 hold power-on contents, and with
a 64-byte CAN FD layout they are past the end of the mailbox RAM region
entirely.
s32k1xx_flexcan.c already does this; carry the same two lines over.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
imxrt_transmit() wrote the caller's deadline into txmb[] before testing
whether it had already passed, and the early return for an expired deadline
then left that deadline behind on a mailbox holding no frame. The next
watchdog expiry finds it, counts a transmit timeout that did not happen, and
writes CAN_TXMB_ABORT into a mailbox the allocator may have handed to a live
frame in the meantime.
Compute the timeout first and store the deadline after the early return.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
imxrt_txtimeout_work() had four defects that together let one expired frame
take the interface down permanently.
It aborted mailbox RXMBCOUNT + mbi while the deadline it consulted belongs to
RXMBCOUNT + 1 + mbi, so every abort landed one mailbox low and mbi == 0 wrote
CAN_TXMB_ABORT into the buffer reserved for the ERR005829 workaround, while
the highest TX mailbox was never aborted at all.
Its expiry test read `now.tv_sec > d.tv_sec || now.tv_usec > d.tv_usec`, which
declares any deadline that crosses a second boundary expired: in that case the
deadline's microsecond field is always the smaller of the two. The `now` it
compared against was a struct timespec cast to a struct timeval, so writing
tv_usec wrote over tv_nsec and tv_sec was whatever the cast happened to line
up with.
imxrt_txdone() cancelled the watchdog but left txmb[].deadline set, so a
retired mailbox looked expired forever and the next watchdog expiry on any
other mailbox aborted whatever frame had since been loaded there.
The walk ran to TXMBCOUNT, which counts the reserved mailbox as well, so its
last iteration addressed mailbox TOTALMBCOUNT - one past the ring, and
mb_address[] one past its end. Only txmb[] never being written that far kept
it in bounds. TXMBRINGSIZE now names the ring size that the rest of the driver
already assumes.
Aborting a frame that is already on the wire raises a bit error, so the
transmit error counter climbs and the node goes error passive. Since
imxrt_txmb_next() only hands out a mailbox above every pending one, a mailbox
left in DATAORREMOTE also pins the allocator at TOTALMBCOUNT and transmit
never recovers.
Measured on an ARK FMU-v6XRT with a DroneCAN GNSS node on the bus, offering
736 frames/s (9% of a 1 Mbit/s bus) from the PX4 uavcan driver: before, the
interface transmitted 0 frames/s with ECR[TXERRCNT] pinned at 128 and
ESR1[FLTCONF] error passive, and stayed dead across a reboot. After, 734
frames/s, 0.1% loss, TXERRCNT 0, error active.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The idle stack area started at _ebss + CONFIG_IDLETHREAD_STACKSIZE *
CONFIG_SMP_NCPUS, so the first CONFIG_SMP_NCPUS stack slots after .bss
were never used - 16MiB on a 4-CPU configuration with a 4MiB idle
stack. Start the area at _ebss and let the heap begin that much
earlier.
The -16 offset is kept: it is what places the AP initial RSP set up in
intel64_head.S below the xcp->regs block that up_cpu_idlestack()
reserves at the top of the same stack. Without it both land on the
same 64-byte slot and the first context save corrupts the AP stack.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
intel64 port explicitly enumerates five idle-stack
addresses and rejects configurations with more than five CPUs.
Store the CPU0 stack top and calculate every CPU stack address
from its index.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
The AP boot path masked RSP with ~XCPTCONTEXT_SIZE, which just clears
whichever bits happen to be set in the size (0x340 -> mask 0xfffffcbf).
That drops RSP by an arbitrary amount and only guarantees 16-byte
alignment, while the XSAVE area in the context needs 64.
Mask with ~(XCPTCONTEXT_ALIGN - 1) instead.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
nxstyle now checks case labels against their enclosing brace, and the
DWC2-derived OTG device drivers align every case label with the switch
brace itself, so any change that touches one of these files fails
checkpatch on hundreds of pre-existing lines.
Indent the switch bodies by two columns as the standard requires and
re-wrap the lines that this pushes past the width limit. Whitespace and
comment re-flow only; no code changes.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Every DWC2-derived USB device driver enables USBSUSP in GINTMSK but not
WKUP, and every one of them ANDs GINTSTS with GINTMSK before dispatch.
The resume handler is therefore unreachable: CLASS_SUSPEND is delivered
on suspend, CLASS_RESUME never is.
For CDC/ACM that is fatal. cdcacm_suspend() calls uart_connected(false),
after which serial.c refuses every open() and write() with -ENOTCONN,
and the cdcacm_resume() that would clear it never runs. On a Linux host
with the default USB autosuspend (power/control=auto, 2000 ms) simply
closing the tty is enough to trip it, and the port stays dead for the
rest of the boot while the device remains enumerated.
Verified on STM32H7 (ARK FMU v6X): before, one host suspend leaves the
CDC/ACM port permanently -ENOTCONN; after, ten forced suspend/resume
cycles all recover with the MAVLink stream intact. The remaining
drivers carry a line-for-line copy of the same initialisation.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
