When enabling CONFIG_READLINE_EDIT the CI fails because it reports
there is not left space in this device.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
adc_shutdown() gates the ADC clock (RCU_APB2EN.ADCEN) when the device is
closed, but the one-shot adc_reset() that first enabled it only runs at
registration and adc_setup() never re-enabled it. A second open() then drove
a clock-gated peripheral whose conversions never completed, so a second run of
a reader such as the adc example hung after opening the device. adc_setup()
now re-enables the ADC clock; clock gating preserves the register
configuration, so nothing else has to be re-programmed.
Add an "adc" configuration that exercises the driver. It is the nsh base plus
the ADC driver, registered as /dev/adc0 and read by the adc example. ADC
channel 8 (ADC_IN8) is routed to PB0 on the J1 header so an analog voltage
applied there is sampled. The board bringup samples that channel when the pin
is routed, and PB0 is only claimed for the ADC when SPI is off (with SPI on it
belongs to the I2C0 fallback), so the periph configuration is unaffected.
The GD32VW55x ADC converts on demand rather than continuously, so the example
uses the software trigger (CONFIG_EXAMPLES_ADC_SWTRIG) and is bounded to 20
sample groups so it returns to the prompt.
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Add an "sdcard" configuration that mounts an SD card over SPI0 with a FAT
filesystem. The board provides the SPI chip-select glue (gd32_spi0select,
gd32_spi0status and gd32_spi0register in a new gd32_spi.c) and gd32_bringup()
binds the slot with mmcsd_spislotinitialize() and mounts /dev/mmcsd0 on
/mnt/sd.
The card is wired to the J1 header: SCK PA2, MISO PA1, MOSI PA0, and a
software chip select on PA4. CONFIG_MMCSD_MMCSUPPORT is left off (its MMC
CMD1 probe upsets SD cards).
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Add a "pwm" configuration that exercises the PWM driver on TIMER1. It is the
nsh base plus the PWM driver, registered as /dev/pwm0 and driven by the pwm
example (100 Hz, 50 % duty by default).
TIMER1 channel 0 is routed to PA0 on the J1 header (AF1) so the waveform can
be probed there; the other channels stay unrouted.
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
The GD32VW55x I2C master (the STM32-style "v2" IP) never completed a real
transfer. Two bugs:
1. Wrong kernel clock. The protocol state machine is clocked by the I2C
kernel clock selected in RCU_CFG1.I2C0SEL, not by the APB1 bus clock that
only feeds the register interface. The driver left it at the APB1 default
and computed TIMING for PCLK1 (~80 MHz); the resulting prescaled period is
so short that the SDADEL/SCLDEL setup and hold times fall below the
analog-filter minimum of the IP, so the master latches START but never
drives SCL (STAT stuck with BUSY set). Route I2C0 to IRC16M (16 MHz) and
use it as clk_freq, and never let the prescaler drop below the value that
keeps the prescaled clock at/under 4 MHz (250 ns) so SDADEL/SCLDEL stay in
spec. This matches the vendor BSP (IRC16M, PSC=3).
2. Transfer timeout was zero. CONFIG_GD32VW55X_I2C_TIMEOTICKS has a Kconfig
default of 0 ("override when non-zero"), but the driver derived the timeout
with a plain #ifndef, which never triggers because the symbol is always
defined. The polled wait loop therefore ran a single iteration and gave
up. Address probes (NACK on the first pass) still worked and masked it;
only multi-byte transfers exercised the loop. Honour the "0 means derive
from seconds/milliseconds" contract.
Also make the interrupt wait immune to the ISR completing between startmsg()
and the wait (do not clobber a posted DONE), and drop a redundant cast.
To exercise this on hardware, add an "sht3x" configuration to the
gd32vw553k-start: the nsh base plus I2C0, the i2ctool and the Sensirion SHT3x
temperature/humidity driver, registered as /dev/i2c0 and /dev/temp0. I2C0 is
routed to PA2 (SCL) / PA3 (SDA) on AF4, the pins broken out on the J1 header
(datasheet Table 2-5); when SPI is enabled it claims PA2, so I2C0 falls back
to PB0/PB1, whose SDA pin is not broken out (the periph case).
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Adds a driver for the external QSPI PSRAM hanging off QMI chip select 1,
such as the 8 MiB APS6404 fitted on the Pimoroni Pico Plus 2.
rp23xx_psramconfig() assigns the CS1 pin, reads the device ID over the QMI
direct interface to confirm an APS6404-family part (KGD 0x5D), resets it
into quad mode and programs the QMI M1 timing/read/write formats so the
region at 0x11000000 becomes directly addressable and writable. Because
driving the QMI in direct mode stalls execute-in-place from the flash, the
detection and (re)configuration code runs from RAM (.time_critical) with
interrupts disabled; the command bytes are selected with immediates rather
than a .rodata table for the same reason. The register values follow the
Raspberry Pi Pico SDK setup_psram().
The detection routine only keeps the QMI DIRECT_CSR synchronization that is
strictly necessary. Each candidate busy-wait was removed one at a time and
re-verified on hardware: the post-enable "cooldown" waits, the READ_ID
TXEMPTY wait (redundant with the BUSY wait after it), and a fixed nop delay
proved unnecessary and are omitted. The three BUSY waits that remain -- after
the quad-mode nudge, after each READ_ID byte, and after each reset/quad-enable
command -- are required and carry a comment explaining that the frame must
finish shifting before the chip select is deasserted, and what breaks
otherwise (garbage ID reads, or the shared QMI bus wedging).
rp23xx_psram_restore() re-applies the M1 configuration and is meant to be
called from the flash write path, which goes through the bootrom and
reconfigures the shared QMI for chip select 0.
rp23xx_heaps.c is wired into the build and now uses the detected size, so
the PSRAM is exposed to the memory manager (added to the main heap, used as
a separate heap, or as the user heap) and is skipped cleanly when no PSRAM
is present.
Enabled by default on the pimoroni-pico-2-plus:nsh configuration, where it
adds the 8 MiB to the main heap. A documentation page for the Pimoroni Pico
Plus 2 is added alongside the other rp23xx boards, covering its serial
console, LED, the external PSRAM and how it is exposed to the heap, the
supported capabilities and the available configurations, with a photo of the
board.
Tested on Pimoroni Pico Plus 2 hardware: detection reports the 8 MiB
APS6404, the region is read/write across its whole range (ramtest word,
half-word and byte passes, marching/pattern/address-in-address), and the
heap reports the extra 8 MiB.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
The RP2350 has two system timer blocks (TIMER0, TIMER1), each a free-running
64-bit counter incremented once per microsecond by the TICKS block (set up in
rp23xx_clock.c). They are independent of the ARM SysTick that drives the OS
tick, so they are free for application use, but the port had no driver for
them.
Add rp23xx_timer.c, a NuttX timer lower-half that binds a block to a
/dev/timerN device. It uses ALARM0 of the block, which matches the low 32
bits of the microsecond counter, to implement single-shot and periodic
timeouts with 1 us resolution and a maximum interval of 2^32 - 1 us (~71.5
minutes). Periodic reloads are scheduled relative to the previous expiry to
avoid drift, but never behind the counter (an alarm set in the past would not
match until the 32-bit counter wraps).
Enable with CONFIG_RP23XX_TIMER (which selects CONFIG_TIMER), then turn on each
block independently: CONFIG_RP23XX_TIMER0 registers /dev/timer0 and
CONFIG_RP23XX_TIMER1 registers /dev/timer1. A block claimed by the tickless
oneshot (CONFIG_RP23XX_SYSTIMER_TICKLESS) is excluded from these choices in
Kconfig, so the two features can be enabled together without colliding on the
same block or its alarm IRQ.
Tested on Pimoroni Pico Plus 2 (RP2350B) hardware with examples/timer and a
CMSIS-DAP probe. The device registers as /dev/timer0; the ALARM0 interrupt
fires at the programmed period (verified over SWD at the configured 1 s
interval, not a busy loop), and the full path -- alarm match, the driver ISR,
the timer notification and delivery of the SIGNO to user space -- reaches the
example's signal handler and increments its counter.
Assisted-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
The rp2350 executes in place from external QSPI flash, and a NuttX image
normally leaves most of that flash unused. This exposes the unused region
as an MTD device so it can carry a filesystem, mirroring what the rp2040
port already provides with rp2040_flash_mtd.c.
The region is given by RP23XX_FLASH_MTD_OFFSET and RP23XX_FLASH_MTD_SIZE,
both multiples of the 4096 byte erase sector. Initialization fails rather
than corrupting the running image if the region would overlap the NuttX
binary, checked against __flash_binary_end.
Erase and program use the bootrom flash routines. Those stall instruction
fetch from the same flash, so they run from SRAM with interrupts disabled
and, on SMP builds, the other core parked; afterwards the QSPI interface is
returned to execute-in-place mode. By default that restores the fast read
mode the bootrom configured at boot; RP23XX_FLASH_MTD_SAFE_XIP instead
always uses the bootrom flash_enter_cmd_xip routine, which is slower to
execute from but depends only on the documented bootrom entry point.
The driver answers BIOC_XIPBASE with the memory-mapped address of the
region, so a filesystem supporting execute in place can hand out real flash
pointers rather than copying into RAM.
The common board bringup registers the device as /dev/rpflash.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Since sim:nsh doesn't use much resource and it is used for testing
let's enable the complete line editing support.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Toolchain.defs adds --fixed-r10 to CFLAGS under CONFIG_PIC, but nearly
every board Make.defs includes that file and then assigns
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) ...
with ':=', which discards it. 266 of the 269 ARM board files assign
CFLAGS that way; the remaining three delegate to a shared makefile that
does the same thing.
The flag is what keeps the base firmware from allocating r10, the
register a PIC module reaches its own data through. Losing it is silent
and the symptom is remote from the cause: the build succeeds, and only a
callback from base firmware into module code -- qsort() with a module
comparison function is the standard case -- misbehaves, reading its data
through a register the firmware has since felt free to reuse.
Adding it to ARCHCFLAGS puts it on the far side of that ':=', which
re-expands ARCHCFLAGS, so every board picks it up with no board changes
at all.
A module is the other side of the --fixed-r10 contract: it gets r10 via
-mpic-register=r10, and GCC rejects both on one command line with
"unable to use 'r10' for PIC register". Every ARM board carried the
same three lines to set that up:
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
They move to arch/arm/src/common/Toolchain.defs, which also filters
--fixed-r10 back out of CPICFLAGS, CXXPICFLAGS, CELFFLAGS and
CXXELFFLAGS in one place instead of each board having to know about the
interaction. ARCHPICFLAGS uses '?=' and the derived flags use deferred
'=', so a board can still override or append after including the file,
and CFLAGS is whatever the board finally set it to.
Two boards keep a definition because they genuinely differ: am67 adds
-ffixed-r10 and tiva conditionally adds -mno-pic-data-is-text-relative.
tlsr82 previously appended -fpic to an unset variable, so only -fpic
ever reached its compiler; it now inherits the standard set, verified
against tc32-elf-gcc 4.5.1.tc32-elf-1.5 (Telink TC32 v2.0), whose
ARM-derived backend honors -msingle-pic-base and -mpic-register=r10.
The mps2, mps3, qemu-armv7a, qemu-armv7r, fvp and mcx-nxxx families
referenced ARCHPICFLAGS without ever defining it, so their CPICFLAGS
carried no PIC flags at all; they get the standard set too.
Also adds the missing space in
CXXELFFLAGS = $(CXXFLAGS)-fvisibility=hidden -mlong-calls
which ran the last token of CXXFLAGS into -fvisibility=hidden, yielding
a single malformed token such as -DNDEBUG-fvisibility=hidden.
Also exempts the pre-existing "*.siz" gsize comment in Toolchain.defs
from codespell, which reads "siz" as a misspelling and fires for any
patch touching the file, since checkpatch scans whole files rather than
changed lines.
Before, with CONFIG_PIC=y: CFLAGS has --fixed-r10: NO
After: CFLAGS has --fixed-r10: YES
CPICFLAGS/CELFFLAGS: filtered out
Assisted-by: Claude Code:claude-opus-4-8
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
Add EHCI and OHCI USB host drivers for the Ingenic JZ4780 SoC, derived
from the existing sama5 implementation.
Additionally, introduce the display controller driver using code ported
from FreeBSD under its original license terms. Note that this driver
lacks EDID support and is currently hardcoded to 1360x768.
Update the linker script memory layout to utilize the full 256 MiB RAM,
excluding the 8 MiB reserved at the top of memory for the framebuffer.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Adds support for Python on M5 Stack ESP32-P4 Tab5 board.
This board runs on P4 chip revision v1.3 and needs special changes in linker
script.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
nuttx-apps#3557 switches FSUTILS_PASSWD and NETUTILS_DROPBEAR to depend on
CRYPTO, CRYPTO_RANDOM_POOL, NETUTILS_CODECS and CODECS_BASE64 instead of
selecting them. stm32f746g-disco/dropbear must enable these explicitly so
olddefconfig/CI normalize keeps dropbear and FSUTILS_PASSWD enabled.
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
nuttx-apps#3557 switches NETUTILS_DROPBEAR to depend on CRYPTO and
CRYPTO_RANDOM_POOL instead of selecting them. sim/dropbear must enable
CONFIG_CRYPTO and CONFIG_CRYPTO_RANDOM_POOL explicitly so olddefconfig and
CI normalize keep dropbear and FSUTILS_PASSWD enabled.
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
Document PBKDF2-HMAC-SHA256 ROMFS passwd generation and update board
Kconfig help text accordingly. Set the documented sim/login CI credential
in GitHub Actions.
Enable CONFIG_CODECS_BASE64 and CONFIG_NETUTILS_CODECS on sim:dropbear for
link compatibility with dropbear's bundled libtomcrypt.
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
Migrate moxa:nsh from fixed telnet password to build-time ROMFS
/etc/passwd with PBKDF2-HMAC-SHA256 and cryptodev.
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
Add standalone host PBKDF2-HMAC-SHA256 mkpasswd, board_romfs_mkpasswd.sh,
and promptpasswd.sh with confirm-password support. Integrate ROMFS passwd
generation in Board.mk and CMake. Drop TEA key checks from passwd_keys.mk.
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
The common mips_cache.S only handles generic L1 cache operations and
does not support L2 (secondary) cache operations required for the
JZ4780 target.
This commit introduces mti_cache.S to support both L1 and L2 cache
operations.
The mti_cache.S implementation is BSD licensed from Imagination
Technologies.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Add stm32h7 support for HASH HW accelerator for MD5, SHA1, SHA2-224,
and SHA2-256 as well as their HMAC variants.
Signed-off-by: Peter Barada <peter.barada@gmail.com>
Add a "curl" configuration for the linum-stm32h753bi board, based on the
netnsh configuration (ethernet + DHCP). It enables the system/curl HTTP
client command, SD card support (mounted manually, as in the sdcard
configuration) and a larger console line buffer (CONFIG_LINE_MAX=256) so
long URLs and JSON bodies are not truncated at the NSH prompt.
Also document the curl command: add a man page under
Documentation/applications/system/curl and a usage example (download,
POST JSON, multipart upload) to the board documentation.
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
Add a board-agnostic GPIO driver for Realtek Ameba chips, exposing pins
through the NuttX GPIO (ioexpander) upper half at /dev/gpioN.
- arch/arm/src/common/ameba/ameba_gpio.{c,h}: the shared driver, sitting
directly on the SDK fwlib register layer. The fwlib GPIO API it calls
resolves at link time from the on-chip ROM symbol table, except
GPIO_INTStatusGet/ClearEdge which are not in ROM and are compiled in
from fwlib ram_common/ameba_gpio.c (that object also carries GPIO_Init,
harmlessly overriding the equivalent ROM copy). Pin interrupts are
dispatched NuttX-natively: the port's NVIC vector is owned by NuttX
via irq_attach, and the ISR reads and clears status through the fwlib
GPIO_INTStatus* helpers.
- The driver keeps nothing IC-specific: the port count, the per-port
NVIC vectors and the RCC gate bits come from a per-chip
<ameba_gpio_chip.h> resolved on the include path, so bringing up a new
Ameba chip only adds that header, not a change to the shared driver.
- arch/arm/src/common/ameba/Kconfig: a shared "Ameba Peripheral Support"
menu with the AMEBA_GPIO option, sourced by each Ameba chip's Kconfig so
it is reused across ICs (RTL8721Dx, RTL8720F, ...).
- arch/arm/src/rtl8721dx: provide ameba_gpio_chip.h, wire the driver into
both the Make/Kconfig and CMake builds, and compile the fwlib
ameba_gpio.c register layer into libameba_fwlib for the RTL8721Dx.
- boards/arm/rtl8721dx/pke8721daf: board pin table (rtl8721dx_gpio.c),
bring-up registration, and a standalone gpio defconfig.
- Documentation: describe the gpio configuration and pin encoding.
tools/nxstyle: whitelist the Ameba "GPIO_" SDK ROM symbol prefix (alongside
the existing FLASH_/IPC_/... Ameba prefixes) so the vendor GPIO API's mixed-case
identifiers do not trip nxstyle, matching how the other Ameba SDK prefixes are
handled.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Users can try the barometer dashboard example on the simulator. The
recommended way of simulating the barometer is using uorb_generator,
like in the following command:
uorb_generator -n 10000 -r 1 -s -t sensor_baro0 timestamp:23191100,pressure:999.12,temperature:26.34 &
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Adds a new configuration which allows users to try the barometer
monitoring example with a connected barometer over I2C.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Add NSH and OSTest configurations, the DRAM linker script, and the minimal board initialization and reset hooks for RK3588S.
Signed-off-by: Emre Cecanpunar <emreleno@gmail.com>
Drop the esp32c3-devkit:dropbear defconfig and its documentation.
The companion apps#3636 (Dropbear over /dev/crypto for this board)
is stuck on an unrelated Espressif CI dependency issue, and the
port is moving to different hardware.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Add a stm32f746g-disco:dropbear config for NSH over SSH on the
board's Ethernet, with the password file and Dropbear host key
persisted on QSPI flash (LittleFS) instead of RAM.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Add a LittleFS mount option for the on-board N25Q QSPI flash,
mirroring the existing NXFFS/LittleFS toggle already used by the
sibling stm32_w25q.c driver. Needed because NXFFS does not support
rename(), which the companion Dropbear config depends on.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Dropbear's NSH PTY session reaps the child task with waitpid() and needs
CONFIG_SCHED_CHILD_STATUS (which depends on SCHED_HAVE_PARENT). Without it
the session fails with ECHILD right after authentication
("NSH session wait failed: Unknown error 10").
netutils/dropbear now "depends on SCHED_CHILD_STATUS" per the project's
depends-on-over-select policy (apache/nuttx-apps#3648), so enable it in the
sim and esp32c3-devkit Dropbear defconfigs (SCHED_HAVE_PARENT is already
enabled there).
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Dropbear's NSH PTY session reaps the child task with waitpid() and needs
CONFIG_SCHED_CHILD_STATUS, which depends on SCHED_HAVE_PARENT. The
netutils/dropbear Kconfig now depends on SCHED_HAVE_PARENT and selects
SCHED_CHILD_STATUS (apache/nuttx-apps#3648); set SCHED_HAVE_PARENT here so
the dropbear defconfig stays consistent and the session no longer fails
with ECHILD after authentication.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Introduce networking capabilities to the Creator CI20 board by leveraging
the pre-existing dm9000 ethernet driver.
To achieve this, the following changes were made:
- Integrated the jz4780 GPIO module to properly configure and enable the
interrupt pin required by the ethernet controller.
- Added `dm90x0.h` to export the dm9000 initialization function, allowing
the board-specific setup code to initialize the network interface.
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Without SCHED_WAITPID, NSH cannot waitpid() on a spawned builtin application,
so every foreground builtin (e.g. wapi) is run in the background and NSH echoes
"<cmd> [pid:priority]" instead of blocking until it finishes. Enable
CONFIG_SCHED_WAITPID (the setting used by the large majority of nsh defconfigs)
so foreground builtins run synchronously with a correct exit status and no
spurious [pid:priority] echo.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: raul_chen <raul_chen@realsil.com.cn>
Both Ameba WHC boards (pke8721daf, rtl8720f_evb) previously built only via the
make build; the board CMakeLists fell back to a FATAL_ERROR. Wire up the full
vendor-SDK machinery for CMake so `cmake --build` produces the same flashable
nuttx.bin as make, with no change to any shared/arch-common file:
- tools/ameba/env.sh: source it once before cmake. It resolves/auto-fetches
the ameba-rtos SDK + its pinned asdk toolchain (reusing the same helper
scripts the make build uses) and puts the toolchain on PATH, so cmake's
normal compiler probe finds it -- exactly like every other NuttX board's
toolchain. No per-chip hook is added to the shared arch Toolchain.cmake.
- common/ameba/cmake/ameba_sdk.cmake: resolve AMEBA_SDK + asdk dir from that
environment (fall back to the in-tree checkout) and sanity-check the
compiler; included by each arch chip CMakeLists before its SDK-relative
source lists.
- common/ameba/cmake/ameba_board.cmake: the shared mechanism -- autoconf,
libameba_fwlib.a / libameba_wifi.a compiled with the isolated SDK include
set, the image2 linker script, the image2 link flags + EXTRA_LIBS, nuttx.bin
packaging and the flash target. Per-IC inputs are set by each arch chip
CMakeLists.
- common/ameba/tools/{ameba_gen_ldscript,ameba_package,ameba_flash}.sh:
shared shell steps used by both the make and cmake paths so the two produce
identical output; tools/ameba/Config.mk now flashes via ameba_flash.sh too.
- Fix a latent rtl8720f CMakeLists source list bug (ameba_ipc.c was missing
for the WiFi / flash-fs configs).
The make build is unchanged (it still auto-fetches everything, so sourcing
env.sh is optional there and required only for cmake). Verified on hardware:
both boards build, flash and boot with WiFi over the CMake path.
Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: raul_chen <raul_chen@realsil.com.cn>
Provide per-instance capture automonitor lookup for watchdog lower halves
that pass callback context, and avoid selecting an unrelated watchdog when
legacy lower halves provide no context. Update STM32 WWDG lower halves to pass
their instance context so multiple watchdog devices remain distinguishable.
Signed-off-by: hanzhijian <hanzhijian@zepp.com>
Assisted-by: OpenAI Codex
The NP and bootloader images are built from the vendored ameba-rtos SDK.
Rework how that sub-build is configured and driven:
- Materialize the SDK menuconfig once, guarded by a stamp (SDK revision +
board overlay). A no-change rebuild no longer rewrites the SDK .config, so
the SDK stops reconfiguring and recompiling most of the NP image every time;
only the AP-driven "noused" file is regenerated. (ameba_sdk_config.sh)
- Configure the SDK from a two-tier prj.conf-style overlay per board:
ameba_sdk.conf (user-editable) layered under ameba_sdk_force.conf (forced
options such as CONFIG_SHELL=n, always applied last and re-applied after an
edit), so options that must stay fixed cannot be overridden.
- Add "make ameba_menuconfig": edit the SDK options in the SDK's own native
menuconfig UI and save the diff back to the board overlay.
- Silence -Wint-conversion for the vendored SDK sources (both the NuttX fwlib
compile and the SDK NP/boot build): the SDK passes NULL to irq_register()'s
u32 "Data" argument in many places; the warning is suppressed for vendor
code instead of editing every call site.
Signed-off-by: raul_chen <raul_chen@realsil.com.cn>
New RISC-V chip port for the GigaDevice GD32VW55x (Nuclei N307, Wi-Fi 6
and BLE 5.3 combo), with the GD32VW553K-START board.
Core:
- ECLIC interrupt controller, clock tree (160 MHz / 40 MHz HXTAL),
64-bit machine timer, serial (USART0/UART1/UART2) and RTC.
- The instruction cache must be enabled in head.S or the UART drops
characters under load; the mask ROM uses the first 0x200 bytes of SRAM
so the image is linked at 0x20000200; the RTC needs PMU_CTL0.BKPWEN or
the register writes are silently discarded.
- The ECLIC only auto-clears the interrupt pending bit in hardware-vectored
mode, so the trap dispatch clears it for edge-triggered sources or they
re-fire forever (level-triggered peripherals clear their own).
Peripherals: DMA (8 channels), GPIO + EXTI, SPI (optional DMA), I2C0/I2C1
(the new STM32-v2-style IP, not the GD32F4 one), ADC, PWM and input
capture on the timers, both watchdogs, PROGMEM, TRNG and CRC. All use
the standard NuttX lower-half interfaces and direct register access, not
the vendor SPL. Three user LEDs (GPIOC), and a software reset through the
Nuclei SysTimer.
Internal flash: it is a system-in-package NOR die behind the real-time
decryption block, so it is not programmed through the FMC registers -- the
driver goes through the mask ROM API (rom_flash_*), the same way the
vendor code does. PROGMEM can be mounted as LittleFS; the region sits
below the Wi-Fi NVDS and must not overlap it.
Wi-Fi (wlan0), station and softAP:
- The MAC/PHY, RF and WPA supplicant are linked as prebuilt BSD-3
libraries. They are RTOS-agnostic, so the OS binding is a sys_* facade
on NuttX primitives (gdwifi/wrapper_nuttx.c). Critical sections mask by
ECLIC priority threshold, not by disabling every interrupt, or the MAC
misses its microsecond deadlines.
- The lwIP stack of the SDK is not used: the interface is a
netdev_lowerhalf driver driven by the standard tools (wapi, ifup, renew,
ping, dhcpd). EAPOL is handed to the supplicant instead of the IP
stack. The lowerhalf "priority" field is the work-queue id (HPWORK/
LPWORK), not a task priority -- a wrong value makes receive() never run
and every packet is dropped.
- The vendor gives the radio 32 KB of shared SRAM as an extra heap; this
needs CONFIG_MM_REGIONS >= 2 or the kernel silently drops the region.
- The DHCP client needs CONFIG_NETUTILS_DHCPC_BOOTP_FLAGS=0x8000 so the
server answers the OFFER by broadcast.
- softAP (wapi master mode -> wifi_management_ap_start): the single-VIF
firmware does station or AP at a time. Use WPA2, not WPA3: the SAE
handshake is deep on the stack and overflows the elliptic-curve crypto
with the default task stacks, so the Wi-Fi configs raise
CONFIG_INIT_STACKSIZE/DEFAULT_TASK_STACKSIZE.
Vendor SDK: cloned by the build at "context" time, pinned to a validated
commit and patched in place -- so CI can build with nothing preinstalled,
the same pattern as esp-hal-3rdparty. The prebuilt libraries are built
for the hard-float ilp32f ABI.
BLE 5.3, marked EXPERIMENTAL and off by default: the prebuilt libble is an
all-in-one controller plus RivieraWaves host (GAP/GATT/SMP inside the blob)
with no HCI transport, so the port drives the vendor host directly
(ble_adp_*, ble_adv_*, ble_gap_*) instead of registering a bt_driver_s.
The SDK's radio interrupt handlers must be attached to the NuttX IRQ table
(they are reached through the ECLIC hardware vector table in the vendor
build); attaching also keeps --gc-sections from dropping them. It ships
with no configuration; enabling it advertises as "NuttX", connectable.
Boards: gd32vw553k-start with nsh, wapi, sta_softap, periph and littlefs
configurations, and the board added to the CI build list.
Tested on hardware (GD32VW553K-START): NSH, the peripheral drivers
(TRNG entropy and the LEDs exercised), LittleFS (write, read, survives a
reboot), the full Wi-Fi station path (scan, WPA2, DHCP, ping to the
internet), the softAP (a client associates with WPA2, gets an address
from the board's DHCP server, and pings the board), and BLE (advertises as
"NuttX"; a central connects and enumerates the GATT database).
Assisted-by: Claude Opus 4.8
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
The ihm07m1_b16 (FOC motor control) configuration overflows the
STM32F302R8 64 KiB flash region by ~470 bytes, so it no longer links.
Enable GNU Full LTO (CONFIG_LTO_FULL=y); cross-module dead-code
elimination brings the image back under the limit (flash drops from
~66.0 KiB to ~57.7 KiB, 88%).
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This commit introduces a rudimentary architecture and board port for the
MIPS Creator CI20, featuring the dual core Ingenic JZ4780 SoC (MIPS32).
Included in this initial implementation:
- Basic architectural initialization and startup code for the JZ4780 Core 0.
- Minimal configuration required to execute from RAM.
- Early UART/serial console support for basic debugging and NSH output.
- Minimal board-specific configuration for the CI20 target.
- Console output is routed via UART0 on the expansion header.
This establishes basic support for running NuttX on the MIPS CI20.
Further peripherals, optimization, and extended documentation are left for
future iterations or community contributions.
Build and Runtime Deployment Info:
----------------------------------
The baseline can be configured, compiled using the MIPS MTI toolchain,
and loaded via U-Boot using the following commands (replace
<tftp_dir> with your local TFTP root directory).
./tools/configure.sh -l ci20/nsh
make CROSSDEV=mips-mti-elf-
mkimage -A mips -O linux -T kernel -C none -a 0x80000180 -e 0x800004ac \
-n "nx" -d nuttx.bin <tftp_dir>/nuttx.umg
Note: U-Boot must be properly configured for networking (e.g., valid ipaddr,
serverip, and ethaddr environment variables) to fetch the image over TFTP.
Run this from U-Boot prompt:
tftp nuttx.umg && bootm $fileaddr
Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
Permissions (Part 2)
Description:
In kernel builds, any unprivileged process running on the NuttX
device can open /dev/efuse and attempt to read/write fuse content.
Reading the fuses may provide valuable information to an attacker
controlling the user process. The write operation, in extreme cases
where the fuse blocks are not locked, may brick the device.
DISCLAIMER: I tried to be strict with the settings, better to relax them
later if it's needed.
This is part of https://github.com/apache/nuttx/issues/19410
See https://github.com/apache/nuttx/issues/19410
Compiles ok.
Signed-off-by: Catalin Visinescu <catalin_visinescu@yahoo.com>
