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rp23xx: Add external QSPI PSRAM (APS6404) support for the Pimoroni Pico Plus 2.
Adds a driver for the external QSPI PSRAM hanging off QMI chip select 1, such as the 8 MiB APS6404 fitted on the Pimoroni Pico Plus 2. rp23xx_psramconfig() assigns the CS1 pin, reads the device ID over the QMI direct interface to confirm an APS6404-family part (KGD 0x5D), resets it into quad mode and programs the QMI M1 timing/read/write formats so the region at 0x11000000 becomes directly addressable and writable. Because driving the QMI in direct mode stalls execute-in-place from the flash, the detection and (re)configuration code runs from RAM (.time_critical) with interrupts disabled; the command bytes are selected with immediates rather than a .rodata table for the same reason. The register values follow the Raspberry Pi Pico SDK setup_psram(). The detection routine only keeps the QMI DIRECT_CSR synchronization that is strictly necessary. Each candidate busy-wait was removed one at a time and re-verified on hardware: the post-enable "cooldown" waits, the READ_ID TXEMPTY wait (redundant with the BUSY wait after it), and a fixed nop delay proved unnecessary and are omitted. The three BUSY waits that remain -- after the quad-mode nudge, after each READ_ID byte, and after each reset/quad-enable command -- are required and carry a comment explaining that the frame must finish shifting before the chip select is deasserted, and what breaks otherwise (garbage ID reads, or the shared QMI bus wedging). rp23xx_psram_restore() re-applies the M1 configuration and is meant to be called from the flash write path, which goes through the bootrom and reconfigures the shared QMI for chip select 0. rp23xx_heaps.c is wired into the build and now uses the detected size, so the PSRAM is exposed to the memory manager (added to the main heap, used as a separate heap, or as the user heap) and is skipped cleanly when no PSRAM is present. Enabled by default on the pimoroni-pico-2-plus:nsh configuration, where it adds the 8 MiB to the main heap. A documentation page for the Pimoroni Pico Plus 2 is added alongside the other rp23xx boards, covering its serial console, LED, the external PSRAM and how it is exposed to the heap, the supported capabilities and the available configurations, with a photo of the board. Tested on Pimoroni Pico Plus 2 hardware: detection reports the 8 MiB APS6404, the region is read/write across its whole range (ramtest word, half-word and byte passes, marching/pattern/address-in-address), and the heap reports the extra 8 MiB. Assisted-by: Claude Code:claude-opus-4-8 Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
This commit is contained in:
Marco Casaroli
Alan C. Assis
parent
5fd518a27c
commit
8770fbea0f
10 changed files with 691 additions and 8 deletions
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@ -0,0 +1,172 @@
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===============================
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Pimoroni Pico Plus 2
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===============================
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.. tags:: chip:rp2350
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The `Pimoroni Pico Plus 2 <https://shop.pimoroni.com/products/pimoroni-pico-plus-2>`_
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is an RP2350B based board in the Raspberry Pi Pico form factor, with a
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USB-C connector, a large 16 MiB of flash and 8 MiB of external QSPI PSRAM.
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.. figure:: pico-plus-2.jpg
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:align: center
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Features
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========
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* RP2350B microcontroller chip (QFN-80 variant)
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* Dual-core Arm Cortex-M33 processor running up to 150 MHz
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* 520 KiB of internal SRAM
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* 16 MiB of on-board QSPI flash memory
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* 8 MiB of on-board QSPI PSRAM (APS6404) on chip select 1
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* USB-C connector, USB 1.1 host and device support
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* Qwiic / STEMMA QT (I2C) connector
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* SP/CE debug and expansion connectors
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* Reset and BOOTSEL buttons
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* 48 multi-function GPIO pins broken out on castellated and through-hole pads
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* Drag & drop programming using mass storage over USB
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* 12 Programmable IO (PIO) state machines for custom peripheral support
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Serial Console
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==============
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By default a serial console appears on GPIO0 (TX) and GPIO1 (RX). This
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console runs at 115200-8N1.
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The board can be configured to use the USB connection as the serial console.
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See the ``usbnsh`` configuration.
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Buttons and LEDs
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================
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The user LED is controlled by GPIO25 and is configured as autoled by default.
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A BOOTSEL button, which if held down when power is first applied to the board,
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will cause the RP2350 to boot into programming mode and appear as a storage
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device to the computer connected via USB. Saving a ``.uf2`` file to this
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device will replace the flash contents. A separate RESET button is also
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provided.
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PSRAM
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=====
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The distinguishing feature of the Pimoroni Pico Plus 2 is the 8 MiB of
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external QSPI PSRAM (an APS6404 part) hanging off the QMI on chip select 1
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(GPIO47). NuttX detects the PSRAM at boot, switches it to quad mode and
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maps it read/write at ``0x11000000``.
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PSRAM support is enabled by default in the ``nsh`` configuration
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(``CONFIG_RP23XX_PSRAM``), which adds the 8 MiB to the main heap. The
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chip select pin is configured with ``CONFIG_RP23XX_PSRAM_CS1_GPIO`` (47 on
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this board) and the way the PSRAM is exposed to the memory manager (single
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heap, separate heap, or user heap) is selectable. See the
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:doc:`RP23xx PSRAM section <../../index>` for the details of each mode.
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.. note::
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The PSRAM is considerably slower than the internal SRAM. The QMI is
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shared with the flash: writing to the flash goes through the bootrom,
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which reconfigures the QMI for chip select 0 and disturbs the PSRAM
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configuration on chip select 1. ``rp23xx_psram_restore()`` re-applies it
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and is intended to be called from the flash write path after each erase or
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program.
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Supported Capabilities
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======================
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NuttX supports the following Pico Plus 2 capabilities:
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* UART (console port)
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* GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
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* External QSPI PSRAM (8 MiB)
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* I2C
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* SPI (master only)
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* DMAC
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* PWM
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* ADC
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* Watchdog
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* USB device
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* MSC, CDC/ACM serial and composite devices are supported.
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* CDC/ACM serial device can be used for the console.
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* PIO (RP2350 Programmable I/O)
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* Flash ROM Boot
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* SRAM Boot
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* If the Pico SDK is available, a ``nuttx.uf2`` file which can be used in
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BOOTSEL mode will be created.
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* Persistent flash filesystem in unused flash ROM
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Installation
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============
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1. Download and install the toolchain and, optionally, the Raspberry Pi
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Pico SDK (needed to generate the ``nuttx.uf2`` image).
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.. code-block:: console
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$ git clone -b 2.2.0 --recurse-submodules https://github.com/raspberrypi/pico-sdk.git
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$ export PICO_SDK_PATH=<absolute_path_to_pico-sdk_directory>
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2. Configure and build NuttX
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.. code-block:: console
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$ git clone https://github.com/apache/nuttx.git nuttx
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$ git clone https://github.com/apache/nuttx-apps.git apps
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$ cd nuttx
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$ make distclean
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$ ./tools/configure.sh pimoroni-pico-2-plus:nsh
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$ make V=1
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3. Connect the board to the USB port while pressing BOOTSEL. The board will
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be detected as a USB Mass Storage Device. Then copy ``nuttx.uf2`` into
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the device (the same way as standard Pico SDK applications).
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4. To access the console, connect GPIO 0 and 1 to a device such as a
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USB-serial converter, or use the ``usbnsh`` configuration for a console
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over USB CDC/ACM.
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Configurations
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==============
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nsh
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---
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Basic NuttShell configuration (console enabled on UART0, at 115200 bps) with
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the external PSRAM added to the main heap.
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usbnsh
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------
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Basic NuttShell configuration (console enabled via USB CDC/ACM).
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smp
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---
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Basic NuttShell configuration (console enabled on UART0, at 115200 bps) with
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both Arm cores enabled.
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audiopack
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---------
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Configuration for the Pimoroni Pico Audio Pack.
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composite
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---------
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USB composite device configuration.
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usbmsc
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------
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USB mass storage device configuration.
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userled
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-------
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Configuration demonstrating user-controlled LED access.
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Binary file not shown.
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After Width: | Height: | Size: 320 KiB |
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@ -105,4 +105,8 @@ if(CONFIG_RP23XX_FLASH_MTD)
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list(APPEND SRCS rp23xx_flash_mtd.c)
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endif()
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if(CONFIG_RP23XX_PSRAM)
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list(APPEND SRCS rp23xx_psram.c rp23xx_heaps.c)
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endif()
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target_sources(arch PRIVATE ${SRCS})
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@ -9,6 +9,51 @@ config RP23XX_RP2350B
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bool "Use RP2350B variant (QFN-80)"
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default n
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config RP23XX_PSRAM
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bool "External QSPI PSRAM"
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default n
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---help---
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Enable support for external QSPI PSRAM connected to QMI chip
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select 1, such as the 8 MiB APS6404 fitted on the Pimoroni Pico
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Plus 2. The chip is detected and switched to quad mode at boot,
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after which it is directly addressable and writable at
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0x11000000. Configure the chip-select pin under the Board
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Selection menu (RP23XX_PSRAM_CS1_GPIO).
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if RP23XX_PSRAM
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choice
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prompt "PSRAM heap usage"
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default RP23XX_PSRAM_HEAP_SINGLE
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---help---
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How the detected PSRAM is exposed to the memory manager.
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config RP23XX_PSRAM_HEAP_SINGLE
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bool "Add PSRAM to the main heap"
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depends on !MM_KERNEL_HEAP
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---help---
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Add the PSRAM region to the main heap. Requires
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CONFIG_MM_REGIONS greater than 1 so the extra region can be
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registered.
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config RP23XX_PSRAM_HEAP_USER
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bool "PSRAM as the user heap"
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depends on MM_KERNEL_HEAP
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---help---
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Use the PSRAM as the (user) heap and the internal SRAM as the
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kernel heap.
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config RP23XX_PSRAM_HEAP_SEPARATE
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bool "Separate PSRAM heap"
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select ARCH_HAVE_EXTRA_HEAPS
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---help---
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Expose the PSRAM as a separate named heap ("psram") rather than
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adding it to the main heap.
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endchoice
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endif # RP23XX_PSRAM
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config RP23XX_DMAC
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bool "DMAC support"
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default y
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@ -108,3 +108,8 @@ endif
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ifeq ($(CONFIG_RP23XX_FLASH_MTD),y)
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CHIP_CSRCS += rp23xx_flash_mtd.c
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endif
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ifeq ($(CONFIG_RP23XX_PSRAM),y)
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CHIP_CSRCS += rp23xx_psram.c
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CHIP_CSRCS += rp23xx_heaps.c
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endif
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@ -33,6 +33,10 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* The QMI registers share the XIP-QMI peripheral base. */
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#define RP23XX_QMI_BASE RP23XX_XIP_QMI_BASE
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/* Register offsets *********************************************************/
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#define RP23XX_QMI_DIRECT_CSR_OFFSET 0x00000000
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@ -30,15 +30,21 @@
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#include <nuttx/mm/mm.h>
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#include "arm_internal.h"
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#include "rp23xx_psram.h"
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#if defined(CONFIG_RP23XX_PSRAM)
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/****************************************************************************
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* Private Data
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* Pre-processor Definitions
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****************************************************************************/
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static void * const psram_start = (void *)0x11000000ul;
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static const size_t psram_size = 8 * 1024 * 1024;
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/* The PSRAM base address is fixed; the size is whatever rp23xx_psramconfig()
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* detected at boot (0 if no PSRAM is fitted). psramconfig() runs from
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* rp23xx_boardinitialize(), before any of the heap hooks below, so the
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* detected size is always available here.
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*/
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#define PSRAM_START ((void *)RP23XX_PSRAM_BASE)
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/****************************************************************************
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* Public Functions
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@ -56,9 +62,14 @@ static struct mm_heap_s *g_psramheap;
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#if CONFIG_MM_REGIONS > 1
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void arm_addregion(void)
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{
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/* Add the PSRAM region to main heap */
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size_t psram_size = rp23xx_psram_size();
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kumm_addregion(psram_start, psram_size);
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/* Add the detected PSRAM region to the main heap */
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if (psram_size > 0)
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{
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kumm_addregion(PSRAM_START, psram_size);
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}
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}
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#endif
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@ -85,8 +96,8 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
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void up_allocate_heap(void **heap_start, size_t *heap_size)
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{
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*heap_start = psram_start;
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*heap_size = psram_size;
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*heap_start = PSRAM_START;
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*heap_size = rp23xx_psram_size();
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}
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#elif defined (CONFIG_RP23XX_PSRAM_HEAP_SEPARATE)
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@ -97,7 +108,12 @@ void up_allocate_heap(void **heap_start, size_t *heap_size)
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void up_extraheaps_init(void)
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{
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g_psramheap = mm_initialize("psram", psram_start, psram_size);
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size_t psram_size = rp23xx_psram_size();
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if (psram_size > 0)
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{
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g_psramheap = mm_initialize("psram", PSRAM_START, psram_size);
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}
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}
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#endif
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346
arch/arm/src/rp23xx/rp23xx_psram.c
Normal file
346
arch/arm/src/rp23xx/rp23xx_psram.c
Normal file
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@ -0,0 +1,346 @@
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/****************************************************************************
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* arch/arm/src/rp23xx/rp23xx_psram.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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*
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* Driver for the external QSPI PSRAM (an APS6404-family part) fitted on
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* boards such as the Pimoroni Pico Plus 2. It hangs off QMI chip select 1
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* and, once configured, is directly addressable and writable at
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* RP23XX_PSRAM_BASE (0x11000000).
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*
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* The QMI is the same serial interface that serves execute-in-place from the
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* flash on chip select 0. Reprogramming it uses direct (non-XIP) mode,
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* which stalls all XIP fetches, so the detection and configuration code must
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* run from RAM with interrupts disabled -- hence the .time_critical section,
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* which the board linker scripts copy to RAM. The sequence follows the
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* Raspberry Pi Pico SDK's setup_psram().
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <nuttx/irq.h>
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#include "arm_internal.h"
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#include "rp23xx_gpio.h"
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#include "rp23xx_psram.h"
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#include "hardware/rp23xx_qmi.h"
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#include "hardware/rp23xx_xip.h"
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#include "hardware/rp23xx_memorymap.h"
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#ifdef CONFIG_RP23XX_PSRAM
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Detection and (re)configuration touch the QMI in direct mode, which stalls
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* execute-in-place from the flash. The code that does so must therefore run
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* from RAM: the board linker scripts copy the .time_critical section there.
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*/
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#define RP23XX_PSRAM_RAMFUNC \
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__attribute__((section(".time_critical.rp23xx_psram"), noinline))
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/* GPIO function select for the XIP chip-select-1 line (PSRAM). */
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#define RP23XX_GPIO_FUNC_XIP_CS1 9
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/* PSRAM interface width for direct-mode transfers (quad). */
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#define QMI_DIRECT_TX_IWIDTH_Q (2 << RP23XX_QMI_DIRECT_TX_IWIDTH_SHIFT)
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/* Final QMI M1 register values for the APS6404 in quad mode. Computed from
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* the field layout in the RP2350 datasheet to match the Pico SDK:
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*
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* TIMING: COOLDOWN=1, PAGEBREAK=1024, SELECT_HOLD=3, MAX_SELECT=16,
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* MIN_DESELECT=7, RXDELAY=1, CLKDIV=2.
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* RFMT: quad prefix/addr/suffix/dummy/data, 8-bit prefix, 24 dummy bits.
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* RCMD: read prefix 0xeb.
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* WFMT: quad prefix/addr/suffix/dummy/data, 8-bit prefix, no dummy.
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* WCMD: write prefix 0x38.
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*/
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#define RP23XX_PSRAM_M1_TIMING 0x61a07102
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#define RP23XX_PSRAM_M1_RFMT 0x000612aa
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#define RP23XX_PSRAM_M1_RCMD 0x000000eb
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#define RP23XX_PSRAM_M1_WFMT 0x000012aa
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#define RP23XX_PSRAM_M1_WCMD 0x00000038
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/* APS6404 SPI opcodes used during detection and mode switching. */
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#define PSRAM_CMD_READ_ID 0x9f
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#define PSRAM_CMD_RSTEN 0x66
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#define PSRAM_CMD_RST 0x99
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#define PSRAM_CMD_QUAD_ENABLE 0x35
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#define PSRAM_KGD_PASS 0x5d
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/****************************************************************************
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* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static size_t g_psram_size;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psram_apply_format
|
||||
*
|
||||
* Description:
|
||||
* Program the QMI M1 timing/format/command registers and mark the region
|
||||
* writable. Shared by the initial configuration and the post-flash
|
||||
* restore. Runs from RAM.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void RP23XX_PSRAM_RAMFUNC
|
||||
rp23xx_psram_apply_format(void)
|
||||
{
|
||||
putreg32(RP23XX_PSRAM_M1_TIMING, RP23XX_QMI_M1_TIMING);
|
||||
putreg32(RP23XX_PSRAM_M1_RFMT, RP23XX_QMI_M1_RFMT);
|
||||
putreg32(RP23XX_PSRAM_M1_RCMD, RP23XX_QMI_M1_RCMD);
|
||||
putreg32(RP23XX_PSRAM_M1_WFMT, RP23XX_QMI_M1_WFMT);
|
||||
putreg32(RP23XX_PSRAM_M1_WCMD, RP23XX_QMI_M1_WCMD);
|
||||
|
||||
/* Allow the memory-mapped window to accept writes. */
|
||||
|
||||
putreg32(getreg32(RP23XX_XIP_CTRL_BASE) | RP23XX_XIP_CTRL_WRITABLE_M1,
|
||||
RP23XX_XIP_CTRL_BASE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psram_detect
|
||||
*
|
||||
* Description:
|
||||
* Read the PSRAM device ID over the QMI direct interface and return the
|
||||
* detected size in bytes, or 0 if the part does not respond correctly.
|
||||
* Runs from RAM with the caller holding interrupts disabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static size_t RP23XX_PSRAM_RAMFUNC
|
||||
rp23xx_psram_detect(void)
|
||||
{
|
||||
uint8_t kgd = 0;
|
||||
uint8_t eid = 0;
|
||||
size_t size;
|
||||
size_t i;
|
||||
|
||||
/* Enable direct mode at a conservative clock divisor. No BUSY wait is
|
||||
* needed for the previous XIP transfer's cooldown: it drains before the
|
||||
* first chip-select assertion below (verified on hardware).
|
||||
*/
|
||||
|
||||
putreg32((30 << RP23XX_QMI_DIRECT_CSR_CLKDIV_SHIFT) |
|
||||
RP23XX_QMI_DIRECT_CSR_EN, RP23XX_QMI_DIRECT_CSR);
|
||||
|
||||
/* Nudge the part out of any quad-continuation mode left by a prior init by
|
||||
* clocking one quad byte with CS asserted.
|
||||
*/
|
||||
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) |
|
||||
RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N, RP23XX_QMI_DIRECT_CSR);
|
||||
putreg32(RP23XX_QMI_DIRECT_TX_OE | QMI_DIRECT_TX_IWIDTH_Q | 0xf5,
|
||||
RP23XX_QMI_DIRECT_TX);
|
||||
|
||||
/* This BUSY wait is required: the frame must finish shifting before the
|
||||
* chip select is deasserted, else the nudge is truncated, the part stays
|
||||
* in quad-continuation mode, and the ID read below returns garbage so
|
||||
* detection fails (verified on hardware).
|
||||
*/
|
||||
|
||||
while ((getreg32(RP23XX_QMI_DIRECT_CSR) & RP23XX_QMI_DIRECT_CSR_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
(void)getreg32(RP23XX_QMI_DIRECT_RX);
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) &
|
||||
~RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N, RP23XX_QMI_DIRECT_CSR);
|
||||
|
||||
/* Read the identification: command 0x9f followed by six bytes. The
|
||||
* Known-Good-Die marker is byte 5 and the size code is byte 6.
|
||||
*/
|
||||
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) |
|
||||
RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N, RP23XX_QMI_DIRECT_CSR);
|
||||
for (i = 0; i < 7; i++)
|
||||
{
|
||||
putreg32(i == 0 ? PSRAM_CMD_READ_ID : 0xff, RP23XX_QMI_DIRECT_TX);
|
||||
|
||||
/* This BUSY wait is required: the byte must finish shifting in before
|
||||
* DIRECT_RX is read, else the KGD/EID bytes are sampled early as
|
||||
* garbage and detection fails (verified on hardware). A TXEMPTY wait
|
||||
* ahead of it is redundant -- BUSY already covers the whole transfer.
|
||||
*/
|
||||
|
||||
while ((getreg32(RP23XX_QMI_DIRECT_CSR) &
|
||||
RP23XX_QMI_DIRECT_CSR_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
if (i == 5)
|
||||
{
|
||||
kgd = (uint8_t)getreg32(RP23XX_QMI_DIRECT_RX);
|
||||
}
|
||||
else if (i == 6)
|
||||
{
|
||||
eid = (uint8_t)getreg32(RP23XX_QMI_DIRECT_RX);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)getreg32(RP23XX_QMI_DIRECT_RX);
|
||||
}
|
||||
}
|
||||
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) &
|
||||
~(RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N | RP23XX_QMI_DIRECT_CSR_EN),
|
||||
RP23XX_QMI_DIRECT_CSR);
|
||||
|
||||
if (kgd != PSRAM_KGD_PASS)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Reset the device and place it in quad mode: RSTEN, RST, quad-enable. */
|
||||
|
||||
putreg32((30 << RP23XX_QMI_DIRECT_CSR_CLKDIV_SHIFT) |
|
||||
RP23XX_QMI_DIRECT_CSR_EN, RP23XX_QMI_DIRECT_CSR);
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
/* The command byte is selected with a ternary rather than a lookup
|
||||
* table on purpose: a "static const" array is emitted to .rodata in
|
||||
* flash, and reading it here -- while the QMI is in direct mode and
|
||||
* flash is inaccessible -- would fault. An immediate keeps it in RAM.
|
||||
*/
|
||||
|
||||
uint8_t cmd = (i == 0) ? PSRAM_CMD_RSTEN :
|
||||
(i == 1) ? PSRAM_CMD_RST :
|
||||
PSRAM_CMD_QUAD_ENABLE;
|
||||
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) |
|
||||
RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N, RP23XX_QMI_DIRECT_CSR);
|
||||
putreg32(cmd, RP23XX_QMI_DIRECT_TX);
|
||||
|
||||
/* This BUSY wait is required: the command must finish shifting before
|
||||
* the chip select is deasserted. Cutting it short truncates the
|
||||
* RSTEN/RST/quad-enable commands, so the part is not reset into quad
|
||||
* mode and later accesses fail or wedge the shared QMI bus (verified
|
||||
* on hardware). No extra settling delay is needed after CS deassert:
|
||||
* the QMI's own minimum-deselect timing covers it.
|
||||
*/
|
||||
|
||||
while ((getreg32(RP23XX_QMI_DIRECT_CSR) &
|
||||
RP23XX_QMI_DIRECT_CSR_BUSY) != 0)
|
||||
{
|
||||
}
|
||||
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) &
|
||||
~RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N, RP23XX_QMI_DIRECT_CSR);
|
||||
|
||||
(void)getreg32(RP23XX_QMI_DIRECT_RX);
|
||||
}
|
||||
|
||||
putreg32(getreg32(RP23XX_QMI_DIRECT_CSR) &
|
||||
~(RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N | RP23XX_QMI_DIRECT_CSR_EN),
|
||||
RP23XX_QMI_DIRECT_CSR);
|
||||
|
||||
/* Decode the size from the EID byte (APS6404 family). */
|
||||
|
||||
size = 1024 * 1024;
|
||||
if (eid == 0x26 || (eid >> 5) == 2)
|
||||
{
|
||||
size *= 8;
|
||||
}
|
||||
else if ((eid >> 5) == 0)
|
||||
{
|
||||
size *= 2;
|
||||
}
|
||||
else if ((eid >> 5) == 1)
|
||||
{
|
||||
size *= 4;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psramconfig
|
||||
****************************************************************************/
|
||||
|
||||
size_t RP23XX_PSRAM_RAMFUNC
|
||||
rp23xx_psramconfig(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
size_t size;
|
||||
|
||||
rp23xx_gpio_set_function(CONFIG_RP23XX_PSRAM_CS1_GPIO,
|
||||
RP23XX_GPIO_FUNC_XIP_CS1);
|
||||
|
||||
flags = up_irq_save();
|
||||
|
||||
size = rp23xx_psram_detect();
|
||||
if (size != 0)
|
||||
{
|
||||
rp23xx_psram_apply_format();
|
||||
}
|
||||
|
||||
up_irq_restore(flags);
|
||||
|
||||
g_psram_size = size;
|
||||
return size;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psram_size
|
||||
****************************************************************************/
|
||||
|
||||
size_t rp23xx_psram_size(void)
|
||||
{
|
||||
return g_psram_size;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psram_restore
|
||||
****************************************************************************/
|
||||
|
||||
void RP23XX_PSRAM_RAMFUNC
|
||||
rp23xx_psram_restore(void)
|
||||
{
|
||||
if (g_psram_size != 0)
|
||||
{
|
||||
rp23xx_psram_apply_format();
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RP23XX_PSRAM */
|
||||
89
arch/arm/src/rp23xx/rp23xx_psram.h
Normal file
89
arch/arm/src/rp23xx/rp23xx_psram.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/****************************************************************************
|
||||
* arch/arm/src/rp23xx/rp23xx_psram.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_RP23XX_RP23XX_PSRAM_H
|
||||
#define __ARCH_ARM_SRC_RP23XX_RP23XX_PSRAM_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The QSPI PSRAM is mapped through QMI chip select 1 at this address */
|
||||
|
||||
#define RP23XX_PSRAM_BASE 0x11000000
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psramconfig
|
||||
*
|
||||
* Description:
|
||||
* Detect and initialise the external QSPI PSRAM on QMI chip select 1.
|
||||
* Assigns the CS1 function to CONFIG_RP23XX_PSRAM_CS1_GPIO, reads the
|
||||
* device ID to confirm an APS6404-family part is present, switches it to
|
||||
* quad mode and programs the QMI M1 read/write formats so the region at
|
||||
* RP23XX_PSRAM_BASE becomes directly addressable (and writable).
|
||||
*
|
||||
* Returned Value:
|
||||
* The size of the detected PSRAM in bytes, or 0 if no PSRAM was found.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t rp23xx_psramconfig(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psram_size
|
||||
*
|
||||
* Description:
|
||||
* Return the size in bytes detected by the last rp23xx_psramconfig(), or 0
|
||||
* if PSRAM is absent or has not been configured.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t rp23xx_psram_size(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp23xx_psram_restore
|
||||
*
|
||||
* Description:
|
||||
* Re-apply the QMI M1 (PSRAM) format and timing registers. Programming
|
||||
* the flash goes through the bootrom, which reconfigures the shared QMI
|
||||
* interface for chip select 0; this restores the CS1 configuration
|
||||
* afterwards so the memory-mapped PSRAM keeps working across a flash
|
||||
* erase or program. Runs from RAM and does nothing when no PSRAM was
|
||||
* detected.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void rp23xx_psram_restore(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_RP23XX_RP23XX_PSRAM_H */
|
||||
|
|
@ -28,12 +28,14 @@ CONFIG_EXAMPLES_HELLO=y
|
|||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_RAM_SIZE=532480
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_READLINE_CMD_HISTORY=y
|
||||
CONFIG_RP23XX_PSRAM=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=9
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue