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arch/mips/jz4780: Add support for L2 cache operations

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The common mips_cache.S only handles generic L1 cache operations and
does not support L2 (secondary) cache operations required for the
JZ4780 target.

This commit introduces mti_cache.S to support both L1 and L2 cache
operations.

The mti_cache.S implementation is BSD licensed from Imagination
Technologies.

Signed-off-by: Lwazi Dube <lwazeh@gmail.com>
This commit is contained in:
Lwazi Dube 2026-07-20 19:00:19 -04:00 • committed by Xiang Xiao
parent c0e796e55d
commit 784035a3e9
10 changed files with 1213 additions and 19 deletions
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8
boards/mips/jz4780/ci20/configs/net/defconfig
View file

@ -15,6 +15,7 @@ CONFIG_16550_UART0_CLOCK=14745600
CONFIG_16550_UART0_IRQ=51
CONFIG_16550_UART0_SERIAL_CONSOLE=y
CONFIG_16550_UART=y
CONFIG_ALLOW_BSD_COMPONENTS=y
CONFIG_ARCH="mips"
CONFIG_ARCH_BOARD="ci20"
CONFIG_ARCH_BOARD_CI20=y
@ -40,13 +41,6 @@ CONFIG_FS_PROCFS=y
CONFIG_GRAN=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_MIPS32_DCACHE=y
CONFIG_MIPS32_DCACHE_SIZE=32768
CONFIG_MIPS32_DLINE_SIZE=32
CONFIG_MIPS32_ICACHE=y
CONFIG_MIPS32_ICACHE_SIZE=32768
CONFIG_MIPS32_ILINE_SIZE=32
CONFIG_MIPS32_KSEG0_IBASE=0x80000000
CONFIG_MQ_MAXMSGSIZE=64
CONFIG_NET=y
CONFIG_NETDEV_IFINDEX=y

8
boards/mips/jz4780/ci20/configs/nsh/defconfig
View file

@ -15,6 +15,7 @@ CONFIG_16550_UART0_CLOCK=14745600
CONFIG_16550_UART0_IRQ=51
CONFIG_16550_UART0_SERIAL_CONSOLE=y
CONFIG_16550_UART=y
CONFIG_ALLOW_BSD_COMPONENTS=y
CONFIG_ARCH="mips"
CONFIG_ARCH_BOARD="ci20"
CONFIG_ARCH_BOARD_CI20=y
@ -37,13 +38,6 @@ CONFIG_FS_PROCFS=y
CONFIG_GRAN=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_MIPS32_DCACHE=y
CONFIG_MIPS32_DCACHE_SIZE=32768
CONFIG_MIPS32_DLINE_SIZE=32
CONFIG_MIPS32_ICACHE=y
CONFIG_MIPS32_ICACHE_SIZE=32768
CONFIG_MIPS32_ILINE_SIZE=32
CONFIG_MIPS32_KSEG0_IBASE=0x80000000
CONFIG_MQ_MAXMSGSIZE=64
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512