Add LPTIM 1, 3, 4, 5 support. Based on STM32H7. setperiod and
setcompare have been made to wait for the auto-reload value to
be applied before returning.
6 is absent since generic stm32 configs for a 6th LPTIM are not
present yet. 2 is absent for no good reason besides maybe
that it's in a different RCC APB register. I am not adding
support last-minute without more testing. The build fails
noisily when LPTIM2 is enabled so the shortcoming is clear.
Corrected some RCC definitions. They are needed for selecting the LPTIMx
clock source. This is not done in the LPTIM driver. It is done
outside and the definitions should ideally be correct for that.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Co-authored-by: Farzan Farhangian <farzanfarhangian@geotab.com>
Adds PSEUDOTERM as selected Kconfig option on lvglterm demo defconfigs.
Required after changes on lvgl_term example app.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
The fixed list of type names holds neither uint64_t nor any NuttX
typedef, so declarations using them went unchecked.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
The brace was compared against the line before it rather than the line
the statement began on, so a macro broken over two lines was reported.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
imxrt_transmit() handed out the lowest free TX mailbox. FlexCAN breaks an
arbitration tie between mailboxes holding equal CAN IDs by taking the lowest
mailbox number, so refilling a just-drained low mailbox while older frames
are still pending in higher ones puts the newer frame on the wire first.
imxrt_txdone_work() re-polls after each individual TX completion, which is
exactly the condition that triggers it.
Every frame of a multi-frame transport transfer carries the same CAN ID, so
this reorders transfers. On a DroneCAN bus the receiver sees a broken toggle
bit and discards the transfer: measured on the wire, a 6-frame message from
an i.MX RT1176 failed 82% of the time, while a node on the same bus running
a different controller was flawless over the same capture.
Hand out a mailbox above every pending one instead, and wrap back to the
bottom only once the ring has drained. Ordering then holds for any transfer
length; the cost is that the ring stalls at a wrap rather than refilling
immediately.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Correct the switch case label indentation in imxrt_netinitialize(), the brace
alignment in imxrt_ioctl(), and the indentation of the ERR005829 workaround
statements so imxrt_flexcan.c passes nxstyle. The last of these is only
reported since commit c81cc02e83.
These predate this series; CONTRIBUTING.md section 2.1 asks that modified
files be brought into compliance even where the contributor did not introduce
the problem.
Whitespace only, no functional change: `git diff -w` against the parent is
empty.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Select LIBC_ATOMIC_ARCH for TriCore when not using Tasking toolchain,
so that the tricore arch-atomic implementation is used instead of
the toolchain builtin.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Replace ILLD intrinsics (__swap, __ld32, __cmpAndSwap) with inline
assembly functions (tricore_atomic_swap, tricore_atomic_cmpswap) to
remove the dependency on IfxCpu_Intrinsics.h.
Also fix the expect parameter type to use volatile void * to match
the declaration in atomic.h, avoiding type conflicts.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Add an NXTerm framebuffer configuration for QEMU and Intel64 hardware.
Enable USB keyboard input, PCI serial logging, CPython, and serial fallback.
Signed-off-by: raiden00pl <raiden00@railab.me>
PCI endpoints cannot perform memory transactions when a bridge in
their hierarchy has memory forwarding or bus mastering disabled.
Firmware may leave these bits clear when handing a device over
after PXE boot.
Enable both bits on every parent bridge before enabling the
endpoint.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Only lines beginning with a C keyword were checked, so an assignment or
a call could sit at any column.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add HSI48 clock selection, USB pull-up control, automatic CDC/ACM registration during board bring-up, USB test configurations, and board documentation.
Assisted-by: OpenAI Codex
Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
libelf_elfsize() takes textalign and dataalign from the section headers,
which only the ET_REL path walks. An ET_DYN object is sized from its
program headers instead, so both fields stay at zero, and the allocation
a few lines later asks for that alignment:
loadinfo->textalloc = lib_memalign(loadinfo->textalign, ...);
Zero is not a valid alignment, and every path that receives it divides by
it. mm_memalign() accepts zero as a power of two, because 0 & -0 is 0,
then takes the "alignment <= MM_ALIGN" branch and evaluates
"((uintptr_t)ptr) % alignment" in a DEBUGASSERT. With
CONFIG_MM_HEAP_MEMPOOL and a pool that fits the request the object never
reaches that branch and gets ALIGN_UP(blk, 0) instead, which is
((blk - 1) / 0) * 0.
On Cortex-M this is usually invisible: UDIV returns zero for a division
by zero unless CCR.DIV_0_TRP is set, which NuttX does not set, so the
assertion compares zero against zero and passes. It is a SIGFPE on the
simulator, and the mempool path returns a null pointer wherever the
division yields zero, which the loader reports as -ENOMEM.
Ask for a natural word when the program headers gave nothing. p_align is
the linker's page granularity, not a section requirement, so honouring it
would cost a page per module for no gain, and the sections of a shared
object need no more than a word.
Built for mps3-an547:picostest, which is CONFIG_ELF with CONFIG_PIC.
Runtime evidence on hardware follows.
Assisted-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Signed-off-by: Marco Casaroli <marco.casaroli@gmail.com>
A residue modulo four expresses neither the indentation unit nor the
alignment of case logic, and all of it was disabled from the first
switch to the end of the enclosing function.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
This patch get some fixes from ESP-IDF to fix a rolling issue
that happens on big resolution LCDs such as 800x480 LCDs.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
Assisted-by: Claude Code
The CH422G offers eight bi-directional pins, IO0-IO7, and four open-drain
outputs, OC0-OC3. It appears on boards that have run out of usable GPIOs
once a parallel RGB panel has taken its share, the Waveshare
ESP32-S3-Touch-LCD-7 among them, where it holds the panel and touch
controller in and out of reset and switches the backlight.
Two things about the device do not fit the shape a register-per-address
I2C driver usually takes, and both are handled here rather than pushed on
to board logic:
- A register is selected by the I2C address the transfer is addressed
to, not by a register address written ahead of the data. Each access
carries a single byte to one of four addresses.
- None of the write-only registers can be read back, so the driver
keeps a shadow copy of each and updates it in step with the device.
IO0-IO7 have no individual direction control; one bit of the system
parameter register drives the whole group. The driver records the
direction asked of each pin and puts the group in output mode once at
least one of them is an output, which is what a board that drives some of
the pins would expect. Reading a pin of a group held in output mode
reports the value last written, because the hardware cannot report the
level, and that is documented rather than hidden.
The four open-drain outputs are presented as pins 8-11 of the same
ioexpander_dev_s so that one instance covers the chip, which means
CONFIG_IOEXPANDER_NPINS must be at least 12.
Builds clean with no new warnings on esp32s3-touch-lcd7:usbnsh and passes
nxstyle.
Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
Assisted-by: Claude Code
Wire the shared Ameba ADC driver into the RTL8721F build: add the
per-chip ameba_adc_chip.h (12 channels, CH0..CH7 external on
PA20,PA19,PA18,PA17,PA15,PA14,PA13,PA12, PINMUX function 5), the
board ADC table and registration, the adc board config, and build
glue for both cmake and make (including the fwlib RAM-layer
ameba_adc.c in ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Wire the shared Ameba ADC driver into the RTL8720F build: add the
per-chip ameba_adc_chip.h (9 channels, CH0..CH5 external on
PA13..PA18, PINMUX function 5, APB clock on bit24), the board ADC
table and registration, the adc board config, and build glue for
both cmake and make (including the fwlib RAM-layer ameba_adc.c in
ameba_board.mk). Document the ADC on the board index.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
Add a NuttX ADC lower-half for the Ameba SoC family, wired for the
amebadplus/pke8721daf as /dev/adc0. The driver uses the fwlib ROM
API and drives on-demand polled conversions via ADC_ReceiveBuf with
the hardware auto channel-switch FIFO, because amebadplus disables the
ADC software-trigger path. Per-chip wiring (channel count, pinmux
function id, APB clock bits, optional aux clock) lives in a chip
header so a new IC only supplies its own values without touching the
shared driver.
Reports raw conversion codes per the NuttX convention (12-bit
effective, 0..~3876 for 0..3.3V), consistent with the STM32/i.MXRT/
Tiva ADC drivers.
Verified on hardware: 0V->121, 3.3V->3876 on CH0(PB19) while
CH1(PB18) held steady, confirming sampling, full-scale and
multi-channel switch-list isolation.
Signed-off-by: dechao_gong <dechao_gong@realsil.com.cn>
Assisted-by: Claude <noreply@anthropic.com>
1. use _atomic as wrapper because if _Atomic empty, may affects the compilation of other files:
2. for clang builtin function, it donot accept param with keyword "_Atomic"
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Rename atomic_fetch_add/sub/or/and/xor to atomic_add/sub/or/and/xor
to avoid conflicts with the C/C++ standard library naming. The
atomic_fetch_xxx naming is reserved by the standard; keeping it causes
function name conflicts when source files indirectly include both
<nuttx/atomic.h> and <atomic>/<stdatomic.h>.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
The reason for using builtin atomic is that in C++, when include <atomic> in <nuttx/atomic.h> easily conflicts with third-party function libraries. We wanted to completely separate the implementation of <nuttx/atomic.h>.
There are two points:
1. use builtin function directly.
2. Without the standard library implementation, need implement "atomic_fetch_xxx", leading conflicts with the standard library used by third-party programs, introducing redefinition issues and requiring name changes.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
1. for tasking, map __c11_atomic_xxx as tasking_atomic_xxx
2. for msvc, map _Interlocked_xxx as msvc_atomic_xxx
3. if no special map, use gcc/clang as default as they are most widely used.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Replace atomic_load with atomic_read in call sites to use the
unified interface defined in <nuttx/atomic.h>.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Select LIBC_ATOMIC_IRQ at the architecture level (ARM7TDMI, ARM926EJS,
ARMv6M) for chips that do not support atomic operations natively. This
covers all ARM7TDMI, ARM926EJS, and Cortex-M0 based chips automatically.
Also select LIBC_ATOMIC_IRQ for specific non-ARM architectures (AVR,
RISC-V, SPARC, Xtensa) that lack atomic instruction support.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Split the atomic implementation into three files:
- arch_atomic.h: Shared macros (STORE, LOAD, etc.) using atomic_lock()/
atomic_unlock() abstraction
- arch_atomic_irq.c: 32-bit atomic functions using IRQ disable (conditional
on CONFIG_LIBC_ATOMIC_IRQ via Make.defs)
- arch_atomic64.c: 64-bit atomic functions using spinlock (always compiled,
multi-core safe). The __atomic_* functions are always provided (GCC
runtime helpers), while nx_atomic_* functions are conditional on
!CONFIG_LIBC_ATOMIC_TOOLCHAIN.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Refine the atomic Kconfig to support multiple backends:
LIBC_ATOMIC_TOOLCHAIN (compiler builtins), LIBC_ATOMIC_ARCH (arch
instructions), and LIBC_ATOMIC_IRQ (interrupt disable). Rename
arch_atomic.c to arch_atomic_irq.c since it supports the IRQ backend.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Tricore gcc does not support atomic interface but some users need to
use atomic operations, so support atomic function using tricore arch
instructions (__cmpAndSwap/__swap/__ld32).
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
The atomic implementation of machine/arch_atomic.c is achieved by
switching interrupts. This version does not support SMP.
Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
The overloads of std::abs are defined in cstdlib and cmath according to
the C++ standard.
Without these new definitions the `int std::abs(int)` function was
selected for all argument types resulting in a truncation of the return
values.
Signed-off-by: Moritz Pflanzer <moritz@chickadee-engineering.com>
The BSD string functions take a word path only when both pointers are
aligned, and a byte path otherwise. A pair at the same offset from a
boundary takes the byte path even though copying or comparing a few leading
bytes aligns both at once, since aligning one aligns the other.
Add MISALIGNED(), which asks whether two pointers disagree about where a
boundary falls, and walk an agreeing pair up to the boundary before the
existing path selection. MISALIGNED4() does the same for the 4-byte path,
so a pair that is 4-byte but not 8-byte aligned reaches the wide path
instead of the middle one. No existing line changes: the walk is a new step
ahead of the current decisions. A pair at differing offsets still takes the
byte path, since no single boundary serves both.
Measured on an EIC7700 EVB (EIC7700X, RV64GC, 1.4GHz) with the BSD string
functions selected and the RISC-V assembly ones disabled, using the
benchmark in apps#3706, medians of 3 runs in MB/s at its largest size:
equal offset aligned
memcpy 414 -> 4148 10.0x 4214 -> 4208
memcmp 41 -> 361 8.8x 362 -> 360
strncmp 28 -> 202 7.4x 207 -> 207
strcmp 42 -> 273 6.5x 278 -> 276
strncpy 377 -> 1676 4.5x 1824 -> 1748
stpncpy 376 -> 1654 4.4x 1843 -> 1724
stpcpy 551 -> 1833 3.3x 1970 -> 1939
memccpy 650 -> 2012 3.1x 2478 -> 2016
strcpy 636 -> 1837 2.9x 1678 -> 1965
Cases the walk never runs for move in both directions by up to a third, the
largest being memccpy at differing offsets, 648 -> 414. Their code is
unchanged, so that is code placement rather than an effect of the change.
The change is architecture independent but has only been measured on
RV64GC. Word size, alignment cost and byte loop codegen all differ
elsewhere, so the balance wants measuring on other architectures.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Justin Hammond <justin@dynam.ac>
Add a real ESP32-S3 touchscreen photograph to the NXStore guide so the
companion documentation shows the package catalog on target hardware.
Assisted-by: OpenAI Codex:gpt-5.6-sol
Signed-off-by: aviralgarg05 <gargaviral99@gmail.com>
The receive path hands incoming packets to the stack and transmits
whatever reply comes back, without checking that a TX descriptor is
free, though the poll path checks exactly that. Under sustained
bidirectional load the reply lands on a descriptor the DMA still owns:
with assertions built in, a panic from the RX work queue
(DEBUGASSERT(des3 & RD_OWN), reproduced under a VNC pointer flood);
without them, corruption of a frame in flight.
A reply to received data is almost always an acknowledgement, and a
peer that misses one retransmits; overwriting a frame the DMA owns
recovers from nothing. Drop the reply when the ring is full, using the
same descriptor test the poll path already trusts.
Assisted-by: Claude:opus-5
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
On the linum-stm32h753bi, Ethernet throughput collapses in proportion to
what the display panel is showing. With the LTDC scanning a black screen
a 1.2 MiB TCP transfer to a wired peer takes 0.7 s; solid white takes 20
to 55 s and noise over 130 s, all at the same negotiated 100BASE-TX full
duplex, with the same bytes read from the same SDRAM. The display's
switching couples into the PHY hard enough to corrupt 100BASE-TX
signalling, and TCP grinds through the losses at whatever rate survives.
10BASE-T signals at 2.5 V with Manchester coding at a tenth of the
frequency, and does not care: black, white and noise all move at the
link rate. The same transfer that took five minutes with the display
rendering takes 5.6 seconds.
Restricting the ANAR advertisement is deliberately not the same as
disabling autonegotiation. A forced MCR leaves the partner to parallel
detection, which cannot sense duplex and picks half, a genuine
mismatch, verified here to stall bulk traffic completely. Advertising
only 10BASE-T full duplex keeps the negotiation and lands both ends on
the same mode.
Also fix the never-compiled !CONFIG_STM32_AUTONEG path, which still
called stm32_phywrite(); this driver has only ever had mdio_write().
And say what was negotiated at link-up: a duplex mismatch looks exactly
like a bad cable, and nothing else reports which of the two it is.
The vnc configuration of the linum board enables the new option, and its
packet pool sizing from a few commits ago stays: at any link speed, 24
buffers of 196 bytes was never going to stream a display.
Assisted-by: Claude:opus-5
Signed-off-by: Jorge Guzman <jorge.gzm@gmail.com>
The check added by the preceding commit reports ten braces in nxstyle.c
that do not line up with the brace they close, and a comment that does
not share the column of the run it belongs to. Bring the whole file
into line with the standard, so that the checks added by the commits
that follow are not introduced against a file that breaks them.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Braces were only tested against a multiple of the indentation unit, so
one at the wrong level still passed.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add CRC header based on arch/arm/src/common/stm32/hardware/stm32_crc.h
and select STM32_HAVE_CRC in Kconfig
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
Posix open() calls to /dev/adc# were hanging often due
to the ready loop check at the end of adc_enable() never
returning. According to ES0565 document, at least 4 ADC
clock cycles must pass between the time we waited for
calibration to end and before we can set ADEN. This will
depend on what clock is set for ADC. So to ensure enough
time passes, we are adding a short delay (so that even a
slow clock will work). Also, we are clearing the ADRDY
flag before hand to ensure we are detecting a fresh event.
The delay to wait for the voltage regulator is also
increased to account for extra time required in
non-ideal conditions.
Signed-off-by: Liam Howatt <liamhowatt@geotab.com>
The 20 selects that were repeated identically in every STM32_STM32H7*
helper are moved to STM32_H7_PERIPHERALS, leaving only the chip
specific ones in the per-family helpers.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
Add a driver for the STM32H7R/S XSPI controller. The driver implements
the NuttX QSPI interface and supports the memory-mapped mode used to
execute code from the external flash.
Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: OpenAI Codex:gpt-5
