BREAKING CHANGE: STM32WL5 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32WB non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32U5 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32L5 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32L4 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32H7 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32H5 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: STM32F7 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.
Signed-off-by: raiden00pl <raiden00@railab.me>
up_disableusartint() saves USART interrupt state from hardware CTL0-CTL3
registers but omits the CTL selector bits (bits 24-27) in the encoded
ie value. When up_restoreusartint() later restores interrupts, it uses
ie >> 24 to determine which CTL register to write. Without selector bits
this evaluates to 0, so no CTL register is updated and all interrupt
enables (including RBNEIE) are permanently lost.
This causes RX interrupts to never fire after any call to up_putc()
(e.g. via syslog), making the serial console unable to receive input.
Fix by adding the corresponding CTL selector bit (USART_CFG_CTLx_INT
<< USART_CFG_SHIFT) whenever a CTL register has active interrupt bits.
Signed-off-by: lccosy <1191294205@qq.com>
up_rtc_rdalarm() computed tv_sec and tv_nsec from two separate
evaluations of rt_timer_time_us() + offset + deadline. The RT timer
advances between the two calls, so a read that straddles a second
boundary yields an inconsistent timespec.
Compute the microsecond value once into a local variable and derive
both fields from that single snapshot.
Signed-off-by: yushuailong <yyyusl@qq.com>
esp_rtc_rdalarm() computed tv_sec and tv_nsec from two separate
evaluations of esp_hr_timer_time_us() + offset + deadline. The
high-resolution timer advances between the two calls, so a read that
straddles a second boundary yields an inconsistent timespec.
Compute the microsecond value once into a local variable and derive
both fields from that single snapshot.
Signed-off-by: yushuailong <yyyusl@qq.com>
esp_rtc_rdalarm() computed tv_sec and tv_nsec from two separate
evaluations of esp_hr_timer_time_us() + offset + deadline. The
high-resolution timer advances between the two calls, so a read that
straddles a second boundary yields an inconsistent timespec.
Compute the microsecond value once into a local variable and derive
both fields from that single snapshot.
Signed-off-by: yushuailong <yyyusl@qq.com>
BREAKING CHANGE: Convert the legacy STM32 F1/F2/F3/F4/G4/L1 port to the concrete
family selectors while keeping the shared STM32 selector hidden.
Legacy STM32 family selector Kconfig symbols were split by
concrete STM32 sub-family. Out-of-tree defconfigs and code must update
CONFIG_ARCH_CHIP_* selections to the new family-specific selectors.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: CONFIG_STM32F7_QUADSPI and CONFIG_STM32H7_QUADSPI are
renamed to CONFIG_STM32F7_QSPI and CONFIG_STM32H7_QSPI. Out-of-tree F7/H7
board configurations must update the symbol name.
Standardize the F7/H7 QSPI enable symbol on the QSPI name (the QUADSPI and
QSPI peripherals are the same IP block). Only the Kconfig enable symbol and
its CONFIG_ references are renamed; the QUADSPI hardware register/pin/DMA
macros are unchanged.
Signed-off-by: raiden00pl <raiden00@railab.me>
__start is the kernel boot entry for each chip, while _start (defined
in crt0.c) is the correct C runtime entry point for ELF executables.
Signed-off-by: leisiji <2265215145@qq.com>
Add `EXTRA_LIB_DEPS` to the simulator nuttx target prerequisites.
This lets Make notice when an extra application library, such as a Rust
static library rebuilt by Cargo, has changed and ensures the final
simulator binary is relinked.
Signed-off-by: Shoji Tokunaga <toku@mac.com>
Add NULL check for g_uart_devs[i] before accessing ->priv in
arm_earlyserialinit() loop. When a USART is not enabled in defconfig,
g_uart_devs[i] is NULL, causing a HardFault crash during early boot.
The bug occurs because the original code only checked g_uart_devs[i]->priv
without first verifying g_uart_devs[i] is not NULL. On Cortex-M4, NULL
pointer dereference reads from Flash vector table (0x00000000 maps to
0x08000000), returning a function pointer that causes BusFault when
written to.
This fix matches the existing NULL check pattern used in arm_serialinit()
at line 2835 of the same file.
Tested on mplant-gd32f450 board with only USART5 enabled in defconfig.
Before fix: HardFault at boot (IPSR=3, PC=0x080003e0)
After fix: System boots normally to NSH Shell
Signed-off-by: lccosy <1191294205@qq.com>
The previous up_backtrace() relied entirely on host_backtrace() (a thin
wrapper around glibc's backtrace()), which can only unwind the host
thread that calls it. As a result, when assert / dump_tasks() walked the
task list and called sched_dumpstack() for every task, every task other
than the currently-running one returned a zero-length backtrace, and the
output was silently dropped. In practice this meant that on sim only
the crashing task ever produced a usable trace.
Fix this by walking the frame-pointer chain ourselves whenever the
target tcb is not the running task. Because sim's setjmp/longjmp is
provided by NuttX itself (libs/libc/machine/sim/arch_setjmp_*.S) and not
by host libc, the rbp/rsp/rip (or arm fp/sp/pc) saved in tcb->xcp.regs
are plain unmangled pointers, identical across Linux, macOS and Windows
hosts. The frame layout ([fp]=prev fp, [fp+1]=return address) is also
shared by every host ABI sim supports (x86, x86_64, ARM, ARM64).
The walker validates that fp lies inside the task's stack and is
properly aligned, and stops when fp[0] is NULL, so a corrupted stack
cannot make us read out of bounds. The running-task path is unchanged
and still uses host_backtrace() so DWARF unwinding through host
libraries continues to work.
Requires CONFIG_FRAME_POINTER=y so the compiler emits a usable fp link.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
usrsock_ioctl_handler() copies req->arglen bytes from the request
payload into the fixed-size usrsock->out buffer without validating
that the payload fits either the received request or the destination
buffer. This is the same class of vulnerability as the one already
fixed in nrf91_modem_sock.c (commit a43fb69283).
Add three checks before the copy:
- len >= sizeof(*req): ensure the full request header is present.
- copylen <= len - sizeof(*req): payload must fit the received data.
- copylen <= SIM_USRSOCK_BUFSIZE - sizeof(*ack): payload must fit
the destination buffer.
Signed-off-by: hanzj <hanzjian@zepp.com>
nrf91_usrsock_ioctl_handler() copies req->arglen bytes from the
request payload into the fixed-size usrsock->out buffer without
validating that the payload actually fits either the received
request or the destination buffer. A crafted ioctl request with
an inflated arglen triggers:
1. OOB read — memcpy reads past the end of the received request.
2. OOB write — memcpy writes past the end of usrsock->out.
Add three checks before the copy:
- len >= sizeof(*req): ensure the full request header is present.
- copylen <= len - sizeof(*req): payload must fit the received data.
- copylen <= sizeof(usrsock->out) - sizeof(*ack): payload must fit
the destination buffer.
The recvfrom handler in the same file already performs the equivalent
buffer-size check (line 892). Fixes#18515.
Signed-off-by: hanzj <hanzjian@zepp.com>
This change causes the frame buffer allocation to use the connected
device's physical resolution by default. The user also has the option to
force a request for a different, compile-time selected resolution if the
physical display can support something else the user would prefer.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Add a custom aarch64 Mach-O Rust target for macOS sim builds and use it
instead of an Apple Darwin Rust target. This keeps Rust cfg values aligned
with NuttX while producing Mach-O objects required by the simulator link.
Also align sim host handling for aarch64 Linux by detecting `aarch64` as
`HOST_ARM64` and avoiding x86-specific `-mcmodel` and `-no-pie` options
on ARM64 hosts.
Signed-off-by: Shoji Tokunaga <toku@mac.com>
Add the AM62x architecture support needed to boot NuttX on TI K3
AM62x platforms. This includes the chip integration, memory map, IRQ
definitions, low-level console support, boot code, and the AM62x 16550
serial lower half.
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
AM62x enters NuttX through EL2 before dropping to EL1. Enable the
GICv3 system register interface for lower exception levels during the
EL2 handoff so EL1 can use the CPU interface without depending on
firmware state.
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
Guard CMN_UCSRCS += arm_perf.c in arch/arm/src/armv7-r/Make.defs so that arm_perf.o is not added twice during flat builds, preventing the duplicate target make error.
Signed-off-by: Nazmi Aras <nazmi.aras@t3gemstone.org>
This commit introduces basic support for the T3 Gemstone O1 (t3-gem-o1)
development board, including board configuration, linker scripts, and
drivers for NSH. Currently only UART console is supported.
All necessary files and configurations are added to enable building and
running NuttX on this TI AM67-based board.
Co-authored-by: Emre Cecanpunar <emreleno@gmail.com>
Co-authored-by: Abdullah Türkmen <abdullahturkmen@protonmail.com>
Co-authored-by: Muhammet Onur Bayraktar <mobayraktar@t3gemstone.org>
Co-authored-by: Bayram Akay <bakay@t3gemstone.org>
Co-authored-by: Nazmi Aras <nazmi.aras@t3gemstone.org>
Signed-off-by: Erkan Vatan <evatan@t3gemstone.org>
This commit introduces basic support for running NuttX on
main domain R5F core of TI AM67 chips, including irq, mpu, pinmux,
timer, and serial configurations. Currently only UART console is
supported. NuttX can be loaded into R5F core from U-Boot or Linux
via RemoteProc.
Co-authored-by: Emre Cecanpunar <emreleno@gmail.com>
Co-authored-by: Abdullah Türkmen <abdullahturkmen@protonmail.com>
Co-authored-by: Muhammet Onur Bayraktar <mobayraktar@t3gemstone.org>
Co-authored-by: Bayram Akay <bakay@t3gemstone.org>
Signed-off-by: Erkan Vatan <evatan@t3gemstone.org>
Previously, arm_mpu.c was only compiled when CONFIG_BUILD_PROTECTED
was enabled. This caused build failures when CONFIG_ARM_MPU was set
without CONFIG_BUILD_PROTECTED. The build logic has been updated to
include arm_mpu.c whenever either CONFIG_ARM_MPU or
CONFIG_BUILD_PROTECTED is enabled.
Signed-off-by: Erkan Vatan <evatan@t3gemstone.org>
The previous use of `%u` and `%X` for `uint32_t` values triggered
compiler warnings. These have been replaced with the appropriate
format‑specifier macros to ensure type‑correctness and eliminate the
warnings.
Signed-off-by: Erkan Vatan <evatan@t3gemstone.org>
The STM32 serial drivers already treat 0 as not present for optional
GPIO fields (CTS, RTS), guarding each call site with a != 0 check.
TX and RX GPIO fields lacked this guard, so boards that
define GPIO_UARTx_TX or GPIO_UARTx_RX as 0 (pin not routed) caused
stm32_configgpio(0) to be called, which silently configures PA0 as a
floating input, corrupting any other peripheral using that pin.
Having an optional TX/RX UART is useful for several cases:
* RX-only connections: e.g. radio control input on flight-controllers where no TX is wired.
* Single-wire (half-duplex) connections: e.g. ESC telemetry connections.
* Output-only NSH which prints output but does not allow entering inputs.
Without a sentinel value for these cases one must assign the unused GPIO to
a NC pin, which is misleading when reading board configuration files.
Add != 0 guards for tx_gpio and rx_gpio across all STM32 serial driver
families.
Using 0 as the sentinel is safe for TX/RX because any valid UART config requires
GPIO_ALT bits set in the config word, so 0 can never represent a real
TX or RX pin configuration.
Signed-off-by: alexcekay <alexander@auterion.com>
sim_x11events() polls g_display from the idle loop while the
framebuffer teardown path closes the X connection. Clear the global
Display handle before teardown so the event path stops using it, but
keep the saved local Display pointer for XShmDetach(), XUngrabButton(),
and XCloseDisplay().
This only changes the sim X11 framebuffer shutdown ordering and does
not change user-visible APIs or build configuration.
Signed-off-by: hanzhijian <hanzhijian@zepp.com>
The RWDT register offsets were incorrectly set to ESP32-S3 values
instead of ESP32 values. This was introduced when the code was
refactored from using the local NuttX header hardware/esp32_rtccntl.h
(which had the correct offsets) to using the HAL library headers, and
the offsets were moved inline into esp32_wdt.c with wrong values.
Correct the offsets to match the actual ESP32 register layout from
soc/rtc_cntl_reg.h (RTC_CNTL_WDTCONFIG0_REG at 0x8c, INT_ENA at
0x3c, etc). Without this fix, all RWDT operations (enable, configure
timeout, enable interrupt, acknowledge interrupt, feed, write-protect)
were targeting wrong memory addresses, rendering the RWDT completely
non-functional.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Under the BOARD_LATE_INITIALIZE boot flow, rtc_clk_xtal_freq_get()
may return 0 (SOC_XTAL_FREQ_AUTO) because the XTAL frequency has
not yet been stored to the RTC register when the WDT driver is
initialized. This causes rtc_clk_cal() to divide by zero
internally (EXCCAUSE=0006) when computing the RTC slow clock
period.
Fix by explicitly calling rtc_clk_xtal_freq_update() with the
board's configured crystal frequency if rtc_clk_xtal_freq_get()
returns 0. Also add a guard in esp32_wdt_settimeout() to return
-EIO if ESP32_RWDT_CLK() still returns 0 cycles/ms, preventing
a subsequent divide-by-zero when computing the maximum timeout.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Same issue as ESP32-S3/S2: with BOARD_LATE_INITIALIZE, the
constructor function enable_timer_group0_for_calibration() resets
Timer Group 0 registers after board_late_initialize() has
configured the MWDT0 prescaler, causing the watchdog to fire at an
incorrect rate.
Re-apply the prescaler, timeout, and feed the WDT counter in
esp32_wdt_start() just before enabling the timer.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Same issue as ESP32-S3: with BOARD_LATE_INITIALIZE, the constructor
function enable_timer_group0_for_calibration() resets Timer Group 0
registers after board_late_initialize() has configured the MWDT0
prescaler, causing the watchdog to fire at an incorrect rate.
Re-apply the prescaler, timeout, and feed the WDT counter in
wdt_lh_start() just before enabling the timer.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
With the BOARD_LATE_INITIALIZE flow, board_late_initialize() runs
on a kernel thread and sets the MWDT0 prescaler. However, after it
returns, the init task (NSH) is spawned and lib_cxx_initialize()
invokes constructor functions, including
enable_timer_group0_for_calibration() from esp-hal-3rdparty which
calls timg_ll_reset_register(0), resetting all Timer Group 0
registers (including the WDT prescaler) back to their defaults.
Re-apply the prescaler, timeout, and feed the WDT counter in
wdt_lh_start() just before enabling the timer. This ensures
correct WDT configuration regardless of any intermediate register
resets by external code.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
When CONFIG_MM_UMM_CUSTOMIZE_MANAGER is enabled, the sim heap
bypasses mm_heap/tlsf entirely and calls host malloc/free directly,
so MM_FILL_ALLOCATIONS has no effect. Add fill pattern support
directly in sim_ummheap.c:
- malloc: fill user region with 0xaa
- free: fill user region with 0x55
- realloc: fill extended region with 0xaa
This helps detect uninitialized reads in sim environment,
which ASan does not support.
Signed-off-by: yushuailong <yyyusl@qq.com>
remove PULSECOUNT references from PWM drivers that not implemet PWM feature.
PULSECOUNT for these architectures was not implemented, so we just remove all references to it.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
BREAKING CHANGE: separate pulse count from PWM driver
Pulse count handling was removed from PWM driver and moved to a separate driver.
For details about this change, look at previous commit.
Signed-off-by: raiden00pl <raiden00@railab.me>
