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!arch/stm32l4: unify non-standard hardware definition prefixes
BREAKING CHANGE: STM32L4 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Alan C. Assis
parent
8397881df4
commit
feb24082bd
132 changed files with 8786 additions and 8781 deletions
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@ -66,260 +66,260 @@
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*/
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \
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defined(CONFIG_STM32L4_STM32L486XX)
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# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX)
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# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX)
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# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L4 chip"
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#endif
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#if defined(CONFIG_STM32L4_STM32L4XR)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 0 /* No QuadSPI1 */
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# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NSWPMI 0 /* No SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 0 /* No QuadSPI1 */
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# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NSWPMI 0 /* No SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4XR */
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#if defined(CONFIG_STM32L4_STM32L4X5)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 3 /* I2C1-3 */
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# define STM32L4_NSWPMI 1 /* SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 1 /* QuadSPI1 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NSWPMI 1 /* SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4X5 */
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 1 /* QuadSPI1 */
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# define STM32_NSPI 3 /* SPI1-3 */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32_NI2C 4 /* I2C1-4 */
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#else
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# define STM32L4_NI2C 3 /* I2C1-3 */
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# define STM32_NI2C 3 /* I2C1-3 */
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#endif
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# define STM32L4_NSWPMI 1 /* SWPMI1 */
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32_NSWPMI 1 /* SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NCAN 2 /* CAN1-2 */
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# define STM32_NCAN 2 /* CAN1-2 */
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#else
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32_NCAN 1 /* CAN1 */
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#endif
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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#else
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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#endif
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# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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# define STM32_NADC 3 /* 12-bit ADC1-3, up to 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4X6 */
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#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_NFSMC 0 /* No FSMC memory controller */
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# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
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# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */
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# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 1 /* UART 4 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_QSPI 1 /* QuadSPI1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NSWPMI 1 /* SWPMI1 */
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# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
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# define STM32_NFSMC 0 /* No FSMC memory controller */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */
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# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32_NBTIM 1 /* One basic timer, TIM6 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 1 /* UART 4 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 1 /* QuadSPI1 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NSWPMI 1 /* SWPMI1 */
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# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
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#if defined(CONFIG_STM32L4_STM32L451XX)
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# define STM32L4_NUSBFS 0 /* No USB FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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#else
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# define STM32L4_NUSBFS 1 /* USB FS */
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# define STM32_NUSBFS 1 /* USB FS */
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#endif
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 1 /* SAI1 */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 1 /* SAI1 */
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#if defined(CONFIG_STM32L4_HAVE_SDMMC1)
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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#else
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# define STM32L4_NSDMMC 0 /* No SDMMC interface */
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# define STM32_NSDMMC 0 /* No SDMMC interface */
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#endif
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */
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# define STM32L4_NDAC 1 /* 12-bit DAC1 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */
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# define STM32_NDAC 1 /* 12-bit DAC1 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 1 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L451XX */
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|
||||
#if defined(CONFIG_STM32L4_STM32L432XX)
|
||||
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 0 /* No UART */
|
||||
# define STM32L4_NUSART 2 /* USART 1-2 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32L4_NSPI 2 /* SPI1, SPI3 */
|
||||
# define STM32L4_NI2C 2 /* I2C1, I2C3 */
|
||||
# define STM32L4_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32L4_NUSBFS 1 /* USB FS */
|
||||
# define STM32L4_NCAN 1 /* CAN1 */
|
||||
# define STM32L4_NSAI 1 /* SAI1 */
|
||||
# define STM32L4_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32L4_NDMA 2 /* DMA1-2 */
|
||||
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32L4_NCRC 1 /* CRC */
|
||||
# define STM32L4_NCOMP 2 /* Comparators */
|
||||
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
|
||||
# define STM32_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NUART 0 /* No UART */
|
||||
# define STM32_NUSART 2 /* USART 1-2 */
|
||||
# define STM32_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32_NSPI 2 /* SPI1, SPI3 */
|
||||
# define STM32_NI2C 2 /* I2C1, I2C3 */
|
||||
# define STM32_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32_NUSBFS 1 /* USB FS */
|
||||
# define STM32_NCAN 1 /* CAN1 */
|
||||
# define STM32_NSAI 1 /* SAI1 */
|
||||
# define STM32_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NCOMP 2 /* Comparators */
|
||||
# define STM32_NOPAMP 1 /* Operational Amplifiers */
|
||||
#endif /* CONFIG_STM32L4_STM32L432XX */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L433XX)
|
||||
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 0 /* No UART */
|
||||
# define STM32L4_NUSART 3 /* USART 1-3 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32L4_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32L4_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32L4_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32L4_NUSBFS 1 /* USB FS */
|
||||
# define STM32L4_NCAN 1 /* CAN1 */
|
||||
# define STM32L4_NSAI 1 /* SAI1 */
|
||||
# define STM32L4_NSDMMC 1 /* SDMMC interface */
|
||||
# define STM32L4_NDMA 2 /* DMA1-2 */
|
||||
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32L4_NCRC 1 /* CRC */
|
||||
# define STM32L4_NCOMP 2 /* Comparators */
|
||||
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
|
||||
# define STM32_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NUART 0 /* No UART */
|
||||
# define STM32_NUSART 3 /* USART 1-3 */
|
||||
# define STM32_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32_NSWPMI 1 /* SWPMI1 */
|
||||
# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32_NUSBFS 1 /* USB FS */
|
||||
# define STM32_NCAN 1 /* CAN1 */
|
||||
# define STM32_NSAI 1 /* SAI1 */
|
||||
# define STM32_NSDMMC 1 /* SDMMC interface */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */
|
||||
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NCOMP 2 /* Comparators */
|
||||
# define STM32_NOPAMP 1 /* Operational Amplifiers */
|
||||
#endif /* CONFIG_STM32L4_STM32L433XX */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX)
|
||||
# define STM32L4_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 0 /* No UART */
|
||||
# define STM32L4_NUSART 3 /* USART 1-3 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32L4_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32L4_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32L4_NSWPMI 0 /* No SWPMI */
|
||||
# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32L4_NUSBFS 1 /* USB FS */
|
||||
# define STM32L4_NCAN 0 /* No CAN */
|
||||
# define STM32L4_NSAI 0 /* No SAI */
|
||||
# define STM32L4_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32L4_NDMA 2 /* DMA1-2 */
|
||||
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */
|
||||
# define STM32L4_NDAC 0 /* No DAC */
|
||||
# define STM32L4_NCRC 1 /* CRC */
|
||||
# define STM32L4_NCOMP 2 /* Comparators */
|
||||
# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
|
||||
# define STM32_NFSMC 0 /* No FSMC memory controller */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
|
||||
# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
|
||||
# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
|
||||
# define STM32_NBTIM 1 /* One basic timer, TIM6 */
|
||||
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32_NUART 0 /* No UART */
|
||||
# define STM32_NUSART 3 /* USART 1-3 */
|
||||
# define STM32_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32_QSPI 1 /* QuadSPI1 */
|
||||
# define STM32_NSPI 3 /* SPI1-SPI3 */
|
||||
# define STM32_NI2C 3 /* I2C1-I2C3 */
|
||||
# define STM32_NSWPMI 0 /* No SWPMI */
|
||||
# define STM32_NUSBOTGFS 0 /* No USB OTG FS */
|
||||
# define STM32_NUSBFS 1 /* USB FS */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSAI 0 /* No SAI */
|
||||
# define STM32_NSDMMC 0 /* No SDMMC interface */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
|
||||
# define STM32_NADC 2 /* 12-bit ADC1-2, 10 channels */
|
||||
# define STM32_NDAC 0 /* No DAC */
|
||||
# define STM32_NCRC 1 /* CRC */
|
||||
# define STM32_NCOMP 2 /* Comparators */
|
||||
# define STM32_NOPAMP 1 /* Operational Amplifiers */
|
||||
#endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */
|
||||
|
||||
/* NVIC priority levels *****************************************************/
|
||||
|
|
|
|||
|
|
@ -44,26 +44,26 @@
|
|||
|
||||
/* Processor Exceptions (vectors 0-15) */
|
||||
|
||||
#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32L4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define STM32L4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define STM32L4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define STM32L4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
/* Vectors 7-10: Reserved */
|
||||
#define STM32L4_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define STM32L4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define STM32L4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32L4_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
|
||||
/* Vector 0: Reset stack pointer value */
|
||||
/* Vector 1: Reset (not handler as an IRQ) */
|
||||
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
|
||||
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
|
||||
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
|
||||
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
|
||||
/* Vectors 7-10: Reserved */
|
||||
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
|
||||
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
|
||||
/* Vector 13: Reserved */
|
||||
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
|
||||
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
|
||||
|
||||
/* External interrupts (vectors >= 16). These definitions are
|
||||
* chip-specific
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */
|
||||
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
|
|||
|
|
@ -52,99 +52,99 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
/* Reserved 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
/* Reserved 42-48 */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
/* Reserved 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
/* Reserved 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
/* Reserved 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
/* Reserved 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */
|
||||
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
/* Reserved 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
/* Reserved 42-48 */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
/* Reserved 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
/* Reserved 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
/* Reserved 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
/* Reserved 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 82) /* 82: CRS global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define STM32L4_IRQ_NEXTINTS 85
|
||||
# define STM32_IRQ_NEXTINTS 85
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
/* (EXTI interrupts do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -48,99 +48,99 @@
|
|||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */
|
||||
#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST + 78) /* 78: Reserved */
|
||||
#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST + 79) /* 79: Reserved */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
|
||||
#define STM32L4_IRQ_NEXTINTS 82
|
||||
#define STM32_IRQ_NEXTINTS 82
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -48,117 +48,117 @@
|
|||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
|
||||
/* STM32L496xx/4A6xx only: */
|
||||
|
||||
#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */
|
||||
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */
|
||||
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */
|
||||
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
|
||||
# define STM32L4_IRQ_NEXTINTS 82
|
||||
# define STM32_IRQ_NEXTINTS 82
|
||||
#elif defined(CONFIG_STM32L4_STM32L496XX)
|
||||
# define STM32L4_IRQ_NEXTINTS 91
|
||||
# define STM32_IRQ_NEXTINTS 91
|
||||
#else
|
||||
# error "Unsupported STM32L4 chip"
|
||||
#endif
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -48,109 +48,109 @@
|
|||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
/* Reserved 47: ADC3 global interrupt */
|
||||
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */
|
||||
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */
|
||||
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */
|
||||
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
/* Reserved 86-89: CAN2 */
|
||||
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */
|
||||
#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */
|
||||
#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */
|
||||
#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
|
||||
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
|
||||
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
|
||||
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
|
||||
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
|
||||
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
|
||||
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
|
||||
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
|
||||
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
|
||||
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
|
||||
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
|
||||
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
|
||||
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
|
||||
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
|
||||
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
|
||||
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
|
||||
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
|
||||
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
|
||||
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
|
||||
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
|
||||
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
|
||||
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
|
||||
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
|
||||
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
|
||||
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
|
||||
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
|
||||
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
|
||||
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
|
||||
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
|
||||
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
|
||||
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
|
||||
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
|
||||
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
|
||||
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
|
||||
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
|
||||
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
|
||||
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
|
||||
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
|
||||
#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
|
||||
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
|
||||
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
|
||||
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
|
||||
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
|
||||
/* Reserved 47: ADC3 global interrupt */
|
||||
#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
|
||||
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
|
||||
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
|
||||
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
|
||||
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
|
||||
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
|
||||
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
|
||||
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
|
||||
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
|
||||
#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
|
||||
#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
|
||||
#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
|
||||
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
|
||||
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
|
||||
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
|
||||
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
|
||||
#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
|
||||
#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
|
||||
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
|
||||
#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */
|
||||
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
|
||||
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
|
||||
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
|
||||
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
|
||||
#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */
|
||||
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */
|
||||
#define STM32_IRQ_DSIHSOT (STM32_IRQ_FIRST + 78) /* 78: DSI global interrupt */
|
||||
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
|
||||
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */
|
||||
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
|
||||
#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
|
||||
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
|
||||
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
|
||||
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
|
||||
/* Reserved 86-89: CAN2 */
|
||||
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
|
||||
#define STM32_IRQ_LCD_TFT (STM32_IRQ_FIRST + 91) /* 91: LTDC global interrupt */
|
||||
#define STM32_IRQ_LCD_TFT_ER (STM32_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */
|
||||
#define STM32_IRQ_GFXMMU (STM32_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */
|
||||
#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */
|
||||
|
||||
#define STM32L4_IRQ_NEXTINTS 95
|
||||
#define STM32_IRQ_NEXTINTS 95
|
||||
|
||||
/* EXTI interrupts (Do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@
|
|||
* arch/stm32l4/chip.h header file.
|
||||
*/
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
|
||||
|
||||
/* Cache line sizes (in bytes) for the STM32L4 */
|
||||
|
||||
|
|
|
|||
|
|
@ -41,136 +41,136 @@
|
|||
* offset 0x0100 for slave.
|
||||
*/
|
||||
|
||||
#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
|
||||
#define STM32L4_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
|
||||
#define STM32L4_ADC_CR_OFFSET 0x0008 /* ADC control register */
|
||||
#define STM32L4_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */
|
||||
#define STM32L4_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
|
||||
#define STM32L4_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
|
||||
#define STM32L4_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
|
||||
#define STM32L4_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
|
||||
#define STM32L4_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */
|
||||
#define STM32L4_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */
|
||||
#define STM32L4_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */
|
||||
#define STM32L4_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */
|
||||
#define STM32L4_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */
|
||||
#define STM32L4_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */
|
||||
#define STM32L4_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
|
||||
#define STM32L4_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */
|
||||
#define STM32L4_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */
|
||||
#define STM32L4_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */
|
||||
#define STM32L4_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */
|
||||
#define STM32L4_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */
|
||||
#define STM32L4_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */
|
||||
#define STM32L4_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */
|
||||
#define STM32L4_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */
|
||||
#define STM32L4_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */
|
||||
#define STM32L4_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */
|
||||
#define STM32L4_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */
|
||||
#define STM32L4_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */
|
||||
#define STM32L4_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */
|
||||
#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
|
||||
#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
|
||||
#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */
|
||||
#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */
|
||||
#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */
|
||||
#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */
|
||||
#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */
|
||||
#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */
|
||||
#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */
|
||||
#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */
|
||||
#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */
|
||||
#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */
|
||||
#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */
|
||||
#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */
|
||||
#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */
|
||||
#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */
|
||||
#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */
|
||||
#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */
|
||||
|
||||
/* Master and Slave ADC Common Registers */
|
||||
|
||||
#define STM32L4_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32L4_ADC_CCR_OFFSET 0x0008 /* Common control register */
|
||||
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
|
||||
#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */
|
||||
# define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_ADC1_ISR (STM32L4_ADC1_BASE+STM32L4_ADC_ISR_OFFSET)
|
||||
#define STM32L4_ADC1_IER (STM32L4_ADC1_BASE+STM32L4_ADC_IER_OFFSET)
|
||||
#define STM32L4_ADC1_CR (STM32L4_ADC1_BASE+STM32L4_ADC_CR_OFFSET)
|
||||
#define STM32L4_ADC1_CFGR (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR_OFFSET)
|
||||
#define STM32L4_ADC1_CFGR2 (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR2_OFFSET)
|
||||
#define STM32L4_ADC1_SMPR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR1_OFFSET)
|
||||
#define STM32L4_ADC1_SMPR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR2_OFFSET)
|
||||
#define STM32L4_ADC1_TR1 (STM32L4_ADC1_BASE+STM32L4_ADC_TR1_OFFSET)
|
||||
#define STM32L4_ADC1_TR2 (STM32L4_ADC1_BASE+STM32L4_ADC_TR2_OFFSET)
|
||||
#define STM32L4_ADC1_TR3 (STM32L4_ADC1_BASE+STM32L4_ADC_TR3_OFFSET)
|
||||
#define STM32L4_ADC1_SQR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR1_OFFSET)
|
||||
#define STM32L4_ADC1_SQR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR2_OFFSET)
|
||||
#define STM32L4_ADC1_SQR3 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR3_OFFSET)
|
||||
#define STM32L4_ADC1_SQR4 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR4_OFFSET)
|
||||
#define STM32L4_ADC1_DR (STM32L4_ADC1_BASE+STM32L4_ADC_DR_OFFSET)
|
||||
#define STM32L4_ADC1_JSQR (STM32L4_ADC1_BASE+STM32L4_ADC_JSQR_OFFSET)
|
||||
#define STM32L4_ADC1_OFR1 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR1_OFFSET)
|
||||
#define STM32L4_ADC1_OFR2 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR2_OFFSET)
|
||||
#define STM32L4_ADC1_OFR3 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR3_OFFSET)
|
||||
#define STM32L4_ADC1_OFR4 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR4_OFFSET)
|
||||
#define STM32L4_ADC1_JDR1 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR1_OFFSET)
|
||||
#define STM32L4_ADC1_JDR2 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR2_OFFSET)
|
||||
#define STM32L4_ADC1_JDR3 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR3_OFFSET)
|
||||
#define STM32L4_ADC1_JDR4 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR4_OFFSET)
|
||||
#define STM32L4_ADC1_AWD2CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD2CR_OFFSET)
|
||||
#define STM32L4_ADC1_AWD3CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD3CR_OFFSET)
|
||||
#define STM32L4_ADC1_DIFSEL (STM32L4_ADC1_BASE+STM32L4_ADC_DIFSEL_OFFSET)
|
||||
#define STM32L4_ADC1_CALFACT (STM32L4_ADC1_BASE+STM32L4_ADC_CALFACT_OFFSET)
|
||||
#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32L4_ADC2_ISR (STM32L4_ADC2_BASE+STM32L4_ADC_ISR_OFFSET)
|
||||
#define STM32L4_ADC2_IER (STM32L4_ADC2_BASE+STM32L4_ADC_IER_OFFSET)
|
||||
#define STM32L4_ADC2_CR (STM32L4_ADC2_BASE+STM32L4_ADC_CR_OFFSET)
|
||||
#define STM32L4_ADC2_CFGR (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR_OFFSET)
|
||||
#define STM32L4_ADC2_CFGR2 (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR2_OFFSET)
|
||||
#define STM32L4_ADC2_SMPR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR1_OFFSET)
|
||||
#define STM32L4_ADC2_SMPR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR2_OFFSET)
|
||||
#define STM32L4_ADC2_TR1 (STM32L4_ADC2_BASE+STM32L4_ADC_TR1_OFFSET)
|
||||
#define STM32L4_ADC2_TR2 (STM32L4_ADC2_BASE+STM32L4_ADC_TR2_OFFSET)
|
||||
#define STM32L4_ADC2_TR3 (STM32L4_ADC2_BASE+STM32L4_ADC_TR3_OFFSET)
|
||||
#define STM32L4_ADC2_SQR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR1_OFFSET)
|
||||
#define STM32L4_ADC2_SQR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR2_OFFSET)
|
||||
#define STM32L4_ADC2_SQR3 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR3_OFFSET)
|
||||
#define STM32L4_ADC2_SQR4 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR4_OFFSET)
|
||||
#define STM32L4_ADC2_DR (STM32L4_ADC2_BASE+STM32L4_ADC_DR_OFFSET)
|
||||
#define STM32L4_ADC2_JSQR (STM32L4_ADC2_BASE+STM32L4_ADC_JSQR_OFFSET)
|
||||
#define STM32L4_ADC2_OFR1 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR1_OFFSET)
|
||||
#define STM32L4_ADC2_OFR2 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR2_OFFSET)
|
||||
#define STM32L4_ADC2_OFR3 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR3_OFFSET)
|
||||
#define STM32L4_ADC2_OFR4 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR4_OFFSET)
|
||||
#define STM32L4_ADC2_JDR1 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR1_OFFSET)
|
||||
#define STM32L4_ADC2_JDR2 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR2_OFFSET)
|
||||
#define STM32L4_ADC2_JDR3 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR3_OFFSET)
|
||||
#define STM32L4_ADC2_JDR4 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR4_OFFSET)
|
||||
#define STM32L4_ADC2_AWD2CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD2CR_OFFSET)
|
||||
#define STM32L4_ADC2_AWD3CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD3CR_OFFSET)
|
||||
#define STM32L4_ADC2_DIFSEL (STM32L4_ADC2_BASE+STM32L4_ADC_DIFSEL_OFFSET)
|
||||
#define STM32L4_ADC2_CALFACT (STM32L4_ADC2_BASE+STM32L4_ADC_CALFACT_OFFSET)
|
||||
#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32L4_ADC3_ISR (STM32L4_ADC3_BASE+STM32L4_ADC_ISR_OFFSET)
|
||||
#define STM32L4_ADC3_IER (STM32L4_ADC3_BASE+STM32L4_ADC_IER_OFFSET)
|
||||
#define STM32L4_ADC3_CR (STM32L4_ADC3_BASE+STM32L4_ADC_CR_OFFSET)
|
||||
#define STM32L4_ADC3_CFGR (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR_OFFSET)
|
||||
#define STM32L4_ADC3_CFGR2 (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR2_OFFSET)
|
||||
#define STM32L4_ADC3_SMPR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR1_OFFSET)
|
||||
#define STM32L4_ADC3_SMPR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR2_OFFSET)
|
||||
#define STM32L4_ADC3_TR1 (STM32L4_ADC3_BASE+STM32L4_ADC_TR1_OFFSET)
|
||||
#define STM32L4_ADC3_TR2 (STM32L4_ADC3_BASE+STM32L4_ADC_TR2_OFFSET)
|
||||
#define STM32L4_ADC3_TR3 (STM32L4_ADC3_BASE+STM32L4_ADC_TR3_OFFSET)
|
||||
#define STM32L4_ADC3_SQR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR1_OFFSET)
|
||||
#define STM32L4_ADC3_SQR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR2_OFFSET)
|
||||
#define STM32L4_ADC3_SQR3 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR3_OFFSET)
|
||||
#define STM32L4_ADC3_SQR4 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR4_OFFSET)
|
||||
#define STM32L4_ADC3_DR (STM32L4_ADC3_BASE+STM32L4_ADC_DR_OFFSET)
|
||||
#define STM32L4_ADC3_JSQR (STM32L4_ADC3_BASE+STM32L4_ADC_JSQR_OFFSET)
|
||||
#define STM32L4_ADC3_OFR1 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR1_OFFSET)
|
||||
#define STM32L4_ADC3_OFR2 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR2_OFFSET)
|
||||
#define STM32L4_ADC3_OFR3 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR3_OFFSET)
|
||||
#define STM32L4_ADC3_OFR4 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR4_OFFSET)
|
||||
#define STM32L4_ADC3_JDR1 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR1_OFFSET)
|
||||
#define STM32L4_ADC3_JDR2 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR2_OFFSET)
|
||||
#define STM32L4_ADC3_JDR3 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR3_OFFSET)
|
||||
#define STM32L4_ADC3_JDR4 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR4_OFFSET)
|
||||
#define STM32L4_ADC3_AWD2CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD2CR_OFFSET)
|
||||
#define STM32L4_ADC3_AWD3CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD3CR_OFFSET)
|
||||
#define STM32L4_ADC3_DIFSEL (STM32L4_ADC3_BASE+STM32L4_ADC_DIFSEL_OFFSET)
|
||||
#define STM32L4_ADC3_CALFACT (STM32L4_ADC3_BASE+STM32L4_ADC_CALFACT_OFFSET)
|
||||
#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET)
|
||||
#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET)
|
||||
#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET)
|
||||
#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET)
|
||||
#define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET)
|
||||
#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET)
|
||||
#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET)
|
||||
#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET)
|
||||
#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET)
|
||||
#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
|
||||
#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET)
|
||||
#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET)
|
||||
#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET)
|
||||
#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET)
|
||||
#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET)
|
||||
#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET)
|
||||
#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET)
|
||||
#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET)
|
||||
|
||||
#define STM32L4_ADC_CSR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CSR_OFFSET)
|
||||
#define STM32L4_ADC_CCR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CCR_OFFSET)
|
||||
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
|
||||
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_ADC_CDR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CDR_OFFSET)
|
||||
# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
@ -286,10 +286,12 @@
|
|||
# define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */
|
||||
# define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */
|
||||
# define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */
|
||||
|
||||
#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */
|
||||
#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT)
|
||||
# define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT)
|
||||
/* Value = 0..8 */
|
||||
/* Value = 0..8 */
|
||||
|
||||
#define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */
|
||||
#define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */
|
||||
|
||||
|
|
|
|||
|
|
@ -54,61 +54,61 @@
|
|||
|
||||
/* CAN control and status registers */
|
||||
|
||||
#define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
|
||||
#define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
|
||||
#define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
|
||||
#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2))
|
||||
#define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
|
||||
#define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
|
||||
#define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
|
||||
#define STM32L4_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
|
||||
#define STM32L4_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
|
||||
#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */
|
||||
#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */
|
||||
#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */
|
||||
#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2))
|
||||
#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */
|
||||
#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */
|
||||
#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */
|
||||
#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */
|
||||
#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */
|
||||
|
||||
/* CAN mailbox registers (3 TX and 2 RX) */
|
||||
|
||||
#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4))
|
||||
#define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */
|
||||
#define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */
|
||||
#define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */
|
||||
#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4))
|
||||
#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */
|
||||
#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */
|
||||
#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */
|
||||
|
||||
#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4))
|
||||
#define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */
|
||||
#define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */
|
||||
#define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */
|
||||
#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4))
|
||||
#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */
|
||||
#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */
|
||||
#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */
|
||||
|
||||
#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4))
|
||||
#define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */
|
||||
#define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */
|
||||
#define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */
|
||||
#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4))
|
||||
#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */
|
||||
#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */
|
||||
#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */
|
||||
|
||||
#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4))
|
||||
#define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */
|
||||
#define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */
|
||||
#define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */
|
||||
#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4))
|
||||
#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */
|
||||
#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */
|
||||
#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */
|
||||
|
||||
#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4))
|
||||
#define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */
|
||||
#define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */
|
||||
#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4))
|
||||
#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */
|
||||
#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */
|
||||
|
||||
#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4))
|
||||
#define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */
|
||||
#define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */
|
||||
#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4))
|
||||
#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */
|
||||
#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */
|
||||
|
||||
#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4))
|
||||
#define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */
|
||||
#define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */
|
||||
#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4))
|
||||
#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */
|
||||
#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */
|
||||
|
||||
#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4))
|
||||
#define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */
|
||||
#define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */
|
||||
#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4))
|
||||
#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */
|
||||
#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */
|
||||
|
||||
/* CAN filter registers */
|
||||
|
||||
#define STM32L4_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */
|
||||
#define STM32L4_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */
|
||||
#define STM32L4_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */
|
||||
#define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
|
||||
#define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
|
||||
#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */
|
||||
#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */
|
||||
#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */
|
||||
#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */
|
||||
#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */
|
||||
|
||||
/* There are 14 filter banks on the device. Each filter bank is
|
||||
* composed of two 32-bit registers, CAN_FiR:
|
||||
|
|
@ -119,63 +119,63 @@
|
|||
* ...
|
||||
*/
|
||||
|
||||
#define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2))
|
||||
#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2))
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NCAN > 0
|
||||
# define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET)
|
||||
# define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET)
|
||||
# define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET)
|
||||
# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET)
|
||||
# define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET)
|
||||
# define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET)
|
||||
# define STM32L4_CAN1_ESR (STM32L4_CAN1_BASE+STM32L4_CAN_ESR_OFFSET)
|
||||
# define STM32L4_CAN1_BTR (STM32L4_CAN1_BASE+STM32L4_CAN_BTR_OFFSET)
|
||||
#if STM32_NCAN > 0
|
||||
# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET)
|
||||
# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET)
|
||||
# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET)
|
||||
# define STM32_CAN1_RFR(m) (STM32_CAN1_BASE+STM32_CAN_RFR_OFFSET(m))
|
||||
# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET)
|
||||
# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET)
|
||||
# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET)
|
||||
# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET)
|
||||
# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TIR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TI0R (STM32L4_CAN1_BASE+STM32L4_CAN_TI0R_OFFSET)
|
||||
# define STM32L4_CAN1_TI1R (STM32L4_CAN1_BASE+STM32L4_CAN_TI1R_OFFSET)
|
||||
# define STM32L4_CAN1_TI2R (STM32L4_CAN1_BASE+STM32L4_CAN_TI2R_OFFSET)
|
||||
# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m))
|
||||
# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET)
|
||||
# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET)
|
||||
# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDTR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT0R_OFFSET)
|
||||
# define STM32L4_CAN1_TDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT1R_OFFSET)
|
||||
# define STM32L4_CAN1_TDT2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT2R_OFFSET)
|
||||
# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m))
|
||||
# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET)
|
||||
# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET)
|
||||
# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDLR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL0R_OFFSET)
|
||||
# define STM32L4_CAN1_TDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL1R_OFFSET)
|
||||
# define STM32L4_CAN1_TDL2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL2R_OFFSET)
|
||||
# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m))
|
||||
# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET)
|
||||
# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET)
|
||||
# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_TDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDHR_OFFSET(m))
|
||||
# define STM32L4_CAN1_TDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH0R_OFFSET)
|
||||
# define STM32L4_CAN1_TDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH1R_OFFSET)
|
||||
# define STM32L4_CAN1_TDH2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH2R_OFFSET)
|
||||
# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m))
|
||||
# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET)
|
||||
# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET)
|
||||
# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RIR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RI0R (STM32L4_CAN1_BASE+STM32L4_CAN_RI0R_OFFSET)
|
||||
# define STM32L4_CAN1_RI1R (STM32L4_CAN1_BASE+STM32L4_CAN_RI1R_OFFSET)
|
||||
# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m))
|
||||
# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET)
|
||||
# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDTR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT0R_OFFSET)
|
||||
# define STM32L4_CAN1_RDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT1R_OFFSET)
|
||||
# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m))
|
||||
# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET)
|
||||
# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDLR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL0R_OFFSET)
|
||||
# define STM32L4_CAN1_RDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL1R_OFFSET)
|
||||
# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m))
|
||||
# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET)
|
||||
# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_RDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDHR_OFFSET(m))
|
||||
# define STM32L4_CAN1_RDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH0R_OFFSET)
|
||||
# define STM32L4_CAN1_RDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH1R_OFFSET)
|
||||
# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m))
|
||||
# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET)
|
||||
# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET)
|
||||
|
||||
# define STM32L4_CAN1_FMR (STM32L4_CAN1_BASE+STM32L4_CAN_FMR_OFFSET)
|
||||
# define STM32L4_CAN1_FM1R (STM32L4_CAN1_BASE+STM32L4_CAN_FM1R_OFFSET)
|
||||
# define STM32L4_CAN1_FS1R (STM32L4_CAN1_BASE+STM32L4_CAN_FS1R_OFFSET)
|
||||
# define STM32L4_CAN1_FFA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FFA1R_OFFSET)
|
||||
# define STM32L4_CAN1_FA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FA1R_OFFSET)
|
||||
# define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i))
|
||||
# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET)
|
||||
# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET)
|
||||
# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET)
|
||||
# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET)
|
||||
# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET)
|
||||
# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i))
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -29,15 +29,15 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2)
|
||||
#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */
|
||||
#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */
|
||||
#define STM32_COMP_CSR_OFFSET(n) (((n)-1) << 2)
|
||||
#define STM32_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */
|
||||
#define STM32_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n))
|
||||
#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET)
|
||||
#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET)
|
||||
#define STM32_COMP_CSR(n) (STM32_COMP_BASE+STM32_COMP_CSR_OFFSET(n))
|
||||
#define STM32_COMP1_CSR (STM32_COMP_BASE+STM32_COMP1_CSR_OFFSET)
|
||||
#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
@ -109,7 +109,9 @@
|
|||
# define COMP_CSR_INMESEL_PIN4 (2 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 4: COMP1=PA4; COMP2=PA4 */
|
||||
# define COMP_CSR_INMESEL_PIN5 (3 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 5: COMP1=PA5; COMP2=PA5 */
|
||||
#endif
|
||||
/* Bits 27-29: Reserved */
|
||||
|
||||
/* Bits 27-29: Reserved */
|
||||
|
||||
#define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */
|
||||
#define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */
|
||||
# define COMP_CSR_LOCK_RW (0)
|
||||
|
|
|
|||
|
|
@ -29,17 +29,17 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */
|
||||
#define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
|
||||
#define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
|
||||
#define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
|
||||
#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */
|
||||
#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
|
||||
#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
|
||||
#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET)
|
||||
#define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET)
|
||||
#define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET)
|
||||
#define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET)
|
||||
#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET)
|
||||
#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET)
|
||||
#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET)
|
||||
#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -36,51 +36,51 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DAC_CR_OFFSET 0x0000 /* DAC control register */
|
||||
#define STM32L4_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
|
||||
#define STM32L4_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
|
||||
#define STM32L4_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
|
||||
#define STM32L4_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
|
||||
#define STM32L4_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
|
||||
#define STM32L4_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
|
||||
#define STM32L4_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
|
||||
#define STM32L4_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
|
||||
#define STM32L4_DAC_SR_OFFSET 0x0034 /* DAC status register */
|
||||
#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */
|
||||
#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
|
||||
#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
|
||||
#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
|
||||
#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
|
||||
#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */
|
||||
#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
|
||||
#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
|
||||
#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
|
||||
#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
|
||||
#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
|
||||
#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
|
||||
#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
|
||||
#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */
|
||||
|
||||
/* New registers not in STM32L1: */
|
||||
#define STM32L4_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */
|
||||
#define STM32L4_DAC_MCR_OFFSET 0x003c /* DAC mode control register */
|
||||
#define STM32L4_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */
|
||||
#define STM32L4_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */
|
||||
#define STM32L4_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */
|
||||
#define STM32L4_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */
|
||||
#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */
|
||||
#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */
|
||||
#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */
|
||||
#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */
|
||||
#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */
|
||||
#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DAC_CR (STM32L4_DAC_BASE+STM32L4_DAC_CR_OFFSET)
|
||||
#define STM32L4_DAC_SWTRIGR (STM32L4_DAC_BASE+STM32L4_DAC_SWTRIGR_OFFSET)
|
||||
#define STM32L4_DAC_DHR12R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R1_OFFSET)
|
||||
#define STM32L4_DAC_DHR12L1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L1_OFFSET)
|
||||
#define STM32L4_DAC_DHR8R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R1_OFFSET)
|
||||
#define STM32L4_DAC_DHR12R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R2_OFFSET)
|
||||
#define STM32L4_DAC_DHR12L2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L2_OFFSET)
|
||||
#define STM32L4_DAC_DHR8R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R2_OFFSET)
|
||||
#define STM32L4_DAC_DHR12RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12RD_OFFSET)
|
||||
#define STM32L4_DAC_DHR12LD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12LD_OFFSET)
|
||||
#define STM32L4_DAC_DHR8RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR8RD_OFFSET)
|
||||
#define STM32L4_DAC_DOR1 (STM32L4_DAC_BASE+STM32L4_DAC_DOR1_OFFSET)
|
||||
#define STM32L4_DAC_DOR2 (STM32L4_DAC_BASE+STM32L4_DAC_DOR2_OFFSET)
|
||||
#define STM32L4_DAC_SR (STM32L4_DAC_BASE+STM32L4_DAC_SR_OFFSET)
|
||||
#define STM32L4_DAC_CCR (STM32L4_DAC_BASE+STM32L4_DAC_CCR_OFFSET)
|
||||
#define STM32L4_DAC_MCR (STM32L4_DAC_BASE+STM32L4_DAC_MCR_OFFSET)
|
||||
#define STM32L4_DAC_SHSR1 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR1_OFFSET)
|
||||
#define STM32L4_DAC_SHSR2 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR2_OFFSET)
|
||||
#define STM32L4_DAC_SHHR (STM32L4_DAC_BASE+STM32L4_DAC_SHHR_OFFSET)
|
||||
#define STM32L4_DAC_SHRR (STM32L4_DAC_BASE+STM32L4_DAC_SHRR_OFFSET)
|
||||
#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET)
|
||||
#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET)
|
||||
#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET)
|
||||
#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET)
|
||||
#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET)
|
||||
#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET)
|
||||
#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET)
|
||||
#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET)
|
||||
#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET)
|
||||
#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET)
|
||||
#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET)
|
||||
#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET)
|
||||
#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET)
|
||||
#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET)
|
||||
#define STM32_DAC_CCR (STM32_DAC_BASE+STM32_DAC_CCR_OFFSET)
|
||||
#define STM32_DAC_MCR (STM32_DAC_BASE+STM32_DAC_MCR_OFFSET)
|
||||
#define STM32_DAC_SHSR1 (STM32_DAC_BASE+STM32_DAC_SHSR1_OFFSET)
|
||||
#define STM32_DAC_SHSR2 (STM32_DAC_BASE+STM32_DAC_SHSR2_OFFSET)
|
||||
#define STM32_DAC_SHHR (STM32_DAC_BASE+STM32_DAC_SHHR_OFFSET)
|
||||
#define STM32_DAC_SHRR (STM32_DAC_BASE+STM32_DAC_SHRR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -41,134 +41,134 @@
|
|||
|
||||
/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */
|
||||
#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */
|
||||
#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */
|
||||
#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */
|
||||
#define STM32_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */
|
||||
#define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */
|
||||
#define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */
|
||||
#define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */
|
||||
# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */
|
||||
# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */
|
||||
# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */
|
||||
# define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */
|
||||
# define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */
|
||||
# define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */
|
||||
# define STM32_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */
|
||||
#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */
|
||||
#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */
|
||||
#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */
|
||||
#define STM32_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */
|
||||
#define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */
|
||||
#define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */
|
||||
#define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */
|
||||
# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */
|
||||
# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */
|
||||
# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */
|
||||
# define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */
|
||||
# define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */
|
||||
# define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */
|
||||
# define STM32_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */
|
||||
#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */
|
||||
#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */
|
||||
#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */
|
||||
#define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */
|
||||
# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */
|
||||
# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */
|
||||
# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */
|
||||
# define STM32_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y))
|
||||
#define STM32_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y))
|
||||
|
||||
#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */
|
||||
#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */
|
||||
#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */
|
||||
#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */
|
||||
#define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */
|
||||
# define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */
|
||||
# define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */
|
||||
# define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */
|
||||
# define STM32_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */
|
||||
#endif
|
||||
|
||||
#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */
|
||||
#define STM32_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */
|
||||
|
||||
#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */
|
||||
#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */
|
||||
#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */
|
||||
#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */
|
||||
#define STM32_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */
|
||||
#define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */
|
||||
#define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */
|
||||
#define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */
|
||||
# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */
|
||||
# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */
|
||||
# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */
|
||||
# define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */
|
||||
# define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */
|
||||
# define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */
|
||||
# define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */
|
||||
# define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */
|
||||
|
||||
# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */
|
||||
# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */
|
||||
# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */
|
||||
# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */
|
||||
# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */
|
||||
# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */
|
||||
# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */
|
||||
# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */
|
||||
# define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */
|
||||
# define STM32_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */
|
||||
# define STM32_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */
|
||||
# define STM32_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */
|
||||
# define STM32_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */
|
||||
# define STM32_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */
|
||||
# define STM32_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */
|
||||
# define STM32_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */
|
||||
#endif
|
||||
|
||||
/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */
|
||||
#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */
|
||||
#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */
|
||||
#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */
|
||||
#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */
|
||||
#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */
|
||||
#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */
|
||||
#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */
|
||||
#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */
|
||||
#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */
|
||||
#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */
|
||||
#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */
|
||||
#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */
|
||||
#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */
|
||||
#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */
|
||||
#define STM32_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */
|
||||
#define STM32_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */
|
||||
#define STM32_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */
|
||||
#define STM32_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */
|
||||
#define STM32_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */
|
||||
#define STM32_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */
|
||||
#define STM32_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */
|
||||
#define STM32_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */
|
||||
#define STM32_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */
|
||||
#define STM32_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */
|
||||
#define STM32_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */
|
||||
#define STM32_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */
|
||||
#define STM32_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */
|
||||
#define STM32_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */
|
||||
#define STM32_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y))
|
||||
#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET)
|
||||
#define STM32_DFSDM_CHCFGR1(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR1_OFFSET(y))
|
||||
#define STM32_DFSDM_CH0CFGR1 (STM32_DFSDM_BASE + STM32_DFSDM_CH0CFGR1_OFFSET)
|
||||
|
||||
#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y))
|
||||
#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y))
|
||||
#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y)
|
||||
#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y))
|
||||
#define STM32_DFSDM_CHCFGR2(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR2_OFFSET(y))
|
||||
#define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y))
|
||||
#define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y)
|
||||
#define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y))
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y))
|
||||
# define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y))
|
||||
#endif
|
||||
|
||||
/* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */
|
||||
|
||||
#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x))
|
||||
#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTCR1(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR1_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTCR2(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR2_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTISR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTISR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTICR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTICR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTJCHGR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJCHGR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTFCR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTFCR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTJDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJDATAR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTRDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTRDATAR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWHTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWHTR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWLTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWLTR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWSR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWSR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTAWCFR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWCFR_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTEXMAX(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMAX_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTEXMIN(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMIN_OFFSET(x))
|
||||
#define STM32_DFSDM_FLTCNVTIMR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCNVTIMR_OFFSET(x))
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -34,44 +34,44 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32L4_NEXTI1 31
|
||||
#define STM32L4_EXTI1_MASK 0xffffffff
|
||||
#define STM32L4_NEXTI2 9
|
||||
#define STM32L4_EXTI2_MASK 0x000001ff
|
||||
#define STM32_NEXTI1 31
|
||||
#define STM32_EXTI1_MASK 0xffffffff
|
||||
#define STM32_NEXTI2 9
|
||||
#define STM32_EXTI2_MASK 0x000001ff
|
||||
|
||||
#define STM32L4_EXTI1_BIT(n) (1 << (n))
|
||||
#define STM32L4_EXTI2_BIT(n) (1 << (n))
|
||||
#define STM32_EXTI1_BIT(n) (1 << (n))
|
||||
#define STM32_EXTI2_BIT(n) (1 << (n))
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */
|
||||
#define STM32L4_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */
|
||||
#define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */
|
||||
#define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */
|
||||
|
||||
#define STM32L4_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32L4_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32L4_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32L4_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32L4_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32L4_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
|
||||
#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
|
||||
#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
|
||||
#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
|
||||
#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
|
||||
#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_EXTI1_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI1_OFFSET)
|
||||
#define STM32L4_EXTI2_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI2_OFFSET)
|
||||
#define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET)
|
||||
#define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET)
|
||||
|
||||
#define STM32L4_EXTI1_IMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_IMR_OFFSET)
|
||||
#define STM32L4_EXTI1_EMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_EMR_OFFSET)
|
||||
#define STM32L4_EXTI1_RTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_RTSR_OFFSET)
|
||||
#define STM32L4_EXTI1_FTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_FTSR_OFFSET)
|
||||
#define STM32L4_EXTI1_SWIER (STM32L4_EXTI1_BASE+STM32L4_EXTI_SWIER_OFFSET)
|
||||
#define STM32L4_EXTI1_PR (STM32L4_EXTI1_BASE+STM32L4_EXTI_PR_OFFSET)
|
||||
#define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET)
|
||||
|
||||
#define STM32L4_EXTI2_IMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_IMR_OFFSET)
|
||||
#define STM32L4_EXTI2_EMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_EMR_OFFSET)
|
||||
#define STM32L4_EXTI2_RTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_RTSR_OFFSET)
|
||||
#define STM32L4_EXTI2_FTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_FTSR_OFFSET)
|
||||
#define STM32L4_EXTI2_SWIER (STM32L4_EXTI2_BASE+STM32L4_EXTI_SWIER_OFFSET)
|
||||
#define STM32L4_EXTI2_PR (STM32L4_EXTI2_BASE+STM32L4_EXTI_PR_OFFSET)
|
||||
#define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET)
|
||||
#define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET)
|
||||
#define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET)
|
||||
#define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET)
|
||||
#define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET)
|
||||
#define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
@ -105,62 +105,62 @@
|
|||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_IMR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */
|
||||
#define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
|
||||
#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_IMR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Event mask register */
|
||||
|
||||
#define EXTI_EMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_EMR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_EMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Event request from line x is not mask */
|
||||
#define EXTI_EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
|
||||
#define EXTI_EMR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_EMR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Rising Trigger selection register */
|
||||
|
||||
#define EXTI_RTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_RTSR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_RTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
|
||||
#define EXTI_RTSR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_RTSR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Falling Trigger selection register */
|
||||
|
||||
#define EXTI_FTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_FTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_FTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_FTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
|
||||
#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
|
||||
#define EXTI_FTSR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Software interrupt event register */
|
||||
|
||||
#define EXTI_SWIER1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_SWIER1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_SWIER2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_SWIER2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
|
||||
#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
|
||||
#define EXTI_SWIER2_MASK STM32_EXTI2_MASK
|
||||
|
||||
/* Pending register */
|
||||
|
||||
#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR1_MASK STM32L4_EXTI1_MASK
|
||||
#define EXTI_PR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR1_MASK STM32_EXTI1_MASK
|
||||
|
||||
#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR2_MASK STM32L4_EXTI2_MASK
|
||||
#define EXTI_PR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Selected trigger request occurred */
|
||||
#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
|
||||
#define EXTI_PR2_MASK STM32_EXTI2_MASK
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */
|
||||
|
|
|
|||
|
|
@ -113,79 +113,79 @@
|
|||
/* Define the valid configuration */
|
||||
|
||||
#if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */
|
||||
# define STM32L4_FLASH_NPAGES 32
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 32
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
|
||||
# define STM32L4_FLASH_NPAGES 64
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 64
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
|
||||
# define STM32L4_FLASH_NPAGES 128
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 128
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */
|
||||
# define STM32L4_FLASH_NPAGES 256
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 256
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 512
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 4096
|
||||
# define STM32_FLASH_NPAGES 512
|
||||
# define STM32_FLASH_PAGESIZE 4096
|
||||
#else
|
||||
# error "unknown flash configuration!"
|
||||
#endif
|
||||
|
||||
#ifdef STM32L4_FLASH_PAGESIZE
|
||||
# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE)
|
||||
#ifdef STM32_FLASH_PAGESIZE
|
||||
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
|
||||
#endif
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004
|
||||
#define STM32L4_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32L4_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32L4_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32L4_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32L4_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024
|
||||
#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_PDKEYR_OFFSET 0x0004
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32_FLASH_PCROP1SR_OFFSET 0x0024
|
||||
#define STM32_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
|
||||
defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c
|
||||
# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050
|
||||
# define STM32_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32_FLASH_WRP2AR_OFFSET 0x004c
|
||||
# define STM32_FLASH_WRP2BR_OFFSET 0x0050
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_CFGR_OFFSET 0x0130
|
||||
# define STM32_FLASH_CFGR_OFFSET 0x0130
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET)
|
||||
#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET)
|
||||
#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET)
|
||||
#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET)
|
||||
#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET)
|
||||
#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET)
|
||||
#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET)
|
||||
#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET)
|
||||
#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET)
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
|
||||
#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
|
||||
defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET)
|
||||
# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET)
|
||||
# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET)
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_FLASH_CFGR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CFGR_OFFSET)
|
||||
# define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -36,154 +36,154 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32L4_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32L4_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32L4_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32L4_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32L4_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32L4_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
#define STM32_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NPORTS > 0
|
||||
# define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOA_PUPDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOA_IDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOA_ODR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOA_BSRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 0
|
||||
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 1
|
||||
# define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOB_PUPDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOB_IDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOB_ODR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOB_BSRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 1
|
||||
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 2
|
||||
# define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOC_PUPDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOC_IDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOC_ODR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOC_BSRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 2
|
||||
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 3
|
||||
# define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOD_PUPDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOD_IDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOD_ODR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOD_BSRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 3
|
||||
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOD_ASCR (STM32_GPIOD_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 4
|
||||
# define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOE_PUPDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOE_IDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOE_ODR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOE_BSRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 4
|
||||
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOE_ASCR (STM32_GPIOE_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 5
|
||||
# define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOF_PUPDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOF_IDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOF_ODR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOF_BSRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 5
|
||||
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOF_ASCR (STM32_GPIOF_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 6
|
||||
# define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOG_PUPDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOG_IDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOG_ODR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOG_BSRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 6
|
||||
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOG_ASCR (STM32_GPIOG_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 7
|
||||
# define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOH_PUPDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOH_IDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOH_ODR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOH_BSRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 7
|
||||
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NPORTS > 8
|
||||
# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET)
|
||||
# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET)
|
||||
# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET)
|
||||
# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET)
|
||||
# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET)
|
||||
# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET)
|
||||
# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET)
|
||||
# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET)
|
||||
# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET)
|
||||
# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET)
|
||||
# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET)
|
||||
# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET)
|
||||
#if STM32_NPORTS > 8
|
||||
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
# define STM32_GPIOI_ASCR (STM32_GPIOI_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -29,74 +29,74 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32L4_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32L4_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32L4_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32L4_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32L4_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32L4_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32L4_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32L4_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32L4_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32L4_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
|
||||
#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
|
||||
#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
|
||||
#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
|
||||
#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
|
||||
#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NI2C > 0
|
||||
# define STM32L4_I2C1_CR1 (STM32L4_I2C1_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C1_CR2 (STM32L4_I2C1_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C1_OAR1 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C1_OAR2 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C1_TIMINGR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C1_TIMEOUTR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C1_ISR (STM32L4_I2C1_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C1_ICR (STM32L4_I2C1_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C1_PECR (STM32L4_I2C1_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C1_RXDR (STM32L4_I2C1_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C1_TXDR (STM32L4_I2C1_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 0
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NI2C > 1
|
||||
# define STM32L4_I2C2_CR1 (STM32L4_I2C2_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C2_CR2 (STM32L4_I2C2_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C2_OAR1 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C2_OAR2 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C2_TIMINGR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C2_TIMEOUTR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C2_ISR (STM32L4_I2C2_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C2_ICR (STM32L4_I2C2_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C2_PECR (STM32L4_I2C2_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C2_RXDR (STM32L4_I2C2_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C2_TXDR (STM32L4_I2C2_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 1
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NI2C > 2
|
||||
# define STM32L4_I2C3_CR1 (STM32L4_I2C3_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C3_CR2 (STM32L4_I2C3_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C3_OAR1 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C3_OAR2 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C3_TIMINGR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C3_TIMEOUTR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C3_ISR (STM32L4_I2C3_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C3_ICR (STM32L4_I2C3_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C3_PECR (STM32L4_I2C3_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C3_RXDR (STM32L4_I2C3_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 2
|
||||
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NI2C > 3
|
||||
# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET)
|
||||
# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET)
|
||||
# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET)
|
||||
# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET)
|
||||
# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET)
|
||||
# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET)
|
||||
# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET)
|
||||
# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET)
|
||||
# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET)
|
||||
# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET)
|
||||
#if STM32_NI2C > 3
|
||||
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET)
|
||||
# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET)
|
||||
# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET)
|
||||
# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET)
|
||||
# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET)
|
||||
# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET)
|
||||
# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -47,36 +47,36 @@
|
|||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */
|
||||
#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */
|
||||
#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */
|
||||
#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */
|
||||
#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */
|
||||
#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */
|
||||
#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */
|
||||
#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */
|
||||
#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */
|
||||
#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */
|
||||
#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */
|
||||
#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */
|
||||
#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */
|
||||
#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */
|
||||
#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */
|
||||
#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Low-Power Timers - LPTIM1 and LPTIM2 */
|
||||
|
||||
#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET)
|
||||
#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET)
|
||||
#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET)
|
||||
#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET)
|
||||
#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET)
|
||||
#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET)
|
||||
#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET)
|
||||
#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET)
|
||||
#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET)
|
||||
#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET)
|
||||
#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET)
|
||||
#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET)
|
||||
#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET)
|
||||
#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET)
|
||||
#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET)
|
||||
#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET)
|
||||
|
||||
#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET)
|
||||
#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET)
|
||||
#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET)
|
||||
#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET)
|
||||
#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET)
|
||||
#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET)
|
||||
#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET)
|
||||
#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET)
|
||||
#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET)
|
||||
#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET)
|
||||
#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET)
|
||||
#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET)
|
||||
#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET)
|
||||
#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET)
|
||||
#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET)
|
||||
#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -29,60 +29,60 @@
|
|||
|
||||
/* STM32L4XXX Address Blocks ************************************************/
|
||||
|
||||
#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
|
||||
#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
|
||||
# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
|
||||
#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */
|
||||
#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
|
||||
#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */
|
||||
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
|
||||
#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
|
||||
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
|
||||
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
|
||||
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
|
||||
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
|
||||
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
|
||||
# define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
|
||||
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */
|
||||
#define STM32_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */
|
||||
#define STM32_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */
|
||||
#define STM32_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */
|
||||
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
|
||||
|
||||
#define STM32L4_REGION_MASK 0xf0000000
|
||||
#define STM32L4_IS_SRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_SRAM_BASE)
|
||||
#define STM32L4_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_FSMC_BANK1)
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
|
||||
|
||||
/* Code Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
/* 0x00100000-0x07ffffff: Reserved */
|
||||
#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
|
||||
/* 0x08100000-0x0fffffff: Reserved */
|
||||
#define STM32L4_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
|
||||
#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */
|
||||
/* 0x10010000-0x1ffeffff: Reserved */
|
||||
#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */
|
||||
#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
|
||||
#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
|
||||
/* 0x00100000-0x07ffffff: Reserved */
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
|
||||
/* 0x08100000-0x0fffffff: Reserved */
|
||||
#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
|
||||
#define STM32_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */
|
||||
/* 0x10010000-0x1ffeffff: Reserved */
|
||||
#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */
|
||||
#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */
|
||||
#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
|
||||
/* 0x1fff7400-0x1fff77ff: Reserved */
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */
|
||||
/* 0x1ff00010-0x1ff00fff: Reserved */
|
||||
# define STM32L4_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */
|
||||
/* 0x1ff01010-0x1ff01fff: Reserved */
|
||||
# define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */
|
||||
/* 0x1ff00010-0x1ff00fff: Reserved */
|
||||
# define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */
|
||||
/* 0x1ff01010-0x1ff01fff: Reserved */
|
||||
#else
|
||||
# define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */
|
||||
/* 0x1fff7810-0x1ffff7ff: Reserved */
|
||||
# define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */
|
||||
/* 0x1ffff810-0x1fffffff: Reserved */
|
||||
# define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */
|
||||
/* 0x1fff7810-0x1ffff7ff: Reserved */
|
||||
# define STM32_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */
|
||||
/* 0x1ffff810-0x1fffffff: Reserved */
|
||||
#endif
|
||||
|
||||
/* System Memory Addresses **************************************************/
|
||||
|
||||
#define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of
|
||||
#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of
|
||||
* the device Flash memory expressed in
|
||||
* Kbytes. Example: 0x0400 corresponds
|
||||
* to 1024 Kbytes.
|
||||
*/
|
||||
#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
|
||||
#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
|
||||
* type.
|
||||
* 0: LQFP64
|
||||
* 1: WLCSP64
|
||||
|
|
@ -105,123 +105,123 @@
|
|||
/* 0x2001c000-0x2001ffff:
|
||||
* 16Kb aliased by bit-banding
|
||||
*/
|
||||
#define STM32L4_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
|
||||
#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
|
||||
|
||||
/* Peripheral Base Addresses ************************************************/
|
||||
|
||||
#define STM32L4_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
|
||||
/* 0x40009800-0x4000ffff: Reserved */
|
||||
#define STM32L4_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
|
||||
/* 0x40016400-0x4001ffff: Reserved */
|
||||
#define STM32L4_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
|
||||
/* 0x40024400-0x47ffffff: Reserved */
|
||||
#define STM32L4_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
|
||||
/* 0x50060c00-0x5fffffff: Reserved */
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
|
||||
/* 0x40009800-0x4000ffff: Reserved */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */
|
||||
/* 0x40016400-0x4001ffff: Reserved */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
|
||||
/* 0x40024400-0x47ffffff: Reserved */
|
||||
#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */
|
||||
/* 0x50060c00-0x5fffffff: Reserved */
|
||||
|
||||
/* FSMC/QSPI Base Addresses *************************************************/
|
||||
|
||||
#define STM32L4_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */
|
||||
#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */
|
||||
|
||||
/* in datasheet order */
|
||||
|
||||
/* APB1 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_LPTIM2_BASE 0x40009400
|
||||
#define STM32L4_SWPMI1_BASE 0x40008800
|
||||
#define STM32L4_I2C4_BASE 0x40008400
|
||||
#define STM32L4_LPUART1_BASE 0x40008000
|
||||
#define STM32L4_LPTIM1_BASE 0x40007c00
|
||||
#define STM32L4_OPAMP_BASE 0x40007800
|
||||
#define STM32L4_DAC_BASE 0x40007400
|
||||
#define STM32L4_PWR_BASE 0x40007000
|
||||
#define STM32_LPTIM2_BASE 0x40009400
|
||||
#define STM32_SWPMI1_BASE 0x40008800
|
||||
#define STM32_I2C4_BASE 0x40008400
|
||||
#define STM32_LPUART1_BASE 0x40008000
|
||||
#define STM32_LPTIM1_BASE 0x40007c00
|
||||
#define STM32_OPAMP_BASE 0x40007800
|
||||
#define STM32_DAC_BASE 0x40007400
|
||||
#define STM32_PWR_BASE 0x40007000
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define STM32L4_USB_SRAM_BASE 0x40006c00
|
||||
# define STM32L4_USB_FS_BASE 0x40006800
|
||||
# define STM32_USB_SRAM_BASE 0x40006c00
|
||||
# define STM32_USB_FS_BASE 0x40006800
|
||||
#else
|
||||
# define STM32L4_CAN2_BASE 0x40006800
|
||||
# define STM32_CAN2_BASE 0x40006800
|
||||
#endif
|
||||
#define STM32L4_CAN1_BASE 0x40006400
|
||||
#define STM32L4_CRS_BASE 0x40006000
|
||||
#define STM32L4_I2C3_BASE 0x40005c00
|
||||
#define STM32L4_I2C2_BASE 0x40005800
|
||||
#define STM32L4_I2C1_BASE 0x40005400
|
||||
#define STM32L4_UART5_BASE 0x40005000
|
||||
#define STM32L4_UART4_BASE 0x40004c00
|
||||
#define STM32L4_USART3_BASE 0x40004800
|
||||
#define STM32L4_USART2_BASE 0x40004400
|
||||
#define STM32L4_SPI3_BASE 0x40003c00
|
||||
#define STM32L4_SPI2_BASE 0x40003800
|
||||
#define STM32L4_IWDG_BASE 0x40003000
|
||||
#define STM32L4_WWDG_BASE 0x40002c00
|
||||
#define STM32L4_RTC_BASE 0x40002800
|
||||
#define STM32L4_LCD_BASE 0x40002400
|
||||
#define STM32L4_TIM7_BASE 0x40001400
|
||||
#define STM32L4_TIM6_BASE 0x40001000
|
||||
#define STM32L4_TIM5_BASE 0x40000c00
|
||||
#define STM32L4_TIM4_BASE 0x40000800
|
||||
#define STM32L4_TIM3_BASE 0x40000400
|
||||
#define STM32L4_TIM2_BASE 0x40000000
|
||||
#define STM32_CAN1_BASE 0x40006400
|
||||
#define STM32_CRS_BASE 0x40006000
|
||||
#define STM32_I2C3_BASE 0x40005c00
|
||||
#define STM32_I2C2_BASE 0x40005800
|
||||
#define STM32_I2C1_BASE 0x40005400
|
||||
#define STM32_UART5_BASE 0x40005000
|
||||
#define STM32_UART4_BASE 0x40004c00
|
||||
#define STM32_USART3_BASE 0x40004800
|
||||
#define STM32_USART2_BASE 0x40004400
|
||||
#define STM32_SPI3_BASE 0x40003c00
|
||||
#define STM32_SPI2_BASE 0x40003800
|
||||
#define STM32_IWDG_BASE 0x40003000
|
||||
#define STM32_WWDG_BASE 0x40002c00
|
||||
#define STM32_RTC_BASE 0x40002800
|
||||
#define STM32_LCD_BASE 0x40002400
|
||||
#define STM32_TIM7_BASE 0x40001400
|
||||
#define STM32_TIM6_BASE 0x40001000
|
||||
#define STM32_TIM5_BASE 0x40000c00
|
||||
#define STM32_TIM4_BASE 0x40000800
|
||||
#define STM32_TIM3_BASE 0x40000400
|
||||
#define STM32_TIM2_BASE 0x40000000
|
||||
|
||||
/* APB2 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_DSI_BASE 0x40016c00
|
||||
#define STM32L4_LTDC_BASE 0x40016800
|
||||
#define STM32L4_DFSDM_BASE 0x40016000
|
||||
#define STM32L4_SAI2_BASE 0x40015800
|
||||
#define STM32L4_SAI1_BASE 0x40015400
|
||||
#define STM32L4_TIM17_BASE 0x40014800
|
||||
#define STM32L4_TIM16_BASE 0x40014400
|
||||
#define STM32L4_TIM15_BASE 0x40014000
|
||||
#define STM32L4_USART1_BASE 0x40013800
|
||||
#define STM32L4_TIM8_BASE 0x40013400
|
||||
#define STM32L4_SPI1_BASE 0x40013000
|
||||
#define STM32L4_TIM1_BASE 0x40012c00
|
||||
#define STM32_DSI_BASE 0x40016c00
|
||||
#define STM32_LTDC_BASE 0x40016800
|
||||
#define STM32_DFSDM_BASE 0x40016000
|
||||
#define STM32_SAI2_BASE 0x40015800
|
||||
#define STM32_SAI1_BASE 0x40015400
|
||||
#define STM32_TIM17_BASE 0x40014800
|
||||
#define STM32_TIM16_BASE 0x40014400
|
||||
#define STM32_TIM15_BASE 0x40014000
|
||||
#define STM32_USART1_BASE 0x40013800
|
||||
#define STM32_TIM8_BASE 0x40013400
|
||||
#define STM32_SPI1_BASE 0x40013000
|
||||
#define STM32_TIM1_BASE 0x40012c00
|
||||
#ifndef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x40012800
|
||||
# define STM32_SDMMC1_BASE 0x40012800
|
||||
#endif
|
||||
#define STM32L4_FIREWALL_BASE 0x40011c00
|
||||
#define STM32L4_EXTI_BASE 0x40010400
|
||||
#define STM32L4_COMP_BASE 0x40010200
|
||||
#define STM32L4_VREFBUF_BASE 0x40010030
|
||||
#define STM32L4_SYSCFG_BASE 0x40010000
|
||||
#define STM32_FIREWALL_BASE 0x40011c00
|
||||
#define STM32_EXTI_BASE 0x40010400
|
||||
#define STM32_COMP_BASE 0x40010200
|
||||
#define STM32_VREFBUF_BASE 0x40010030
|
||||
#define STM32_SYSCFG_BASE 0x40010000
|
||||
|
||||
/* AHB1 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32L4_GFXMMU_BASE 0x4002c000
|
||||
#define STM32L4_DMA2D_BASE 0x4002b000
|
||||
#define STM32L4_TSC_BASE 0x40024000
|
||||
#define STM32L4_CRC_BASE 0x40023000
|
||||
#define STM32L4_FLASHIF_BASE 0x40022000
|
||||
#define STM32L4_RCC_BASE 0x40021000
|
||||
#define STM32L4_DMAMUX1_BASE 0x40020800
|
||||
#define STM32L4_DMA2_BASE 0x40020400
|
||||
#define STM32L4_DMA1_BASE 0x40020000
|
||||
#define STM32_GFXMMU_BASE 0x4002c000
|
||||
#define STM32_DMA2D_BASE 0x4002b000
|
||||
#define STM32_TSC_BASE 0x40024000
|
||||
#define STM32_CRC_BASE 0x40023000
|
||||
#define STM32_FLASHIF_BASE 0x40022000
|
||||
#define STM32_RCC_BASE 0x40021000
|
||||
#define STM32_DMAMUX1_BASE 0x40020800
|
||||
#define STM32_DMA2_BASE 0x40020400
|
||||
#define STM32_DMA1_BASE 0x40020000
|
||||
|
||||
/* AHB2 Base Addresses ******************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32L4_STM32L4XR
|
||||
# define STM32L4_SDMMC1_BASE 0x50062400
|
||||
# define STM32_SDMMC1_BASE 0x50062400
|
||||
#endif
|
||||
#define STM32L4_OCTOSPIIOM_BASE 0x50061c00
|
||||
#define STM32L4_RNG_BASE 0x50060800
|
||||
#define STM32L4_HASH_BASE 0x50060400
|
||||
#define STM32L4_AES_BASE 0x50060000
|
||||
#define STM32L4_DCMI_BASE 0x50050000
|
||||
#define STM32L4_ADC_BASE 0x50040000
|
||||
# define STM32L4_ADC1_BASE 0x50040000 /* ADC1 */
|
||||
# define STM32L4_ADC2_BASE 0x50040100 /* ADC2 */
|
||||
# define STM32L4_ADC3_BASE 0x50040200 /* ADC3 */
|
||||
# define STM32L4_ADCCMN_BASE 0x50040300 /* Common */
|
||||
#define STM32L4_OTGFS_BASE 0x50000000
|
||||
#define STM32L4_GPIOI_BASE 0x48002000
|
||||
#define STM32L4_GPIOH_BASE 0x48001c00
|
||||
#define STM32L4_GPIOG_BASE 0x48001800
|
||||
#define STM32L4_GPIOF_BASE 0x48001400
|
||||
#define STM32L4_GPIOE_BASE 0x48001000
|
||||
#define STM32L4_GPIOD_BASE 0x48000c00
|
||||
#define STM32L4_GPIOC_BASE 0x48000800
|
||||
#define STM32L4_GPIOB_BASE 0x48000400
|
||||
#define STM32L4_GPIOA_BASE 0x48000000
|
||||
#define STM32_OCTOSPIIOM_BASE 0x50061c00
|
||||
#define STM32_RNG_BASE 0x50060800
|
||||
#define STM32_HASH_BASE 0x50060400
|
||||
#define STM32_AES_BASE 0x50060000
|
||||
#define STM32_DCMI_BASE 0x50050000
|
||||
#define STM32_ADC_BASE 0x50040000
|
||||
# define STM32_ADC1_BASE 0x50040000 /* ADC1 */
|
||||
# define STM32_ADC2_BASE 0x50040100 /* ADC2 */
|
||||
# define STM32_ADC3_BASE 0x50040200 /* ADC3 */
|
||||
# define STM32_ADCCMN_BASE 0x50040300 /* Common */
|
||||
#define STM32_OTGFS_BASE 0x50000000
|
||||
#define STM32_GPIOI_BASE 0x48002000
|
||||
#define STM32_GPIOH_BASE 0x48001c00
|
||||
#define STM32_GPIOG_BASE 0x48001800
|
||||
#define STM32_GPIOF_BASE 0x48001400
|
||||
#define STM32_GPIOE_BASE 0x48001000
|
||||
#define STM32_GPIOD_BASE 0x48000c00
|
||||
#define STM32_GPIOC_BASE 0x48000800
|
||||
#define STM32_GPIOB_BASE 0x48000400
|
||||
#define STM32_GPIOA_BASE 0x48000000
|
||||
|
||||
/* Cortex-M4 Base Addresses *************************************************/
|
||||
|
||||
|
|
@ -229,7 +229,7 @@
|
|||
* this address range
|
||||
*/
|
||||
|
||||
#define STM32L4_SCS_BASE 0xe000e000
|
||||
#define STM32L4_DEBUGMCU_BASE 0xe0042000
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */
|
||||
|
|
|
|||
|
|
@ -36,64 +36,64 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32L4_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32L4_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32L4_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32L4_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32L4_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32L4_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32L4_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32L4_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32L4_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32L4_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32L4_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32L4_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32L4_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
|
||||
#define STM32L4_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
|
||||
#define STM32L4_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */
|
||||
#define STM32L4_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */
|
||||
#define STM32L4_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */
|
||||
#define STM32L4_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */
|
||||
#define STM32L4_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */
|
||||
#define STM32L4_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */
|
||||
#define STM32L4_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */
|
||||
#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
|
||||
#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
|
||||
#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */
|
||||
#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */
|
||||
#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */
|
||||
#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */
|
||||
#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */
|
||||
#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */
|
||||
#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */
|
||||
#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */
|
||||
# define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_PWR_CR1 (STM32L4_PWR_BASE+STM32L4_PWR_CR1_OFFSET)
|
||||
#define STM32L4_PWR_CR2 (STM32L4_PWR_BASE+STM32L4_PWR_CR2_OFFSET)
|
||||
#define STM32L4_PWR_CR3 (STM32L4_PWR_BASE+STM32L4_PWR_CR3_OFFSET)
|
||||
#define STM32L4_PWR_CR4 (STM32L4_PWR_BASE+STM32L4_PWR_CR4_OFFSET)
|
||||
#define STM32L4_PWR_SR1 (STM32L4_PWR_BASE+STM32L4_PWR_SR1_OFFSET)
|
||||
#define STM32L4_PWR_SR2 (STM32L4_PWR_BASE+STM32L4_PWR_SR2_OFFSET)
|
||||
#define STM32L4_PWR_SCR (STM32L4_PWR_BASE+STM32L4_PWR_SCR_OFFSET)
|
||||
#define STM32L4_PWR_PUCRA (STM32L4_PWR_BASE+STM32L4_PWR_PUCRA_OFFSET)
|
||||
#define STM32L4_PWR_PDCRA (STM32L4_PWR_BASE+STM32L4_PWR_PDCRA_OFFSET)
|
||||
#define STM32L4_PWR_PUCRB (STM32L4_PWR_BASE+STM32L4_PWR_PUCRB_OFFSET)
|
||||
#define STM32L4_PWR_PDCRB (STM32L4_PWR_BASE+STM32L4_PWR_PDCRB_OFFSET)
|
||||
#define STM32L4_PWR_PUCRC (STM32L4_PWR_BASE+STM32L4_PWR_PUCRC_OFFSET)
|
||||
#define STM32L4_PWR_PDCRC (STM32L4_PWR_BASE+STM32L4_PWR_PDCRC_OFFSET)
|
||||
#define STM32L4_PWR_PUCRD (STM32L4_PWR_BASE+STM32L4_PWR_PUCRD_OFFSET)
|
||||
#define STM32L4_PWR_PDCRD (STM32L4_PWR_BASE+STM32L4_PWR_PDCRD_OFFSET)
|
||||
#define STM32L4_PWR_PUCRE (STM32L4_PWR_BASE+STM32L4_PWR_PUCRE_OFFSET)
|
||||
#define STM32L4_PWR_PDCRE (STM32L4_PWR_BASE+STM32L4_PWR_PDCRE_OFFSET)
|
||||
#define STM32L4_PWR_PUCRF (STM32L4_PWR_BASE+STM32L4_PWR_PUCRF_OFFSET)
|
||||
#define STM32L4_PWR_PDCRF (STM32L4_PWR_BASE+STM32L4_PWR_PDCRF_OFFSET)
|
||||
#define STM32L4_PWR_PUCRG (STM32L4_PWR_BASE+STM32L4_PWR_PUCRG_OFFSET)
|
||||
#define STM32L4_PWR_PDCRG (STM32L4_PWR_BASE+STM32L4_PWR_PDCRG_OFFSET)
|
||||
#define STM32L4_PWR_PUCRH (STM32L4_PWR_BASE+STM32L4_PWR_PUCRH_OFFSET)
|
||||
#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET)
|
||||
#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET)
|
||||
#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET)
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET)
|
||||
#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET)
|
||||
#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET)
|
||||
#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET)
|
||||
#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET)
|
||||
#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET)
|
||||
#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET)
|
||||
#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET)
|
||||
#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET)
|
||||
#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET)
|
||||
#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET)
|
||||
#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET)
|
||||
#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET)
|
||||
#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET)
|
||||
#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET)
|
||||
#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET)
|
||||
#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET)
|
||||
#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET)
|
||||
#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET)
|
||||
#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET)
|
||||
#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET)
|
||||
#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET)
|
||||
#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET)
|
||||
# define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -38,40 +38,40 @@
|
|||
|
||||
/* General Characteristics **************************************************/
|
||||
|
||||
#define STM32L4_QSPI_MINBITS 8 /* Minimum word width */
|
||||
#define STM32L4_QSPI_MAXBITS 32 /* Maximum word width */
|
||||
#define STM32_QSPI_MINBITS 8 /* Minimum word width */
|
||||
#define STM32_QSPI_MAXBITS 32 /* Maximum word width */
|
||||
|
||||
/* QSPI register offsets ****************************************************/
|
||||
|
||||
#define STM32L4_QUADSPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define STM32L4_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */
|
||||
#define STM32L4_QUADSPI_SR_OFFSET 0x0008 /* Status Register */
|
||||
#define STM32L4_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */
|
||||
#define STM32L4_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */
|
||||
#define STM32L4_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */
|
||||
#define STM32L4_QUADSPI_AR_OFFSET 0x0018 /* Address Register */
|
||||
#define STM32L4_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */
|
||||
#define STM32L4_QUADSPI_DR_OFFSET 0x0020 /* Data Register */
|
||||
#define STM32L4_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */
|
||||
#define STM32L4_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */
|
||||
#define STM32L4_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */
|
||||
#define STM32L4_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */
|
||||
#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */
|
||||
#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */
|
||||
#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */
|
||||
#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */
|
||||
#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */
|
||||
#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */
|
||||
#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */
|
||||
#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */
|
||||
#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */
|
||||
#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */
|
||||
#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */
|
||||
#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */
|
||||
#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */
|
||||
|
||||
/* QSPI register addresses **************************************************/
|
||||
|
||||
#define STM32L4_QUADSPI_CR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET) /* Control Register */
|
||||
#define STM32L4_QUADSPI_DCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET) /* Device Configuration Register */
|
||||
#define STM32L4_QUADSPI_SR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET) /* Status Register */
|
||||
#define STM32L4_QUADSPI_FCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET) /* Flag Clear Register */
|
||||
#define STM32L4_QUADSPI_DLR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET) /* Data Length Register */
|
||||
#define STM32L4_QUADSPI_CCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */
|
||||
#define STM32L4_QUADSPI_AR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET) /* Address Register */
|
||||
#define STM32L4_QUADSPI_ABR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */
|
||||
#define STM32L4_QUADSPI_DR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET) /* Data Register */
|
||||
#define STM32L4_QUADSPI_PSMKR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */
|
||||
#define STM32L4_QUADSPI_PSMAR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */
|
||||
#define STM32L4_QUADSPI_PIR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET) /* Polling Interval Register */
|
||||
#define STM32L4_QUADSPI_LPTR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */
|
||||
#define STM32_QUADSPI_CR (STM32_QSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */
|
||||
#define STM32_QUADSPI_DCR (STM32_QSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */
|
||||
#define STM32_QUADSPI_SR (STM32_QSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */
|
||||
#define STM32_QUADSPI_FCR (STM32_QSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */
|
||||
#define STM32_QUADSPI_DLR (STM32_QSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */
|
||||
#define STM32_QUADSPI_CCR (STM32_QSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */
|
||||
#define STM32_QUADSPI_AR (STM32_QSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */
|
||||
#define STM32_QUADSPI_ABR (STM32_QSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */
|
||||
#define STM32_QUADSPI_DR (STM32_QSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */
|
||||
#define STM32_QUADSPI_PSMKR (STM32_QSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */
|
||||
#define STM32_QUADSPI_PSMAR (STM32_QSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */
|
||||
#define STM32_QUADSPI_PIR (STM32_QSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */
|
||||
#define STM32_QUADSPI_LPTR (STM32_QSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */
|
||||
|
||||
/* QSPI register bit definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -36,15 +36,15 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
|
||||
#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
|
||||
#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
|
||||
#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
|
||||
#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
|
||||
#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET)
|
||||
#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET)
|
||||
#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET)
|
||||
#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET)
|
||||
#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET)
|
||||
#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -29,117 +29,117 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */
|
||||
#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */
|
||||
#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */
|
||||
#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
|
||||
#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
|
||||
#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
|
||||
#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
|
||||
#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
|
||||
#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
|
||||
#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
|
||||
#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
|
||||
#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
|
||||
#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
|
||||
#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
|
||||
#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
|
||||
#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
|
||||
#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
|
||||
#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
|
||||
#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */
|
||||
#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
|
||||
#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
|
||||
#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */
|
||||
#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
|
||||
#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
|
||||
#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
|
||||
#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
|
||||
#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
|
||||
#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
|
||||
#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
|
||||
#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
|
||||
#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
|
||||
#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
|
||||
#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
|
||||
#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
|
||||
#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
|
||||
#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
|
||||
#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
|
||||
#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */
|
||||
|
||||
#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
|
||||
#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
|
||||
#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
|
||||
#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
|
||||
#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
|
||||
#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
|
||||
#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
|
||||
#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
|
||||
#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
|
||||
#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
|
||||
#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
|
||||
#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
|
||||
#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
|
||||
#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
|
||||
#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
|
||||
#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
|
||||
#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
|
||||
#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
|
||||
#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
|
||||
#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
|
||||
#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
|
||||
#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
|
||||
#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
|
||||
#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
|
||||
#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
|
||||
#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
|
||||
#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
|
||||
#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
|
||||
#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
|
||||
#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
|
||||
#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
|
||||
#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
|
||||
#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
|
||||
#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
|
||||
#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
|
||||
#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
|
||||
#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
|
||||
#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
|
||||
#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
|
||||
#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
|
||||
#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
|
||||
#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
|
||||
#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
|
||||
#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
|
||||
#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
|
||||
#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
|
||||
#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
|
||||
#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
|
||||
#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
|
||||
#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
|
||||
#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
|
||||
#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
|
||||
#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
|
||||
#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
|
||||
#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
|
||||
#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
|
||||
#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
|
||||
#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
|
||||
#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
|
||||
#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
|
||||
#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
|
||||
#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
|
||||
#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
|
||||
#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
|
||||
#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
|
||||
#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET)
|
||||
#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET)
|
||||
#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET)
|
||||
#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET)
|
||||
#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET)
|
||||
#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET)
|
||||
#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET)
|
||||
#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET)
|
||||
#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET)
|
||||
#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET)
|
||||
#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET)
|
||||
#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET)
|
||||
#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET)
|
||||
#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET)
|
||||
#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET)
|
||||
#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET)
|
||||
#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET)
|
||||
#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET)
|
||||
#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET)
|
||||
#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET)
|
||||
#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET)
|
||||
#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET)
|
||||
#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET)
|
||||
#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET)
|
||||
#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET)
|
||||
#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET)
|
||||
#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET)
|
||||
#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET)
|
||||
#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET)
|
||||
#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET)
|
||||
#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET)
|
||||
#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET)
|
||||
#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET)
|
||||
#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET)
|
||||
#define STM32_RTC_OR (STM32_RTC_BASE+STM32_RTC_OR_OFFSET)
|
||||
|
||||
#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n))
|
||||
#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET)
|
||||
#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET)
|
||||
#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET)
|
||||
#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET)
|
||||
#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET)
|
||||
#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET)
|
||||
#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET)
|
||||
#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET)
|
||||
#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET)
|
||||
#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET)
|
||||
#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET)
|
||||
#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET)
|
||||
#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET)
|
||||
#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET)
|
||||
#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET)
|
||||
#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET)
|
||||
#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET)
|
||||
#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET)
|
||||
#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET)
|
||||
#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET)
|
||||
#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET)
|
||||
#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET)
|
||||
#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET)
|
||||
#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET)
|
||||
#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET)
|
||||
#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET)
|
||||
#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET)
|
||||
#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET)
|
||||
#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET)
|
||||
#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET)
|
||||
#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET)
|
||||
#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET)
|
||||
#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n))
|
||||
#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET)
|
||||
#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET)
|
||||
#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET)
|
||||
#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET)
|
||||
#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET)
|
||||
#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET)
|
||||
#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET)
|
||||
#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET)
|
||||
#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET)
|
||||
#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET)
|
||||
#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET)
|
||||
#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET)
|
||||
#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET)
|
||||
#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET)
|
||||
#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET)
|
||||
#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET)
|
||||
#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET)
|
||||
#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET)
|
||||
#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET)
|
||||
#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET)
|
||||
#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET)
|
||||
#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET)
|
||||
#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET)
|
||||
#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET)
|
||||
#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET)
|
||||
#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET)
|
||||
#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET)
|
||||
#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET)
|
||||
#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET)
|
||||
#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET)
|
||||
#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET)
|
||||
#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET)
|
||||
|
||||
# define STM32L4_RTC_BKCOUNT 32
|
||||
# define STM32_RTC_BKCOUNT 32
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -36,67 +36,67 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
|
||||
#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */
|
||||
|
||||
#define STM32L4_SAI_A_OFFSET 0x0004
|
||||
#define STM32L4_SAI_B_OFFSET 0x0024
|
||||
#define STM32_SAI_A_OFFSET 0x0004
|
||||
#define STM32_SAI_B_OFFSET 0x0024
|
||||
|
||||
#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */
|
||||
#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */
|
||||
#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */
|
||||
#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */
|
||||
#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */
|
||||
#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */
|
||||
#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */
|
||||
#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */
|
||||
#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */
|
||||
#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */
|
||||
#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */
|
||||
#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */
|
||||
#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */
|
||||
#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */
|
||||
#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */
|
||||
#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET)
|
||||
#define STM32_SAI1_GCR (STM32_SAI_GCR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET)
|
||||
#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET)
|
||||
#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET)
|
||||
#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET)
|
||||
|
||||
#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET)
|
||||
#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET)
|
||||
#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET)
|
||||
#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET)
|
||||
#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET)
|
||||
#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET)
|
||||
#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET)
|
||||
#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET)
|
||||
#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_ACR1_OFFSET)
|
||||
#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_ACR2_OFFSET)
|
||||
#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_AFRCR_OFFSET)
|
||||
#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_ASLOTR_OFFSET)
|
||||
#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_AIM_OFFSET)
|
||||
#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_ASR_OFFSET)
|
||||
#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_ACLRFR_OFFSET)
|
||||
#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_ADR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET)
|
||||
#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET)
|
||||
#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET)
|
||||
#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET)
|
||||
#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET)
|
||||
#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET)
|
||||
#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET)
|
||||
#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET)
|
||||
#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_BCR1_OFFSET)
|
||||
#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_BCR2_OFFSET)
|
||||
#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_BFRCR_OFFSET)
|
||||
#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_BSLOTR_OFFSET)
|
||||
#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_BIM_OFFSET)
|
||||
#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_BSR_OFFSET)
|
||||
#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_BCLRFR_OFFSET)
|
||||
#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_BDR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET)
|
||||
#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET)
|
||||
#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET)
|
||||
#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET)
|
||||
#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET)
|
||||
#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET)
|
||||
#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET)
|
||||
#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET)
|
||||
#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET)
|
||||
#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET)
|
||||
#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET)
|
||||
#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET)
|
||||
#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_ACR1_OFFSET)
|
||||
#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_ACR2_OFFSET)
|
||||
#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_AFRCR_OFFSET)
|
||||
#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_ASLOTR_OFFSET)
|
||||
#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_AIM_OFFSET)
|
||||
#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_ASR_OFFSET)
|
||||
#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_ACLRFR_OFFSET)
|
||||
#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_ADR_OFFSET)
|
||||
|
||||
#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET)
|
||||
#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET)
|
||||
#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET)
|
||||
#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET)
|
||||
#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET)
|
||||
#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET)
|
||||
#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET)
|
||||
#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET)
|
||||
#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_BCR1_OFFSET)
|
||||
#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_BCR2_OFFSET)
|
||||
#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_BFRCR_OFFSET)
|
||||
#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_BSLOTR_OFFSET)
|
||||
#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_BIM_OFFSET)
|
||||
#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_BSR_OFFSET)
|
||||
#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_BCLRFR_OFFSET)
|
||||
#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_BDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -36,48 +36,48 @@
|
|||
|
||||
/* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
#define STM32L4_SPI_CLK_MAX 40000000UL
|
||||
#define STM32_SPI_CLK_MAX 40000000UL
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32L4_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32L4_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32L4_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32L4_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32L4_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32L4_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NSPI > 0
|
||||
# define STM32L4_SPI1_CR1 (STM32L4_SPI1_BASE+STM32L4_SPI_CR1_OFFSET)
|
||||
# define STM32L4_SPI1_CR2 (STM32L4_SPI1_BASE+STM32L4_SPI_CR2_OFFSET)
|
||||
# define STM32L4_SPI1_SR (STM32L4_SPI1_BASE+STM32L4_SPI_SR_OFFSET)
|
||||
# define STM32L4_SPI1_DR (STM32L4_SPI1_BASE+STM32L4_SPI_DR_OFFSET)
|
||||
# define STM32L4_SPI1_CRCPR (STM32L4_SPI1_BASE+STM32L4_SPI_CRCPR_OFFSET)
|
||||
# define STM32L4_SPI1_RXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L4_SPI1_TXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NSPI > 1
|
||||
# define STM32L4_SPI2_CR1 (STM32L4_SPI2_BASE+STM32L4_SPI_CR1_OFFSET)
|
||||
# define STM32L4_SPI2_CR2 (STM32L4_SPI2_BASE+STM32L4_SPI_CR2_OFFSET)
|
||||
# define STM32L4_SPI2_SR (STM32L4_SPI2_BASE+STM32L4_SPI_SR_OFFSET)
|
||||
# define STM32L4_SPI2_DR (STM32L4_SPI2_BASE+STM32L4_SPI_DR_OFFSET)
|
||||
# define STM32L4_SPI2_CRCPR (STM32L4_SPI2_BASE+STM32L4_SPI_CRCPR_OFFSET)
|
||||
# define STM32L4_SPI2_RXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L4_SPI2_TXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NSPI > 2
|
||||
# define STM32L4_SPI3_CR1 (STM32L4_SPI3_BASE+STM32L4_SPI_CR1_OFFSET)
|
||||
# define STM32L4_SPI3_CR2 (STM32L4_SPI3_BASE+STM32L4_SPI_CR2_OFFSET)
|
||||
# define STM32L4_SPI3_SR (STM32L4_SPI3_BASE+STM32L4_SPI_SR_OFFSET)
|
||||
# define STM32L4_SPI3_DR (STM32L4_SPI3_BASE+STM32L4_SPI_DR_OFFSET)
|
||||
# define STM32L4_SPI3_CRCPR (STM32L4_SPI3_BASE+STM32L4_SPI_CRCPR_OFFSET)
|
||||
# define STM32L4_SPI3_RXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_RXCRCR_OFFSET)
|
||||
# define STM32L4_SPI3_TXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -31,14 +31,14 @@
|
|||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32L4_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32L4_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32L4_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32L4_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32L4_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32L4_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32L4_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32L4_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
|
||||
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17.
|
||||
* TIM3 and 4 are 16-bit.
|
||||
|
|
@ -46,119 +46,119 @@
|
|||
* TIM15, 16 and 17 are 16-bit.
|
||||
*/
|
||||
|
||||
#define STM32L4_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */
|
||||
#define STM32L4_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32L4_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32L4_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */
|
||||
#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */
|
||||
#define STM32L4_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32L4_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */
|
||||
#define STM32L4_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */
|
||||
#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */
|
||||
#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */
|
||||
#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */
|
||||
#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */
|
||||
#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */
|
||||
|
||||
/* TIM15, 16, and 17 only.
|
||||
*/
|
||||
|
||||
#define STM32L4_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */
|
||||
#define STM32L4_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */
|
||||
#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */
|
||||
#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#define STM32L4_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32L4_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */
|
||||
#define STM32L4_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32L4_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32L4_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */
|
||||
#define STM32L4_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32L4_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */
|
||||
#define STM32L4_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */
|
||||
#define STM32L4_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */
|
||||
#define STM32L4_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32L4_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32L4_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32L4_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
|
||||
#define STM32L4_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32L4_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32L4_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32L4_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32L4_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */
|
||||
#define STM32L4_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32L4_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32L4_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */
|
||||
#define STM32L4_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */
|
||||
#define STM32L4_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32L4_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */
|
||||
#define STM32L4_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */
|
||||
#define STM32L4_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */
|
||||
#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */
|
||||
#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */
|
||||
#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */
|
||||
#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */
|
||||
#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */
|
||||
#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
|
||||
#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */
|
||||
#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */
|
||||
#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */
|
||||
#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */
|
||||
#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */
|
||||
#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#define STM32L4_TIM1_CR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM1_CR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM1_SMCR (STM32L4_TIM1_BASE+STM32L4_ATIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM1_DIER (STM32L4_TIM1_BASE+STM32L4_ATIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM1_SR (STM32L4_TIM1_BASE+STM32L4_ATIM_SR_OFFSET)
|
||||
#define STM32L4_TIM1_EGR (STM32L4_TIM1_BASE+STM32L4_ATIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM1_CCMR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM1_CCMR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM1_CCER (STM32L4_TIM1_BASE+STM32L4_ATIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM1_CNT (STM32L4_TIM1_BASE+STM32L4_ATIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM1_PSC (STM32L4_TIM1_BASE+STM32L4_ATIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM1_ARR (STM32L4_TIM1_BASE+STM32L4_ATIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM1_RCR (STM32L4_TIM1_BASE+STM32L4_ATIM_RCR_OFFSET)
|
||||
#define STM32L4_TIM1_CCR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM1_CCR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM1_CCR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR3_OFFSET)
|
||||
#define STM32L4_TIM1_CCR4 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR4_OFFSET)
|
||||
#define STM32L4_TIM1_BDTR (STM32L4_TIM1_BASE+STM32L4_ATIM_BDTR_OFFSET)
|
||||
#define STM32L4_TIM1_DCR (STM32L4_TIM1_BASE+STM32L4_ATIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM1_DMAR (STM32L4_TIM1_BASE+STM32L4_ATIM_DMAR_OFFSET)
|
||||
#define STM32L4_TIM1_OR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR1_OFFSET)
|
||||
#define STM32L4_TIM1_CCMR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR3_OFFSET)
|
||||
#define STM32L4_TIM1_CCR5 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR5_OFFSET)
|
||||
#define STM32L4_TIM1_CCR6 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR6_OFFSET)
|
||||
#define STM32L4_TIM1_OR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR2_OFFSET)
|
||||
#define STM32L4_TIM1_OR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR3_OFFSET)
|
||||
#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
|
||||
#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET)
|
||||
#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET)
|
||||
#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET)
|
||||
#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET)
|
||||
#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET)
|
||||
#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET)
|
||||
|
||||
#define STM32L4_TIM8_CR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM8_CR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM8_SMCR (STM32L4_TIM8_BASE+STM32L4_ATIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM8_DIER (STM32L4_TIM8_BASE+STM32L4_ATIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM8_SR (STM32L4_TIM8_BASE+STM32L4_ATIM_SR_OFFSET)
|
||||
#define STM32L4_TIM8_EGR (STM32L4_TIM8_BASE+STM32L4_ATIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM8_CCMR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM8_CCMR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM8_CCER (STM32L4_TIM8_BASE+STM32L4_ATIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM8_CNT (STM32L4_TIM8_BASE+STM32L4_ATIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM8_PSC (STM32L4_TIM8_BASE+STM32L4_ATIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM8_ARR (STM32L4_TIM8_BASE+STM32L4_ATIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM8_RCR (STM32L4_TIM8_BASE+STM32L4_ATIM_RCR_OFFSET)
|
||||
#define STM32L4_TIM8_CCR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM8_CCR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM8_CCR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR3_OFFSET)
|
||||
#define STM32L4_TIM8_CCR4 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR4_OFFSET)
|
||||
#define STM32L4_TIM8_BDTR (STM32L4_TIM8_BASE+STM32L4_ATIM_BDTR_OFFSET)
|
||||
#define STM32L4_TIM8_DCR (STM32L4_TIM8_BASE+STM32L4_ATIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM8_DMAR (STM32L4_TIM8_BASE+STM32L4_ATIM_DMAR_OFFSET)
|
||||
#define STM32L4_TIM8_OR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR1_OFFSET)
|
||||
#define STM32L4_TIM8_CCMR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR3_OFFSET)
|
||||
#define STM32L4_TIM8_CCR5 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR5_OFFSET)
|
||||
#define STM32L4_TIM8_CCR6 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR6_OFFSET)
|
||||
#define STM32L4_TIM8_OR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR2_OFFSET)
|
||||
#define STM32L4_TIM8_OR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR3_OFFSET)
|
||||
#define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
#define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
#define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
#define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
#define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
|
||||
#define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
#define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
#define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
#define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
#define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
#define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
#define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
#define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
#define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
#define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
#define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
#define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#define STM32_TIM8_OR1 (STM32_TIM8_BASE+STM32_ATIM_OR1_OFFSET)
|
||||
#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET)
|
||||
#define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET)
|
||||
#define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET)
|
||||
#define STM32_TIM8_OR2 (STM32_TIM8_BASE+STM32_ATIM_OR2_OFFSET)
|
||||
#define STM32_TIM8_OR3 (STM32_TIM8_BASE+STM32_ATIM_OR3_OFFSET)
|
||||
|
||||
/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17.
|
||||
* TIM3 and 4 are 16-bit.
|
||||
|
|
@ -166,154 +166,154 @@
|
|||
* TIM15, 16 and 17 are 16-bit.
|
||||
*/
|
||||
|
||||
#define STM32L4_TIM2_CR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM2_CR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM2_SMCR (STM32L4_TIM2_BASE+STM32L4_GTIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM2_DIER (STM32L4_TIM2_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM2_SR (STM32L4_TIM2_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM2_EGR (STM32L4_TIM2_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM2_CCMR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM2_CCMR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM2_CCER (STM32L4_TIM2_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM2_CNT (STM32L4_TIM2_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM2_PSC (STM32L4_TIM2_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM2_ARR (STM32L4_TIM2_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM2_CCR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM2_CCR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM2_CCR3 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR3_OFFSET)
|
||||
#define STM32L4_TIM2_CCR4 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR4_OFFSET)
|
||||
#define STM32L4_TIM2_DCR (STM32L4_TIM2_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM2_DMAR (STM32L4_TIM2_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32L4_TIM2_OR (STM32L4_TIM2_BASE+STM32L4_GTIM_OR_OFFSET)
|
||||
#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM3_CR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM3_CR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM3_SMCR (STM32L4_TIM3_BASE+STM32L4_GTIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM3_DIER (STM32L4_TIM3_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM3_SR (STM32L4_TIM3_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM3_EGR (STM32L4_TIM3_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM3_CCMR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM3_CCMR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM3_CCER (STM32L4_TIM3_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM3_CNT (STM32L4_TIM3_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM3_PSC (STM32L4_TIM3_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM3_ARR (STM32L4_TIM3_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM3_CCR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM3_CCR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM3_CCR3 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR3_OFFSET)
|
||||
#define STM32L4_TIM3_CCR4 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR4_OFFSET)
|
||||
#define STM32L4_TIM3_DCR (STM32L4_TIM3_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM3_DMAR (STM32L4_TIM3_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM4_CR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM4_CR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM4_SMCR (STM32L4_TIM4_BASE+STM32L4_GTIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM4_DIER (STM32L4_TIM4_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM4_SR (STM32L4_TIM4_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM4_EGR (STM32L4_TIM4_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM4_CCMR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM4_CCMR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM4_CCER (STM32L4_TIM4_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM4_CNT (STM32L4_TIM4_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM4_PSC (STM32L4_TIM4_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM4_ARR (STM32L4_TIM4_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM4_CCR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM4_CCR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM4_CCR3 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR3_OFFSET)
|
||||
#define STM32L4_TIM4_CCR4 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR4_OFFSET)
|
||||
#define STM32L4_TIM4_DCR (STM32L4_TIM4_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM4_DMAR (STM32L4_TIM4_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
#define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
#define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
#define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
#define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM5_CR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM5_CR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM5_SMCR (STM32L4_TIM5_BASE+STM32L4_GTIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM5_DIER (STM32L4_TIM5_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM5_SR (STM32L4_TIM5_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM5_EGR (STM32L4_TIM5_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM5_CCMR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM5_CCMR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR2_OFFSET)
|
||||
#define STM32L4_TIM5_CCER (STM32L4_TIM5_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM5_CNT (STM32L4_TIM5_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM5_PSC (STM32L4_TIM5_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM5_ARR (STM32L4_TIM5_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM5_CCR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM5_CCR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM5_CCR3 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR3_OFFSET)
|
||||
#define STM32L4_TIM5_CCR4 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR4_OFFSET)
|
||||
#define STM32L4_TIM5_DCR (STM32L4_TIM5_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM5_DMAR (STM32L4_TIM5_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32L4_TIM5_OR (STM32L4_TIM5_BASE+STM32L4_GTIM_OR_OFFSET)
|
||||
#define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
#define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
#define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
#define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
#define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM15_CR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM15_CR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM15_SMCR (STM32L4_TIM15_BASE+STM32L4_GTIM_SMCR_OFFSET)
|
||||
#define STM32L4_TIM15_DIER (STM32L4_TIM15_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM15_SR (STM32L4_TIM15_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM15_EGR (STM32L4_TIM15_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM15_CCMR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM15_CCER (STM32L4_TIM15_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM15_CNT (STM32L4_TIM15_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM15_PSC (STM32L4_TIM15_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM15_ARR (STM32L4_TIM15_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM15_RCR (STM32L4_TIM15_BASE+STM32L4_GTIM_RCR_OFFSET)
|
||||
#define STM32L4_TIM15_CCR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM15_CCR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR2_OFFSET)
|
||||
#define STM32L4_TIM15_BDTR (STM32L4_TIM15_BASE+STM32L4_GTIM_BDTR_OFFSET)
|
||||
#define STM32L4_TIM15_DCR (STM32L4_TIM15_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM15_DMAR (STM32L4_TIM15_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET)
|
||||
#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET)
|
||||
#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM16_CR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM16_CR2 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM16_DIER (STM32L4_TIM16_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM16_SR (STM32L4_TIM16_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM16_EGR (STM32L4_TIM16_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM16_CCMR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM16_CCER (STM32L4_TIM16_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM16_CNT (STM32L4_TIM16_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM16_PSC (STM32L4_TIM16_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM16_ARR (STM32L4_TIM16_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM16_RCR (STM32L4_TIM16_BASE+STM32L4_GTIM_RCR_OFFSET)
|
||||
#define STM32L4_TIM16_CCR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM16_BDTR (STM32L4_TIM16_BASE+STM32L4_GTIM_BDTR_OFFSET)
|
||||
#define STM32L4_TIM16_DCR (STM32L4_TIM16_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM16_DMAR (STM32L4_TIM16_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32L4_TIM16_OR (STM32L4_TIM16_BASE+STM32L4_GTIM_OR_OFFSET)
|
||||
#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET)
|
||||
#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET)
|
||||
#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM17_CR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM17_CR2 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM17_DIER (STM32L4_TIM17_BASE+STM32L4_GTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM17_SR (STM32L4_TIM17_BASE+STM32L4_GTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM17_EGR (STM32L4_TIM17_BASE+STM32L4_GTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM17_CCMR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR1_OFFSET)
|
||||
#define STM32L4_TIM17_CCER (STM32L4_TIM17_BASE+STM32L4_GTIM_CCER_OFFSET)
|
||||
#define STM32L4_TIM17_CNT (STM32L4_TIM17_BASE+STM32L4_GTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM17_PSC (STM32L4_TIM17_BASE+STM32L4_GTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM17_ARR (STM32L4_TIM17_BASE+STM32L4_GTIM_ARR_OFFSET)
|
||||
#define STM32L4_TIM17_RCR (STM32L4_TIM17_BASE+STM32L4_GTIM_RCR_OFFSET)
|
||||
#define STM32L4_TIM17_CCR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCR1_OFFSET)
|
||||
#define STM32L4_TIM17_BDTR (STM32L4_TIM17_BASE+STM32L4_GTIM_BDTR_OFFSET)
|
||||
#define STM32L4_TIM17_DCR (STM32L4_TIM17_BASE+STM32L4_GTIM_DCR_OFFSET)
|
||||
#define STM32L4_TIM17_DMAR (STM32L4_TIM17_BASE+STM32L4_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
|
||||
#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
|
||||
#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32L4_TIM6_CR1 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM6_CR2 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM6_DIER (STM32L4_TIM6_BASE+STM32L4_BTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM6_SR (STM32L4_TIM6_BASE+STM32L4_BTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM6_EGR (STM32L4_TIM6_BASE+STM32L4_BTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM6_CNT (STM32L4_TIM6_BASE+STM32L4_BTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM6_PSC (STM32L4_TIM6_BASE+STM32L4_BTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM6_ARR (STM32L4_TIM6_BASE+STM32L4_BTIM_ARR_OFFSET)
|
||||
#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
|
||||
#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
|
||||
#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
|
||||
#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
|
||||
#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
|
||||
#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
|
||||
#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
|
||||
#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
|
||||
|
||||
#define STM32L4_TIM7_CR1 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR1_OFFSET)
|
||||
#define STM32L4_TIM7_CR2 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR2_OFFSET)
|
||||
#define STM32L4_TIM7_DIER (STM32L4_TIM7_BASE+STM32L4_BTIM_DIER_OFFSET)
|
||||
#define STM32L4_TIM7_SR (STM32L4_TIM7_BASE+STM32L4_BTIM_SR_OFFSET)
|
||||
#define STM32L4_TIM7_EGR (STM32L4_TIM7_BASE+STM32L4_BTIM_EGR_OFFSET)
|
||||
#define STM32L4_TIM7_CNT (STM32L4_TIM7_BASE+STM32L4_BTIM_CNT_OFFSET)
|
||||
#define STM32L4_TIM7_PSC (STM32L4_TIM7_BASE+STM32L4_BTIM_PSC_OFFSET)
|
||||
#define STM32L4_TIM7_ARR (STM32L4_TIM7_BASE+STM32L4_BTIM_ARR_OFFSET)
|
||||
#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
|
||||
#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
|
||||
#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
|
||||
#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
|
||||
#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
|
||||
#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
|
||||
#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
|
||||
#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -37,88 +37,88 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32L4_NUSART > 0
|
||||
# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 1
|
||||
# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 2
|
||||
# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 3
|
||||
# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32L4_NUSART > 4
|
||||
# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET)
|
||||
# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET)
|
||||
# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET)
|
||||
# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET)
|
||||
# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET)
|
||||
# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET)
|
||||
# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET)
|
||||
# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET)
|
||||
# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET)
|
||||
# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET)
|
||||
# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET)
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
|
|
|||
|
|
@ -40,71 +40,71 @@
|
|||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
|
||||
#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
|
||||
|
||||
#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
|
||||
#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
|
||||
#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
|
||||
#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
|
||||
#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
|
||||
#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
|
||||
#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
|
||||
#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
|
||||
#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
|
||||
#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
|
||||
#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
|
||||
#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
|
||||
#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
|
||||
#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
|
||||
#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
|
||||
#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
|
||||
#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
|
||||
#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
|
||||
#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
|
||||
#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
|
||||
#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
|
||||
#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
|
||||
#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
|
||||
#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
|
||||
#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
|
||||
#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
|
||||
#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
|
||||
#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
|
||||
#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
|
||||
#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
|
||||
#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
|
||||
#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
|
||||
#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
|
||||
#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
|
||||
|
||||
#define STM32L4_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o))
|
||||
#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
|
||||
#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o))
|
||||
#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n))
|
||||
#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET)
|
||||
#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET)
|
||||
#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET)
|
||||
#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET)
|
||||
#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET)
|
||||
#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET)
|
||||
#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET)
|
||||
#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET)
|
||||
#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n))
|
||||
#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET)
|
||||
#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET)
|
||||
#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET)
|
||||
#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET)
|
||||
#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET)
|
||||
#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET)
|
||||
#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET)
|
||||
#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET)
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET)
|
||||
#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET)
|
||||
#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET)
|
||||
#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET)
|
||||
#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET)
|
||||
#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET)
|
||||
#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET)
|
||||
#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET)
|
||||
#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET)
|
||||
#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET)
|
||||
#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET)
|
||||
#define STM32_USB_BTABLE (STM32_USB_FS_BASE + STM32_USB_BTABLE_OFFSET)
|
||||
#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET)
|
||||
#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET)
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o))
|
||||
#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
|
||||
#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_SRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o))
|
||||
#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -37,27 +37,27 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
|
||||
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
|
||||
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
|
||||
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
|
||||
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
|
||||
#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */
|
||||
|
||||
#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
|
||||
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
|
||||
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET)
|
||||
#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET)
|
||||
#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET)
|
||||
#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET)
|
||||
#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET)
|
||||
#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
|
||||
#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
|
||||
#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
|
||||
#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
|
||||
#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
|
||||
|
||||
#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET)
|
||||
#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET)
|
||||
#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET)
|
||||
#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
|
||||
#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
|
||||
#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -34,141 +34,141 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32L4_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32L4_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32L4_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32L4_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32L4_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32L4_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32L4_DMACHAN7_OFFSET 0x0078
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
@ -277,21 +277,21 @@
|
|||
* numeric suffix. Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32L4_DMA1_CHAN1 (0)
|
||||
#define STM32L4_DMA1_CHAN2 (1)
|
||||
#define STM32L4_DMA1_CHAN3 (2)
|
||||
#define STM32L4_DMA1_CHAN4 (3)
|
||||
#define STM32L4_DMA1_CHAN5 (4)
|
||||
#define STM32L4_DMA1_CHAN6 (5)
|
||||
#define STM32L4_DMA1_CHAN7 (6)
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32L4_DMA2_CHAN1 (7)
|
||||
#define STM32L4_DMA2_CHAN2 (8)
|
||||
#define STM32L4_DMA2_CHAN3 (9)
|
||||
#define STM32L4_DMA2_CHAN4 (10)
|
||||
#define STM32L4_DMA2_CHAN5 (11)
|
||||
#define STM32L4_DMA2_CHAN6 (12)
|
||||
#define STM32L4_DMA2_CHAN7 (13)
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
#define STM32_DMA2_CHAN6 (12)
|
||||
#define STM32_DMA2_CHAN7 (13)
|
||||
|
||||
/* DMA Channel settings include a channel and an alternative function.
|
||||
* Channel is in bits 0..7
|
||||
|
|
@ -306,145 +306,145 @@
|
|||
|
||||
/* ADC */
|
||||
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0)
|
||||
|
||||
/* AES */
|
||||
|
||||
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6)
|
||||
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6)
|
||||
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6)
|
||||
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6)
|
||||
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6)
|
||||
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6)
|
||||
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6)
|
||||
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
/* DCMI */
|
||||
|
||||
#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4)
|
||||
#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0)
|
||||
#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4)
|
||||
#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0)
|
||||
|
||||
/* DFSDM */
|
||||
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5)
|
||||
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
|
||||
|
||||
#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0)
|
||||
#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0)
|
||||
#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0)
|
||||
#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0)
|
||||
|
||||
/* QUADSPI */
|
||||
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3)
|
||||
|
||||
/* SAI */
|
||||
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1)
|
||||
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1)
|
||||
|
||||
/* SDMMC */
|
||||
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4)
|
||||
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1)
|
||||
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3)
|
||||
|
||||
/* SWPMI */
|
||||
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4)
|
||||
|
||||
/* TIM */
|
||||
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7)
|
||||
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4)
|
||||
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
|
||||
/* UART */
|
||||
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2)
|
||||
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
|
||||
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2)
|
||||
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2)
|
||||
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H */
|
||||
|
|
|
|||
|
|
@ -38,23 +38,23 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -37,73 +37,73 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -38,33 +38,33 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -34,141 +34,141 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32L4_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32L4_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32L4_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32L4_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32L4_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32L4_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32L4_DMACHAN7_OFFSET 0x0078
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
@ -277,21 +277,21 @@
|
|||
* numeric suffix. Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32L4_DMA1_CHAN1 (0)
|
||||
#define STM32L4_DMA1_CHAN2 (1)
|
||||
#define STM32L4_DMA1_CHAN3 (2)
|
||||
#define STM32L4_DMA1_CHAN4 (3)
|
||||
#define STM32L4_DMA1_CHAN5 (4)
|
||||
#define STM32L4_DMA1_CHAN6 (5)
|
||||
#define STM32L4_DMA1_CHAN7 (6)
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32L4_DMA2_CHAN1 (7)
|
||||
#define STM32L4_DMA2_CHAN2 (8)
|
||||
#define STM32L4_DMA2_CHAN3 (9)
|
||||
#define STM32L4_DMA2_CHAN4 (10)
|
||||
#define STM32L4_DMA2_CHAN5 (11)
|
||||
#define STM32L4_DMA2_CHAN6 (12)
|
||||
#define STM32L4_DMA2_CHAN7 (13)
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
#define STM32_DMA2_CHAN6 (12)
|
||||
#define STM32_DMA2_CHAN7 (13)
|
||||
|
||||
/* DMA Channel settings include a channel and an alternative function.
|
||||
* Channel is in bits 0..7
|
||||
|
|
@ -306,167 +306,167 @@
|
|||
|
||||
/* ADC */
|
||||
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0)
|
||||
|
||||
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0)
|
||||
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0)
|
||||
|
||||
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0)
|
||||
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
/* DFSDM */
|
||||
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0)
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5)
|
||||
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 3)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
|
||||
|
||||
/* QUADSPI */
|
||||
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3)
|
||||
|
||||
/* SAI */
|
||||
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1)
|
||||
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1)
|
||||
|
||||
/* SDMMC */
|
||||
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4)
|
||||
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1)
|
||||
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3)
|
||||
|
||||
/* SWPMI */
|
||||
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4)
|
||||
|
||||
/* TIM */
|
||||
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7)
|
||||
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4)
|
||||
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
|
||||
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6)
|
||||
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6)
|
||||
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6)
|
||||
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6)
|
||||
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6)
|
||||
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6)
|
||||
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6)
|
||||
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6)
|
||||
|
||||
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5)
|
||||
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5)
|
||||
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5)
|
||||
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5)
|
||||
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7)
|
||||
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7)
|
||||
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7)
|
||||
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7)
|
||||
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
|
||||
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
|
||||
/* UART */
|
||||
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2)
|
||||
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
|
||||
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2)
|
||||
|
||||
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2)
|
||||
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2)
|
||||
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2)
|
||||
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2)
|
||||
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2)
|
||||
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H */
|
||||
|
|
|
|||
|
|
@ -38,23 +38,23 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -48,182 +48,182 @@
|
|||
|
||||
/* Core global control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
|
||||
#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET)
|
||||
#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET)
|
||||
#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET)
|
||||
#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET)
|
||||
#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET)
|
||||
#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET)
|
||||
#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET)
|
||||
#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n))
|
||||
#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n))
|
||||
#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET)
|
||||
#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET)
|
||||
#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET)
|
||||
#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET)
|
||||
#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n))
|
||||
#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET)
|
||||
#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET)
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
@ -741,7 +741,7 @@
|
|||
#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0
|
||||
#define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */
|
||||
#define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT)
|
||||
/* Bits 24-31: Reserved, must be kept at reset value */
|
||||
/* Bits 24-31: Reserved, must be kept at reset value */
|
||||
|
||||
/* Device IN endpoint common interrupt mask register */
|
||||
|
||||
|
|
|
|||
|
|
@ -37,69 +37,69 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -38,33 +38,33 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -34,141 +34,141 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32L4_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32L4_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32L4_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32L4_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32L4_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32L4_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32L4_DMACHAN7_OFFSET 0x0078
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
@ -276,21 +276,21 @@
|
|||
* numeric suffix. Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32L4_DMA1_CHAN1 (0)
|
||||
#define STM32L4_DMA1_CHAN2 (1)
|
||||
#define STM32L4_DMA1_CHAN3 (2)
|
||||
#define STM32L4_DMA1_CHAN4 (3)
|
||||
#define STM32L4_DMA1_CHAN5 (4)
|
||||
#define STM32L4_DMA1_CHAN6 (5)
|
||||
#define STM32L4_DMA1_CHAN7 (6)
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32L4_DMA2_CHAN1 (7)
|
||||
#define STM32L4_DMA2_CHAN2 (8)
|
||||
#define STM32L4_DMA2_CHAN3 (9)
|
||||
#define STM32L4_DMA2_CHAN4 (10)
|
||||
#define STM32L4_DMA2_CHAN5 (11)
|
||||
#define STM32L4_DMA2_CHAN6 (12)
|
||||
#define STM32L4_DMA2_CHAN7 (13)
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
#define STM32_DMA2_CHAN6 (12)
|
||||
#define STM32_DMA2_CHAN7 (13)
|
||||
|
||||
/* DMA Channel settings include a channel and an alternative function.
|
||||
* Channel is in bits 0..7
|
||||
|
|
@ -305,186 +305,186 @@
|
|||
|
||||
/* ADC */
|
||||
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0)
|
||||
#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0)
|
||||
|
||||
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0)
|
||||
#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0)
|
||||
|
||||
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0)
|
||||
#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0)
|
||||
#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0)
|
||||
|
||||
/* AES */
|
||||
|
||||
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6)
|
||||
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6)
|
||||
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6)
|
||||
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6)
|
||||
#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6)
|
||||
#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6)
|
||||
#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6)
|
||||
#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6)
|
||||
|
||||
/* DAC */
|
||||
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
/* DCMI */
|
||||
|
||||
#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4)
|
||||
#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0)
|
||||
#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4)
|
||||
#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0)
|
||||
|
||||
/* DFSDM */
|
||||
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0)
|
||||
#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0)
|
||||
#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0)
|
||||
#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0)
|
||||
#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0)
|
||||
|
||||
/* HASH */
|
||||
|
||||
#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 6)
|
||||
#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32_DMA2_CHAN7, 6)
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5)
|
||||
#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3)
|
||||
#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5)
|
||||
#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3)
|
||||
#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5)
|
||||
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3)
|
||||
#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3)
|
||||
#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3)
|
||||
#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3)
|
||||
|
||||
#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0)
|
||||
#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0)
|
||||
#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0)
|
||||
#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0)
|
||||
|
||||
/* QUADSPI */
|
||||
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3)
|
||||
#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5)
|
||||
#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3)
|
||||
|
||||
/* SAI */
|
||||
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1)
|
||||
#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1)
|
||||
#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1)
|
||||
#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1)
|
||||
#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1)
|
||||
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1)
|
||||
#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1)
|
||||
#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1)
|
||||
#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1)
|
||||
#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1)
|
||||
|
||||
/* SDMMC */
|
||||
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7)
|
||||
#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7)
|
||||
#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7)
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4)
|
||||
#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1)
|
||||
#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4)
|
||||
#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1)
|
||||
#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4)
|
||||
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1)
|
||||
#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1)
|
||||
#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1)
|
||||
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3)
|
||||
#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3)
|
||||
#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3)
|
||||
|
||||
/* SWPMI */
|
||||
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4)
|
||||
#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4)
|
||||
#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4)
|
||||
|
||||
/* TIM */
|
||||
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7)
|
||||
#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7)
|
||||
#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7)
|
||||
#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7)
|
||||
#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7)
|
||||
#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7)
|
||||
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4)
|
||||
#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4)
|
||||
#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4)
|
||||
#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4)
|
||||
#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4)
|
||||
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5)
|
||||
#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5)
|
||||
#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5)
|
||||
|
||||
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6)
|
||||
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6)
|
||||
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6)
|
||||
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6)
|
||||
#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6)
|
||||
#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6)
|
||||
#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6)
|
||||
#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6)
|
||||
|
||||
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5)
|
||||
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5)
|
||||
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5)
|
||||
#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5)
|
||||
#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5)
|
||||
#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5)
|
||||
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3)
|
||||
#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6)
|
||||
#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3)
|
||||
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3)
|
||||
#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5)
|
||||
#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3)
|
||||
|
||||
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7)
|
||||
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7)
|
||||
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7)
|
||||
#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7)
|
||||
#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7)
|
||||
#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7)
|
||||
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7)
|
||||
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4)
|
||||
#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4)
|
||||
|
||||
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5)
|
||||
#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5)
|
||||
|
||||
/* UART */
|
||||
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2)
|
||||
#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2)
|
||||
#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2)
|
||||
#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2)
|
||||
#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2)
|
||||
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
|
||||
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2)
|
||||
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2)
|
||||
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
|
||||
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2)
|
||||
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2)
|
||||
|
||||
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2)
|
||||
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2)
|
||||
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2)
|
||||
#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2)
|
||||
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2)
|
||||
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2)
|
||||
#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2)
|
||||
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
|
||||
#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4)
|
||||
#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H */
|
||||
|
|
|
|||
|
|
@ -38,23 +38,23 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -48,182 +48,182 @@
|
|||
|
||||
/* Core global control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */
|
||||
#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */
|
||||
#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
|
||||
#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */
|
||||
#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */
|
||||
#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
|
||||
#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
|
||||
#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
|
||||
#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
|
||||
#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
|
||||
#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
|
||||
#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
|
||||
#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */
|
||||
#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */
|
||||
#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */
|
||||
#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */
|
||||
#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */
|
||||
#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */
|
||||
#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */
|
||||
#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
|
||||
#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
|
||||
#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
|
||||
#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
|
||||
#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */
|
||||
|
||||
#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5)
|
||||
#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
|
||||
#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
|
||||
#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
|
||||
#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */
|
||||
#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */
|
||||
#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */
|
||||
#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
|
||||
#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
|
||||
#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
|
||||
#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
|
||||
#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
|
||||
#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
|
||||
#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
|
||||
#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
|
||||
#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
|
||||
#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
|
||||
#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET)
|
||||
#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET)
|
||||
#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET)
|
||||
#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET)
|
||||
#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET)
|
||||
#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET)
|
||||
#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET)
|
||||
#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET)
|
||||
#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET)
|
||||
#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET)
|
||||
#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET)
|
||||
#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET)
|
||||
#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET)
|
||||
#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET)
|
||||
#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET)
|
||||
#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n))
|
||||
|
||||
/* Host-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET)
|
||||
#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET)
|
||||
#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET)
|
||||
#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET)
|
||||
#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET)
|
||||
#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET)
|
||||
#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET)
|
||||
#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n))
|
||||
#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n))
|
||||
#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n))
|
||||
#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n))
|
||||
|
||||
/* Device-mode control and status registers */
|
||||
|
||||
#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET)
|
||||
#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET)
|
||||
#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET)
|
||||
#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET)
|
||||
#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET)
|
||||
#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET)
|
||||
#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET)
|
||||
#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET)
|
||||
#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET)
|
||||
#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET)
|
||||
#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET)
|
||||
|
||||
#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n))
|
||||
#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n))
|
||||
|
||||
#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n))
|
||||
|
||||
/* Power and clock gating registers */
|
||||
|
||||
#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET)
|
||||
#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET)
|
||||
|
||||
/* Data FIFO (DFIFO) access registers */
|
||||
|
||||
#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n))
|
||||
#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n))
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -37,73 +37,73 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -38,35 +38,35 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -41,139 +41,139 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32L4_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32L4_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32L4_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32L4_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32L4_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32L4_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32L4_DMACHAN7_OFFSET 0x0078
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN1_OFFSET 0x0000
|
||||
#define STM32_DMACHAN2_OFFSET 0x0014
|
||||
#define STM32_DMACHAN3_OFFSET 0x0028
|
||||
#define STM32_DMACHAN4_OFFSET 0x003c
|
||||
#define STM32_DMACHAN5_OFFSET 0x0050
|
||||
#define STM32_DMACHAN6_OFFSET 0x0064
|
||||
#define STM32_DMACHAN7_OFFSET 0x0078
|
||||
|
||||
#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
|
||||
|
||||
#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET)
|
||||
#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET)
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET)
|
||||
#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET)
|
||||
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
|
||||
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
|
||||
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
|
||||
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
|
||||
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
|
||||
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
|
||||
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
|
||||
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -39,64 +39,65 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */
|
||||
#define STM32L4_DMAMUX_C0CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(0)
|
||||
#define STM32L4_DMAMUX_C1CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(1)
|
||||
#define STM32L4_DMAMUX_C2CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(2)
|
||||
#define STM32L4_DMAMUX_C3CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(3)
|
||||
#define STM32L4_DMAMUX_C4CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(4)
|
||||
#define STM32L4_DMAMUX_C5CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(5)
|
||||
#define STM32L4_DMAMUX_C6CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(6)
|
||||
#define STM32L4_DMAMUX_C7CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(7)
|
||||
#define STM32L4_DMAMUX_C8CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(8)
|
||||
#define STM32L4_DMAMUX_C9CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(9)
|
||||
#define STM32L4_DMAMUX_C10CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(10)
|
||||
#define STM32L4_DMAMUX_C11CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(11)
|
||||
#define STM32L4_DMAMUX_C12CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(12)
|
||||
#define STM32L4_DMAMUX_C13CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(13)
|
||||
/* 0x034-0x07C: Reserved */
|
||||
#define STM32L4_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */
|
||||
#define STM32L4_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */
|
||||
/* 0x088-0x0FC: Reserved */
|
||||
#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */
|
||||
#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4)
|
||||
#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5)
|
||||
#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6)
|
||||
#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7)
|
||||
#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8)
|
||||
#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9)
|
||||
#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10)
|
||||
#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11)
|
||||
#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12)
|
||||
#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13)
|
||||
/* 0x034-0x07C: Reserved */
|
||||
|
||||
#define STM32L4_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */
|
||||
#define STM32L4_DMAMUX_RG0CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(0)
|
||||
#define STM32L4_DMAMUX_RG1CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(1)
|
||||
#define STM32L4_DMAMUX_RG2CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(2)
|
||||
#define STM32L4_DMAMUX_RG3CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(3)
|
||||
#define STM32L4_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */
|
||||
#define STM32L4_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */
|
||||
/* 0x148-0x3FC: Reserved */
|
||||
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */
|
||||
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */
|
||||
/* 0x088-0x0FC: Reserved */
|
||||
|
||||
#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */
|
||||
#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0)
|
||||
#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1)
|
||||
#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2)
|
||||
#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3)
|
||||
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */
|
||||
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */
|
||||
/* 0x148-0x3FC: Reserved */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_DMAMUX1_CXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32L4_DMAMUX1_C0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C4CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C5CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C6CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C6CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C7CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C7CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C8CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C8CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C9CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C9CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C10CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C10CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C11CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C11CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C12CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_C13CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C13CR_OFFSET)
|
||||
#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET)
|
||||
#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET)
|
||||
|
||||
#define STM32L4_DMAMUX1_CSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CSR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_CFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CFR_OFFSET)
|
||||
#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET)
|
||||
#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET)
|
||||
|
||||
#define STM32L4_DMAMUX1_RGXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32L4_DMAMUX1_RG0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RG1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RG2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RG3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG3CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
|
||||
#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET)
|
||||
#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET)
|
||||
|
||||
#define STM32L4_DMAMUX1_RGSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32L4_DMAMUX1_RGCFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGCFR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET)
|
||||
#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -38,23 +38,23 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32L4_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32L4_FIREWALL_CR_OFFSET 0x0020
|
||||
#define STM32_FIREWALL_CSSA_OFFSET 0x0000
|
||||
#define STM32_FIREWALL_CSL_OFFSET 0x0004
|
||||
#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008
|
||||
#define STM32_FIREWALL_NVDSL_OFFSET 0x000c
|
||||
#define STM32_FIREWALL_VDSSA_OFFSET 0x0010
|
||||
#define STM32_FIREWALL_VDSL_OFFSET 0x0014
|
||||
#define STM32_FIREWALL_CR_OFFSET 0x0020
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET)
|
||||
#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET)
|
||||
#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET)
|
||||
#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET)
|
||||
#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET)
|
||||
#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -37,73 +37,73 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
|
||||
#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
|
||||
#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET)
|
||||
#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET)
|
||||
#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET)
|
||||
#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET)
|
||||
#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET)
|
||||
#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET)
|
||||
#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
|
||||
#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
|
||||
#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
|
||||
#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET)
|
||||
#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET)
|
||||
#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -38,35 +38,35 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET)
|
||||
#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET)
|
||||
#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -176,10 +176,10 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain,
|
|||
|
||||
static const struct stm32_1wire_config_s stm32_1wire1_config =
|
||||
{
|
||||
.usartbase = STM32L4_USART1_BASE,
|
||||
.apbclock = STM32L4_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32_USART1_BASE,
|
||||
.apbclock = STM32_PCLK2_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_USART1_TX),
|
||||
.irq = STM32L4_IRQ_USART1,
|
||||
.irq = STM32_IRQ_USART1,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire1_priv =
|
||||
|
|
@ -200,10 +200,10 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv =
|
|||
|
||||
static const struct stm32_1wire_config_s stm32_1wire2_config =
|
||||
{
|
||||
.usartbase = STM32L4_USART2_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART2_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_USART2_TX),
|
||||
.irq = STM32L4_IRQ_USART2,
|
||||
.irq = STM32_IRQ_USART2,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire2_priv =
|
||||
|
|
@ -224,10 +224,10 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv =
|
|||
|
||||
static const struct stm32_1wire_config_s stm32_1wire3_config =
|
||||
{
|
||||
.usartbase = STM32L4_USART3_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART3_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_USART3_TX),
|
||||
.irq = STM32L4_IRQ_USART3,
|
||||
.irq = STM32_IRQ_USART3,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire3_priv =
|
||||
|
|
@ -248,10 +248,10 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv =
|
|||
|
||||
static const struct stm32_1wire_config_s stm32_1wire4_config =
|
||||
{
|
||||
.usartbase = STM32L4_UART4_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_UART4_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_UART4_TX),
|
||||
.irq = STM32L4_IRQ_UART4,
|
||||
.irq = STM32_IRQ_UART4,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire4_priv =
|
||||
|
|
@ -272,10 +272,10 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv =
|
|||
|
||||
static const struct stm32_1wire_config_s stm32_1wire5_config =
|
||||
{
|
||||
.usartbase = STM32L4_UART5_BASE,
|
||||
.apbclock = STM32L4_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_UART5_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.data_pin = PIN_OPENDRAIN(GPIO_UART5_TX),
|
||||
.irq = STM32L4_IRQ_UART5,
|
||||
.irq = STM32_IRQ_UART5,
|
||||
};
|
||||
|
||||
static struct stm32_1wire_priv_s stm32_1wire5_priv =
|
||||
|
|
@ -338,7 +338,7 @@ static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv,
|
|||
|
||||
static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv)
|
||||
{
|
||||
return stm32_1wire_in(priv, STM32L4_USART_RDR_OFFSET) & 0xff;
|
||||
return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -351,7 +351,7 @@ static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv)
|
|||
|
||||
static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch)
|
||||
{
|
||||
stm32_1wire_out(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)(ch & 0xff));
|
||||
stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -377,13 +377,13 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv)
|
|||
* for baud changing.
|
||||
*/
|
||||
|
||||
cr1 = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
|
||||
enabled = cr1 & USART_CR1_UE;
|
||||
if (enabled)
|
||||
{
|
||||
cr1 &= ~USART_CR1_UE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
}
|
||||
|
||||
/* In case of oversampling by 8, the equation is:
|
||||
|
|
@ -428,12 +428,12 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv)
|
|||
cr1 |= USART_CR1_OVER8;
|
||||
}
|
||||
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1);
|
||||
stm32_1wire_out(priv, STM32L4_USART_BRR_OFFSET, brr);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr);
|
||||
|
||||
if (enabled)
|
||||
{
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_UE);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -464,37 +464,37 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv,
|
|||
return;
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER
|
||||
case STM32L4_USART1_BASE:
|
||||
case STM32_USART1_BASE:
|
||||
rcc_en = RCC_APB2ENR_USART1EN;
|
||||
regaddr = STM32L4_RCC_APB2ENR;
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER
|
||||
case STM32L4_USART2_BASE:
|
||||
case STM32_USART2_BASE:
|
||||
rcc_en = RCC_APB1ENR1_USART2EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER
|
||||
case STM32L4_USART3_BASE:
|
||||
case STM32_USART3_BASE:
|
||||
rcc_en = RCC_APB1ENR1_USART3EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER
|
||||
case STM32L4_UART4_BASE:
|
||||
case STM32_UART4_BASE:
|
||||
rcc_en = RCC_APB1ENR1_UART4EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER
|
||||
case STM32L4_UART5_BASE:
|
||||
case STM32_UART5_BASE:
|
||||
rcc_en = RCC_APB1ENR1_UART5EN;
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -534,33 +534,33 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv)
|
|||
* Set LBDIE
|
||||
*/
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL |
|
||||
USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE);
|
||||
regval |= USART_CR2_LBDIE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure CR1
|
||||
* Clear TE, REm, all interrupt enable bits, PCE, PS and M
|
||||
* Set RXNEIE
|
||||
*/
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS |
|
||||
USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1);
|
||||
regval |= USART_CR1_RXNEIE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure CR3
|
||||
* Clear CTSE, RTSE, and all interrupt enable bits
|
||||
* Set ONEBIT, HDSEL and EIE
|
||||
*/
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE |
|
||||
USART_CR3_EIE);
|
||||
regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
/* Set baud rate */
|
||||
|
||||
|
|
@ -569,9 +569,9 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv)
|
|||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure pins for USART use */
|
||||
|
||||
|
|
@ -608,21 +608,21 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv)
|
|||
|
||||
/* Disable RXNEIE, Rx, Tx, and the USART */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Clear LBDIE */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~USART_CR2_LBDIE;
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Clear ONEBIT, HDSEL and EIE */
|
||||
|
||||
regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET);
|
||||
regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE);
|
||||
stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval);
|
||||
stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
/* Disable USART APB1/2 clock */
|
||||
|
||||
|
|
@ -765,7 +765,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Get the masked USART status word. */
|
||||
|
||||
sr = stm32_1wire_in(priv, STM32L4_USART_ISR_OFFSET);
|
||||
sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET);
|
||||
|
||||
/* Receive loop */
|
||||
|
||||
|
|
@ -858,7 +858,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg)
|
|||
* interrupt clear register (ICR).
|
||||
*/
|
||||
|
||||
stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET,
|
||||
stm32_1wire_out(priv, STM32_USART_ICR_OFFSET,
|
||||
(USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF));
|
||||
|
||||
if (priv->msgs != NULL)
|
||||
|
|
@ -873,7 +873,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg)
|
|||
|
||||
if ((sr & USART_ISR_LBDF) != 0)
|
||||
{
|
||||
stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, USART_ICR_LBDCF);
|
||||
stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF);
|
||||
|
||||
if (priv->msgs != NULL)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@
|
|||
|
||||
/* RCC reset ****************************************************************/
|
||||
|
||||
#define STM32L4_RCC_RSTR STM32L4_RCC_AHB2RSTR
|
||||
#define STM32_RCC_RSTR STM32_RCC_AHB2RSTR
|
||||
#define RCC_RSTR_ADC1RST RCC_AHB2RSTR_ADCRST
|
||||
#define RCC_RSTR_ADC2RST RCC_AHB2RSTR_ADCRST
|
||||
#define RCC_RSTR_ADC3RST RCC_AHB2RSTR_ADCRST
|
||||
|
|
@ -89,7 +89,7 @@
|
|||
/* ADC interrupts ***********************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1
|
||||
# define STM32_IRQ_ADC12 STM32_IRQ_ADC1
|
||||
#endif
|
||||
|
||||
/* ADC Channels/DMA *********************************************************/
|
||||
|
|
@ -425,14 +425,14 @@ static struct stm32_dev_s g_adcpriv1 =
|
|||
.llops = &g_adc_llops,
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_ADC_NOIRQ
|
||||
.irq = STM32L4_IRQ_ADC12,
|
||||
.irq = STM32_IRQ_ADC12,
|
||||
.isr = adc12_interrupt,
|
||||
#endif /* CONFIG_STM32L4_ADC_NOIRQ */
|
||||
.intf = 1,
|
||||
#ifdef HAVE_ADC_RESOLUTION
|
||||
.resolution = CONFIG_STM32L4_ADC1_RESOLUTION,
|
||||
#endif
|
||||
.base = STM32L4_ADC1_BASE,
|
||||
.base = STM32_ADC1_BASE,
|
||||
#if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_EXTCFG)
|
||||
.extcfg = ADC1_EXTCFG_VALUE,
|
||||
#endif
|
||||
|
|
@ -485,14 +485,14 @@ static struct stm32_dev_s g_adcpriv2 =
|
|||
.llops = &g_adc_llops,
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_ADC_NOIRQ
|
||||
.irq = STM32L4_IRQ_ADC12,
|
||||
.irq = STM32_IRQ_ADC12,
|
||||
.isr = adc12_interrupt,
|
||||
#endif /* CONFIG_STM32L4_ADC_NOIRQ */
|
||||
.intf = 2,
|
||||
#ifdef HAVE_ADC_RESOLUTION
|
||||
.resolution = CONFIG_STM32L4_ADC2_RESOLUTION,
|
||||
#endif
|
||||
.base = STM32L4_ADC2_BASE,
|
||||
.base = STM32_ADC2_BASE,
|
||||
#if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_EXTCFG)
|
||||
.extcfg = ADC2_EXTCFG_VALUE,
|
||||
#endif
|
||||
|
|
@ -545,14 +545,14 @@ static struct stm32_dev_s g_adcpriv3 =
|
|||
.llops = &g_adc_llops,
|
||||
#endif
|
||||
#ifndef CONFIG_STM32L4_ADC_NOIRQ
|
||||
.irq = STM32L4_IRQ_ADC3,
|
||||
.irq = STM32_IRQ_ADC3,
|
||||
.isr = adc3_interrupt,
|
||||
#endif /* CONFIG_STM32L4_ADC_NOIRQ */
|
||||
.intf = 3,
|
||||
#ifdef HAVE_ADC_RESOLUTION
|
||||
.resolution = CONFIG_STM32L4_ADC3_RESOLUTION,
|
||||
#endif
|
||||
.base = STM32L4_ADC3_BASE,
|
||||
.base = STM32_ADC3_BASE,
|
||||
#if defined(ADC3_HAVE_TIMER) || defined(ADC3_HAVE_EXTCFG)
|
||||
.extcfg = ADC3_EXTCFG_VALUE,
|
||||
#endif
|
||||
|
|
@ -771,38 +771,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg)
|
|||
{
|
||||
ainfo("%s:\n", msg);
|
||||
ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
|
||||
ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_SR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_SR_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
|
||||
ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
|
||||
ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
|
||||
|
||||
if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE)
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
|
||||
tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET));
|
||||
tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
|
||||
tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
|
||||
tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
|
||||
}
|
||||
else
|
||||
{
|
||||
ainfo(" DCR: %04x DMAR: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -830,14 +830,14 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable)
|
|||
{
|
||||
/* Start the counter */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG);
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the counter */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -870,7 +870,7 @@ static int adc_timinit(struct stm32_dev_s *priv)
|
|||
uint16_t ccmr_val = 0;
|
||||
uint16_t ccmr_mask = 0xff;
|
||||
uint16_t ccer_val;
|
||||
uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET;
|
||||
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
|
||||
uint32_t channel = priv->channel - 1;
|
||||
|
||||
/* If the timer base address is zero, then this ADC was not configured to
|
||||
|
|
@ -955,30 +955,30 @@ static int adc_timinit(struct stm32_dev_s *priv)
|
|||
|
||||
clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK;
|
||||
setbits = GTIM_CR1_EDGE;
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits);
|
||||
|
||||
/* Set the ARR Preload Bit */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
|
||||
/* Set the reload and prescaler values */
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1);
|
||||
tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload);
|
||||
tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1);
|
||||
tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
|
||||
|
||||
/* Clear the advanced timers repetition counter in TIM1 */
|
||||
|
||||
if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE)
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0);
|
||||
tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
|
||||
tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
|
||||
tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
|
||||
}
|
||||
|
||||
/* Handle channel specific setup */
|
||||
|
||||
/* Assume that channel is disabled and polarity is active high */
|
||||
|
||||
ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccer_val = tim_getreg(priv, STM32_GTIM_CCER_OFFSET);
|
||||
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
|
||||
GTIM_CCER_CCXBASE(channel));
|
||||
|
||||
|
|
@ -995,41 +995,41 @@ static int adc_timinit(struct stm32_dev_s *priv)
|
|||
|
||||
if (channel > 1)
|
||||
{
|
||||
ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET;
|
||||
ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
|
||||
}
|
||||
|
||||
ccmr_orig = tim_getreg(priv, ccmr_offset);
|
||||
ccmr_orig &= ~ccmr_mask;
|
||||
ccmr_orig |= ccmr_val;
|
||||
tim_putreg(priv, ccmr_offset, ccmr_orig);
|
||||
tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer_val);
|
||||
tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer_val);
|
||||
|
||||
switch (channel)
|
||||
{
|
||||
case 0: /* TIMx CC1 */
|
||||
{
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR1_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: /* TIMx CC2 */
|
||||
{
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR2_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* TIMx CC3 */
|
||||
{
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR3_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: /* TIMx CC4 */
|
||||
{
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
|
@ -1063,7 +1063,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain,
|
|||
container_of(cb, struct stm32_dev_s, pm_callback);
|
||||
uint32_t regval;
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
|
||||
if ((state >= PM_IDLE) && (regval & ADC_CR_ADSTART))
|
||||
{
|
||||
return -EBUSY;
|
||||
|
|
@ -1087,16 +1087,16 @@ static void adc_wdog_enable(struct stm32_dev_s *priv)
|
|||
|
||||
/* Initialize the Analog watchdog enable */
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CFGR_OFFSET);
|
||||
regval |= ADC_CFGR_AWD1EN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD;
|
||||
adc_putreg(priv, STM32L4_ADC_CFGR_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_CFGR_OFFSET, regval);
|
||||
|
||||
/* Switch to analog watchdog interrupt */
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_IER_OFFSET);
|
||||
regval |= ADC_INT_AWD1;
|
||||
regval &= ~ADC_INT_EOC;
|
||||
adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_IER_OFFSET, regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1119,7 +1119,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
|
|||
|
||||
ainfo("enable: %d\n", enable ? 1 : 0);
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
|
||||
if (enable)
|
||||
{
|
||||
/* Start conversion of regular channels */
|
||||
|
|
@ -1133,7 +1133,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
|
|||
regval |= ADC_CR_ADSTP;
|
||||
}
|
||||
|
||||
adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_CR_OFFSET, regval);
|
||||
}
|
||||
|
||||
#ifdef ADC_HAVE_INJECTED
|
||||
|
|
@ -1162,11 +1162,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable)
|
|||
{
|
||||
/* Start the conversion of regular channels */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_CR_OFFSET, 0, ADC_CR_JADSTART);
|
||||
adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
|
||||
|
||||
/* Is a conversion ongoing? */
|
||||
|
||||
|
|
@ -1174,11 +1174,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable)
|
|||
{
|
||||
/* Stop the conversion */
|
||||
|
||||
adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval | ADC_CR_JADSTP);
|
||||
adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP);
|
||||
|
||||
/* Wait for the conversion to stop */
|
||||
|
||||
while ((adc_getreg(priv, STM32L4_ADC_CR_OFFSET) &
|
||||
while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) &
|
||||
ADC_CR_JADSTP) != 0);
|
||||
}
|
||||
}
|
||||
|
|
@ -1216,7 +1216,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset)
|
|||
|
||||
/* Set or clear the selected bit in the AHB2 reset register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_AHB2RSTR);
|
||||
regval = getreg32(STM32_RCC_AHB2RSTR);
|
||||
if (reset)
|
||||
{
|
||||
regval |= RCC_AHB2RSTR_ADCRST;
|
||||
|
|
@ -1226,7 +1226,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset)
|
|||
regval &= ~RCC_AHB2RSTR_ADCRST;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32L4_RCC_AHB2RSTR);
|
||||
putreg32(regval, STM32_RCC_AHB2RSTR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
|
|
@ -1247,13 +1247,13 @@ static void adc_enable(struct stm32_dev_s *priv)
|
|||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
|
||||
|
||||
/* Exit deep power down mode and enable voltage regulator */
|
||||
|
||||
regval &= ~ADC_CR_DEEPPWD;
|
||||
regval |= ADC_CR_ADVREGEN;
|
||||
adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_CR_OFFSET, regval);
|
||||
|
||||
/* Wait for voltage regulator to power up */
|
||||
|
||||
|
|
@ -1264,11 +1264,11 @@ static void adc_enable(struct stm32_dev_s *priv)
|
|||
*/
|
||||
|
||||
regval |= ADC_CR_ADCAL;
|
||||
adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_CR_OFFSET, regval);
|
||||
|
||||
/* Wait for calibration to complete */
|
||||
|
||||
while (adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & ADC_CR_ADCAL);
|
||||
while (adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL);
|
||||
|
||||
/* Enable ADC
|
||||
* Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle
|
||||
|
|
@ -1277,13 +1277,13 @@ static void adc_enable(struct stm32_dev_s *priv)
|
|||
* ARM instructions.
|
||||
*/
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
|
||||
regval |= ADC_CR_ADEN;
|
||||
adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_CR_OFFSET, regval);
|
||||
|
||||
/* Wait for hardware to be ready for conversions */
|
||||
|
||||
while (!(adc_getreg(priv, STM32L4_ADC_ISR_OFFSET) & ADC_INT_ADRDY));
|
||||
while (!(adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ADRDY));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1400,7 +1400,7 @@ static int adc_setup(struct adc_dev_s *dev)
|
|||
|
||||
/* Set CFGR configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
|
||||
/* Configuration of the channel conversions */
|
||||
|
||||
|
|
@ -1432,7 +1432,7 @@ static int adc_setup(struct adc_dev_s *dev)
|
|||
|
||||
adc_internal(priv, &setbits);
|
||||
|
||||
stm32_modifyreg32(STM32L4_ADC_CCR, clrbits, setbits);
|
||||
stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits);
|
||||
|
||||
#ifdef ADC_HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
|
|
@ -1569,7 +1569,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable)
|
|||
|
||||
ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_IER_OFFSET);
|
||||
if (enable)
|
||||
{
|
||||
/* Enable end of conversion interrupt */
|
||||
|
|
@ -1592,7 +1592,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable)
|
|||
regval &= ~ADC_INT_MASK;
|
||||
}
|
||||
|
||||
adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_IER_OFFSET, regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1615,7 +1615,7 @@ static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res)
|
|||
|
||||
/* Modify appropriate register */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK,
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK,
|
||||
res << ADC_CFGR_RES_SHIFT);
|
||||
|
||||
errout:
|
||||
|
|
@ -1635,8 +1635,8 @@ static void adc_sample_time_set(struct adc_dev_s *dev)
|
|||
|
||||
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv;
|
||||
|
||||
adc_putreg(priv, STM32L4_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT);
|
||||
adc_putreg(priv, STM32L4_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
|
||||
adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT);
|
||||
adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1673,7 +1673,7 @@ static int adc_extsel_set(struct stm32_dev_s *priv, uint32_t extcfg)
|
|||
|
||||
/* Write register */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
}
|
||||
|
||||
return OK;
|
||||
|
|
@ -1714,7 +1714,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg)
|
|||
|
||||
/* Write register */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits);
|
||||
adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits);
|
||||
}
|
||||
|
||||
return OK;
|
||||
|
|
@ -1731,25 +1731,25 @@ static void adc_dumpregs(struct stm32_dev_s *priv)
|
|||
|
||||
ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32
|
||||
" CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n",
|
||||
adc_getreg(priv, STM32L4_ADC_ISR_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_IER_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_CR_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET));
|
||||
adc_getreg(priv, STM32_ADC_ISR_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_IER_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_CR_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_CFGR_OFFSET));
|
||||
|
||||
ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32
|
||||
" SQR3: 0x%08" PRIx32 " SQR4: 0x%08" PRIx32 "\n",
|
||||
adc_getreg(priv, STM32L4_ADC_SQR1_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_SQR2_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_SQR3_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_SQR4_OFFSET));
|
||||
adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_SQR3_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
|
||||
|
||||
ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n",
|
||||
adc_getreg(priv, STM32L4_ADC_SMPR1_OFFSET),
|
||||
adc_getreg(priv, STM32L4_ADC_SMPR2_OFFSET));
|
||||
adc_getreg(priv, STM32_ADC_SMPR1_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_SMPR2_OFFSET));
|
||||
|
||||
#ifdef ADC_HAVE_INJECTED
|
||||
ainfo("JSQR: 0x%08" PRIx32 "\n",
|
||||
adc_getreg(priv, STM32L4_ADC_JSQR_OFFSET));
|
||||
adc_getreg(priv, STM32_ADC_JSQR_OFFSET));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -1841,7 +1841,7 @@ static int adc_offset_set(struct stm32_dev_s *priv,
|
|||
goto errout;
|
||||
}
|
||||
|
||||
reg = STM32L4_ADC_OFR1_OFFSET + i * 4;
|
||||
reg = STM32_ADC_OFR1_OFFSET + i * 4;
|
||||
|
||||
regval = ADC_OFR_OFFSETY_EN;
|
||||
adc_putreg(priv, reg, regval);
|
||||
|
|
@ -1898,23 +1898,23 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch)
|
|||
bits = adc_sqrbits(priv,
|
||||
ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET);
|
||||
adc_modifyreg(priv,
|
||||
STM32L4_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits);
|
||||
STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits);
|
||||
|
||||
bits = adc_sqrbits(priv,
|
||||
ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET);
|
||||
adc_modifyreg(priv,
|
||||
STM32L4_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits);
|
||||
STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits);
|
||||
|
||||
bits = adc_sqrbits(priv,
|
||||
ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET);
|
||||
adc_modifyreg(priv,
|
||||
STM32L4_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits);
|
||||
STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits);
|
||||
|
||||
bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT |
|
||||
adc_sqrbits(priv,
|
||||
ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET);
|
||||
adc_modifyreg(priv,
|
||||
STM32L4_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits);
|
||||
STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits);
|
||||
|
||||
#ifdef ADC_HAVE_DFSDM
|
||||
if (priv->hasdfsdm)
|
||||
|
|
@ -1966,7 +1966,7 @@ static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch)
|
|||
|
||||
/* Write register */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits);
|
||||
adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -2026,7 +2026,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
|
|||
|
||||
case ANIOC_WDOG_UPPER: /* Set watchdog upper threshold */
|
||||
{
|
||||
regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET);
|
||||
|
||||
/* Verify new upper threshold greater than lower threshold */
|
||||
|
||||
|
|
@ -2041,7 +2041,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
|
|||
|
||||
regval &= ~ADC_TR1_HT_MASK;
|
||||
regval |= ((arg << ADC_TR1_HT_SHIFT) & ADC_TR1_HT_MASK);
|
||||
adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval);
|
||||
|
||||
/* Ensure analog watchdog is enabled */
|
||||
|
||||
|
|
@ -2051,7 +2051,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
|
|||
|
||||
case ANIOC_WDOG_LOWER: /* Set watchdog lower threshold */
|
||||
{
|
||||
regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET);
|
||||
|
||||
/* Verify new lower threshold less than upper threshold */
|
||||
|
||||
|
|
@ -2066,7 +2066,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
|
|||
|
||||
regval &= ~ADC_TR1_LT_MASK;
|
||||
regval |= ((arg << ADC_TR1_LT_SHIFT) & ADC_TR1_LT_MASK);
|
||||
adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval);
|
||||
adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval);
|
||||
|
||||
/* Ensure analog watchdog is enabled */
|
||||
|
||||
|
|
@ -2133,7 +2133,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
|
|||
|
||||
if ((adcisr & ADC_INT_AWD1) != 0)
|
||||
{
|
||||
value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET);
|
||||
value = adc_getreg(priv, STM32_ADC_DR_OFFSET);
|
||||
value &= ADC_DR_MASK;
|
||||
|
||||
awarn("WARNING: Analog Watchdog, "
|
||||
|
|
@ -2158,7 +2158,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
|
|||
* (It is cleared by reading the ADC_DR)
|
||||
*/
|
||||
|
||||
value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET);
|
||||
value = adc_getreg(priv, STM32_ADC_DR_OFFSET);
|
||||
value &= ADC_DR_MASK;
|
||||
|
||||
/* Verify that the upper-half driver has bound its callback functions */
|
||||
|
|
@ -2198,7 +2198,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr)
|
|||
{
|
||||
for (i = 0; i < priv->cjchannels; i++)
|
||||
{
|
||||
value = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * i)) &
|
||||
value = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * i)) &
|
||||
ADC_JDR_MASK;
|
||||
|
||||
if (priv->cb != NULL)
|
||||
|
|
@ -2232,7 +2232,7 @@ static int adc12_interrupt(int irq, void *context, void *arg)
|
|||
uint32_t pending;
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC1
|
||||
regval = getreg32(STM32L4_ADC1_ISR);
|
||||
regval = getreg32(STM32_ADC1_ISR);
|
||||
pending = regval & ADC_INT_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
@ -2240,12 +2240,12 @@ static int adc12_interrupt(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear interrupts */
|
||||
|
||||
putreg32(regval, STM32L4_ADC1_ISR);
|
||||
putreg32(regval, STM32_ADC1_ISR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
regval = getreg32(STM32L4_ADC2_ISR);
|
||||
regval = getreg32(STM32_ADC2_ISR);
|
||||
pending = regval & ADC_INT_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
@ -2253,7 +2253,7 @@ static int adc12_interrupt(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear interrupts */
|
||||
|
||||
putreg32(regval, STM32L4_ADC2_ISR);
|
||||
putreg32(regval, STM32_ADC2_ISR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -2279,7 +2279,7 @@ static int adc3_interrupt(int irq, void *context, void *arg)
|
|||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
regval = getreg32(STM32L4_ADC3_ISR);
|
||||
regval = getreg32(STM32_ADC3_ISR);
|
||||
pending = regval & ADC_INT_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
@ -2287,7 +2287,7 @@ static int adc3_interrupt(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear interrupts */
|
||||
|
||||
putreg32(regval, STM32L4_ADC3_ISR);
|
||||
putreg32(regval, STM32_ADC3_ISR);
|
||||
}
|
||||
|
||||
return OK;
|
||||
|
|
@ -2339,7 +2339,7 @@ static void adc_dma_cfg(struct stm32_dev_s *priv)
|
|||
|
||||
/* Modify CFGR configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -2362,7 +2362,7 @@ static void adc_dma_start(struct adc_dev_s *dev)
|
|||
|
||||
#ifndef CONFIG_STM32L4_ADC_NOIRQ
|
||||
stm32l4_dmasetup(priv->dma,
|
||||
priv->base + STM32L4_ADC_DR_OFFSET,
|
||||
priv->base + STM32_ADC_DR_OFFSET,
|
||||
(uint32_t)priv->r_dmabuffer,
|
||||
priv->rnchannels * priv->dmabatch,
|
||||
ADC_DMA_CONTROL_WORD);
|
||||
|
|
@ -2418,8 +2418,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle,
|
|||
|
||||
/* Restart DMA for the next conversion series */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0);
|
||||
adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN);
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0);
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN);
|
||||
}
|
||||
#endif
|
||||
#endif /* ADC_HAVE_DMA */
|
||||
|
|
@ -2437,7 +2437,7 @@ static void adc_llops_intack(struct stm32_adc_dev_s *dev,
|
|||
|
||||
/* Clear pending interrupts */
|
||||
|
||||
adc_putreg(priv, STM32L4_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS));
|
||||
adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -2451,7 +2451,7 @@ static void adc_llops_inten(struct stm32_adc_dev_s *dev,
|
|||
|
||||
/* Enable interrupts */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS));
|
||||
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -2465,7 +2465,7 @@ static void adc_llops_intdis(struct stm32_adc_dev_s *dev,
|
|||
|
||||
/* Disable interrupts */
|
||||
|
||||
adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0);
|
||||
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -2478,7 +2478,7 @@ static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev)
|
|||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_ISR_OFFSET);
|
||||
regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET);
|
||||
pending = regval & ADC_ISR_ALLINTS;
|
||||
|
||||
return pending;
|
||||
|
|
@ -2492,7 +2492,7 @@ static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev)
|
|||
{
|
||||
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
|
||||
|
||||
return adc_getreg(priv, STM32L4_ADC_DR_OFFSET) & ADC_DR_MASK;
|
||||
return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_MASK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -2545,7 +2545,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev,
|
|||
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
|
||||
|
||||
stm32l4_dmasetup(priv->dma,
|
||||
priv->base + STM32L4_ADC_DR_OFFSET,
|
||||
priv->base + STM32_ADC_DR_OFFSET,
|
||||
(uint32_t)buffer,
|
||||
len,
|
||||
ADC_DMA_CONTROL_WORD);
|
||||
|
|
@ -2578,7 +2578,7 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc,
|
|||
dev->dma = stm32l4_dmachannel(dev->dmachan);
|
||||
|
||||
stm32l4_dmasetup(dev->dma,
|
||||
dev->base + STM32L4_ADC_DR_OFFSET,
|
||||
dev->base + STM32_ADC_DR_OFFSET,
|
||||
(uint32_t)buffer,
|
||||
len,
|
||||
ADC_DMA_CONTROL_WORD);
|
||||
|
|
@ -2639,7 +2639,7 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev,
|
|||
goto errout;
|
||||
}
|
||||
|
||||
regval = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * chan)) &
|
||||
regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * chan)) &
|
||||
ADC_JDR_MASK;
|
||||
|
||||
errout:
|
||||
|
|
|
|||
|
|
@ -91,15 +91,15 @@
|
|||
|
||||
/* Up to 3 ADC interfaces are supported */
|
||||
|
||||
#if STM32L4_NADC < 3
|
||||
#if STM32_NADC < 3
|
||||
# undef CONFIG_STM32L4_ADC3
|
||||
#endif
|
||||
|
||||
#if STM32L4_NADC < 2
|
||||
#if STM32_NADC < 2
|
||||
# undef CONFIG_STM32L4_ADC2
|
||||
#endif
|
||||
|
||||
#if STM32L4_NADC < 1
|
||||
#if STM32_NADC < 1
|
||||
# undef CONFIG_STM32L4_ADC1
|
||||
#endif
|
||||
|
||||
|
|
@ -178,38 +178,38 @@
|
|||
|
||||
#if defined(CONFIG_STM32L4_TIM1_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM2_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM6_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM15_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM15_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
|
||||
# define ADC1_TIMER_BASE STM32_TIM15_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
|
||||
#else
|
||||
# undef ADC1_HAVE_TIMER
|
||||
|
|
@ -227,38 +227,38 @@
|
|||
|
||||
#if defined(CONFIG_STM32L4_TIM1_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM2_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM6_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM15_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM15_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
|
||||
# define ADC2_TIMER_BASE STM32_TIM15_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
|
||||
#else
|
||||
# undef ADC2_HAVE_TIMER
|
||||
|
|
@ -276,38 +276,38 @@
|
|||
|
||||
#if defined(CONFIG_STM32L4_TIM1_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM2_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM6_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM15_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM15_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
|
||||
# define ADC3_TIMER_BASE STM32_TIM15_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
|
||||
#else
|
||||
# undef ADC3_HAVE_TIMER
|
||||
|
|
|
|||
|
|
@ -96,19 +96,19 @@
|
|||
|
||||
/* Set the range of system SRAM */
|
||||
|
||||
#define SRAM1_START STM32L4_SRAM_BASE
|
||||
#define SRAM1_END (SRAM1_START + STM32L4_SRAM1_SIZE)
|
||||
#define SRAM1_START STM32_SRAM_BASE
|
||||
#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE)
|
||||
|
||||
/* Set the range of SRAM2 as well, requires a second memory region */
|
||||
|
||||
#define SRAM2_START STM32L4_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE)
|
||||
#define SRAM2_START STM32_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
|
||||
|
||||
/* Set the range of SRAM3, requiring a third memory region */
|
||||
|
||||
#ifdef STM32L4_SRAM3_SIZE
|
||||
# define SRAM3_START STM32L4_SRAM3_BASE
|
||||
# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE)
|
||||
#ifdef STM32_SRAM3_SIZE
|
||||
# define SRAM3_START STM32_SRAM3_BASE
|
||||
# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE)
|
||||
#endif
|
||||
|
||||
/* Some sanity checking. If multiple memory regions are defined, verify
|
||||
|
|
|
|||
|
|
@ -181,13 +181,13 @@ static struct stm32l4_can_s g_can1priv =
|
|||
.port = 1,
|
||||
.canrx =
|
||||
{
|
||||
STM32L4_IRQ_CAN1RX0,
|
||||
STM32L4_IRQ_CAN1RX1,
|
||||
STM32_IRQ_CAN1RX0,
|
||||
STM32_IRQ_CAN1RX1,
|
||||
},
|
||||
.cantx = STM32L4_IRQ_CAN1TX,
|
||||
.cantx = STM32_IRQ_CAN1TX,
|
||||
.filter = 0,
|
||||
.base = STM32L4_CAN1_BASE,
|
||||
.fbase = STM32L4_CAN1_BASE,
|
||||
.base = STM32_CAN1_BASE,
|
||||
.fbase = STM32_CAN1_BASE,
|
||||
.baud = CONFIG_STM32L4_CAN1_BAUD,
|
||||
};
|
||||
|
||||
|
|
@ -381,18 +381,18 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv,
|
|||
/* CAN control and status registers */
|
||||
|
||||
caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_MCR_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_MSR_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TSR_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_MCR_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_MSR_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TSR_OFFSET));
|
||||
|
||||
caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_RF0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RF1R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_RF0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RF1R_OFFSET));
|
||||
|
||||
caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_IER_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_ESR_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_BTR_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_IER_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_ESR_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_BTR_OFFSET));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -427,38 +427,38 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv,
|
|||
|
||||
caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32
|
||||
" TDL0R: %08" PRIx32 " TDH0R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_TI0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDT0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDL0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDH0R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_TI0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDT0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDL0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDH0R_OFFSET));
|
||||
|
||||
caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32
|
||||
" TDL1R: %08" PRIx32 " TDH1R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_TI1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDT1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDL1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDH1R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_TI1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDT1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDL1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDH1R_OFFSET));
|
||||
|
||||
caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32
|
||||
" TDL2R: %08" PRIx32 " TDH2R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_TI2R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDT2R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDL2R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_TDH2R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_TI2R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDT2R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDL2R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_TDH2R_OFFSET));
|
||||
|
||||
caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32
|
||||
" RDL0R: %08" PRIx32 " RDH0R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_RI0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RDT0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RDL0R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RDH0R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_RI0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RDT0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RDL0R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RDH0R_OFFSET));
|
||||
|
||||
caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32
|
||||
" RDL1R: %08" PRIx32 " RDH1R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_RI1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RDT1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RDL1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_RDH1R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_RI1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RDT1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RDL1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_RDH1R_OFFSET));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -494,17 +494,17 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv,
|
|||
caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32
|
||||
" FS1R: %08" PRIx32 " FFA1R: %08" PRIx32
|
||||
" FA1R: %08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_CAN_FMR_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_FM1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_FS1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_FFA1R_OFFSET),
|
||||
getreg32(priv->base + STM32L4_CAN_FA1R_OFFSET));
|
||||
getreg32(priv->base + STM32_CAN_FMR_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_FM1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_FS1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_FFA1R_OFFSET),
|
||||
getreg32(priv->base + STM32_CAN_FA1R_OFFSET));
|
||||
|
||||
for (i = 0; i < CAN_NFILTERS; i++)
|
||||
{
|
||||
caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n",
|
||||
i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 1)),
|
||||
i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 2)));
|
||||
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)),
|
||||
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2)));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -555,12 +555,12 @@ static void stm32l4can_reset(struct can_dev_s *dev)
|
|||
|
||||
/* Reset the CAN */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1RSTR1);
|
||||
regval = getreg32(STM32_RCC_APB1RSTR1);
|
||||
regval |= regbit;
|
||||
putreg32(regval, STM32L4_RCC_APB1RSTR1);
|
||||
putreg32(regval, STM32_RCC_APB1RSTR1);
|
||||
|
||||
regval &= ~regbit;
|
||||
putreg32(regval, STM32L4_RCC_APB1RSTR1);
|
||||
putreg32(regval, STM32_RCC_APB1RSTR1);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
|
|
@ -714,7 +714,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable)
|
|||
|
||||
/* Enable/disable the FIFO 0/1 message pending interrupt */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET);
|
||||
if (enable)
|
||||
{
|
||||
regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1;
|
||||
|
|
@ -724,7 +724,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable)
|
|||
regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1);
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -752,9 +752,9 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable)
|
|||
|
||||
if (!enable)
|
||||
{
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET);
|
||||
regval &= ~CAN_IER_TMEIE;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -806,7 +806,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
uint32_t brp;
|
||||
|
||||
DEBUGASSERT(bt != NULL);
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET);
|
||||
bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >>
|
||||
CAN_BTR_SJW_SHIFT) + 1;
|
||||
bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >>
|
||||
|
|
@ -815,7 +815,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
CAN_BTR_TS2_SHIFT) + 1;
|
||||
brp = ((regval & CAN_BTR_BRP_MASK) >>
|
||||
CAN_BTR_BRP_SHIFT) + 1;
|
||||
bt->bt_baud = STM32L4_PCLK1_FREQUENCY /
|
||||
bt->bt_baud = STM32_PCLK1_FREQUENCY /
|
||||
(brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
|
||||
ret = OK;
|
||||
}
|
||||
|
|
@ -848,18 +848,18 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
uint32_t regval;
|
||||
|
||||
DEBUGASSERT(bt != NULL);
|
||||
DEBUGASSERT(bt->bt_baud < STM32L4_PCLK1_FREQUENCY);
|
||||
DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY);
|
||||
DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4);
|
||||
DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16);
|
||||
DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8);
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET);
|
||||
|
||||
/* Extract bit timing data.
|
||||
* tmp is in clocks per bit time.
|
||||
*/
|
||||
|
||||
tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud;
|
||||
tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud;
|
||||
|
||||
/* This value is dynamic as requested by user */
|
||||
|
||||
|
|
@ -904,12 +904,12 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
break;
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval);
|
||||
|
||||
ret = stm32l4can_exitinitmode(priv);
|
||||
if (ret >= 0)
|
||||
{
|
||||
priv->baud = STM32L4_PCLK1_FREQUENCY /
|
||||
priv->baud = STM32_PCLK1_FREQUENCY /
|
||||
(brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1));
|
||||
}
|
||||
}
|
||||
|
|
@ -934,7 +934,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
|
||||
DEBUGASSERT(bm != NULL);
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET);
|
||||
|
||||
bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM);
|
||||
bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM);
|
||||
|
|
@ -961,7 +961,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
|
||||
DEBUGASSERT(bm != NULL);
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET);
|
||||
|
||||
if (bm->bm_loopback)
|
||||
{
|
||||
|
|
@ -989,7 +989,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
break;
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval);
|
||||
|
||||
ret = stm32l4can_exitinitmode(priv);
|
||||
}
|
||||
|
|
@ -1078,7 +1078,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
return ret;
|
||||
}
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
if (arg == 1)
|
||||
{
|
||||
regval |= CAN_MCR_NART;
|
||||
|
|
@ -1088,7 +1088,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
regval &= ~CAN_MCR_NART;
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
return stm32l4can_exitinitmode(priv);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1102,7 +1102,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
return ret;
|
||||
}
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
if (arg == 1)
|
||||
{
|
||||
regval |= CAN_MCR_ABOM;
|
||||
|
|
@ -1112,7 +1112,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd,
|
|||
regval &= ~CAN_MCR_ABOM;
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
return stm32l4can_exitinitmode(priv);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1185,7 +1185,7 @@ static int stm32l4can_send(struct can_dev_s *dev,
|
|||
|
||||
/* Select one empty transmit mailbox */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET);
|
||||
if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0)
|
||||
{
|
||||
txmb = 0;
|
||||
|
|
@ -1206,10 +1206,10 @@ static int stm32l4can_send(struct can_dev_s *dev,
|
|||
|
||||
/* Clear TXRQ, RTR, IDE, EXID, and STID fields */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
|
||||
regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE |
|
||||
CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK);
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
|
||||
|
||||
/* Set up the ID, standard 11-bit or extended 29-bit. */
|
||||
|
||||
|
|
@ -1233,15 +1233,15 @@ static int stm32l4can_send(struct can_dev_s *dev,
|
|||
regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0);
|
||||
#endif
|
||||
#endif
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
|
||||
|
||||
/* Set up the DLC */
|
||||
|
||||
dlc = msg->cm_hdr.ch_dlc;
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb));
|
||||
regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT);
|
||||
regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval);
|
||||
|
||||
/* Set up the data fields */
|
||||
|
||||
|
|
@ -1272,7 +1272,7 @@ static int stm32l4can_send(struct can_dev_s *dev,
|
|||
}
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TDLR_OFFSET(txmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval);
|
||||
|
||||
regval = 0;
|
||||
if (dlc > 4)
|
||||
|
|
@ -1299,19 +1299,19 @@ static int stm32l4can_send(struct can_dev_s *dev,
|
|||
}
|
||||
}
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TDHR_OFFSET(txmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval);
|
||||
|
||||
/* Enable the transmit mailbox empty interrupt (may already be enabled) */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET);
|
||||
regval |= CAN_IER_TMEIE;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval);
|
||||
|
||||
/* Request transmission */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb));
|
||||
regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval);
|
||||
|
||||
stm32l4can_dumpmbregs(priv, "After send");
|
||||
return OK;
|
||||
|
|
@ -1338,7 +1338,7 @@ static bool stm32l4can_txready(struct can_dev_s *dev)
|
|||
|
||||
/* Return true if any mailbox is available */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET);
|
||||
caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval);
|
||||
|
||||
return (regval & CAN_ALL_MAILBOXES) != 0;
|
||||
|
|
@ -1369,7 +1369,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev)
|
|||
|
||||
/* Return true if all mailboxes are available */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET);
|
||||
caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval);
|
||||
|
||||
return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES;
|
||||
|
|
@ -1406,7 +1406,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb)
|
|||
|
||||
/* Verify that a message is pending in the FIFO */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
|
||||
npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT;
|
||||
if (npending < 1)
|
||||
{
|
||||
|
|
@ -1425,7 +1425,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb)
|
|||
|
||||
/* Get the CAN identifier. */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_RIR_OFFSET(rxmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb));
|
||||
|
||||
#ifdef CONFIG_CAN_EXTID
|
||||
if ((regval & CAN_RIR_IDE) != 0)
|
||||
|
|
@ -1462,18 +1462,18 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb)
|
|||
|
||||
/* Get the DLC */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_RDTR_OFFSET(rxmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb));
|
||||
hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT;
|
||||
|
||||
/* Save the message data */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_RDLR_OFFSET(rxmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb));
|
||||
data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT;
|
||||
data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT;
|
||||
data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT;
|
||||
data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT;
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_RDHR_OFFSET(rxmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb));
|
||||
data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT;
|
||||
data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT;
|
||||
data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT;
|
||||
|
|
@ -1488,9 +1488,9 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb)
|
|||
#ifndef CONFIG_CAN_EXTID
|
||||
errout:
|
||||
#endif
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb));
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb));
|
||||
regval |= CAN_RFR_RFOM;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb), regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1560,7 +1560,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg)
|
|||
|
||||
/* Get the transmit status */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET);
|
||||
|
||||
/* Check for RQCP0: Request completed mailbox 0 */
|
||||
|
||||
|
|
@ -1570,7 +1570,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg)
|
|||
* ALST0 and TERR0) for Mailbox 0.
|
||||
*/
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP0);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0);
|
||||
|
||||
/* Check for errors */
|
||||
|
||||
|
|
@ -1590,7 +1590,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg)
|
|||
* ALST1 and TERR1) for Mailbox 1.
|
||||
*/
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP1);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1);
|
||||
|
||||
/* Check for errors */
|
||||
|
||||
|
|
@ -1610,7 +1610,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg)
|
|||
* ALST2 and TERR2) for Mailbox 2.
|
||||
*/
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP2);
|
||||
stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2);
|
||||
|
||||
/* Check for errors */
|
||||
|
||||
|
|
@ -1690,7 +1690,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv)
|
|||
uint32_t ts2;
|
||||
|
||||
caninfo("CAN%d PCLK1: %d baud: %d\n",
|
||||
priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud);
|
||||
priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
|
||||
|
||||
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
|
||||
*
|
||||
|
|
@ -1708,7 +1708,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv)
|
|||
* PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4
|
||||
*/
|
||||
|
||||
tmp = STM32L4_PCLK1_FREQUENCY / priv->baud;
|
||||
tmp = STM32_PCLK1_FREQUENCY / priv->baud;
|
||||
if (tmp < CAN_BIT_QUANTA)
|
||||
{
|
||||
/* At the smallest brp value (1), there are already too few bit times
|
||||
|
|
@ -1762,7 +1762,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv)
|
|||
tmp |= CAN_BTR_LBKM;
|
||||
#endif
|
||||
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, tmp);
|
||||
stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -1791,15 +1791,15 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv)
|
|||
|
||||
/* Enter initialization mode */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
regval |= CAN_MCR_INRQ;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
/* Wait until initialization mode is acknowledged */
|
||||
|
||||
for (timeout = INAK_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET);
|
||||
if ((regval & CAN_MSR_INAK) != 0)
|
||||
{
|
||||
/* We are in initialization mode */
|
||||
|
|
@ -1840,15 +1840,15 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv)
|
|||
|
||||
/* Exit Initialization mode, enter Normal mode */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
regval &= ~CAN_MCR_INRQ;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
/* Wait until the initialization mode exit is acknowledged */
|
||||
|
||||
for (timeout = INAK_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET);
|
||||
if ((regval & CAN_MSR_INAK) == 0)
|
||||
{
|
||||
/* We are out of initialization mode */
|
||||
|
|
@ -1893,9 +1893,9 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv)
|
|||
|
||||
/* Exit from sleep mode */
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
regval &= ~CAN_MCR_SLEEP;
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
ret = stm32l4can_enterinitmode(priv);
|
||||
if (ret != 0)
|
||||
|
|
@ -1913,10 +1913,10 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv)
|
|||
* - Transmit FIFO priority
|
||||
*/
|
||||
|
||||
regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET);
|
||||
regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET);
|
||||
regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART |
|
||||
CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM);
|
||||
stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval);
|
||||
stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval);
|
||||
|
||||
/* Configure bit timing. */
|
||||
|
||||
|
|
@ -1975,52 +1975,52 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv)
|
|||
|
||||
/* Enter filter initialization mode */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET);
|
||||
regval |= CAN_FMR_FINIT;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
|
||||
|
||||
/* Disable the filter */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
|
||||
regval &= ~bitmask;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
|
||||
|
||||
/* Select the 32-bit scale for the filter */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FS1R_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FS1R_OFFSET);
|
||||
regval |= bitmask;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FS1R_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval);
|
||||
|
||||
/* There are 14 or 28 filter banks (depending) on the device.
|
||||
* Each filter bank is composed of two 32-bit registers, CAN_FiR:
|
||||
*/
|
||||
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0);
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0);
|
||||
|
||||
/* Set Id/Mask mode for the filter */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FM1R_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FM1R_OFFSET);
|
||||
regval &= ~bitmask;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FM1R_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval);
|
||||
|
||||
/* Assign FIFO 0 for the filter */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FFA1R_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FFA1R_OFFSET);
|
||||
regval &= ~bitmask;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FFA1R_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval);
|
||||
|
||||
/* Enable the filter */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET);
|
||||
regval |= bitmask;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval);
|
||||
|
||||
/* Exit filter initialization mode */
|
||||
|
||||
regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET);
|
||||
regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET);
|
||||
regval &= ~CAN_FMR_FINIT;
|
||||
stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval);
|
||||
stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
|
||||
/* Up to 1 CAN interfaces are supported */
|
||||
|
||||
#if STM32L4_NCAN < 1
|
||||
#if STM32_NCAN < 1
|
||||
# undef CONFIG_STM32L4_CAN1
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -104,12 +104,12 @@ static struct stm32l4_comp_config_s g_comp1priv =
|
|||
.rising = true,
|
||||
.falling = false
|
||||
},
|
||||
.inp = STM32L4_COMP_INP_PIN_2,
|
||||
.inm = STM32L4_COMP_INM_VREF,
|
||||
.hyst = STM32L4_COMP_HYST_LOW,
|
||||
.speed = STM32L4_COMP_SPEED_MEDIUM,
|
||||
.inp = STM32_COMP_INP_PIN_2,
|
||||
.inm = STM32_COMP_INM_VREF,
|
||||
.hyst = STM32_COMP_HYST_LOW,
|
||||
.speed = STM32_COMP_SPEED_MEDIUM,
|
||||
.inverted = false,
|
||||
.csr = STM32L4_COMP1_CSR,
|
||||
.csr = STM32_COMP1_CSR,
|
||||
};
|
||||
|
||||
static struct comp_dev_s g_comp1dev =
|
||||
|
|
@ -126,12 +126,12 @@ static struct stm32l4_comp_config_s g_comp2priv =
|
|||
.rising = true,
|
||||
.falling = false
|
||||
},
|
||||
.inp = STM32L4_COMP_INP_PIN_1,
|
||||
.inm = STM32L4_COMP_INM_DAC_1,
|
||||
.hyst = STM32L4_COMP_HYST_LOW,
|
||||
.speed = STM32L4_COMP_SPEED_MEDIUM,
|
||||
.inp = STM32_COMP_INP_PIN_1,
|
||||
.inm = STM32_COMP_INM_DAC_1,
|
||||
.hyst = STM32_COMP_HYST_LOW,
|
||||
.speed = STM32_COMP_SPEED_MEDIUM,
|
||||
.inverted = false,
|
||||
.csr = STM32L4_COMP2_CSR,
|
||||
.csr = STM32_COMP2_CSR,
|
||||
};
|
||||
|
||||
static struct comp_dev_s g_comp2dev =
|
||||
|
|
@ -324,7 +324,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg)
|
|||
DEBUGASSERT(cfg->interrupt.cb &&
|
||||
(cfg->interrupt.rising || cfg->interrupt.falling));
|
||||
|
||||
ainfo("isr: %d\n", (cfg->csr == STM32L4_COMP1_CSR ? 0 : 1));
|
||||
ainfo("isr: %d\n", (cfg->csr == STM32_COMP1_CSR ? 0 : 1));
|
||||
|
||||
cfg->interrupt.cb->au_notify(dev, comp_read(dev));
|
||||
|
||||
|
|
@ -356,28 +356,28 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev)
|
|||
int cmp;
|
||||
|
||||
cfg = dev->ad_priv;
|
||||
cmp = cfg->csr == STM32L4_COMP1_CSR ? STM32L4_COMP1 : STM32L4_COMP2;
|
||||
cmp = cfg->csr == STM32_COMP1_CSR ? STM32_COMP1 : STM32_COMP2;
|
||||
|
||||
/* Input plus */
|
||||
|
||||
mask |= COMP_CSR_INPSEL_MASK;
|
||||
switch (cfg->inp)
|
||||
{
|
||||
case STM32L4_COMP_INP_PIN_1:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 :
|
||||
case STM32_COMP_INP_PIN_1:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 :
|
||||
GPIO_COMP2_INP_1);
|
||||
regval |= COMP_CSR_INPSEL_PIN1;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INP_PIN_2:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 :
|
||||
case STM32_COMP_INP_PIN_2:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 :
|
||||
GPIO_COMP2_INP_2);
|
||||
regval |= COMP_CSR_INPSEL_PIN2;
|
||||
break;
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
case STM32L4_COMP_INP_PIN_3:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 :
|
||||
case STM32_COMP_INP_PIN_3:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 :
|
||||
GPIO_COMP2_INP_3);
|
||||
regval |= COMP_CSR_INPSEL_PIN3;
|
||||
break;
|
||||
|
|
@ -392,46 +392,46 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev)
|
|||
mask |= COMP_CSR_INMSEL_MASK;
|
||||
switch (cfg->inm)
|
||||
{
|
||||
case STM32L4_COMP_INM_1_4_VREF:
|
||||
case STM32_COMP_INM_1_4_VREF:
|
||||
regval |= COMP_CSR_INMSEL_25PCT;
|
||||
mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_1_2_VREF:
|
||||
case STM32_COMP_INM_1_2_VREF:
|
||||
regval |= COMP_CSR_INMSEL_50PCT;
|
||||
mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_3_4_VREF:
|
||||
case STM32_COMP_INM_3_4_VREF:
|
||||
regval |= COMP_CSR_INMSEL_75PCT;
|
||||
mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_VREF:
|
||||
case STM32_COMP_INM_VREF:
|
||||
regval |= COMP_CSR_INMSEL_VREF;
|
||||
mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN);
|
||||
regval |= COMP_CSR_SCALEN;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_DAC_1:
|
||||
case STM32_COMP_INM_DAC_1:
|
||||
regval |= COMP_CSR_INMSEL_DAC1;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_DAC_2:
|
||||
case STM32_COMP_INM_DAC_2:
|
||||
regval |= COMP_CSR_INMSEL_DAC2;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_PIN_1:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 :
|
||||
case STM32_COMP_INM_PIN_1:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 :
|
||||
GPIO_COMP2_INM_1);
|
||||
regval |= COMP_CSR_INMSEL_PIN1;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_PIN_2:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 :
|
||||
case STM32_COMP_INM_PIN_2:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 :
|
||||
GPIO_COMP2_INM_2);
|
||||
#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \
|
||||
defined(CONFIG_STM32L4_STM32L4XR)
|
||||
|
|
@ -444,24 +444,24 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev)
|
|||
break;
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
case STM32L4_COMP_INM_PIN_3:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 :
|
||||
case STM32_COMP_INM_PIN_3:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 :
|
||||
GPIO_COMP2_INM_3);
|
||||
regval |= COMP_CSR_INMSEL_INMESEL;
|
||||
mask |= COMP_CSR_INMESEL_MASK;
|
||||
regval |= COMP_CSR_INMESEL_PIN3;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_PIN_4:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 :
|
||||
case STM32_COMP_INM_PIN_4:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 :
|
||||
GPIO_COMP2_INM_4);
|
||||
regval |= COMP_CSR_INMSEL_INMESEL;
|
||||
mask |= COMP_CSR_INMESEL_MASK;
|
||||
regval |= COMP_CSR_INMESEL_PIN4;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_INM_PIN_5:
|
||||
stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 :
|
||||
case STM32_COMP_INM_PIN_5:
|
||||
stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 :
|
||||
GPIO_COMP2_INM_5);
|
||||
regval |= COMP_CSR_INMSEL_INMESEL;
|
||||
mask |= COMP_CSR_INMESEL_MASK;
|
||||
|
|
@ -478,19 +478,19 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev)
|
|||
mask |= COMP_CSR_HYST_MASK;
|
||||
switch (cfg->hyst)
|
||||
{
|
||||
case STM32L4_COMP_HYST_NONE:
|
||||
case STM32_COMP_HYST_NONE:
|
||||
regval |= COMP_CSR_HYST_NONE;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_HYST_LOW:
|
||||
case STM32_COMP_HYST_LOW:
|
||||
regval |= COMP_CSR_HYST_LOW;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_HYST_MEDIUM:
|
||||
case STM32_COMP_HYST_MEDIUM:
|
||||
regval |= COMP_CSR_HYST_MEDIUM;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_HYST_HIGH:
|
||||
case STM32_COMP_HYST_HIGH:
|
||||
regval |= COMP_CSR_HYST_HIGH;
|
||||
break;
|
||||
|
||||
|
|
@ -503,15 +503,15 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev)
|
|||
mask |= COMP_CSR_PWRMODE_MASK;
|
||||
switch (cfg->speed)
|
||||
{
|
||||
case STM32L4_COMP_SPEED_HIGH:
|
||||
case STM32_COMP_SPEED_HIGH:
|
||||
regval |= COMP_CSR_PWRMODE_HIGH;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_SPEED_MEDIUM:
|
||||
case STM32_COMP_SPEED_MEDIUM:
|
||||
regval |= COMP_CSR_PWRMODE_MEDIUM;
|
||||
break;
|
||||
|
||||
case STM32L4_COMP_SPEED_LOW:
|
||||
case STM32_COMP_SPEED_LOW:
|
||||
regval |= COMP_CSR_PWRMODE_LOW;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -56,35 +56,35 @@
|
|||
|
||||
enum stm32l4_comp_e
|
||||
{
|
||||
STM32L4_COMP1,
|
||||
STM32L4_COMP2,
|
||||
STM32L4_COMP_NUM /* Number of comparators */
|
||||
STM32_COMP1,
|
||||
STM32_COMP2,
|
||||
STM32_COMP_NUM /* Number of comparators */
|
||||
};
|
||||
|
||||
/* Plus input */
|
||||
|
||||
enum stm32l4_comp_inp_e
|
||||
{
|
||||
STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */
|
||||
STM32L4_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */
|
||||
STM32L4_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */
|
||||
STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */
|
||||
STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */
|
||||
STM32_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */
|
||||
};
|
||||
|
||||
/* Minus input */
|
||||
|
||||
enum stm32l4_comp_inm_e
|
||||
{
|
||||
STM32L4_COMP_INM_1_4_VREF,
|
||||
STM32L4_COMP_INM_1_2_VREF,
|
||||
STM32L4_COMP_INM_3_4_VREF,
|
||||
STM32L4_COMP_INM_VREF,
|
||||
STM32L4_COMP_INM_DAC_1,
|
||||
STM32L4_COMP_INM_DAC_2,
|
||||
STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */
|
||||
STM32L4_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */
|
||||
STM32L4_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */
|
||||
STM32L4_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */
|
||||
STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */
|
||||
STM32_COMP_INM_1_4_VREF,
|
||||
STM32_COMP_INM_1_2_VREF,
|
||||
STM32_COMP_INM_3_4_VREF,
|
||||
STM32_COMP_INM_VREF,
|
||||
STM32_COMP_INM_DAC_1,
|
||||
STM32_COMP_INM_DAC_2,
|
||||
STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */
|
||||
STM32_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */
|
||||
STM32_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */
|
||||
STM32_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */
|
||||
STM32_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */
|
||||
};
|
||||
|
||||
#else
|
||||
|
|
@ -93,31 +93,31 @@ enum stm32l4_comp_inm_e
|
|||
|
||||
enum stm32l4_comp_e
|
||||
{
|
||||
STM32L4_COMP1,
|
||||
STM32L4_COMP2,
|
||||
STM32L4_COMP_NUM /* Number of comparators */
|
||||
STM32_COMP1,
|
||||
STM32_COMP2,
|
||||
STM32_COMP_NUM /* Number of comparators */
|
||||
};
|
||||
|
||||
/* Plus input */
|
||||
|
||||
enum stm32l4_comp_inp_e
|
||||
{
|
||||
STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */
|
||||
STM32L4_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */
|
||||
STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */
|
||||
STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */
|
||||
};
|
||||
|
||||
/* Minus input */
|
||||
|
||||
enum stm32l4_comp_inm_e
|
||||
{
|
||||
STM32L4_COMP_INM_1_4_VREF,
|
||||
STM32L4_COMP_INM_1_2_VREF,
|
||||
STM32L4_COMP_INM_3_4_VREF,
|
||||
STM32L4_COMP_INM_VREF,
|
||||
STM32L4_COMP_INM_DAC_1,
|
||||
STM32L4_COMP_INM_DAC_2,
|
||||
STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */
|
||||
STM32L4_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */
|
||||
STM32_COMP_INM_1_4_VREF,
|
||||
STM32_COMP_INM_1_2_VREF,
|
||||
STM32_COMP_INM_3_4_VREF,
|
||||
STM32_COMP_INM_VREF,
|
||||
STM32_COMP_INM_DAC_1,
|
||||
STM32_COMP_INM_DAC_2,
|
||||
STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */
|
||||
STM32_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -125,19 +125,19 @@ enum stm32l4_comp_inm_e
|
|||
|
||||
enum stm32l4_comp_hyst_e
|
||||
{
|
||||
STM32L4_COMP_HYST_NONE,
|
||||
STM32L4_COMP_HYST_LOW,
|
||||
STM32L4_COMP_HYST_MEDIUM,
|
||||
STM32L4_COMP_HYST_HIGH
|
||||
STM32_COMP_HYST_NONE,
|
||||
STM32_COMP_HYST_LOW,
|
||||
STM32_COMP_HYST_MEDIUM,
|
||||
STM32_COMP_HYST_HIGH
|
||||
};
|
||||
|
||||
/* Power/Speed Modes */
|
||||
|
||||
enum stm32l4_comp_speed_e
|
||||
{
|
||||
STM32L4_COMP_SPEED_HIGH,
|
||||
STM32L4_COMP_SPEED_MEDIUM,
|
||||
STM32L4_COMP_SPEED_LOW
|
||||
STM32_COMP_SPEED_HIGH,
|
||||
STM32_COMP_SPEED_MEDIUM,
|
||||
STM32_COMP_SPEED_LOW
|
||||
};
|
||||
|
||||
/* Comparator configuration *************************************************/
|
||||
|
|
|
|||
|
|
@ -55,18 +55,18 @@
|
|||
|
||||
/* Up to 1 DAC interface for up to 2 channels are supported */
|
||||
|
||||
#if STM32L4_NDAC > 2
|
||||
#if STM32_NDAC > 2
|
||||
# warning "Extra DAC channels. Only DAC1 and DAC2 are supported"
|
||||
#endif
|
||||
|
||||
#if STM32L4_NDAC < 2
|
||||
#if STM32_NDAC < 2
|
||||
# undef CONFIG_STM32L4_DAC2
|
||||
# undef CONFIG_STM32L4_DAC2_DMA
|
||||
# undef CONFIG_STM32L4_DAC2_TIMER
|
||||
# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY
|
||||
#endif
|
||||
|
||||
#if STM32L4_NDAC < 1
|
||||
#if STM32_NDAC < 1
|
||||
# undef CONFIG_STM32L4_DAC1
|
||||
# undef CONFIG_STM32L4_DAC1_DMA
|
||||
# undef CONFIG_STM32L4_DAC1_TIMER
|
||||
|
|
@ -178,47 +178,47 @@
|
|||
# endif
|
||||
# define NEED_TIM6
|
||||
# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6
|
||||
# define DAC1_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC1_TIMER_BASE STM32_TIM6_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC1_TIMER == 8
|
||||
# ifndef CONFIG_STM32L4_TIM8_DAC
|
||||
# error "CONFIG_STM32L4_TIM8_DAC required for DAC1"
|
||||
# endif
|
||||
# define NEED_TIM8
|
||||
# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8
|
||||
# define DAC1_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY
|
||||
# define DAC1_TIMER_BASE STM32_TIM8_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC1_TIMER == 7
|
||||
# ifndef CONFIG_STM32L4_TIM7_DAC
|
||||
# error "CONFIG_STM32L4_TIM7_DAC required for DAC1"
|
||||
# endif
|
||||
# define NEED_TIM7
|
||||
# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7
|
||||
# define DAC1_TIMER_BASE STM32L4_TIM7_BASE
|
||||
# define DAC1_TIMER_BASE STM32_TIM7_BASE
|
||||
# elif CONFIG_STM32L4_DAC1_TIMER == 5
|
||||
# ifndef CONFIG_STM32L4_TIM5_DAC
|
||||
# error "CONFIG_STM32L4_TIM5_DAC required for DAC1"
|
||||
# endif
|
||||
# define NEED_TIM5
|
||||
# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5
|
||||
# define DAC1_TIMER_BASE STM32L4_TIM5_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC1_TIMER_BASE STM32_TIM5_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC1_TIMER == 2
|
||||
# ifndef CONFIG_STM32L4_TIM2_DAC
|
||||
# error "CONFIG_STM32L4_TIM2_DAC required for DAC1"
|
||||
# endif
|
||||
# define NEED_TIM2
|
||||
# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2
|
||||
# define DAC1_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC1_TIMER_BASE STM32_TIM2_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC1_TIMER == 4
|
||||
# ifndef CONFIG_STM32L4_TIM4_DAC
|
||||
# error "CONFIG_STM32L4_TIM4_DAC required for DAC1"
|
||||
# endif
|
||||
# define NEED_TIM4
|
||||
# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4
|
||||
# define DAC1_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC1_TIMER_BASE STM32_TIM4_BASE
|
||||
# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# else
|
||||
# error "Unsupported CONFIG_STM32L4_DAC1_TIMER"
|
||||
# endif
|
||||
|
|
@ -232,43 +232,43 @@
|
|||
# error "CONFIG_STM32L4_TIM6_DAC required for DAC2"
|
||||
# endif
|
||||
# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6
|
||||
# define DAC2_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC2_TIMER_BASE STM32_TIM6_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC2_TIMER == 8
|
||||
# ifndef CONFIG_STM32L4_TIM8_DAC
|
||||
# error "CONFIG_STM32L4_TIM8_DAC required for DAC2"
|
||||
# endif
|
||||
# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8
|
||||
# define DAC2_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY
|
||||
# define DAC2_TIMER_BASE STM32_TIM8_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC2_TIMER == 7
|
||||
# ifndef CONFIG_STM32L4_TIM7_DAC
|
||||
# error "CONFIG_STM32L4_TIM7_DAC required for DAC2"
|
||||
# endif
|
||||
# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7
|
||||
# define DAC2_TIMER_BASE STM32L4_TIM7_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC2_TIMER_BASE STM32_TIM7_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC2_TIMER == 5
|
||||
# ifndef CONFIG_STM32L4_TIM5_DAC
|
||||
# error "CONFIG_STM32L4_TIM5_DAC required for DAC2"
|
||||
# endif
|
||||
# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5
|
||||
# define DAC2_TIMER_BASE STM32L4_TIM5_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC2_TIMER_BASE STM32_TIM5_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC2_TIMER == 2
|
||||
# ifndef CONFIG_STM32L4_TIM2_DAC
|
||||
# error "CONFIG_STM32L4_TIM2_DAC required for DAC2"
|
||||
# endif
|
||||
# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2
|
||||
# define DAC2_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC2_TIMER_BASE STM32_TIM2_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# elif CONFIG_STM32L4_DAC2_TIMER == 4
|
||||
# ifndef CONFIG_STM32L4_TIM4_DAC
|
||||
# error "CONFIG_STM32L4_TIM4_DAC required for DAC2"
|
||||
# endif
|
||||
# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4
|
||||
# define DAC2_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
|
||||
# define DAC2_TIMER_BASE STM32_TIM4_BASE
|
||||
# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
# else
|
||||
# error "Unsupported CONFIG_STM32L4_DAC2_TIMER"
|
||||
# endif
|
||||
|
|
@ -422,8 +422,8 @@ static struct stm32_chan_s g_dac1priv =
|
|||
#else
|
||||
.pin = GPIO_DAC1_OUT,
|
||||
#endif
|
||||
.dro = STM32L4_DAC_DHR12R1,
|
||||
.cr = STM32L4_DAC_CR,
|
||||
.dro = STM32_DAC_DHR12R1,
|
||||
.cr = STM32_DAC_CR,
|
||||
#ifdef CONFIG_STM32L4_DAC1_DMA
|
||||
.hasdma = 1,
|
||||
.dmachan = DAC1_DMA_CHAN,
|
||||
|
|
@ -462,8 +462,8 @@ static struct stm32_chan_s g_dac2priv =
|
|||
#else
|
||||
.pin = GPIO_DAC2_OUT,
|
||||
#endif
|
||||
.dro = STM32L4_DAC_DHR12R2,
|
||||
.cr = STM32L4_DAC_CR,
|
||||
.dro = STM32_DAC_DHR12R2,
|
||||
.cr = STM32_DAC_CR,
|
||||
#ifdef CONFIG_STM32L4_DAC2_DMA
|
||||
.hasdma = 1,
|
||||
.dmachan = DAC2_DMA_CHAN,
|
||||
|
|
@ -507,7 +507,7 @@ static struct stm32_dac_s g_dacblock;
|
|||
|
||||
static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset)
|
||||
{
|
||||
return getreg32(STM32L4_DAC_BASE + offset);
|
||||
return getreg32(STM32_DAC_BASE + offset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -532,7 +532,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan,
|
|||
{
|
||||
unsigned int shift;
|
||||
|
||||
/* DAC channels 1 and 2 share the STM32L4_DAC[1]_CR control register. If
|
||||
/* DAC channels 1 and 2 share the STM32_DAC[1]_CR control register. If
|
||||
* future chips have DAC channel 3 (and perhaps channel 4) they likely have
|
||||
* their own register like in STM32. In either case, bit 0 of the interface
|
||||
* number provides the correct shift.
|
||||
|
|
@ -567,7 +567,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan,
|
|||
{
|
||||
unsigned int shift;
|
||||
|
||||
/* DAC channels 1 and 2 share the STM32L4_DAC_MCR control register.
|
||||
/* DAC channels 1 and 2 share the STM32_DAC_MCR control register.
|
||||
* Bit 0 of the interface number provides the correct shift.
|
||||
*
|
||||
* Bit 0 = 0: Shift = 0
|
||||
|
|
@ -575,7 +575,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan,
|
|||
*/
|
||||
|
||||
shift = (chan->intf & 1) << 4;
|
||||
modifyreg32(STM32L4_DAC_MCR, clearbits << shift, setbits << shift);
|
||||
modifyreg32(STM32_DAC_MCR, clearbits << shift, setbits << shift);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -588,10 +588,10 @@ static void dac_dumpregs(struct stm32_chan_s *priv)
|
|||
|
||||
ainfo("CR: 0x%08" PRIx32 " SWTRGR: 0x%08" PRIx32
|
||||
"SR: 0x%08" PRIx32 " MCR: 0x%08" PRIx32 "\n",
|
||||
dac_getreg(priv, STM32L4_DAC_CR_OFFSET),
|
||||
dac_getreg(priv, STM32L4_DAC_SWTRIGR_OFFSET),
|
||||
dac_getreg(priv, STM32L4_DAC_SR_OFFSET),
|
||||
dac_getreg(priv, STM32L4_DAC_MCR_OFFSET));
|
||||
dac_getreg(priv, STM32_DAC_CR_OFFSET),
|
||||
dac_getreg(priv, STM32_DAC_SWTRIGR_OFFSET),
|
||||
dac_getreg(priv, STM32_DAC_SR_OFFSET),
|
||||
dac_getreg(priv, STM32_DAC_MCR_OFFSET));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -867,7 +867,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg)
|
|||
/* Reset counters (generate an update) */
|
||||
|
||||
#ifdef HAVE_DMA
|
||||
tim_modifyreg(chan, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG);
|
||||
tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG);
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -923,7 +923,7 @@ static int dac_timinit(struct stm32_chan_s *chan)
|
|||
* default) will be enabled
|
||||
*/
|
||||
|
||||
regaddr = STM32L4_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
|
||||
switch (chan->timer)
|
||||
{
|
||||
|
|
@ -965,7 +965,7 @@ static int dac_timinit(struct stm32_chan_s *chan)
|
|||
#endif
|
||||
#ifdef NEED_TIM8
|
||||
case 8:
|
||||
regaddr = STM32L4_RCC_APB2ENR;
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
setbits = RCC_APB2ENR_TIM8EN;
|
||||
pclk = BOARD_TIM8_FREQUENCY;
|
||||
break;
|
||||
|
|
@ -1036,26 +1036,26 @@ static int dac_timinit(struct stm32_chan_s *chan)
|
|||
|
||||
/* Set the reload and prescaler values */
|
||||
|
||||
tim_putreg(chan, STM32L4_GTIM_ARR_OFFSET, (uint16_t)reload);
|
||||
tim_putreg(chan, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1));
|
||||
tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload);
|
||||
tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1));
|
||||
|
||||
/* Count mode up, auto reload */
|
||||
|
||||
tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
|
||||
/* Selection TRGO selection: update */
|
||||
|
||||
tim_modifyreg(chan, STM32L4_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK,
|
||||
tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK,
|
||||
GTIM_CR2_MMS_UPDATE);
|
||||
|
||||
/* Update DMA request enable ???? */
|
||||
#if 0
|
||||
tim_modifyreg(chan, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE);
|
||||
tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE);
|
||||
#endif
|
||||
|
||||
/* Enable the counter */
|
||||
|
||||
tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1200,14 +1200,14 @@ static void dac_blockinit(void)
|
|||
/* Put the entire DAC block in reset state */
|
||||
|
||||
flags = enter_critical_section();
|
||||
regval = getreg32(STM32L4_RCC_APB1RSTR1);
|
||||
regval = getreg32(STM32_RCC_APB1RSTR1);
|
||||
regval |= RCC_APB1RSTR1_DAC1RST;
|
||||
putreg32(regval, STM32L4_RCC_APB1RSTR1);
|
||||
putreg32(regval, STM32_RCC_APB1RSTR1);
|
||||
|
||||
/* Take the DAC out of reset state */
|
||||
|
||||
regval &= ~RCC_APB1RSTR1_DAC1RST;
|
||||
putreg32(regval, STM32L4_RCC_APB1RSTR1);
|
||||
putreg32(regval, STM32_RCC_APB1RSTR1);
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Mark the DAC block as initialized */
|
||||
|
|
@ -1286,7 +1286,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev)
|
|||
|
||||
/* Reset counters (generate an update) */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG);
|
||||
tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -75,21 +75,21 @@
|
|||
|
||||
/* Abbreviated register access **********************************************/
|
||||
|
||||
#define CHCFGR1_OFFSET(priv) STM32L4_DFSDM_CHCFGR1_OFFSET((priv)->current)
|
||||
#define CHCFGR2_OFFSET(priv) STM32L4_DFSDM_CHCFGR2_OFFSET((priv)->current)
|
||||
#define CHCFGR1_OFFSET(priv) STM32_DFSDM_CHCFGR1_OFFSET((priv)->current)
|
||||
#define CHCFGR2_OFFSET(priv) STM32_DFSDM_CHCFGR2_OFFSET((priv)->current)
|
||||
|
||||
#define FLTCR1_OFFSET(priv) STM32L4_DFSDM_FLTCR1_OFFSET((priv)->intf)
|
||||
#define FLTCR2_OFFSET(priv) STM32L4_DFSDM_FLTCR2_OFFSET((priv)->intf)
|
||||
#define FLTISR_OFFSET(priv) STM32L4_DFSDM_FLTISR_OFFSET((priv)->intf)
|
||||
#define FLTICR_OFFSET(priv) STM32L4_DFSDM_FLTICR_OFFSET((priv)->intf)
|
||||
#define FLTFCR_OFFSET(priv) STM32L4_DFSDM_FLTFCR_OFFSET((priv)->intf)
|
||||
#define FLTRDATAR_OFFSET(priv) STM32L4_DFSDM_FLTRDATAR_OFFSET((priv)->intf)
|
||||
#define FLTAWHTR_OFFSET(priv) STM32L4_DFSDM_FLTAWHTR_OFFSET((priv)->intf)
|
||||
#define FLTAWLTR_OFFSET(priv) STM32L4_DFSDM_FLTAWLTR_OFFSET((priv)->intf)
|
||||
#define FLTAWSR_OFFSET(priv) STM32L4_DFSDM_FLTAWSR_OFFSET((priv)->intf)
|
||||
#define FLTAWCFR_OFFSET(priv) STM32L4_DFSDM_FLTAWCFR_OFFSET((priv)->intf)
|
||||
#define FLTEXMAX_OFFSET(priv) STM32L4_DFSDM_FLTEXMAX_OFFSET((priv)->intf)
|
||||
#define FLTEXMIN_OFFSET(priv) STM32L4_DFSDM_FLTEXMIN_OFFSET((priv)->intf)
|
||||
#define FLTCR1_OFFSET(priv) STM32_DFSDM_FLTCR1_OFFSET((priv)->intf)
|
||||
#define FLTCR2_OFFSET(priv) STM32_DFSDM_FLTCR2_OFFSET((priv)->intf)
|
||||
#define FLTISR_OFFSET(priv) STM32_DFSDM_FLTISR_OFFSET((priv)->intf)
|
||||
#define FLTICR_OFFSET(priv) STM32_DFSDM_FLTICR_OFFSET((priv)->intf)
|
||||
#define FLTFCR_OFFSET(priv) STM32_DFSDM_FLTFCR_OFFSET((priv)->intf)
|
||||
#define FLTRDATAR_OFFSET(priv) STM32_DFSDM_FLTRDATAR_OFFSET((priv)->intf)
|
||||
#define FLTAWHTR_OFFSET(priv) STM32_DFSDM_FLTAWHTR_OFFSET((priv)->intf)
|
||||
#define FLTAWLTR_OFFSET(priv) STM32_DFSDM_FLTAWLTR_OFFSET((priv)->intf)
|
||||
#define FLTAWSR_OFFSET(priv) STM32_DFSDM_FLTAWSR_OFFSET((priv)->intf)
|
||||
#define FLTAWCFR_OFFSET(priv) STM32_DFSDM_FLTAWCFR_OFFSET((priv)->intf)
|
||||
#define FLTEXMAX_OFFSET(priv) STM32_DFSDM_FLTEXMAX_OFFSET((priv)->intf)
|
||||
#define FLTEXMIN_OFFSET(priv) STM32_DFSDM_FLTEXMIN_OFFSET((priv)->intf)
|
||||
|
||||
/* DFSDM Filter interrupts **************************************************/
|
||||
|
||||
|
|
@ -277,10 +277,10 @@ static const struct adc_ops_s g_adcops =
|
|||
#if defined(CONFIG_STM32L4_DFSDM1_FLT0)
|
||||
static struct stm32_dev_s g_dfsdmpriv0 =
|
||||
{
|
||||
.irq = STM32L4_IRQ_DFSDM0,
|
||||
.irq = STM32_IRQ_DFSDM0,
|
||||
.isr = dfsdm_flt0_interrupt,
|
||||
.intf = 0,
|
||||
.base = STM32L4_DFSDM_BASE,
|
||||
.base = STM32_DFSDM_BASE,
|
||||
#ifdef DFSDM_HAVE_TIMER
|
||||
.trigger = CONFIG_STM32L4_DFSDM_TIMTRIG,
|
||||
.tbase = DFSDM_TIMER_BASE,
|
||||
|
|
@ -306,10 +306,10 @@ static struct adc_dev_s g_dfsdmdev0 =
|
|||
#if defined(CONFIG_STM32L4_DFSDM1_FLT1)
|
||||
static struct stm32_dev_s g_dfsdmpriv1 =
|
||||
{
|
||||
.irq = STM32L4_IRQ_DFSDM1,
|
||||
.irq = STM32_IRQ_DFSDM1,
|
||||
.isr = dfsdm_flt1_interrupt,
|
||||
.intf = 1,
|
||||
.base = STM32L4_DFSDM_BASE,
|
||||
.base = STM32_DFSDM_BASE,
|
||||
#ifdef DFSDM_HAVE_TIMER
|
||||
.trigger = CONFIG_STM32L4_DFSDM_TIMTRIG,
|
||||
.tbase = DFSDM_TIMER_BASE,
|
||||
|
|
@ -335,10 +335,10 @@ static struct adc_dev_s g_dfsdmdev1 =
|
|||
#if defined(CONFIG_STM32L4_DFSDM1_FLT2)
|
||||
static struct stm32_dev_s g_dfsdmpriv2 =
|
||||
{
|
||||
.irq = STM32L4_IRQ_DFSDM2,
|
||||
.irq = STM32_IRQ_DFSDM2,
|
||||
.isr = dfsdm_flt2_interrupt,
|
||||
.intf = 0,
|
||||
.base = STM32L4_DFSDM_BASE,
|
||||
.base = STM32_DFSDM_BASE,
|
||||
#ifdef DFSDM_HAVE_TIMER
|
||||
.trigger = CONFIG_STM32L4_DFSDM_TIMTRIG,
|
||||
.tbase = DFSDM_TIMER_BASE,
|
||||
|
|
@ -364,10 +364,10 @@ static struct adc_dev_s g_dfsdmdev2 =
|
|||
#if defined(CONFIG_STM32L4_DFSDM1_FLT3)
|
||||
static struct stm32_dev_s g_dfsdmpriv3 =
|
||||
{
|
||||
.irq = STM32L4_IRQ_DFSDM3,
|
||||
.irq = STM32_IRQ_DFSDM3,
|
||||
.isr = dfsdm_flt3_interrupt,
|
||||
.intf = 0,
|
||||
.base = STM32L4_DFSDM_BASE,
|
||||
.base = STM32_DFSDM_BASE,
|
||||
#ifdef DFSDM_HAVE_TIMER
|
||||
.trigger = CONFIG_STM32L4_DFSDM_TIMTRIG,
|
||||
.tbase = DFSDM_TIMER_BASE,
|
||||
|
|
@ -548,38 +548,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg)
|
|||
{
|
||||
ainfo("%s:\n", msg);
|
||||
ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
|
||||
ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_SR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_SR_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
|
||||
ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
|
||||
ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
|
||||
|
||||
if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE)
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
|
||||
tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET));
|
||||
tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
|
||||
tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
|
||||
tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
|
||||
}
|
||||
else
|
||||
{
|
||||
ainfo(" DCR: %04x DMAR: %04x\n",
|
||||
tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET));
|
||||
tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
|
||||
tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -607,13 +607,13 @@ static void dfsdm_timstart(struct stm32_dev_s *priv, bool enable)
|
|||
{
|
||||
/* Start the counter */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the counter */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -747,24 +747,24 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
|
||||
clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK;
|
||||
setbits = GTIM_CR1_EDGE;
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits);
|
||||
|
||||
/* Set the reload and prescaler values */
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1);
|
||||
tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload);
|
||||
tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1);
|
||||
tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
|
||||
|
||||
/* Clear the advanced timers repetition counter in TIM1 */
|
||||
|
||||
if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE)
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0);
|
||||
tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
|
||||
tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
|
||||
tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */
|
||||
}
|
||||
|
||||
/* TIMx event generation: Bit 0 UG: Update generation */
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
|
||||
/* Handle channel specific setup */
|
||||
|
||||
|
|
@ -788,7 +788,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR1_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
|
@ -808,7 +808,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR2_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
|
@ -828,7 +828,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR3_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
|
@ -848,7 +848,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
|
@ -866,7 +866,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
* channel
|
||||
*/
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET,
|
||||
tim_putreg(priv, STM32_GTIM_CCR4_OFFSET,
|
||||
(uint16_t)(reload >> 1));
|
||||
}
|
||||
break;
|
||||
|
|
@ -878,15 +878,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
|
||||
/* Disable the Channel by resetting the CCxE Bit in the CCER register */
|
||||
|
||||
ccer = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET);
|
||||
ccer &= ~ccenable;
|
||||
tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
/* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */
|
||||
|
||||
cr2 = tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET);
|
||||
ccmr1 = tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET);
|
||||
ccmr2 = tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET);
|
||||
cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET);
|
||||
ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
|
||||
ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
|
||||
|
||||
/* Reset the Output Compare Mode Bits and set the select output compare
|
||||
* mode
|
||||
|
|
@ -912,7 +912,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
ATIM_CCER_CC3E | ATIM_CCER_CC4E);
|
||||
ccer |= ccenable;
|
||||
|
||||
if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE)
|
||||
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
|
||||
{
|
||||
/* Reset output N polarity level, output N state, output compare state,
|
||||
* output compare N idle state.
|
||||
|
|
@ -937,15 +937,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv)
|
|||
|
||||
/* Save the modified register values */
|
||||
|
||||
tim_putreg(priv, STM32L4_GTIM_CR2_OFFSET, cr2);
|
||||
tim_putreg(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
tim_putreg(priv, STM32L4_GTIM_CCMR2_OFFSET, ccmr2);
|
||||
tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, egr);
|
||||
tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2);
|
||||
tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2);
|
||||
tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr);
|
||||
|
||||
/* Set the ARR Preload Bit */
|
||||
|
||||
tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE);
|
||||
|
||||
/* Enable the timer counter */
|
||||
|
||||
|
|
@ -1050,7 +1050,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset)
|
|||
|
||||
/* Set or clear the selected bit in the APB2 reset register */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB2RSTR);
|
||||
regval = getreg32(STM32_RCC_APB2RSTR);
|
||||
if (reset)
|
||||
{
|
||||
regval |= RCC_APB2RSTR_DFSDMRST;
|
||||
|
|
@ -1060,7 +1060,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset)
|
|||
regval &= ~RCC_APB2RSTR_DFSDMRST;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32L4_RCC_APB2RSTR);
|
||||
putreg32(regval, STM32_RCC_APB2RSTR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
|
|
@ -1079,12 +1079,12 @@ static void dfsdm_enable(struct stm32_dev_s *priv)
|
|||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = dfsdm_getreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET);
|
||||
regval = dfsdm_getreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET);
|
||||
|
||||
/* Enable DFSMDM */
|
||||
|
||||
regval |= DFSDM_CH0CFGR1_DFSDMEN;
|
||||
dfsdm_putreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET, regval);
|
||||
dfsdm_putreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET, regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1588,7 +1588,7 @@ static int dfsdm_flt0_interrupt(int irq, void *context, void *arg)
|
|||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
regval = getreg32(STM32L4_DFSDM_FLTISR(0));
|
||||
regval = getreg32(STM32_DFSDM_FLTISR(0));
|
||||
pending = regval & DFSDM_ISR_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
@ -1613,7 +1613,7 @@ static int dfsdm_flt1_interrupt(int irq, void *context, void *arg)
|
|||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
regval = getreg32(STM32L4_DFSDM_FLTISR(1));
|
||||
regval = getreg32(STM32_DFSDM_FLTISR(1));
|
||||
pending = regval & DFSDM_ISR_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
@ -1638,7 +1638,7 @@ static int dfsdm_flt2_interrupt(int irq, void *context, void *arg)
|
|||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
regval = getreg32(STM32L4_DFSDM_FLTISR(2));
|
||||
regval = getreg32(STM32_DFSDM_FLTISR(2));
|
||||
pending = regval & DFSDM_ISR_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
@ -1663,7 +1663,7 @@ static int dfsdm_flt3_interrupt(int irq, void *context, void *arg)
|
|||
uint32_t regval;
|
||||
uint32_t pending;
|
||||
|
||||
regval = getreg32(STM32L4_DFSDM_FLTISR(3));
|
||||
regval = getreg32(STM32_DFSDM_FLTISR(3));
|
||||
pending = regval & DFSDM_ISR_MASK;
|
||||
if (pending != 0)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -91,32 +91,32 @@
|
|||
|
||||
#if defined(CONFIG_STM32L4_TIM1_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM1_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM3_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM4_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM6_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM7_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM7_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM7_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM7_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM8_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#elif defined(CONFIG_STM32L4_TIM16_DFSDM)
|
||||
# define DFSDM_HAVE_TIMER 1
|
||||
# define DFSDM_TIMER_BASE STM32L4_TIM16_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM16_CLKIN
|
||||
# define DFSDM_TIMER_BASE STM32_TIM16_BASE
|
||||
# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN
|
||||
#else
|
||||
# undef DFSDM_HAVE_TIMER
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -51,67 +51,67 @@ static inline void rcc_reset(void)
|
|||
|
||||
/* Enable the MSI clock */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_MSION;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
while (!(getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY));
|
||||
while (!(getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY));
|
||||
|
||||
/* Set MSI to 4MHz */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_MSIRANGE_MASK;
|
||||
regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSIRGSEL;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Reset CFGR register */
|
||||
|
||||
putreg32(0x00000000, STM32L4_RCC_CFGR);
|
||||
putreg32(0x00000000, STM32_RCC_CFGR);
|
||||
|
||||
/* Reset enable bits for other clocks than MSI */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~(RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON |
|
||||
RCC_CR_HSIASFS | RCC_CR_CSSON | RCC_CR_PLLON |
|
||||
RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON);
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Reset PLLCFGR register to reset default */
|
||||
|
||||
putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG);
|
||||
putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
|
||||
|
||||
putreg32(0, STM32L4_RCC_PLLSAI1CFG);
|
||||
putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG);
|
||||
putreg32(0, STM32_RCC_PLLSAI1CFG);
|
||||
putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32_RCC_PLLSAI1CFG);
|
||||
|
||||
putreg32(0, STM32L4_RCC_PLLSAI2CFG);
|
||||
putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG);
|
||||
putreg32(0, STM32_RCC_PLLSAI2CFG);
|
||||
putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32_RCC_PLLSAI1CFG);
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_HSEBYP;
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0x00000000, STM32L4_RCC_CIER);
|
||||
putreg32(0x00000000, STM32_RCC_CIER);
|
||||
}
|
||||
|
||||
static inline void apb_reset(void)
|
||||
{
|
||||
putreg32(0xffffffff, STM32L4_RCC_APB1RSTR1);
|
||||
putreg32(0xffffffff, STM32L4_RCC_APB1RSTR2);
|
||||
putreg32(0xffffffff, STM32L4_RCC_APB2RSTR);
|
||||
putreg32(0xffffffff, STM32L4_RCC_AHB1RSTR);
|
||||
putreg32(0xffffffff, STM32L4_RCC_AHB2RSTR);
|
||||
putreg32(0xffffffff, STM32L4_RCC_AHB3RSTR);
|
||||
putreg32(0xffffffff, STM32_RCC_APB1RSTR1);
|
||||
putreg32(0xffffffff, STM32_RCC_APB1RSTR2);
|
||||
putreg32(0xffffffff, STM32_RCC_APB2RSTR);
|
||||
putreg32(0xffffffff, STM32_RCC_AHB1RSTR);
|
||||
putreg32(0xffffffff, STM32_RCC_AHB2RSTR);
|
||||
putreg32(0xffffffff, STM32_RCC_AHB3RSTR);
|
||||
|
||||
putreg32(0, STM32L4_RCC_APB1RSTR1);
|
||||
putreg32(0, STM32L4_RCC_APB1RSTR2);
|
||||
putreg32(0, STM32L4_RCC_APB2RSTR);
|
||||
putreg32(0, STM32L4_RCC_AHB1RSTR);
|
||||
putreg32(0, STM32L4_RCC_AHB2RSTR);
|
||||
putreg32(0, STM32L4_RCC_AHB3RSTR);
|
||||
putreg32(0, STM32_RCC_APB1RSTR1);
|
||||
putreg32(0, STM32_RCC_APB1RSTR2);
|
||||
putreg32(0, STM32_RCC_APB2RSTR);
|
||||
putreg32(0, STM32_RCC_AHB1RSTR);
|
||||
putreg32(0, STM32_RCC_AHB2RSTR);
|
||||
putreg32(0, STM32_RCC_AHB3RSTR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -144,10 +144,10 @@ void stm32l4_dfumode(void)
|
|||
|
||||
/* remap ROM at address zero */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB2ENR);
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
putreg32(regval, STM32L4_RCC_APB2ENR);
|
||||
putreg32(SYSCFG_MEMRMP_SYSTEM, STM32L4_SYSCFG_MEMRMP);
|
||||
putreg32(regval, STM32_RCC_APB2ENR);
|
||||
putreg32(SYSCFG_MEMRMP_SYSTEM, STM32_SYSCFG_MEMRMP);
|
||||
|
||||
/* set stack pointer and program-counter to ROM values */
|
||||
|
||||
|
|
|
|||
|
|
@ -50,31 +50,31 @@
|
|||
|
||||
/* Port letters for prettier debug output */
|
||||
|
||||
static const char g_portchar[STM32L4_NPORTS] =
|
||||
static const char g_portchar[STM32_NPORTS] =
|
||||
{
|
||||
#if STM32L4_NPORTS > 11
|
||||
#if STM32_NPORTS > 11
|
||||
# error "Additional support required for this number of GPIOs"
|
||||
#elif STM32L4_NPORTS > 10
|
||||
#elif STM32_NPORTS > 10
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
|
||||
#elif STM32L4_NPORTS > 9
|
||||
#elif STM32_NPORTS > 9
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
|
||||
#elif STM32L4_NPORTS > 8
|
||||
#elif STM32_NPORTS > 8
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
|
||||
#elif STM32L4_NPORTS > 7
|
||||
#elif STM32_NPORTS > 7
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
|
||||
#elif STM32L4_NPORTS > 6
|
||||
#elif STM32_NPORTS > 6
|
||||
'A', 'B', 'C', 'D', 'E', 'F', 'G'
|
||||
#elif STM32L4_NPORTS > 5
|
||||
#elif STM32_NPORTS > 5
|
||||
'A', 'B', 'C', 'D', 'E', 'F'
|
||||
#elif STM32L4_NPORTS > 4
|
||||
#elif STM32_NPORTS > 4
|
||||
'A', 'B', 'C', 'D', 'E'
|
||||
#elif STM32L4_NPORTS > 3
|
||||
#elif STM32_NPORTS > 3
|
||||
'A', 'B', 'C', 'D'
|
||||
#elif STM32L4_NPORTS > 2
|
||||
#elif STM32_NPORTS > 2
|
||||
'A', 'B', 'C'
|
||||
#elif STM32L4_NPORTS > 1
|
||||
#elif STM32_NPORTS > 1
|
||||
'A', 'B'
|
||||
#elif STM32L4_NPORTS > 0
|
||||
#elif STM32_NPORTS > 0
|
||||
'A'
|
||||
#else
|
||||
# error "Bad number of GPIOs"
|
||||
|
|
@ -108,33 +108,33 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg)
|
|||
|
||||
flags = enter_critical_section();
|
||||
|
||||
DEBUGASSERT(port < STM32L4_NPORTS);
|
||||
DEBUGASSERT(port < STM32_NPORTS);
|
||||
|
||||
_info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n",
|
||||
g_portchar[port], pinset, base, msg);
|
||||
|
||||
if ((getreg32(STM32L4_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
|
||||
if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
|
||||
{
|
||||
_info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32
|
||||
" OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n",
|
||||
getreg32(base + STM32L4_GPIO_MODER_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_OTYPER_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_OSPEED_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_PUPDR_OFFSET));
|
||||
getreg32(base + STM32_GPIO_MODER_OFFSET),
|
||||
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
|
||||
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
|
||||
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
|
||||
_info(" IDR: %04" PRIx32 " ODR: %04" PRIx32
|
||||
" BSRR: %08" PRIx32 " LCKR: %04x\n",
|
||||
getreg32(base + STM32L4_GPIO_IDR_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_ODR_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_BSRR_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_LCKR_OFFSET));
|
||||
getreg32(base + STM32_GPIO_IDR_OFFSET),
|
||||
getreg32(base + STM32_GPIO_ODR_OFFSET),
|
||||
getreg32(base + STM32_GPIO_BSRR_OFFSET),
|
||||
getreg32(base + STM32_GPIO_LCKR_OFFSET));
|
||||
_info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n",
|
||||
getreg32(base + STM32L4_GPIO_AFRH_OFFSET),
|
||||
getreg32(base + STM32L4_GPIO_AFRL_OFFSET));
|
||||
getreg32(base + STM32_GPIO_AFRH_OFFSET),
|
||||
getreg32(base + STM32_GPIO_AFRL_OFFSET));
|
||||
}
|
||||
else
|
||||
{
|
||||
_info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n",
|
||||
g_portchar[port], getreg32(STM32L4_RCC_AHB2ENR));
|
||||
g_portchar[port], getreg32(STM32_RCC_AHB2ENR));
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending EXTI interrupt */
|
||||
|
||||
putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR);
|
||||
putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -109,29 +109,29 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event,
|
|||
|
||||
if (func)
|
||||
{
|
||||
irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL);
|
||||
up_enable_irq(STM32L4_IRQ_RTCALRM);
|
||||
irq_attach(STM32_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL);
|
||||
up_enable_irq(STM32_IRQ_RTCALRM);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(STM32L4_IRQ_RTCALRM);
|
||||
up_disable_irq(STM32_IRQ_RTCALRM);
|
||||
}
|
||||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_RTSR,
|
||||
modifyreg32(STM32_EXTI1_RTSR,
|
||||
risingedge ? 0 : EXTI1_RTC_ALARM,
|
||||
risingedge ? EXTI1_RTC_ALARM : 0);
|
||||
modifyreg32(STM32L4_EXTI1_FTSR,
|
||||
modifyreg32(STM32_EXTI1_FTSR,
|
||||
fallingedge ? 0 : EXTI1_RTC_ALARM,
|
||||
fallingedge ? EXTI1_RTC_ALARM : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_EMR,
|
||||
modifyreg32(STM32_EXTI1_EMR,
|
||||
event ? 0 : EXTI1_RTC_ALARM,
|
||||
event ? EXTI1_RTC_ALARM : 0);
|
||||
modifyreg32(STM32L4_EXTI1_IMR,
|
||||
modifyreg32(STM32_EXTI1_IMR,
|
||||
func ? 0 : EXTI1_RTC_ALARM,
|
||||
func ? EXTI1_RTC_ALARM : 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -64,11 +64,11 @@ struct comp_callback_s
|
|||
|
||||
/* Interrupt handlers attached to the COMP EXTI lines */
|
||||
|
||||
static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM];
|
||||
static struct comp_callback_s g_comp_handlers[STM32_COMP_NUM];
|
||||
|
||||
/* Comparator EXTI lines */
|
||||
|
||||
static const uint32_t g_comp_lines[STM32L4_COMP_NUM] =
|
||||
static const uint32_t g_comp_lines[STM32_COMP_NUM] =
|
||||
{
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
|
||||
|
|
@ -92,15 +92,15 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Examine the state of each comparator line and dispatch interrupts */
|
||||
|
||||
pr = getreg32(STM32L4_EXTI1_PR);
|
||||
for (i = 0; i < STM32L4_COMP_NUM; i++)
|
||||
pr = getreg32(STM32_EXTI1_PR);
|
||||
for (i = 0; i < STM32_COMP_NUM; i++)
|
||||
{
|
||||
ln = g_comp_lines[i];
|
||||
if ((pr & ln) != 0)
|
||||
{
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(ln, STM32L4_EXTI1_PR);
|
||||
putreg32(ln, STM32_EXTI1_PR);
|
||||
if (g_comp_handlers[i].callback != NULL)
|
||||
{
|
||||
xcpt_t callback = g_comp_handlers[i].callback;
|
||||
|
|
@ -152,25 +152,25 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge,
|
|||
|
||||
if (func != NULL)
|
||||
{
|
||||
irq_attach(STM32L4_IRQ_COMP, stm32l4_exti_comp_isr, NULL);
|
||||
up_enable_irq(STM32L4_IRQ_COMP);
|
||||
irq_attach(STM32_IRQ_COMP, stm32l4_exti_comp_isr, NULL);
|
||||
up_enable_irq(STM32_IRQ_COMP);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(STM32L4_IRQ_COMP);
|
||||
up_disable_irq(STM32_IRQ_COMP);
|
||||
}
|
||||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_RTSR, risingedge ?
|
||||
modifyreg32(STM32_EXTI1_RTSR, risingedge ?
|
||||
0 : ln, risingedge ? ln : 0);
|
||||
modifyreg32(STM32L4_EXTI1_FTSR, fallingedge ?
|
||||
modifyreg32(STM32_EXTI1_FTSR, fallingedge ?
|
||||
0 : ln, fallingedge ? ln : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_EMR, event ? 0 : ln, event ? ln : 0);
|
||||
modifyreg32(STM32L4_EXTI1_IMR, func ? 0 : ln, func ? ln : 0);
|
||||
modifyreg32(STM32_EXTI1_EMR, event ? 0 : ln, event ? ln : 0);
|
||||
modifyreg32(STM32_EXTI1_IMR, func ? 0 : ln, func ? ln : 0);
|
||||
|
||||
/* Get the previous IRQ handler and save the new IRQ handler. */
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0001, STM32L4_EXTI1_PR);
|
||||
putreg32(0x0001, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -93,7 +93,7 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0002, STM32L4_EXTI1_PR);
|
||||
putreg32(0x0002, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -114,7 +114,7 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0004, STM32L4_EXTI1_PR);
|
||||
putreg32(0x0004, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -135,7 +135,7 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0008, STM32L4_EXTI1_PR);
|
||||
putreg32(0x0008, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0010, STM32L4_EXTI1_PR);
|
||||
putreg32(0x0010, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -180,7 +180,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg,
|
|||
|
||||
/* Examine the state of each pin in the group */
|
||||
|
||||
pr = getreg32(STM32L4_EXTI1_PR);
|
||||
pr = getreg32(STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -193,7 +193,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg,
|
|||
{
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(mask, STM32L4_EXTI1_PR);
|
||||
putreg32(mask, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -257,7 +257,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
{
|
||||
struct gpio_callback_s *shared_cbs;
|
||||
uint32_t pin = pinset & GPIO_PIN_MASK;
|
||||
uint32_t exti = STM32L4_EXTI1_BIT(pin);
|
||||
uint32_t exti = STM32_EXTI1_BIT(pin);
|
||||
int irq;
|
||||
xcpt_t handler;
|
||||
int nshared;
|
||||
|
|
@ -267,7 +267,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
|
||||
if (pin < 5)
|
||||
{
|
||||
irq = pin + STM32L4_IRQ_EXTI0;
|
||||
irq = pin + STM32_IRQ_EXTI0;
|
||||
nshared = 1;
|
||||
shared_cbs = &g_gpio_handlers[pin];
|
||||
switch (pin)
|
||||
|
|
@ -295,14 +295,14 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
}
|
||||
else if (pin < 10)
|
||||
{
|
||||
irq = STM32L4_IRQ_EXTI95;
|
||||
irq = STM32_IRQ_EXTI95;
|
||||
handler = stm32l4_exti95_isr;
|
||||
shared_cbs = &g_gpio_handlers[5];
|
||||
nshared = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
irq = STM32L4_IRQ_EXTI1510;
|
||||
irq = STM32_IRQ_EXTI1510;
|
||||
handler = stm32l4_exti1510_isr;
|
||||
shared_cbs = &g_gpio_handlers[10];
|
||||
nshared = 6;
|
||||
|
|
@ -353,19 +353,19 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_RTSR,
|
||||
modifyreg32(STM32_EXTI1_RTSR,
|
||||
risingedge ? 0 : exti,
|
||||
risingedge ? exti : 0);
|
||||
modifyreg32(STM32L4_EXTI1_FTSR,
|
||||
modifyreg32(STM32_EXTI1_FTSR,
|
||||
fallingedge ? 0 : exti,
|
||||
fallingedge ? exti : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_EMR,
|
||||
modifyreg32(STM32_EXTI1_EMR,
|
||||
event ? 0 : exti,
|
||||
event ? exti : 0);
|
||||
modifyreg32(STM32L4_EXTI1_IMR,
|
||||
modifyreg32(STM32_EXTI1_IMR,
|
||||
func ? 0 : exti,
|
||||
func ? exti : 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending EXTI interrupt */
|
||||
|
||||
putreg32(EXTI1_PVD_LINE, STM32L4_EXTI1_PR);
|
||||
putreg32(EXTI1_PVD_LINE, STM32_EXTI1_PR);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -116,29 +116,29 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event,
|
|||
|
||||
if (func)
|
||||
{
|
||||
irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr, NULL);
|
||||
up_enable_irq(STM32L4_IRQ_PVD);
|
||||
irq_attach(STM32_IRQ_PVD, stm32l4_exti_pvd_isr, NULL);
|
||||
up_enable_irq(STM32_IRQ_PVD);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(STM32L4_IRQ_PVD);
|
||||
up_disable_irq(STM32_IRQ_PVD);
|
||||
}
|
||||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_RTSR,
|
||||
modifyreg32(STM32_EXTI1_RTSR,
|
||||
risingedge ? 0 : EXTI1_PVD_LINE,
|
||||
risingedge ? EXTI1_PVD_LINE : 0);
|
||||
modifyreg32(STM32L4_EXTI1_FTSR,
|
||||
modifyreg32(STM32_EXTI1_FTSR,
|
||||
fallingedge ? 0 : EXTI1_PVD_LINE,
|
||||
fallingedge ? EXTI1_PVD_LINE : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_EMR,
|
||||
modifyreg32(STM32_EXTI1_EMR,
|
||||
event ? 0 : EXTI1_PVD_LINE,
|
||||
event ? EXTI1_PVD_LINE : 0);
|
||||
modifyreg32(STM32L4_EXTI1_IMR,
|
||||
modifyreg32(STM32_EXTI1_IMR,
|
||||
func ? 0 : EXTI1_PVD_LINE,
|
||||
func ? EXTI1_PVD_LINE : 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending EXTI interrupt */
|
||||
|
||||
putreg32(EXTI1_RTC_WAKEUP, STM32L4_EXTI1_PR);
|
||||
putreg32(EXTI1_RTC_WAKEUP, STM32_EXTI1_PR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -109,29 +109,29 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event,
|
|||
|
||||
if (func)
|
||||
{
|
||||
irq_attach(STM32L4_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL);
|
||||
up_enable_irq(STM32L4_IRQ_RTC_WKUP);
|
||||
irq_attach(STM32_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL);
|
||||
up_enable_irq(STM32_IRQ_RTC_WKUP);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(STM32L4_IRQ_RTC_WKUP);
|
||||
up_disable_irq(STM32_IRQ_RTC_WKUP);
|
||||
}
|
||||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_RTSR,
|
||||
modifyreg32(STM32_EXTI1_RTSR,
|
||||
risingedge ? 0 : EXTI1_RTC_WAKEUP,
|
||||
risingedge ? EXTI1_RTC_WAKEUP : 0);
|
||||
modifyreg32(STM32L4_EXTI1_FTSR,
|
||||
modifyreg32(STM32_EXTI1_FTSR,
|
||||
fallingedge ? 0 : EXTI1_RTC_WAKEUP,
|
||||
fallingedge ? EXTI1_RTC_WAKEUP : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32L4_EXTI1_EMR,
|
||||
modifyreg32(STM32_EXTI1_EMR,
|
||||
event ? 0 : EXTI1_RTC_WAKEUP,
|
||||
event ? EXTI1_RTC_WAKEUP : 0);
|
||||
modifyreg32(STM32L4_EXTI1_IMR,
|
||||
modifyreg32(STM32_EXTI1_IMR,
|
||||
func ? 0 : EXTI1_RTC_WAKEUP,
|
||||
func ? EXTI1_RTC_WAKEUP : 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -67,34 +67,34 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup)
|
|||
* data must be in SRAM1
|
||||
*/
|
||||
|
||||
if ((setup->codestart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE)
|
||||
if ((setup->codestart & STM32_FLASH_MASK) != STM32_FLASH_BASE)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((setup->nvdatastart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE)
|
||||
if ((setup->nvdatastart & STM32_FLASH_MASK) != STM32_FLASH_BASE)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Define address and length registers */
|
||||
|
||||
modifyreg32(STM32L4_FIREWALL_CSSA, FIREWALL_CSSADD_MASK,
|
||||
modifyreg32(STM32_FIREWALL_CSSA, FIREWALL_CSSADD_MASK,
|
||||
setup->codestart);
|
||||
modifyreg32(STM32L4_FIREWALL_CSL, FIREWALL_CSSLENG_MASK,
|
||||
modifyreg32(STM32_FIREWALL_CSL, FIREWALL_CSSLENG_MASK,
|
||||
setup->codelen);
|
||||
modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK,
|
||||
modifyreg32(STM32_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK,
|
||||
setup->nvdatastart);
|
||||
modifyreg32(STM32L4_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK,
|
||||
modifyreg32(STM32_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK,
|
||||
setup->nvdatalen);
|
||||
modifyreg32(STM32L4_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK,
|
||||
modifyreg32(STM32_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK,
|
||||
setup->datastart);
|
||||
modifyreg32(STM32L4_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK,
|
||||
modifyreg32(STM32_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK,
|
||||
setup->datalen);
|
||||
|
||||
/* Define access options */
|
||||
|
||||
reg = getreg32(STM32L4_FIREWALL_CR);
|
||||
reg = getreg32(STM32_FIREWALL_CR);
|
||||
if (setup->datashared)
|
||||
{
|
||||
reg |= FIREWALL_CR_VDS;
|
||||
|
|
@ -105,13 +105,13 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup)
|
|||
reg |= FIREWALL_CR_VDE;
|
||||
}
|
||||
|
||||
putreg32(reg, STM32L4_FIREWALL_CR);
|
||||
putreg32(reg, STM32_FIREWALL_CR);
|
||||
|
||||
/* Enable firewall */
|
||||
|
||||
reg = getreg32(STM32L4_SYSCFG_CFGR1);
|
||||
reg = getreg32(STM32_SYSCFG_CFGR1);
|
||||
reg &= ~SYSCFG_CFGR1_FWDIS;
|
||||
putreg32(reg, STM32L4_SYSCFG_CFGR1);
|
||||
putreg32(reg, STM32_SYSCFG_CFGR1);
|
||||
|
||||
/* Now protected code can only be accessed by jumping to the FW gate */
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@
|
|||
#define OPTBYTES_KEY1 0x08192A3B
|
||||
#define OPTBYTES_KEY2 0x4C5D6E7F
|
||||
|
||||
#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4)
|
||||
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
|
||||
#if FLASH_PAGE_SIZE == 2048
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
#elif FLASH_PAGE_SIZE == 4096
|
||||
# define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */
|
||||
#else
|
||||
# error Unsupported STM32L4_FLASH_PAGESIZE
|
||||
# error Unsupported STM32_FLASH_PAGESIZE
|
||||
#endif
|
||||
#define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT)
|
||||
|
||||
|
|
@ -104,35 +104,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS];
|
|||
|
||||
static void flash_unlock(void)
|
||||
{
|
||||
while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32l4_waste();
|
||||
}
|
||||
|
||||
if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_LOCK)
|
||||
if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK)
|
||||
{
|
||||
/* Unlock sequence */
|
||||
|
||||
putreg32(FLASH_KEY1, STM32L4_FLASH_KEYR);
|
||||
putreg32(FLASH_KEY2, STM32L4_FLASH_KEYR);
|
||||
putreg32(FLASH_KEY1, STM32_FLASH_KEYR);
|
||||
putreg32(FLASH_KEY2, STM32_FLASH_KEYR);
|
||||
}
|
||||
}
|
||||
|
||||
static void flash_lock(void)
|
||||
{
|
||||
modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_LOCK);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
|
||||
}
|
||||
|
||||
static void flash_optbytes_unlock(void)
|
||||
{
|
||||
flash_unlock();
|
||||
|
||||
if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_OPTLOCK)
|
||||
if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK)
|
||||
{
|
||||
/* Unlock Option Bytes sequence */
|
||||
|
||||
putreg32(OPTBYTES_KEY1, STM32L4_FLASH_OPTKEYR);
|
||||
putreg32(OPTBYTES_KEY2, STM32L4_FLASH_OPTKEYR);
|
||||
putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR);
|
||||
putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -149,8 +149,8 @@ static inline void flash_erase(size_t page)
|
|||
{
|
||||
finfo("erase page %u\n", page);
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
|
||||
modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PNB_MASK,
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK,
|
||||
FLASH_CR_PNB(page & 0xff));
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X5) || \
|
||||
|
|
@ -160,41 +160,41 @@ static inline void flash_erase(size_t page)
|
|||
{
|
||||
/* Select bank 1 */
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, FLASH_CR_BKER, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Select bank 2 */
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_BKER);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER);
|
||||
}
|
||||
#endif
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_START);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START);
|
||||
|
||||
while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32l4_waste();
|
||||
}
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
|
||||
static void data_cache_disable(void)
|
||||
{
|
||||
modifyreg32(STM32L4_FLASH_ACR, FLASH_ACR_DCEN, 0);
|
||||
modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0);
|
||||
}
|
||||
|
||||
static void data_cache_enable(void)
|
||||
{
|
||||
/* Reset data cache */
|
||||
|
||||
modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCRST);
|
||||
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST);
|
||||
|
||||
/* Enable data cache */
|
||||
|
||||
modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCEN);
|
||||
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN);
|
||||
}
|
||||
#endif /* defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
|
||||
|
||||
|
|
@ -274,20 +274,20 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
|
|||
|
||||
/* Modify Option Bytes in register. */
|
||||
|
||||
regval = getreg32(STM32L4_FLASH_OPTR);
|
||||
regval = getreg32(STM32_FLASH_OPTR);
|
||||
|
||||
finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval);
|
||||
|
||||
regval = (regval & ~clrbits) | setbits;
|
||||
putreg32(regval, STM32L4_FLASH_OPTR);
|
||||
putreg32(regval, STM32_FLASH_OPTR);
|
||||
|
||||
finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval);
|
||||
|
||||
/* Start Option Bytes programming and wait for completion. */
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_OPTSTRT);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT);
|
||||
|
||||
while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32l4_waste();
|
||||
}
|
||||
|
|
@ -300,42 +300,42 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
|
|||
|
||||
size_t up_progmem_pagesize(size_t page)
|
||||
{
|
||||
return STM32L4_FLASH_PAGESIZE;
|
||||
return STM32_FLASH_PAGESIZE;
|
||||
}
|
||||
|
||||
size_t up_progmem_erasesize(size_t block)
|
||||
{
|
||||
return STM32L4_FLASH_PAGESIZE;
|
||||
return STM32_FLASH_PAGESIZE;
|
||||
}
|
||||
|
||||
ssize_t up_progmem_getpage(size_t addr)
|
||||
{
|
||||
if (addr >= STM32L4_FLASH_BASE)
|
||||
if (addr >= STM32_FLASH_BASE)
|
||||
{
|
||||
addr -= STM32L4_FLASH_BASE;
|
||||
addr -= STM32_FLASH_BASE;
|
||||
}
|
||||
|
||||
if (addr >= STM32L4_FLASH_SIZE)
|
||||
if (addr >= STM32_FLASH_SIZE)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return addr / STM32L4_FLASH_PAGESIZE;
|
||||
return addr / STM32_FLASH_PAGESIZE;
|
||||
}
|
||||
|
||||
size_t up_progmem_getaddress(size_t page)
|
||||
{
|
||||
if (page >= STM32L4_FLASH_NPAGES)
|
||||
if (page >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
return SIZE_MAX;
|
||||
}
|
||||
|
||||
return page * STM32L4_FLASH_PAGESIZE + STM32L4_FLASH_BASE;
|
||||
return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE;
|
||||
}
|
||||
|
||||
size_t up_progmem_neraseblocks(void)
|
||||
{
|
||||
return STM32L4_FLASH_NPAGES;
|
||||
return STM32_FLASH_NPAGES;
|
||||
}
|
||||
|
||||
bool up_progmem_isuniform(void)
|
||||
|
|
@ -347,7 +347,7 @@ ssize_t up_progmem_eraseblock(size_t block)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (block >= STM32L4_FLASH_NPAGES)
|
||||
if (block >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
|
@ -385,7 +385,7 @@ ssize_t up_progmem_ispageerased(size_t page)
|
|||
size_t count;
|
||||
size_t bwritten = 0;
|
||||
|
||||
if (page >= STM32L4_FLASH_NPAGES)
|
||||
if (page >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
|
@ -419,12 +419,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
/* Check for valid address range. */
|
||||
|
||||
offset = addr;
|
||||
if (addr >= STM32L4_FLASH_BASE)
|
||||
if (addr >= STM32_FLASH_BASE)
|
||||
{
|
||||
offset -= STM32L4_FLASH_BASE;
|
||||
offset -= STM32_FLASH_BASE;
|
||||
}
|
||||
|
||||
if (offset + buflen > STM32L4_FLASH_SIZE)
|
||||
if (offset + buflen > STM32_FLASH_SIZE)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
|
@ -498,7 +498,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
data_cache_disable();
|
||||
#endif
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PG);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
|
||||
set_pg_bit = true;
|
||||
|
||||
for (i = 0; i < FLASH_PAGE_WORDS; i += 2)
|
||||
|
|
@ -506,14 +506,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
*dest++ = *src++;
|
||||
*dest++ = *src++;
|
||||
|
||||
while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32l4_waste();
|
||||
}
|
||||
|
||||
/* Verify */
|
||||
|
||||
if (getreg32(STM32L4_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
|
||||
if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
|
||||
{
|
||||
ret = -EROFS;
|
||||
goto out;
|
||||
|
|
@ -527,7 +527,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
}
|
||||
}
|
||||
|
||||
modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
|
||||
set_pg_bit = false;
|
||||
|
||||
#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
|
||||
|
|
@ -547,7 +547,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
out:
|
||||
if (set_pg_bit)
|
||||
{
|
||||
modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
|
||||
#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
|
||||
data_cache_enable();
|
||||
#endif
|
||||
|
|
@ -560,9 +560,9 @@ out:
|
|||
if (ret != OK)
|
||||
{
|
||||
ferr("flash write error: %d, status: 0x%" PRIx32 "\n",
|
||||
ret, getreg32(STM32L4_FLASH_SR));
|
||||
ret, getreg32(STM32_FLASH_SR));
|
||||
|
||||
modifyreg32(STM32L4_FLASH_SR, 0, FLASH_SR_ALLERRS);
|
||||
modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS);
|
||||
}
|
||||
|
||||
flash_lock();
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg)
|
|||
DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX);
|
||||
freerun->overflow++;
|
||||
|
||||
STM32L4_TIM_ACKINT(freerun->tch, 0);
|
||||
STM32_TIM_ACKINT(freerun->tch, 0);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -117,7 +117,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun,
|
|||
return -EBUSY;
|
||||
}
|
||||
|
||||
STM32L4_TIM_SETCLOCK(freerun->tch, frequency);
|
||||
STM32_TIM_SETCLOCK(freerun->tch, frequency);
|
||||
|
||||
/* Initialize the remaining fields in the state structure and return
|
||||
* success.
|
||||
|
|
@ -128,17 +128,17 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun,
|
|||
|
||||
/* Set up to receive the callback when the counter overflow occurs */
|
||||
|
||||
STM32L4_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0);
|
||||
STM32_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0);
|
||||
|
||||
/* Set timer period */
|
||||
|
||||
STM32L4_TIM_SETPERIOD(freerun->tch, UINT32_MAX);
|
||||
STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX);
|
||||
|
||||
/* Start the counter */
|
||||
|
||||
STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_UP);
|
||||
STM32L4_TIM_ACKINT(freerun->tch, 0);
|
||||
STM32L4_TIM_ENABLEINT(freerun->tch, 0);
|
||||
STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP);
|
||||
STM32_TIM_ACKINT(freerun->tch, 0);
|
||||
STM32_TIM_ENABLEINT(freerun->tch, 0);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -184,9 +184,9 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun,
|
|||
flags = enter_critical_section();
|
||||
|
||||
overflow = freerun->overflow;
|
||||
counter = STM32L4_TIM_GETCOUNTER(freerun->tch);
|
||||
pending = STM32L4_TIM_CHECKINT(freerun->tch, 0);
|
||||
verify = STM32L4_TIM_GETCOUNTER(freerun->tch);
|
||||
counter = STM32_TIM_GETCOUNTER(freerun->tch);
|
||||
pending = STM32_TIM_CHECKINT(freerun->tch, 0);
|
||||
verify = STM32_TIM_GETCOUNTER(freerun->tch);
|
||||
|
||||
/* If an interrupt was pending before we re-enabled interrupts,
|
||||
* then the overflow needs to be incremented.
|
||||
|
|
@ -194,7 +194,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun,
|
|||
|
||||
if (pending)
|
||||
{
|
||||
STM32L4_TIM_ACKINT(freerun->tch, 0);
|
||||
STM32_TIM_ACKINT(freerun->tch, 0);
|
||||
|
||||
/* Increment the overflow count and use the value of the
|
||||
* guaranteed to be AFTER the overflow occurred.
|
||||
|
|
@ -260,9 +260,9 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun)
|
|||
|
||||
/* Now we can disable the timer interrupt and disable the timer. */
|
||||
|
||||
STM32L4_TIM_DISABLEINT(freerun->tch, 0);
|
||||
STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_DISABLED);
|
||||
STM32L4_TIM_SETISR(freerun->tch, NULL, NULL, 0);
|
||||
STM32_TIM_DISABLEINT(freerun->tch, 0);
|
||||
STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED);
|
||||
STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0);
|
||||
|
||||
/* Free the timer */
|
||||
|
||||
|
|
|
|||
|
|
@ -54,34 +54,34 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED;
|
|||
|
||||
/* Base addresses for each GPIO block */
|
||||
|
||||
const uint32_t g_gpiobase[STM32L4_NPORTS] =
|
||||
const uint32_t g_gpiobase[STM32_NPORTS] =
|
||||
{
|
||||
#if STM32L4_NPORTS > 0
|
||||
STM32L4_GPIOA_BASE,
|
||||
#if STM32_NPORTS > 0
|
||||
STM32_GPIOA_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 1
|
||||
STM32L4_GPIOB_BASE,
|
||||
#if STM32_NPORTS > 1
|
||||
STM32_GPIOB_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 2
|
||||
STM32L4_GPIOC_BASE,
|
||||
#if STM32_NPORTS > 2
|
||||
STM32_GPIOC_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 3
|
||||
STM32L4_GPIOD_BASE,
|
||||
#if STM32_NPORTS > 3
|
||||
STM32_GPIOD_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 4
|
||||
STM32L4_GPIOE_BASE,
|
||||
#if STM32_NPORTS > 4
|
||||
STM32_GPIOE_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 5
|
||||
STM32L4_GPIOF_BASE,
|
||||
#if STM32_NPORTS > 5
|
||||
STM32_GPIOF_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 6
|
||||
STM32L4_GPIOG_BASE,
|
||||
#if STM32_NPORTS > 6
|
||||
STM32_GPIOG_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 7
|
||||
STM32L4_GPIOH_BASE,
|
||||
#if STM32_NPORTS > 7
|
||||
STM32_GPIOH_BASE,
|
||||
#endif
|
||||
#if STM32L4_NPORTS > 8
|
||||
STM32L4_GPIOI_BASE,
|
||||
#if STM32_NPORTS > 8
|
||||
STM32_GPIOI_BASE,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -144,7 +144,7 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
/* Verify that this hardware supports the select GPIO port */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port >= STM32L4_NPORTS)
|
||||
if (port >= STM32_NPORTS)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -202,10 +202,10 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
|
||||
/* Now apply the configuration to the mode register */
|
||||
|
||||
regval = getreg32(base + STM32L4_GPIO_MODER_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
|
||||
regval &= ~GPIO_MODER_MASK(pin);
|
||||
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
|
||||
putreg32(regval, base + STM32L4_GPIO_MODER_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
|
||||
|
||||
/* Set up the pull-up/pull-down configuration (all but analog pins) */
|
||||
|
||||
|
|
@ -228,10 +228,10 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
}
|
||||
}
|
||||
|
||||
regval = getreg32(base + STM32L4_GPIO_PUPDR_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
|
||||
regval &= ~GPIO_PUPDR_MASK(pin);
|
||||
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
|
||||
putreg32(regval, base + STM32L4_GPIO_PUPDR_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
|
||||
|
||||
/* Set the alternate function (Only alternate function pins) */
|
||||
|
||||
|
|
@ -246,12 +246,12 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
|
||||
if (pin < 8)
|
||||
{
|
||||
regoffset = STM32L4_GPIO_AFRL_OFFSET;
|
||||
regoffset = STM32_GPIO_AFRL_OFFSET;
|
||||
pos = pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regoffset = STM32L4_GPIO_AFRH_OFFSET;
|
||||
regoffset = STM32_GPIO_AFRH_OFFSET;
|
||||
pos = pin - 8;
|
||||
}
|
||||
|
||||
|
|
@ -289,14 +289,14 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
setting = 0;
|
||||
}
|
||||
|
||||
regval = getreg32(base + STM32L4_GPIO_OSPEED_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
|
||||
regval &= ~GPIO_OSPEED_MASK(pin);
|
||||
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
|
||||
putreg32(regval, base + STM32L4_GPIO_OSPEED_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
|
||||
|
||||
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
|
||||
|
||||
regval = getreg32(base + STM32L4_GPIO_OTYPER_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
|
||||
setting = GPIO_OTYPER_OD(pin);
|
||||
|
||||
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
|
||||
|
|
@ -309,7 +309,7 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
regval &= ~setting;
|
||||
}
|
||||
|
||||
putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
|
||||
|
||||
/* Otherwise, it is an input pin. Should it configured as an
|
||||
* EXTI interrupt?
|
||||
|
|
@ -331,7 +331,7 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
|
||||
/* Set the bits in the SYSCFG EXTICR register */
|
||||
|
||||
regaddr = STM32L4_SYSCFG_EXTICR(pin);
|
||||
regaddr = STM32_SYSCFG_EXTICR(pin);
|
||||
regval = getreg32(regaddr);
|
||||
shift = SYSCFG_EXTICR_EXTI_SHIFT(pin);
|
||||
regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
|
||||
|
|
@ -351,11 +351,11 @@ int stm32l4_configgpio(uint32_t cfgset)
|
|||
|
||||
if (pinmode == GPIO_MODER_ANALOG)
|
||||
{
|
||||
modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin));
|
||||
modifyreg32(base + STM32_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin));
|
||||
}
|
||||
else
|
||||
{
|
||||
modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0);
|
||||
modifyreg32(base + STM32_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -412,7 +412,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value)
|
|||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < STM32L4_NPORTS)
|
||||
if (port < STM32_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
|
|
@ -433,7 +433,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value)
|
|||
bit = GPIO_BSRR_RESET(pin);
|
||||
}
|
||||
|
||||
putreg32(bit, base + STM32L4_GPIO_BSRR_OFFSET);
|
||||
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -452,7 +452,7 @@ bool stm32l4_gpioread(uint32_t pinset)
|
|||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < STM32L4_NPORTS)
|
||||
if (port < STM32_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
|
|
@ -461,7 +461,7 @@ bool stm32l4_gpioread(uint32_t pinset)
|
|||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(base + STM32L4_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
|
||||
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ extern "C"
|
|||
|
||||
/* Base addresses for each GPIO block */
|
||||
|
||||
EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS];
|
||||
EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
|
|
|
|||
|
|
@ -80,13 +80,13 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc)
|
|||
* enabled.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CRRCR);
|
||||
regval = getreg32(STM32_RCC_CRRCR);
|
||||
regval |= RCC_CRRCR_HSI48ON;
|
||||
putreg32(regval, STM32L4_RCC_CRRCR);
|
||||
putreg32(regval, STM32_RCC_CRRCR);
|
||||
|
||||
/* Wait for the HSI48 clock to stabilize */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0);
|
||||
while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0);
|
||||
|
||||
/* Return if no synchronization */
|
||||
|
||||
|
|
@ -100,7 +100,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc)
|
|||
* clock or the USB SOF signal.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_CRS_CFGR);
|
||||
regval = getreg32(STM32_CRS_CFGR);
|
||||
regval &= ~CRS_CFGR_SYNCSRC_MASK;
|
||||
|
||||
switch (syncsrc)
|
||||
|
|
@ -119,7 +119,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc)
|
|||
break;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32L4_CRS_CFGR);
|
||||
putreg32(regval, STM32_CRS_CFGR);
|
||||
|
||||
/* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic
|
||||
* hardware adjustment of TRIM bits according to the measured frequency
|
||||
|
|
@ -127,9 +127,9 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc)
|
|||
* frequency error counter and SYNC events.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_CRS_CR);
|
||||
regval = getreg32(STM32_CRS_CR);
|
||||
regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
|
||||
putreg32(regval, STM32L4_CRS_CR);
|
||||
putreg32(regval, STM32_CRS_CR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -152,17 +152,17 @@ void stm32l4_disable_hsi48(void)
|
|||
|
||||
/* Disable the HSI48 clock */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CRRCR);
|
||||
regval = getreg32(STM32_RCC_CRRCR);
|
||||
regval &= ~RCC_CRRCR_HSI48ON;
|
||||
putreg32(regval, STM32L4_RCC_CRRCR);
|
||||
putreg32(regval, STM32_RCC_CRRCR);
|
||||
|
||||
/* Set other registers to the default settings. */
|
||||
|
||||
regval = getreg32(STM32L4_CRS_CFGR);
|
||||
regval = getreg32(STM32_CRS_CFGR);
|
||||
regval &= ~CRS_CFGR_SYNCSRC_MASK;
|
||||
putreg32(regval, STM32L4_CRS_CFGR);
|
||||
putreg32(regval, STM32_CRS_CFGR);
|
||||
|
||||
regval = getreg32(STM32L4_CRS_CR);
|
||||
regval = getreg32(STM32_CRS_CR);
|
||||
regval &= ~CRS_CR_AUTOTRIMEN;
|
||||
putreg32(regval, STM32L4_CRS_CR);
|
||||
putreg32(regval, STM32_CRS_CR);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -520,14 +520,14 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain,
|
|||
#ifdef CONFIG_STM32L4_I2C1
|
||||
static const struct stm32l4_i2c_config_s stm32l4_i2c1_config =
|
||||
{
|
||||
.base = STM32L4_I2C1_BASE,
|
||||
.base = STM32_I2C1_BASE,
|
||||
.clk_bit = RCC_APB1ENR1_I2C1EN,
|
||||
.reset_bit = RCC_APB1RSTR1_I2C1RST,
|
||||
.scl_pin = GPIO_I2C1_SCL,
|
||||
.sda_pin = GPIO_I2C1_SDA,
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
.ev_irq = STM32L4_IRQ_I2C1EV,
|
||||
.er_irq = STM32L4_IRQ_I2C1ER
|
||||
.ev_irq = STM32_IRQ_I2C1EV,
|
||||
.er_irq = STM32_IRQ_I2C1ER
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -556,14 +556,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv =
|
|||
#ifdef CONFIG_STM32L4_I2C2
|
||||
static const struct stm32l4_i2c_config_s stm32l4_i2c2_config =
|
||||
{
|
||||
.base = STM32L4_I2C2_BASE,
|
||||
.base = STM32_I2C2_BASE,
|
||||
.clk_bit = RCC_APB1ENR1_I2C2EN,
|
||||
.reset_bit = RCC_APB1RSTR1_I2C2RST,
|
||||
.scl_pin = GPIO_I2C2_SCL,
|
||||
.sda_pin = GPIO_I2C2_SDA,
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
.ev_irq = STM32L4_IRQ_I2C2EV,
|
||||
.er_irq = STM32L4_IRQ_I2C2ER
|
||||
.ev_irq = STM32_IRQ_I2C2EV,
|
||||
.er_irq = STM32_IRQ_I2C2ER
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -592,14 +592,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv =
|
|||
#ifdef CONFIG_STM32L4_I2C3
|
||||
static const struct stm32l4_i2c_config_s stm32l4_i2c3_config =
|
||||
{
|
||||
.base = STM32L4_I2C3_BASE,
|
||||
.base = STM32_I2C3_BASE,
|
||||
.clk_bit = RCC_APB1ENR1_I2C3EN,
|
||||
.reset_bit = RCC_APB1RSTR1_I2C3RST,
|
||||
.scl_pin = GPIO_I2C3_SCL,
|
||||
.sda_pin = GPIO_I2C3_SDA,
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
.ev_irq = STM32L4_IRQ_I2C3EV,
|
||||
.er_irq = STM32L4_IRQ_I2C3ER
|
||||
.ev_irq = STM32_IRQ_I2C3EV,
|
||||
.er_irq = STM32_IRQ_I2C3ER
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -628,14 +628,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv =
|
|||
#ifdef CONFIG_STM32L4_I2C4
|
||||
static const struct stm32l4_i2c_config_s stm32l4_i2c4_config =
|
||||
{
|
||||
.base = STM32L4_I2C4_BASE,
|
||||
.base = STM32_I2C4_BASE,
|
||||
.clk_bit = RCC_APB1ENR2_I2C4EN,
|
||||
.reset_bit = RCC_APB1RSTR2_I2C4RST,
|
||||
.scl_pin = GPIO_I2C4_SCL,
|
||||
.sda_pin = GPIO_I2C4_SDA,
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
.ev_irq = STM32L4_IRQ_I2C4EV,
|
||||
.er_irq = STM32L4_IRQ_I2C4ER
|
||||
.ev_irq = STM32_IRQ_I2C4EV,
|
||||
.er_irq = STM32_IRQ_I2C4ER
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -791,7 +791,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs)
|
|||
static inline
|
||||
void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
|
||||
(I2C_CR1_TXRX | I2C_CR1_NACKIE));
|
||||
}
|
||||
#endif
|
||||
|
|
@ -823,7 +823,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
|
|||
* error-related, are enabled here.
|
||||
*/
|
||||
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
|
||||
(I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
|
||||
|
||||
/* Signal the interrupt handler that we are waiting */
|
||||
|
|
@ -861,7 +861,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Disable I2C interrupts */
|
||||
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
|
||||
|
||||
leave_critical_section(flags);
|
||||
return ret;
|
||||
|
|
@ -930,7 +930,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv)
|
|||
static inline void
|
||||
stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
|
||||
((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT));
|
||||
}
|
||||
|
||||
|
|
@ -945,7 +945,7 @@ static inline void
|
|||
stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv,
|
||||
uint8_t n_bytes)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
|
||||
(n_bytes << I2C_CR2_NBYTES_SHIFT));
|
||||
}
|
||||
|
||||
|
|
@ -959,7 +959,7 @@ stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv,
|
|||
static inline void
|
||||
stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -972,7 +972,7 @@ stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv)
|
|||
static inline void
|
||||
stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
|
||||
0, I2C_CR2_RD_WRN);
|
||||
}
|
||||
|
||||
|
|
@ -986,7 +986,7 @@ stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv)
|
|||
static inline void
|
||||
stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
|
||||
0, I2C_CR2_RELOAD);
|
||||
}
|
||||
|
||||
|
|
@ -1000,7 +1000,7 @@ stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv)
|
|||
static inline void
|
||||
stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
|
||||
I2C_CR2_RELOAD, 0);
|
||||
}
|
||||
|
||||
|
|
@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Check for STOP condition */
|
||||
|
||||
cr = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET);
|
||||
cr = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
|
||||
if ((cr & I2C_CR2_STOP) == 0)
|
||||
{
|
||||
return;
|
||||
|
|
@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Check for timeout error */
|
||||
|
||||
sr = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
sr = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
|
||||
if ((sr & I2C_INT_TIMEOUT) != 0)
|
||||
{
|
||||
return;
|
||||
|
|
@ -1253,20 +1253,20 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv,
|
|||
/* I2C peripheral must be disabled to update clocking configuration */
|
||||
|
||||
pe = (stm32l4_i2c_getreg32(priv,
|
||||
STM32L4_I2C_CR1_OFFSET) & I2C_CR1_PE);
|
||||
STM32_I2C_CR1_OFFSET) & I2C_CR1_PE);
|
||||
if (pe)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET,
|
||||
I2C_CR1_PE, 0);
|
||||
}
|
||||
|
||||
#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000)
|
||||
#if defined(STM32_I2C_USE_HSI16) || (STM32_PCLK1_FREQUENCY == 16000000)
|
||||
i2cclk_mhz = 16;
|
||||
#elif STM32L4_PCLK1_FREQUENCY == 48000000
|
||||
#elif STM32_PCLK1_FREQUENCY == 48000000
|
||||
i2cclk_mhz = 48;
|
||||
#elif STM32L4_PCLK1_FREQUENCY == 80000000
|
||||
#elif STM32_PCLK1_FREQUENCY == 80000000
|
||||
i2cclk_mhz = 80;
|
||||
#elif STM32L4_PCLK1_FREQUENCY == 120000000
|
||||
#elif STM32_PCLK1_FREQUENCY == 120000000
|
||||
i2cclk_mhz = 120;
|
||||
#else
|
||||
# warning STM32_I2C_INIT: Peripheral clock is PCLK and the speed/timing calculations need to be redone.
|
||||
|
|
@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv,
|
|||
(scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
|
||||
(scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
|
||||
|
||||
stm32l4_i2c_putreg32(priv, STM32L4_I2C_TIMINGR_OFFSET, timingr);
|
||||
stm32l4_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
|
||||
|
||||
if (pe)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET,
|
||||
0, I2C_CR1_PE);
|
||||
}
|
||||
|
||||
|
|
@ -1605,7 +1605,7 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv)
|
|||
i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
|
||||
priv->dcnt, priv->msgc, priv->flags);
|
||||
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, 0, I2C_CR2_START);
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1626,7 +1626,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv)
|
|||
i2cinfo("Sending STOP\n");
|
||||
stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0);
|
||||
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
|
||||
0, I2C_CR2_STOP);
|
||||
}
|
||||
|
||||
|
|
@ -1641,7 +1641,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv)
|
|||
static inline
|
||||
uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
return getreg32(priv->config->base + STM32L4_I2C_ISR_OFFSET);
|
||||
return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1655,7 +1655,7 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv)
|
|||
static inline
|
||||
void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv)
|
||||
{
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET,
|
||||
0, I2C_ICR_CLEARMASK);
|
||||
}
|
||||
|
||||
|
|
@ -1684,7 +1684,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Get state of the I2C controller */
|
||||
|
||||
status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
|
||||
|
||||
i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status);
|
||||
|
||||
|
|
@ -1853,7 +1853,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Transmit current byte */
|
||||
|
||||
stm32l4_i2c_putreg(priv, STM32L4_I2C_TXDR_OFFSET, *priv->ptr);
|
||||
stm32l4_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr);
|
||||
|
||||
/* Advance to next byte */
|
||||
|
||||
|
|
@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
#endif
|
||||
/* Receive a byte */
|
||||
|
||||
*priv->ptr = stm32l4_i2c_getreg(priv, STM32L4_I2C_RXDR_OFFSET);
|
||||
*priv->ptr = stm32l4_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET);
|
||||
|
||||
i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr);
|
||||
|
||||
|
|
@ -1949,7 +1949,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
/* Unsupported state */
|
||||
|
||||
stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
|
||||
status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
|
||||
i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, "
|
||||
"status 0x%08" PRIx32 "\n",
|
||||
priv->dcnt, status);
|
||||
|
|
@ -2193,7 +2193,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
else if (priv->dcnt == -1 && priv->msgc == 0)
|
||||
{
|
||||
status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
|
||||
i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n",
|
||||
status);
|
||||
stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
|
||||
|
|
@ -2216,7 +2216,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
#else
|
||||
/* Read rest of the state */
|
||||
|
||||
status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
|
||||
|
||||
i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n",
|
||||
status);
|
||||
|
|
@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
priv->intstate = INTSTATE_DONE;
|
||||
#else
|
||||
|
||||
status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
|
||||
|
||||
/* Update private state to capture NACK which is used in combination
|
||||
* with the astart flag to report the type of NACK received (address
|
||||
|
|
@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Clear all interrupts */
|
||||
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET,
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET,
|
||||
0, I2C_ICR_CLEARMASK);
|
||||
|
||||
/* If a thread is waiting then inform it transfer is complete */
|
||||
|
|
@ -2281,7 +2281,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv)
|
|||
#endif
|
||||
}
|
||||
|
||||
status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET);
|
||||
status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
|
||||
i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status);
|
||||
|
||||
return OK;
|
||||
|
|
@ -2320,18 +2320,18 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv)
|
|||
/* Enable power and reset the peripheral */
|
||||
|
||||
#ifdef CONFIG_STM32L4_I2C4
|
||||
if (priv->config->base == STM32L4_I2C4_BASE)
|
||||
if (priv->config->base == STM32_I2C4_BASE)
|
||||
{
|
||||
modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit);
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit);
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0);
|
||||
modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit);
|
||||
modifyreg32(STM32_RCC_APB1RSTR2, 0, priv->config->reset_bit);
|
||||
modifyreg32(STM32_RCC_APB1RSTR2, priv->config->reset_bit, 0);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit);
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit);
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit);
|
||||
modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit);
|
||||
modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0);
|
||||
}
|
||||
|
||||
/* Configure pins */
|
||||
|
|
@ -2368,7 +2368,7 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv)
|
|||
|
||||
/* Enable I2C peripheral */
|
||||
|
||||
stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
|
||||
stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -2385,7 +2385,7 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv)
|
|||
{
|
||||
/* Disable I2C */
|
||||
|
||||
stm32l4_i2c_putreg32(priv, STM32L4_I2C_CR1_OFFSET, 0);
|
||||
stm32l4_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0);
|
||||
|
||||
/* Unconfigure GPIO pins */
|
||||
|
||||
|
|
@ -2405,14 +2405,14 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv)
|
|||
/* Disable clocking */
|
||||
|
||||
#ifdef CONFIG_STM32L4_I2C4
|
||||
if (priv->config->base == STM32L4_I2C4_BASE)
|
||||
if (priv->config->base == STM32_I2C4_BASE)
|
||||
{
|
||||
modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0);
|
||||
modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0);
|
||||
}
|
||||
|
||||
return OK;
|
||||
|
|
@ -2493,8 +2493,8 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev,
|
|||
|
||||
waitrc = stm32l4_i2c_sem_waitdone(priv);
|
||||
|
||||
cr1 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET);
|
||||
cr2 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET);
|
||||
cr1 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET);
|
||||
cr2 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
|
||||
#if !defined(CONFIG_DEBUG_I2C)
|
||||
UNUSED(cr1);
|
||||
UNUSED(cr2);
|
||||
|
|
|
|||
|
|
@ -204,13 +204,13 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
|||
{
|
||||
int n;
|
||||
|
||||
DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS);
|
||||
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= STM32L4_IRQ_FIRST)
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
n = irq - STM32L4_IRQ_FIRST;
|
||||
n = irq - STM32_IRQ_FIRST;
|
||||
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
|
||||
*bit = (uint32_t)1 << (n & 0x1f);
|
||||
}
|
||||
|
|
@ -220,19 +220,19 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
|||
else
|
||||
{
|
||||
*regaddr = NVIC_SYSHCON;
|
||||
if (irq == STM32L4_IRQ_MEMFAULT)
|
||||
if (irq == STM32_IRQ_MEMFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_MEMFAULTENA;
|
||||
}
|
||||
else if (irq == STM32L4_IRQ_BUSFAULT)
|
||||
else if (irq == STM32_IRQ_BUSFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_BUSFAULTENA;
|
||||
}
|
||||
else if (irq == STM32L4_IRQ_USAGEFAULT)
|
||||
else if (irq == STM32_IRQ_USAGEFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_USGFAULTENA;
|
||||
}
|
||||
else if (irq == STM32L4_IRQ_SYSTICK)
|
||||
else if (irq == STM32_IRQ_SYSTICK)
|
||||
{
|
||||
*regaddr = NVIC_SYSTICK_CTRL;
|
||||
*bit = NVIC_SYSTICK_CTRL_ENABLE;
|
||||
|
|
@ -262,7 +262,7 @@ void up_irqinitialize(void)
|
|||
|
||||
/* Disable all interrupts */
|
||||
|
||||
for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32)
|
||||
for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32)
|
||||
{
|
||||
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
|
||||
}
|
||||
|
|
@ -316,13 +316,13 @@ void up_irqinitialize(void)
|
|||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(STM32L4_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(STM32L4_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(STM32L4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
|
||||
stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
|
||||
|
|
@ -332,23 +332,23 @@ void up_irqinitialize(void)
|
|||
*/
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(STM32L4_IRQ_MEMFAULT);
|
||||
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(STM32_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi, NULL);
|
||||
irq_attach(STM32_IRQ_NMI, stm32l4_nmi, NULL);
|
||||
#ifndef CONFIG_ARM_MPU
|
||||
irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
#endif
|
||||
irq_attach(STM32L4_IRQ_BUSFAULT, arm_busfault, NULL);
|
||||
irq_attach(STM32L4_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
||||
irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv, NULL);
|
||||
irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL);
|
||||
irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
||||
irq_attach(STM32_IRQ_PENDSV, stm32l4_pendsv, NULL);
|
||||
arm_enable_dbgmonitor();
|
||||
irq_attach(STM32L4_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
|
||||
irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved, NULL);
|
||||
irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
|
||||
irq_attach(STM32_IRQ_RESERVED, stm32l4_reserved, NULL);
|
||||
#endif
|
||||
|
||||
stm32l4_dumpnvic("initial", NR_IRQS);
|
||||
|
|
@ -384,7 +384,7 @@ void up_disable_irq(int irq)
|
|||
* clear the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= STM32L4_IRQ_FIRST)
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
|
|
@ -419,7 +419,7 @@ void up_enable_irq(int irq)
|
|||
* set the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= STM32L4_IRQ_FIRST)
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
|
|
@ -462,10 +462,10 @@ int up_prioritize_irq(int irq, int priority)
|
|||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= STM32L4_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
if (irq < STM32L4_IRQ_FIRST)
|
||||
if (irq < STM32_IRQ_FIRST)
|
||||
{
|
||||
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
||||
* registers (0-3 are invalid)
|
||||
|
|
@ -478,7 +478,7 @@ int up_prioritize_irq(int irq, int priority)
|
|||
{
|
||||
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
||||
|
||||
irq -= STM32L4_IRQ_FIRST;
|
||||
irq -= STM32_IRQ_FIRST;
|
||||
regaddr = NVIC_IRQ_PRIORITY(irq);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@
|
|||
* 1000 * 4095 / Fmin = 34,944 MSec
|
||||
*/
|
||||
|
||||
#define IWDG_FMIN (STM32L4_LSI_FREQUENCY / 256)
|
||||
#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256)
|
||||
#define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN)
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
|
@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv)
|
|||
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers */
|
||||
|
||||
stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32L4_IWDG_KR);
|
||||
stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR);
|
||||
|
||||
/* Wait for the PVU and RVU bits to be reset by hardware. These bits
|
||||
* were set the last time that the PR register was written and may not
|
||||
* yet be cleared.
|
||||
*/
|
||||
|
||||
while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU));
|
||||
while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU));
|
||||
|
||||
/* Set the prescaler */
|
||||
|
||||
stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR);
|
||||
stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR);
|
||||
|
||||
/* Set the reload value */
|
||||
|
||||
stm32l4_putreg((uint16_t)priv->reload, STM32L4_IWDG_RLR);
|
||||
stm32l4_putreg((uint16_t)priv->reload, STM32_IWDG_RLR);
|
||||
|
||||
/* Reload the counter (and disable write access) */
|
||||
|
||||
stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR);
|
||||
stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
|
||||
|
||||
/* Wait for the PVU and RVU bits to be reset by hardware. This is
|
||||
* to wait for the change to take effect before exiting critical section,
|
||||
|
|
@ -289,7 +289,7 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv)
|
|||
|
||||
if (priv->started)
|
||||
{
|
||||
while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU));
|
||||
while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU));
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
|
@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower)
|
|||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
stm32l4_putreg(IWDG_KR_KEY_START, STM32L4_IWDG_KR);
|
||||
stm32l4_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR);
|
||||
priv->lastreset = clock_systime_ticks();
|
||||
priv->started = true;
|
||||
leave_critical_section(flags);
|
||||
|
|
@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower)
|
|||
/* Reload the IWDG timer */
|
||||
|
||||
flags = enter_critical_section();
|
||||
stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR);
|
||||
stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
|
||||
priv->lastreset = clock_systime_ticks();
|
||||
leave_critical_section(flags);
|
||||
|
||||
|
|
@ -629,7 +629,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq)
|
|||
*/
|
||||
|
||||
stm32l4_rcc_enablelsi();
|
||||
wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32L4_RCC_CSR));
|
||||
wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR));
|
||||
|
||||
/* Select an arbitrary initial timeout value. But don't start the watchdog
|
||||
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
|
||||
|
|
|
|||
|
|
@ -46,127 +46,127 @@
|
|||
|
||||
#ifdef HAVE_CONSOLE
|
||||
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
|
||||
# define STM32L4_CONSOLE_BASE STM32L4_LPUART1_BASE
|
||||
# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY
|
||||
# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR2
|
||||
# define STM32L4_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
|
||||
# define STM32L4_CONSOLE_BAUD CONFIG_LPUART1_BAUD
|
||||
# define STM32L4_CONSOLE_BITS CONFIG_LPUART1_BITS
|
||||
# define STM32L4_CONSOLE_PARITY CONFIG_LPUART1_PARITY
|
||||
# define STM32L4_CONSOLE_2STOP CONFIG_LPUART1_2STOP
|
||||
# define STM32L4_CONSOLE_TX GPIO_LPUART1_TX
|
||||
# define STM32L4_CONSOLE_RX GPIO_LPUART1_RX
|
||||
# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_LPUART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_LPUART1_RX
|
||||
# ifdef CONFIG_LPUART1_RS485
|
||||
# define STM32L4_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
|
||||
# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define STM32L4_CONSOLE_BASE STM32L4_USART1_BASE
|
||||
# define STM32L4_APBCLOCK STM32L4_PCLK2_FREQUENCY
|
||||
# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB2ENR
|
||||
# define STM32L4_CONSOLE_APBEN RCC_APB2ENR_USART1EN
|
||||
# define STM32L4_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32L4_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32L4_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32L4_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# define STM32L4_CONSOLE_TX GPIO_USART1_TX
|
||||
# define STM32L4_CONSOLE_RX GPIO_USART1_RX
|
||||
# define STM32_CONSOLE_BASE STM32_USART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART1_RX
|
||||
# ifdef CONFIG_USART1_RS485
|
||||
# define STM32L4_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define STM32L4_CONSOLE_BASE STM32L4_USART2_BASE
|
||||
# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY
|
||||
# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1
|
||||
# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
|
||||
# define STM32L4_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32L4_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32L4_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32L4_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# define STM32L4_CONSOLE_TX GPIO_USART2_TX
|
||||
# define STM32L4_CONSOLE_RX GPIO_USART2_RX
|
||||
# define STM32_CONSOLE_BASE STM32_USART2_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART2_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART2_RX
|
||||
# ifdef CONFIG_USART2_RS485
|
||||
# define STM32L4_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
|
||||
# define STM32L4_CONSOLE_BASE STM32L4_USART3_BASE
|
||||
# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY
|
||||
# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1
|
||||
# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART3EN
|
||||
# define STM32L4_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define STM32L4_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define STM32L4_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
# define STM32L4_CONSOLE_2STOP CONFIG_USART3_2STOP
|
||||
# define STM32L4_CONSOLE_TX GPIO_USART3_TX
|
||||
# define STM32L4_CONSOLE_RX GPIO_USART3_RX
|
||||
# define STM32_CONSOLE_BASE STM32_USART3_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART3_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART3_RX
|
||||
# ifdef CONFIG_USART3_RS485
|
||||
# define STM32L4_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
|
||||
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define STM32L4_CONSOLE_BASE STM32L4_UART4_BASE
|
||||
# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY
|
||||
# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1
|
||||
# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART4EN
|
||||
# define STM32L4_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define STM32L4_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define STM32L4_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define STM32L4_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
# define STM32L4_CONSOLE_TX GPIO_UART4_TX
|
||||
# define STM32L4_CONSOLE_RX GPIO_UART4_RX
|
||||
# define STM32_CONSOLE_BASE STM32_UART4_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_UART4_TX
|
||||
# define STM32_CONSOLE_RX GPIO_UART4_RX
|
||||
# ifdef CONFIG_UART4_RS485
|
||||
# define STM32L4_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
|
||||
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
|
||||
# define STM32L4_CONSOLE_BASE STM32L4_UART5_BASE
|
||||
# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY
|
||||
# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1
|
||||
# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART5EN
|
||||
# define STM32L4_CONSOLE_BAUD CONFIG_UART5_BAUD
|
||||
# define STM32L4_CONSOLE_BITS CONFIG_UART5_BITS
|
||||
# define STM32L4_CONSOLE_PARITY CONFIG_UART5_PARITY
|
||||
# define STM32L4_CONSOLE_2STOP CONFIG_UART5_2STOP
|
||||
# define STM32L4_CONSOLE_TX GPIO_UART5_TX
|
||||
# define STM32L4_CONSOLE_RX GPIO_UART5_RX
|
||||
# define STM32_CONSOLE_BASE STM32_UART5_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_UART5_TX
|
||||
# define STM32_CONSOLE_RX GPIO_UART5_RX
|
||||
# ifdef CONFIG_UART5_RS485
|
||||
# define STM32L4_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
|
||||
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32L4_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* CR1 settings */
|
||||
|
||||
# if STM32L4_CONSOLE_BITS == 9
|
||||
# if STM32_CONSOLE_BITS == 9
|
||||
# define USART_CR1_M0_VALUE USART_CR1_M0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# elif STM32L4_CONSOLE_BITS == 7
|
||||
# elif STM32_CONSOLE_BITS == 7
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE USART_CR1_M1
|
||||
# else /* 8 bits */
|
||||
|
|
@ -174,9 +174,9 @@
|
|||
# define USART_CR1_M1_VALUE 0
|
||||
# endif
|
||||
|
||||
# if STM32L4_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
|
||||
# elif STM32L4_CONSOLE_PARITY == 2 /* even parity */
|
||||
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
|
||||
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
|
||||
# else /* no parity */
|
||||
# define USART_CR1_PARITY_VALUE 0
|
||||
|
|
@ -192,7 +192,7 @@
|
|||
|
||||
/* CR2 settings */
|
||||
|
||||
# if STM32L4_CONSOLE_2STOP != 0
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
|
|
@ -234,19 +234,19 @@
|
|||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32L4_USARTDIV8 \
|
||||
(((STM32L4_APBCLOCK << 1) + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD)
|
||||
# define STM32L4_USARTDIV16 \
|
||||
((STM32L4_APBCLOCK + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if STM32L4_USARTDIV8 > 100
|
||||
# define STM32L4_BRR_VALUE STM32L4_USARTDIV16
|
||||
# if STM32_USARTDIV8 > 100
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32L4_BRR_VALUE \
|
||||
((STM32L4_USARTDIV8 & 0xfff0) | ((STM32L4_USARTDIV8 & 0x000f) >> 1))
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
|
@ -288,22 +288,22 @@ void arm_lowputc(char ch)
|
|||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) &
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TXE) == 0);
|
||||
#ifdef STM32L4_CONSOLE_RS485_DIR
|
||||
stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR,
|
||||
STM32L4_CONSOLE_RS485_DIR_POLARITY);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32L4_CONSOLE_BASE + STM32L4_USART_TDR_OFFSET);
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#ifdef STM32L4_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) &
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TC) == 0);
|
||||
stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR,
|
||||
!STM32L4_CONSOLE_RS485_DIR_POLARITY);
|
||||
stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
!STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
|
@ -329,7 +329,7 @@ void stm32l4_lowsetup(void)
|
|||
#if defined(HAVE_CONSOLE)
|
||||
/* Enable USART APB1/2 clock */
|
||||
|
||||
modifyreg32(STM32L4_CONSOLE_APBREG, 0, STM32L4_CONSOLE_APBEN);
|
||||
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
|
||||
#endif
|
||||
|
||||
/* Enable the console USART and configure GPIO pins needed for rx/tx.
|
||||
|
|
@ -338,17 +338,17 @@ void stm32l4_lowsetup(void)
|
|||
* stm32l4_rcc.c
|
||||
*/
|
||||
|
||||
#ifdef STM32L4_CONSOLE_TX
|
||||
stm32l4_configgpio(STM32L4_CONSOLE_TX);
|
||||
#ifdef STM32_CONSOLE_TX
|
||||
stm32l4_configgpio(STM32_CONSOLE_TX);
|
||||
#endif
|
||||
#ifdef STM32L4_CONSOLE_RX
|
||||
stm32l4_configgpio(STM32L4_CONSOLE_RX);
|
||||
#ifdef STM32_CONSOLE_RX
|
||||
stm32l4_configgpio(STM32_CONSOLE_RX);
|
||||
#endif
|
||||
|
||||
#ifdef STM32L4_CONSOLE_RS485_DIR
|
||||
stm32l4_configgpio(STM32L4_CONSOLE_RS485_DIR);
|
||||
stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR,
|
||||
!STM32L4_CONSOLE_RS485_DIR_POLARITY);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32l4_configgpio(STM32_CONSOLE_RS485_DIR);
|
||||
stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
!STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
|
@ -356,42 +356,42 @@ void stm32l4_lowsetup(void)
|
|||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Configure CR2 */
|
||||
|
||||
cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
cr &= ~USART_CR2_CLRBITS;
|
||||
cr |= USART_CR2_SETBITS;
|
||||
putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr &= ~USART_CR1_CLRBITS;
|
||||
cr |= USART_CR1_SETBITS;
|
||||
putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_CLRBITS;
|
||||
cr |= USART_CR3_SETBITS;
|
||||
putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Configure the USART Baud Rate */
|
||||
|
||||
putreg32(STM32L4_BRR_VALUE,
|
||||
STM32L4_CONSOLE_BASE + STM32L4_USART_BRR_OFFSET);
|
||||
putreg32(STM32_BRR_VALUE,
|
||||
STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#ifdef USE_OVER8
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
|
|
|
|||
|
|
@ -154,9 +154,9 @@ static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops =
|
|||
static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv =
|
||||
{
|
||||
.ops = &stm32l4_lptim_ops,
|
||||
.mode = STM32L4_LPTIM_MODE_UNUSED,
|
||||
.base = STM32L4_LPTIM1_BASE,
|
||||
.freq = STM32L4_LPTIM1_FREQUENCY, /* Must be defined in board.h */
|
||||
.mode = STM32_LPTIM_MODE_UNUSED,
|
||||
.base = STM32_LPTIM1_BASE,
|
||||
.freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -164,9 +164,9 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv =
|
|||
static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv =
|
||||
{
|
||||
.ops = &stm32l4_lptim_ops,
|
||||
.mode = STM32L4_LPTIM_MODE_UNUSED,
|
||||
.base = STM32L4_LPTIM2_BASE,
|
||||
.freq = STM32L4_LPTIM2_FREQUENCY, /* Must be defined in board.h */
|
||||
.mode = STM32_LPTIM_MODE_UNUSED,
|
||||
.base = STM32_LPTIM2_BASE,
|
||||
.freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -218,13 +218,13 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev)
|
|||
switch (((struct stm32l4_lptim_priv_s *)dev)->base)
|
||||
{
|
||||
#if defined(CONFIG_STM32L4_LPTIM1)
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN);
|
||||
case STM32_LPTIM1_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_LPTIM2)
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN);
|
||||
case STM32_LPTIM2_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -246,13 +246,13 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev)
|
|||
switch (((struct stm32l4_lptim_priv_s *)dev)->base)
|
||||
{
|
||||
#if defined(CONFIG_STM32L4_LPTIM1)
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0);
|
||||
case STM32_LPTIM1_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_LPTIM2)
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0);
|
||||
case STM32_LPTIM2_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -274,15 +274,15 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev)
|
|||
switch (((struct stm32l4_lptim_priv_s *)dev)->base)
|
||||
{
|
||||
#if defined(CONFIG_STM32L4_LPTIM1)
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST);
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0);
|
||||
case STM32_LPTIM1_BASE:
|
||||
modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST);
|
||||
modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_STM32L4_LPTIM2)
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST);
|
||||
modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0);
|
||||
case STM32_LPTIM2_BASE:
|
||||
modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST);
|
||||
modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -300,12 +300,12 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev,
|
|||
{
|
||||
DEBUGASSERT(dev != NULL && cfg != NULL);
|
||||
|
||||
channel &= STM32L4_LPTIM_CH_MASK;
|
||||
channel &= STM32_LPTIM_CH_MASK;
|
||||
|
||||
switch (((struct stm32l4_lptim_priv_s *)dev)->base)
|
||||
{
|
||||
#if defined(CONFIG_STM32L4_LPTIM1)
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
case STM32_LPTIM1_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
# if defined(GPIO_LPTIM1_OUT_1)
|
||||
|
|
@ -330,7 +330,7 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev,
|
|||
#endif /* CONFIG_STM32L4_LPTIM1 */
|
||||
|
||||
#if defined(CONFIG_STM32L4_LPTIM2)
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
case STM32_LPTIM2_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
# if defined(GPIO_LPTIM2_OUT_1)
|
||||
|
|
@ -369,24 +369,24 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev,
|
|||
stm32l4_lptim_mode_t mode)
|
||||
{
|
||||
const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base +
|
||||
STM32L4_LPTIM_CR_OFFSET;
|
||||
STM32_LPTIM_CR_OFFSET;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
/* Mode */
|
||||
|
||||
switch (mode & STM32L4_LPTIM_MODE_MASK)
|
||||
switch (mode & STM32_LPTIM_MODE_MASK)
|
||||
{
|
||||
case STM32L4_LPTIM_MODE_DISABLED:
|
||||
case STM32_LPTIM_MODE_DISABLED:
|
||||
modifyreg32(addr, LPTIM_CR_ENABLE, 0);
|
||||
break;
|
||||
|
||||
case STM32L4_LPTIM_MODE_SINGLE:
|
||||
case STM32_LPTIM_MODE_SINGLE:
|
||||
modifyreg32(addr, 0, LPTIM_CR_ENABLE);
|
||||
modifyreg32(addr, 0, LPTIM_CR_SNGSTRT);
|
||||
break;
|
||||
|
||||
case STM32L4_LPTIM_MODE_CONTINUOUS:
|
||||
case STM32_LPTIM_MODE_CONTINUOUS:
|
||||
modifyreg32(addr, 0, LPTIM_CR_ENABLE);
|
||||
modifyreg32(addr, 0, LPTIM_CR_CNTSTRT);
|
||||
break;
|
||||
|
|
@ -469,7 +469,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev,
|
|||
actual = priv->freq >> 7;
|
||||
}
|
||||
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK,
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK,
|
||||
setbits);
|
||||
stm32l4_lptim_enable(dev);
|
||||
|
||||
|
|
@ -519,9 +519,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev,
|
|||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
if (clksrc == STM32L4_LPTIM_CLK_EXT)
|
||||
if (clksrc == STM32_LPTIM_CLK_EXT)
|
||||
{
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
LPTIM_CFGR_CKSEL_MASK,
|
||||
LPTIM_CFGR_CKSEL_EXTCLK);
|
||||
}
|
||||
|
|
@ -532,12 +532,12 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev,
|
|||
switch (priv->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32L4_LPTIM1
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
case STM32_LPTIM1_BASE:
|
||||
ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_LPTIM2
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
case STM32_LPTIM2_BASE:
|
||||
ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK;
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -547,61 +547,61 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev,
|
|||
|
||||
switch (clksrc)
|
||||
{
|
||||
case STM32L4_LPTIM_CLK_PCLK:
|
||||
case STM32_LPTIM_CLK_PCLK:
|
||||
switch (priv->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32L4_LPTIM1
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
case STM32_LPTIM1_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_LPTIM2
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
case STM32_LPTIM2_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
case STM32L4_LPTIM_CLK_HSI:
|
||||
case STM32_LPTIM_CLK_HSI:
|
||||
switch (priv->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32L4_LPTIM1
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
case STM32_LPTIM1_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_LPTIM2
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
case STM32_LPTIM2_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
case STM32L4_LPTIM_CLK_LSI:
|
||||
case STM32_LPTIM_CLK_LSI:
|
||||
switch (priv->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32L4_LPTIM1
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
case STM32_LPTIM1_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_LPTIM2
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
case STM32_LPTIM2_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
case STM32L4_LPTIM_CLK_LSE:
|
||||
case STM32_LPTIM_CLK_LSE:
|
||||
switch (priv->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32L4_LPTIM1
|
||||
case STM32L4_LPTIM1_BASE:
|
||||
case STM32_LPTIM1_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_LPTIM2
|
||||
case STM32L4_LPTIM2_BASE:
|
||||
case STM32_LPTIM2_BASE:
|
||||
ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE;
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -611,9 +611,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev,
|
|||
break;
|
||||
}
|
||||
|
||||
modifyreg32(STM32L4_RCC_CCIPR, ccr_mask, ccr_bits);
|
||||
modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits);
|
||||
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
LPTIM_CFGR_CKSEL_MASK,
|
||||
LPTIM_CFGR_CKSEL_INTCLK);
|
||||
}
|
||||
|
|
@ -632,7 +632,7 @@ static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev,
|
|||
(struct stm32l4_lptim_priv_s *)dev;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
putreg32(period, (uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET));
|
||||
putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -645,7 +645,7 @@ static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev)
|
|||
(struct stm32l4_lptim_priv_s *)dev;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
return getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET));
|
||||
return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -657,14 +657,14 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev,
|
|||
{
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
if (cntmode == STM32L4_LPTIM_COUNT_CLOCK)
|
||||
if (cntmode == STM32_LPTIM_COUNT_CLOCK)
|
||||
{
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
LPTIM_CFGR_COUNTMODE, 0);
|
||||
}
|
||||
else if (cntmode == STM32L4_LPTIM_COUNT_EXTTRIG)
|
||||
else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG)
|
||||
{
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
0, LPTIM_CFGR_COUNTMODE);
|
||||
}
|
||||
else
|
||||
|
|
@ -686,20 +686,20 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev,
|
|||
|
||||
switch (polarity)
|
||||
{
|
||||
case STM32L4_LPTIM_CLKPOL_RISING:
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
case STM32_LPTIM_CLKPOL_RISING:
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
LPTIM_CFGR_CKPOL_MASK,
|
||||
LPTIM_CFGR_CKPOL_RISING);
|
||||
break;
|
||||
|
||||
case STM32L4_LPTIM_CLKPOL_FALLING:
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
case STM32_LPTIM_CLKPOL_FALLING:
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
LPTIM_CFGR_CKPOL_MASK,
|
||||
LPTIM_CFGR_CKPOL_FALLING);
|
||||
break;
|
||||
|
||||
case STM32L4_LPTIM_CLKPOL_BOTH:
|
||||
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
||||
case STM32_LPTIM_CLKPOL_BOTH:
|
||||
stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET,
|
||||
LPTIM_CFGR_CKPOL_MASK,
|
||||
LPTIM_CFGR_CKPOL_BOTH);
|
||||
break;
|
||||
|
|
@ -725,9 +725,9 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev)
|
|||
do
|
||||
{
|
||||
counter1 = getreg32((uintptr_t)(priv->base +
|
||||
STM32L4_LPTIM_CNT_OFFSET));
|
||||
STM32_LPTIM_CNT_OFFSET));
|
||||
counter2 = getreg32((uintptr_t)(priv->base +
|
||||
STM32L4_LPTIM_CNT_OFFSET));
|
||||
STM32_LPTIM_CNT_OFFSET));
|
||||
}
|
||||
while (counter1 != counter2);
|
||||
|
||||
|
|
@ -757,7 +757,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer)
|
|||
/* Is device already allocated */
|
||||
|
||||
if (((struct stm32l4_lptim_priv_s *)dev)->mode !=
|
||||
STM32L4_LPTIM_MODE_UNUSED)
|
||||
STM32_LPTIM_MODE_UNUSED)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -772,7 +772,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer)
|
|||
|
||||
/* Mark it as used */
|
||||
|
||||
((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED;
|
||||
((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
|
@ -791,7 +791,7 @@ int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev)
|
|||
|
||||
/* Mark it as free */
|
||||
|
||||
((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED;
|
||||
((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED;
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -86,14 +86,14 @@
|
|||
|
||||
/* Helpers ******************************************************************/
|
||||
|
||||
#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en))
|
||||
#define STM32L4_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s))
|
||||
#define STM32L4_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
|
||||
#define STM32L4_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m))
|
||||
#define STM32L4_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
|
||||
#define STM32L4_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d))
|
||||
#define STM32_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define STM32_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
#define STM32_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en))
|
||||
#define STM32_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s))
|
||||
#define STM32_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
|
||||
#define STM32_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m))
|
||||
#define STM32_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
|
||||
#define STM32_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d))
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
@ -121,14 +121,14 @@ struct stm32l4_lptim_dev_s
|
|||
|
||||
typedef enum
|
||||
{
|
||||
STM32L4_LPTIM_MODE_UNUSED = -1,
|
||||
STM32_LPTIM_MODE_UNUSED = -1,
|
||||
|
||||
/* MODES */
|
||||
|
||||
STM32L4_LPTIM_MODE_DISABLED = 0x0000,
|
||||
STM32L4_LPTIM_MODE_SINGLE = 0x0001,
|
||||
STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002,
|
||||
STM32L4_LPTIM_MODE_MASK = 0x000f,
|
||||
STM32_LPTIM_MODE_DISABLED = 0x0000,
|
||||
STM32_LPTIM_MODE_SINGLE = 0x0001,
|
||||
STM32_LPTIM_MODE_CONTINUOUS = 0x0002,
|
||||
STM32_LPTIM_MODE_MASK = 0x000f,
|
||||
} stm32l4_lptim_mode_t;
|
||||
|
||||
/* LPTIM Clock Source */
|
||||
|
|
@ -137,11 +137,11 @@ typedef enum
|
|||
{
|
||||
/* Clock Sources */
|
||||
|
||||
STM32L4_LPTIM_CLK_PCLK = 0x0000,
|
||||
STM32L4_LPTIM_CLK_LSI = 0x0001,
|
||||
STM32L4_LPTIM_CLK_HSI = 0x0002,
|
||||
STM32L4_LPTIM_CLK_LSE = 0x0003,
|
||||
STM32L4_LPTIM_CLK_EXT = 0x0004,
|
||||
STM32_LPTIM_CLK_PCLK = 0x0000,
|
||||
STM32_LPTIM_CLK_LSI = 0x0001,
|
||||
STM32_LPTIM_CLK_HSI = 0x0002,
|
||||
STM32_LPTIM_CLK_LSE = 0x0003,
|
||||
STM32_LPTIM_CLK_EXT = 0x0004,
|
||||
} stm32l4_lptim_clksrc_t;
|
||||
|
||||
/* LPTIM Counter Modes */
|
||||
|
|
@ -150,8 +150,8 @@ typedef enum
|
|||
{
|
||||
/* Modes */
|
||||
|
||||
STM32L4_LPTIM_COUNT_CLOCK = 0x0000,
|
||||
STM32L4_LPTIM_COUNT_EXTTRIG = 0x0001,
|
||||
STM32_LPTIM_COUNT_CLOCK = 0x0000,
|
||||
STM32_LPTIM_COUNT_EXTTRIG = 0x0001,
|
||||
} stm32l4_lptim_cntmode_t;
|
||||
|
||||
/* LPTIM Clock Polarity */
|
||||
|
|
@ -160,24 +160,24 @@ typedef enum
|
|||
{
|
||||
/* MODES */
|
||||
|
||||
STM32L4_LPTIM_CLKPOL_RISING = 0x0000,
|
||||
STM32L4_LPTIM_CLKPOL_FALLING = 0x0001,
|
||||
STM32L4_LPTIM_CLKPOL_BOTH = 0x0002,
|
||||
STM32_LPTIM_CLKPOL_RISING = 0x0000,
|
||||
STM32_LPTIM_CLKPOL_FALLING = 0x0001,
|
||||
STM32_LPTIM_CLKPOL_BOTH = 0x0002,
|
||||
} stm32l4_lptim_clkpol_t;
|
||||
|
||||
/* LPTIM Channel Modes */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
STM32L4_LPTIM_CH_DISABLED = 0x0000,
|
||||
STM32_LPTIM_CH_DISABLED = 0x0000,
|
||||
|
||||
/* CHANNELS */
|
||||
|
||||
STM32L4_LPTIM_CH_CHINVALID = 0x0000,
|
||||
STM32L4_LPTIM_CH_CH1 = 0x0001,
|
||||
STM32L4_LPTIM_CH_CH2 = 0x0002,
|
||||
STM32L4_LPTIM_CH_CH3 = 0x0003,
|
||||
STM32L4_LPTIM_CH_MASK = 0x000f,
|
||||
STM32_LPTIM_CH_CHINVALID = 0x0000,
|
||||
STM32_LPTIM_CH_CH1 = 0x0001,
|
||||
STM32_LPTIM_CH_CH2 = 0x0002,
|
||||
STM32_LPTIM_CH_CH3 = 0x0003,
|
||||
STM32_LPTIM_CH_MASK = 0x000f,
|
||||
} stm32l4_lptim_channel_t;
|
||||
|
||||
/* LPTIM Operations */
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ void stm32l4_rcc_enablelse(void)
|
|||
|
||||
/* Check if the External Low-Speed (LSE) oscillator is already running. */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_BDCR);
|
||||
regval = getreg32(STM32_RCC_BDCR);
|
||||
|
||||
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) !=
|
||||
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY))
|
||||
|
|
@ -94,11 +94,11 @@ void stm32l4_rcc_enablelse(void)
|
|||
RCC_BDCR_LSEDRV_SHIFT;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32L4_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE clock to be ready */
|
||||
|
||||
while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0)
|
||||
while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0)
|
||||
{
|
||||
stm32l4_waste();
|
||||
}
|
||||
|
|
@ -116,7 +116,7 @@ void stm32l4_rcc_enablelse(void)
|
|||
regval &= ~RCC_BDCR_LSEDRV_MASK;
|
||||
regval |= CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
|
||||
RCC_BDCR_LSEDRV_SHIFT;
|
||||
putreg32(regval, STM32L4_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
#endif
|
||||
|
||||
/* Disable backup domain access if it was disabled on entry */
|
||||
|
|
|
|||
|
|
@ -46,11 +46,11 @@ void stm32l4_rcc_enablelsi(void)
|
|||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION);
|
||||
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
|
||||
|
||||
/* Wait for the internal LSI oscillator to be stable. */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
|
||||
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -67,7 +67,7 @@ void stm32l4_rcc_disablelsi(void)
|
|||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0);
|
||||
modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
|
||||
|
||||
/* LSIRDY should go low after 3 LSI clock cycles */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -86,10 +86,10 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg)
|
|||
* Disable the TC now and disable any further interrupts.
|
||||
*/
|
||||
|
||||
STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0);
|
||||
STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
|
||||
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
|
||||
STM32L4_TIM_ACKINT(oneshot->tch, 0);
|
||||
STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0);
|
||||
STM32_TIM_DISABLEINT(oneshot->tch, 0);
|
||||
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
|
||||
STM32_TIM_ACKINT(oneshot->tch, 0);
|
||||
|
||||
/* The timer is no longer running */
|
||||
|
||||
|
|
@ -200,7 +200,7 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot,
|
|||
return -EBUSY;
|
||||
}
|
||||
|
||||
STM32L4_TIM_SETCLOCK(oneshot->tch, frequency);
|
||||
STM32_TIM_SETCLOCK(oneshot->tch, frequency);
|
||||
|
||||
/* Initialize the remaining fields in the state structure. */
|
||||
|
||||
|
|
@ -302,19 +302,19 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot,
|
|||
|
||||
/* Set up to receive the callback when the interrupt occurs */
|
||||
|
||||
STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0);
|
||||
STM32_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0);
|
||||
|
||||
/* Set timer period */
|
||||
|
||||
oneshot->period = (uint32_t)period;
|
||||
STM32L4_TIM_SETPERIOD(oneshot->tch, (uint32_t)period);
|
||||
STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period);
|
||||
|
||||
/* Start the counter */
|
||||
|
||||
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_PULSE);
|
||||
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE);
|
||||
|
||||
STM32L4_TIM_ACKINT(oneshot->tch, 0);
|
||||
STM32L4_TIM_ENABLEINT(oneshot->tch, 0);
|
||||
STM32_TIM_ACKINT(oneshot->tch, 0);
|
||||
STM32_TIM_ENABLEINT(oneshot->tch, 0);
|
||||
|
||||
/* Enable interrupts. We should get the callback when the interrupt
|
||||
* occurs.
|
||||
|
|
@ -389,14 +389,14 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot,
|
|||
|
||||
tmrinfo("Cancelling...\n");
|
||||
|
||||
count = STM32L4_TIM_GETCOUNTER(oneshot->tch);
|
||||
count = STM32_TIM_GETCOUNTER(oneshot->tch);
|
||||
period = oneshot->period;
|
||||
|
||||
/* Now we can disable the interrupt and stop the timer. */
|
||||
|
||||
STM32L4_TIM_DISABLEINT(oneshot->tch, 0);
|
||||
STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0);
|
||||
STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED);
|
||||
STM32_TIM_DISABLEINT(oneshot->tch, 0);
|
||||
STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0);
|
||||
STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED);
|
||||
|
||||
oneshot->running = false;
|
||||
oneshot->handler = NULL;
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@
|
|||
|
||||
/* Number of endpoints */
|
||||
|
||||
#define STM32L4_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */
|
||||
#define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -75,7 +75,7 @@ int stm32l4_pmlpr(void)
|
|||
|
||||
/* Enable MSI clock */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_MSION;
|
||||
|
||||
/* Set MSI clock to 2 MHz */
|
||||
|
|
@ -83,27 +83,27 @@ int stm32l4_pmlpr(void)
|
|||
regval &= ~RCC_CR_MSIRANGE_MASK;
|
||||
regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */
|
||||
regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */
|
||||
putreg32(regval, STM32L4_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Select MSI clock as system clock source */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= RCC_CFGR_SW_MSI;
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the MSI source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_MSI)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable Low-Power Run */
|
||||
|
||||
regval = getreg32(STM32L4_PWR_CR1);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval |= PWR_CR1_LPR;
|
||||
putreg32(regval, STM32L4_PWR_CR1);
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -79,15 +79,15 @@ int stm32l4_pmstandby(void)
|
|||
|
||||
regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 |
|
||||
PWR_SCR_CWUF4 | PWR_SCR_CWUF5;
|
||||
putreg32(regval, STM32L4_PWR_SCR);
|
||||
putreg32(regval, STM32_PWR_SCR);
|
||||
|
||||
/* Select Standby mode */
|
||||
|
||||
regval = getreg32(STM32L4_PWR_CR1);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval &= ~PWR_CR1_LPMS_MASK;
|
||||
regval |= PWR_CR1_LPMS_STANDBY;
|
||||
|
||||
putreg32(regval, STM32L4_PWR_CR1);
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ int stm32l4_pmstop(bool lpds)
|
|||
* register 1.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32L4_PWR_CR1);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval &= ~PWR_CR1_LPMS_MASK;
|
||||
|
||||
/* Select Stop 1 mode with low-power regulator if so requested */
|
||||
|
|
@ -124,7 +124,7 @@ int stm32l4_pmstop(bool lpds)
|
|||
regval |= PWR_CR1_LPMS_STOP1LPR;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32L4_PWR_CR1);
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
|
||||
return do_stop();
|
||||
}
|
||||
|
|
@ -149,7 +149,7 @@ int stm32l4_pmstop2(void)
|
|||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32L4_PWR_CR1);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
#ifdef CONFIG_STM32L4_SRAM3_HEAP
|
||||
/* SRAM3 is used as heap, so it must not be powered off in Stop 2 mode. */
|
||||
|
||||
|
|
@ -160,7 +160,7 @@ int stm32l4_pmstop2(void)
|
|||
|
||||
regval &= ~PWR_CR1_LPMS_MASK;
|
||||
regval |= PWR_CR1_LPMS_STOP2;
|
||||
putreg32(regval, STM32L4_PWR_CR1);
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
|
||||
return do_stop();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -233,9 +233,9 @@ static struct stm32l4_tim_s g_pulsecount1dev =
|
|||
.timid = 1,
|
||||
.timtype = TIMTYPE_TIM1,
|
||||
.t_dts = CONFIG_STM32L4_TIM1_PULSECOUNT_TDTS,
|
||||
.irq = STM32L4_IRQ_TIM1UP,
|
||||
.base = STM32L4_TIM1_BASE,
|
||||
.pclk = STM32L4_APB2_TIM1_CLKIN,
|
||||
.irq = STM32_IRQ_TIM1UP,
|
||||
.base = STM32_TIM1_BASE,
|
||||
.pclk = STM32_APB2_TIM1_CLKIN,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */
|
||||
|
|
@ -284,9 +284,9 @@ static struct stm32l4_tim_s g_pulsecount8dev =
|
|||
.timid = 8,
|
||||
.timtype = TIMTYPE_TIM8,
|
||||
.t_dts = CONFIG_STM32L4_TIM8_PULSECOUNT_TDTS,
|
||||
.irq = STM32L4_IRQ_TIM8UP,
|
||||
.base = STM32L4_TIM8_BASE,
|
||||
.pclk = STM32L4_APB2_TIM8_CLKIN,
|
||||
.irq = STM32_IRQ_TIM8UP,
|
||||
.base = STM32_TIM8_BASE,
|
||||
.pclk = STM32_APB2_TIM8_CLKIN,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */
|
||||
|
|
@ -407,30 +407,30 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
_info("%s:\n", msg);
|
||||
_info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_SMCR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_DIER_OFFSET));
|
||||
pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET));
|
||||
_info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n",
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_SR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_EGR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET));
|
||||
pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
|
||||
_info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CNT_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_PSC_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET));
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET));
|
||||
_info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n",
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCR1_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCR2_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCR3_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_GTIM_CCR4_OFFSET));
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET));
|
||||
_info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
|
||||
pulsecount_getreg(priv, STM32L4_ATIM_RCR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_ATIM_DCR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32L4_ATIM_DMAR_OFFSET));
|
||||
pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET),
|
||||
pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -450,25 +450,25 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev,
|
|||
{
|
||||
case 1:
|
||||
{
|
||||
offset = STM32L4_GTIM_CCR1_OFFSET;
|
||||
offset = STM32_GTIM_CCR1_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
case 2:
|
||||
{
|
||||
offset = STM32L4_GTIM_CCR2_OFFSET;
|
||||
offset = STM32_GTIM_CCR2_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
case 3:
|
||||
{
|
||||
offset = STM32L4_GTIM_CCR3_OFFSET;
|
||||
offset = STM32_GTIM_CCR3_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
case 4:
|
||||
{
|
||||
offset = STM32L4_GTIM_CCR4_OFFSET;
|
||||
offset = STM32_GTIM_CCR4_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -520,7 +520,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
/* Get the reload values */
|
||||
|
||||
reload = pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET);
|
||||
reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET);
|
||||
|
||||
/* Duty cycle:
|
||||
*
|
||||
|
|
@ -617,8 +617,8 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
/* Set the reload and prescaler values */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload);
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_PSC_OFFSET,
|
||||
pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload);
|
||||
pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET,
|
||||
(uint16_t)(prescaler - 1));
|
||||
|
||||
return OK;
|
||||
|
|
@ -638,7 +638,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv)
|
|||
|
||||
/* Set up the advanced timer CR1 register. */
|
||||
|
||||
cr1 = pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET);
|
||||
cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET);
|
||||
|
||||
/* Pulsecount always uses edge-aligned up-counting mode. */
|
||||
|
||||
|
|
@ -653,7 +653,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv)
|
|||
|
||||
/* Write CR1 */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1);
|
||||
pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -689,14 +689,14 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev,
|
|||
case 1:
|
||||
case 2:
|
||||
{
|
||||
offset = STM32L4_GTIM_CCMR1_OFFSET;
|
||||
offset = STM32_GTIM_CCMR1_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
case 3:
|
||||
case 4:
|
||||
{
|
||||
offset = STM32L4_GTIM_CCMR2_OFFSET;
|
||||
offset = STM32_GTIM_CCMR2_OFFSET;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -773,8 +773,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv,
|
|||
|
||||
/* Get current registers state */
|
||||
|
||||
cr2 = pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET);
|
||||
ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET);
|
||||
ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET);
|
||||
|
||||
/* | OISx | IDLE | advanced timers | CR2 register
|
||||
* | CCxP | POL | all pulsecount timers | CCER register
|
||||
|
|
@ -807,8 +807,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv,
|
|||
|
||||
/* Write registers */
|
||||
|
||||
pulsecount_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2);
|
||||
pulsecount_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer);
|
||||
pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2);
|
||||
pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -838,7 +838,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
/* Get current register state */
|
||||
|
||||
ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET);
|
||||
|
||||
/* Get outputs configuration */
|
||||
|
||||
|
|
@ -865,7 +865,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
/* Write register */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -881,11 +881,11 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
if (enable)
|
||||
{
|
||||
pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
|
||||
pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
|
||||
}
|
||||
else
|
||||
{
|
||||
pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0);
|
||||
pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -933,7 +933,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev)
|
|||
|
||||
/* Disable the timer until we get it configured */
|
||||
|
||||
pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
|
||||
pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
|
||||
|
||||
/* Get configured outputs */
|
||||
|
||||
|
|
@ -1015,8 +1015,8 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
/* Disable all interrupts and DMA requests, clear all pending status */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
|
||||
|
||||
/* Set timer frequency */
|
||||
|
||||
|
|
@ -1051,14 +1051,14 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
|
|||
*/
|
||||
|
||||
priv->prev = pulsecount_count(info->count);
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET,
|
||||
pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET,
|
||||
(uint16_t)priv->prev - 1);
|
||||
|
||||
/* Generate an update event to reload the prescaler. This should
|
||||
* preload the RCR into active repetition counter.
|
||||
*/
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
|
||||
/* Now set the value of the RCR that will be loaded on the next
|
||||
* update event.
|
||||
|
|
@ -1066,7 +1066,7 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
|
|||
|
||||
priv->count = info->count;
|
||||
priv->curr = pulsecount_count(info->count - priv->prev);
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET,
|
||||
pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET,
|
||||
(uint16_t)priv->curr - 1);
|
||||
}
|
||||
|
||||
|
|
@ -1076,11 +1076,11 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
|
|||
{
|
||||
/* Set the repetition counter to zero */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0);
|
||||
|
||||
/* Generate an update event to reload the prescaler */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
}
|
||||
|
||||
/* Get configured outputs */
|
||||
|
|
@ -1105,12 +1105,12 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev,
|
|||
{
|
||||
/* Clear all pending interrupts and enable the update interrupt. */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE);
|
||||
pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE);
|
||||
|
||||
/* Enable the timer */
|
||||
|
||||
pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
|
||||
|
||||
/* And enable timer interrupts at the NVIC */
|
||||
|
||||
|
|
@ -1144,12 +1144,12 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev)
|
|||
|
||||
/* Verify that this is an update interrupt. Nothing else is expected. */
|
||||
|
||||
regval = pulsecount_getreg(priv, STM32L4_ATIM_SR_OFFSET);
|
||||
regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET);
|
||||
DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
|
||||
|
||||
/* Clear the UIF interrupt bit */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF);
|
||||
pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF);
|
||||
|
||||
/* Calculate the new count by subtracting the number of pulses
|
||||
* since the last interrupt.
|
||||
|
|
@ -1161,9 +1161,9 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev)
|
|||
* quickly as possible.
|
||||
*/
|
||||
|
||||
regval = pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET);
|
||||
regval = pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET);
|
||||
regval &= ~ATIM_BDTR_MOE;
|
||||
pulsecount_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, regval);
|
||||
pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval);
|
||||
|
||||
/* Disable first interrupts, stop and reset the timer */
|
||||
|
||||
|
|
@ -1194,7 +1194,7 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev)
|
|||
|
||||
priv->prev = priv->curr;
|
||||
priv->curr = pulsecount_count(priv->count - priv->prev);
|
||||
pulsecount_putreg(priv, STM32L4_ATIM_RCR_OFFSET,
|
||||
pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET,
|
||||
(uint16_t)priv->curr - 1);
|
||||
}
|
||||
|
||||
|
|
@ -1311,7 +1311,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv,
|
|||
#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT
|
||||
case 1:
|
||||
{
|
||||
regaddr = STM32L4_RCC_APB2ENR;
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
en_bit = RCC_APB2ENR_TIM1EN;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1320,7 +1320,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv,
|
|||
#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT
|
||||
case 8:
|
||||
{
|
||||
regaddr = STM32L4_RCC_APB2ENR;
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
en_bit = RCC_APB2ENR_TIM8EN;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1484,13 +1484,13 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev)
|
|||
{
|
||||
#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT
|
||||
case 1:
|
||||
regaddr = STM32L4_RCC_APB2RSTR;
|
||||
regaddr = STM32_RCC_APB2RSTR;
|
||||
resetbit = RCC_APB2RSTR_TIM1RST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT
|
||||
case 8:
|
||||
regaddr = STM32L4_RCC_APB2RSTR;
|
||||
regaddr = STM32_RCC_APB2RSTR;
|
||||
resetbit = RCC_APB2RSTR_TIM8RST;
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -1506,8 +1506,8 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev)
|
|||
|
||||
/* Disable further interrupts and stop the timer */
|
||||
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
|
||||
pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
|
||||
|
||||
/* Reset the timer - stopping the output and putting the timer back
|
||||
* into a state where pulsecount_start() can be called.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -844,80 +844,80 @@
|
|||
|
||||
enum stm32l4_timmode_e
|
||||
{
|
||||
STM32L4_TIMMODE_COUNTUP = 0,
|
||||
STM32L4_TIMMODE_COUNTDOWN = 1,
|
||||
STM32L4_TIMMODE_CENTER1 = 2,
|
||||
STM32L4_TIMMODE_CENTER2 = 3,
|
||||
STM32L4_TIMMODE_CENTER3 = 4,
|
||||
STM32_TIMMODE_COUNTUP = 0,
|
||||
STM32_TIMMODE_COUNTDOWN = 1,
|
||||
STM32_TIMMODE_CENTER1 = 2,
|
||||
STM32_TIMMODE_CENTER2 = 3,
|
||||
STM32_TIMMODE_CENTER3 = 4,
|
||||
};
|
||||
|
||||
/* Timer output polarity */
|
||||
|
||||
enum stm32l4_pwm_pol_e
|
||||
{
|
||||
STM32L4_POL_POS = 0,
|
||||
STM32L4_POL_NEG = 1,
|
||||
STM32_POL_POS = 0,
|
||||
STM32_POL_NEG = 1,
|
||||
};
|
||||
|
||||
/* Timer output IDLE state */
|
||||
|
||||
enum stm32l4_pwm_idle_e
|
||||
{
|
||||
STM32L4_IDLE_INACTIVE = 0,
|
||||
STM32L4_IDLE_ACTIVE = 1
|
||||
STM32_IDLE_INACTIVE = 0,
|
||||
STM32_IDLE_ACTIVE = 1
|
||||
};
|
||||
|
||||
/* PWM channel mode */
|
||||
|
||||
enum stm32l4_chanmode_e
|
||||
{
|
||||
STM32L4_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */
|
||||
STM32L4_CHANMODE_CHACT = 1, /* OCxREF active on match */
|
||||
STM32L4_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */
|
||||
STM32L4_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */
|
||||
STM32L4_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */
|
||||
STM32L4_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */
|
||||
STM32L4_CHANMODE_PWM1 = 6, /* PWM mode 1 */
|
||||
STM32L4_CHANMODE_PWM2 = 7, /* PWM mode 2 */
|
||||
STM32L4_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */
|
||||
STM32L4_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */
|
||||
STM32L4_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */
|
||||
STM32L4_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */
|
||||
STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */
|
||||
STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */
|
||||
STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */
|
||||
STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */
|
||||
STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */
|
||||
STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */
|
||||
STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */
|
||||
STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */
|
||||
STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */
|
||||
STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */
|
||||
STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */
|
||||
STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */
|
||||
};
|
||||
|
||||
/* PWM timer channel */
|
||||
|
||||
enum stm32l4_pwm_chan_e
|
||||
{
|
||||
STM32L4_PWM_CHAN1 = 1,
|
||||
STM32L4_PWM_CHAN2 = 2,
|
||||
STM32L4_PWM_CHAN3 = 3,
|
||||
STM32L4_PWM_CHAN4 = 4,
|
||||
STM32L4_PWM_CHAN5 = 5,
|
||||
STM32L4_PWM_CHAN6 = 6,
|
||||
STM32_PWM_CHAN1 = 1,
|
||||
STM32_PWM_CHAN2 = 2,
|
||||
STM32_PWM_CHAN3 = 3,
|
||||
STM32_PWM_CHAN4 = 4,
|
||||
STM32_PWM_CHAN5 = 5,
|
||||
STM32_PWM_CHAN6 = 6,
|
||||
};
|
||||
|
||||
/* PWM timer channel output */
|
||||
|
||||
enum stm32l4_pwm_output_e
|
||||
{
|
||||
STM32L4_PWM_OUT1 = (1 << 0),
|
||||
STM32L4_PWM_OUT1N = (1 << 1),
|
||||
STM32L4_PWM_OUT2 = (1 << 2),
|
||||
STM32L4_PWM_OUT2N = (1 << 3),
|
||||
STM32L4_PWM_OUT3 = (1 << 4),
|
||||
STM32L4_PWM_OUT3N = (1 << 5),
|
||||
STM32L4_PWM_OUT4 = (1 << 6),
|
||||
STM32_PWM_OUT1 = (1 << 0),
|
||||
STM32_PWM_OUT1N = (1 << 1),
|
||||
STM32_PWM_OUT2 = (1 << 2),
|
||||
STM32_PWM_OUT2N = (1 << 3),
|
||||
STM32_PWM_OUT3 = (1 << 4),
|
||||
STM32_PWM_OUT3N = (1 << 5),
|
||||
STM32_PWM_OUT4 = (1 << 6),
|
||||
|
||||
/* 1 << 7 reserved - no complementary output for CH4 */
|
||||
|
||||
/* Only available inside micro */
|
||||
|
||||
STM32L4_PWM_OUT5 = (1 << 8),
|
||||
STM32_PWM_OUT5 = (1 << 8),
|
||||
|
||||
/* 1 << 9 reserved - no complementary output for CH5 */
|
||||
|
||||
STM32L4_PWM_OUT6 = (1 << 10),
|
||||
STM32_PWM_OUT6 = (1 << 10),
|
||||
|
||||
/* 1 << 11 reserved - no complementary output for CH6 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,12 +41,12 @@
|
|||
|
||||
static inline uint16_t stm32l4_pwr_getreg(uint8_t offset)
|
||||
{
|
||||
return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset);
|
||||
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value)
|
||||
{
|
||||
putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset);
|
||||
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -75,7 +75,7 @@ bool stm32l4_pwr_enableclk(bool enable)
|
|||
uint32_t regval;
|
||||
bool wasenabled;
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR1);
|
||||
regval = getreg32(STM32_RCC_APB1ENR1);
|
||||
wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
|
||||
|
||||
/* Power interface clock enable. */
|
||||
|
|
@ -85,14 +85,14 @@ bool stm32l4_pwr_enableclk(bool enable)
|
|||
/* Disable power interface clock */
|
||||
|
||||
regval &= ~RCC_APB1ENR1_PWREN;
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1);
|
||||
putreg32(regval, STM32_RCC_APB1ENR1);
|
||||
}
|
||||
else if (!wasenabled && enable)
|
||||
{
|
||||
/* Enable power interface clock */
|
||||
|
||||
regval |= RCC_APB1ENR1_PWREN;
|
||||
putreg32(regval, STM32L4_RCC_APB1ENR1);
|
||||
putreg32(regval, STM32_RCC_APB1ENR1);
|
||||
}
|
||||
|
||||
return wasenabled;
|
||||
|
|
@ -120,7 +120,7 @@ bool stm32l4_pwr_enablebkp(bool writable)
|
|||
|
||||
/* Get the current state of the STM32L4 PWR control register 1 */
|
||||
|
||||
regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET);
|
||||
regval = stm32l4_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
waswritable = ((regval & PWR_CR1_DBP) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
|
@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable)
|
|||
/* Disable backup domain access */
|
||||
|
||||
regval &= ~PWR_CR1_DBP;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
else if (!waswritable && writable)
|
||||
{
|
||||
/* Enable backup domain access */
|
||||
|
||||
regval |= PWR_CR1_DBP;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
|
||||
/* Enable does not happen right away */
|
||||
|
||||
|
|
@ -169,7 +169,7 @@ bool stm32l4_pwr_enableusv(bool set)
|
|||
bool was_set;
|
||||
bool was_clk_enabled;
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR1);
|
||||
regval = getreg32(STM32_RCC_APB1ENR1);
|
||||
was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -179,7 +179,7 @@ bool stm32l4_pwr_enableusv(bool set)
|
|||
|
||||
/* Get the current state of the STM32L4 PWR control register 2 */
|
||||
|
||||
regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET);
|
||||
regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET);
|
||||
was_set = ((regval & PWR_CR2_USV) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
|
@ -189,14 +189,14 @@ bool stm32l4_pwr_enableusv(bool set)
|
|||
/* Disable the Vddusb monitoring */
|
||||
|
||||
regval &= ~PWR_CR2_USV;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
}
|
||||
else if (!was_set && set)
|
||||
{
|
||||
/* Enable the Vddusb monitoring */
|
||||
|
||||
regval |= PWR_CR2_USV;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
}
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -228,7 +228,7 @@ bool stm32l4_pwr_enable_pvme2(bool set)
|
|||
bool was_set;
|
||||
bool was_clk_enabled;
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR1);
|
||||
regval = getreg32(STM32_RCC_APB1ENR1);
|
||||
was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -238,7 +238,7 @@ bool stm32l4_pwr_enable_pvme2(bool set)
|
|||
|
||||
/* Get the current state of the STM32L4 PWR control register 2 */
|
||||
|
||||
regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET);
|
||||
regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET);
|
||||
was_set = ((regval & PWR_CR2_PVME2) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
|
@ -248,14 +248,14 @@ bool stm32l4_pwr_enable_pvme2(bool set)
|
|||
/* Disable the Vddio2 monitoring */
|
||||
|
||||
regval &= ~PWR_CR2_PVME2;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
}
|
||||
else if (!was_set && set)
|
||||
{
|
||||
/* Enable the Vddio2 monitoring */
|
||||
|
||||
regval |= PWR_CR2_PVME2;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
}
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -283,7 +283,7 @@ bool stm32l4_pwr_get_pvmo2(void)
|
|||
uint32_t regval;
|
||||
bool was_clk_enabled;
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR1);
|
||||
regval = getreg32(STM32_RCC_APB1ENR1);
|
||||
was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -293,7 +293,7 @@ bool stm32l4_pwr_get_pvmo2(void)
|
|||
|
||||
/* Get the current state of the STM32L4 SR2 control register 2 */
|
||||
|
||||
regval = stm32l4_pwr_getreg(STM32L4_PWR_SR2_OFFSET);
|
||||
regval = stm32l4_pwr_getreg(STM32_PWR_SR2_OFFSET);
|
||||
|
||||
if (!was_clk_enabled)
|
||||
{
|
||||
|
|
@ -325,7 +325,7 @@ bool stm32l4_pwr_vddio2_valid(bool set)
|
|||
bool was_set;
|
||||
bool was_clk_enabled;
|
||||
|
||||
regval = getreg32(STM32L4_RCC_APB1ENR1);
|
||||
regval = getreg32(STM32_RCC_APB1ENR1);
|
||||
was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -335,7 +335,7 @@ bool stm32l4_pwr_vddio2_valid(bool set)
|
|||
|
||||
/* Get the current state of the STM32L4 PWR control register 2 */
|
||||
|
||||
regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET);
|
||||
regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET);
|
||||
was_set = ((regval & PWR_CR2_IOSV) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
|
@ -345,14 +345,14 @@ bool stm32l4_pwr_vddio2_valid(bool set)
|
|||
/* Reset the Vddio2 independent I/O supply valid bit. */
|
||||
|
||||
regval &= ~PWR_CR2_IOSV;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
}
|
||||
else if (!was_set && set)
|
||||
{
|
||||
/* Set the Vddio2 independent I/O supply valid bit. */
|
||||
|
||||
regval |= PWR_CR2_IOSV;
|
||||
stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
|
||||
stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval);
|
||||
}
|
||||
|
||||
if (!was_clk_enabled)
|
||||
|
|
@ -392,7 +392,7 @@ void stm32_pwr_setvos(int vos)
|
|||
return;
|
||||
}
|
||||
|
||||
regval = getreg32(STM32L4_PWR_CR1);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval &= ~PWR_CR1_VOS_MASK;
|
||||
|
||||
if (vos == 1)
|
||||
|
|
@ -404,5 +404,5 @@ void stm32_pwr_setvos(int vos)
|
|||
regval |= PWR_CR1_VOS_RANGE2;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32L4_PWR_CR1);
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -94,62 +94,62 @@
|
|||
#ifdef CONFIG_STM32L4_QENCODER_FILTER
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168
|
||||
# endif
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32)
|
||||
# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326
|
||||
# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8)
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328
|
||||
# endif
|
||||
# endif
|
||||
|
||||
# ifndef STM32L4_QENCODER_ICF
|
||||
# ifndef STM32_QENCODER_ICF
|
||||
# warning "Invalid encoder filter combination, filter disabled"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef STM32L4_QENCODER_ICF
|
||||
# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
|
||||
#ifndef STM32_QENCODER_ICF
|
||||
# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT
|
||||
#endif
|
||||
|
||||
#define STM32L4_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
|
||||
#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT)
|
||||
|
||||
/* Debug ********************************************************************/
|
||||
|
||||
|
|
@ -275,11 +275,11 @@ static const struct qe_ops_s g_qecallbacks =
|
|||
static const struct stm32l4_qeconfig_s g_tim1config =
|
||||
{
|
||||
.timid = 1,
|
||||
.irq = STM32L4_IRQ_TIM1UP,
|
||||
.irq = STM32_IRQ_TIM1UP,
|
||||
#ifdef HAVE_MIXEDWIDTH_TIMERS
|
||||
.width = TIM1_BITWIDTH,
|
||||
#endif
|
||||
.base = STM32L4_TIM1_BASE,
|
||||
.base = STM32_TIM1_BASE,
|
||||
.psc = CONFIG_STM32L4_TIM1_QEPSC,
|
||||
.ti1cfg = GPIO_TIM1_CH1IN,
|
||||
.ti2cfg = GPIO_TIM1_CH2IN,
|
||||
|
|
@ -299,11 +299,11 @@ static struct stm32l4_lowerhalf_s g_tim1lower =
|
|||
static const struct stm32l4_qeconfig_s g_tim2config =
|
||||
{
|
||||
.timid = 2,
|
||||
.irq = STM32L4_IRQ_TIM2,
|
||||
.irq = STM32_IRQ_TIM2,
|
||||
#ifdef HAVE_MIXEDWIDTH_TIMERS
|
||||
.width = TIM2_BITWIDTH,
|
||||
#endif
|
||||
.base = STM32L4_TIM2_BASE,
|
||||
.base = STM32_TIM2_BASE,
|
||||
.psc = CONFIG_STM32L4_TIM2_QEPSC,
|
||||
.ti1cfg = GPIO_TIM2_CH1IN,
|
||||
.ti2cfg = GPIO_TIM2_CH2IN,
|
||||
|
|
@ -323,11 +323,11 @@ static struct stm32l4_lowerhalf_s g_tim2lower =
|
|||
static const struct stm32l4_qeconfig_s g_tim3config =
|
||||
{
|
||||
.timid = 3,
|
||||
.irq = STM32L4_IRQ_TIM3,
|
||||
.irq = STM32_IRQ_TIM3,
|
||||
#ifdef HAVE_MIXEDWIDTH_TIMERS
|
||||
.width = TIM3_BITWIDTH,
|
||||
#endif
|
||||
.base = STM32L4_TIM3_BASE,
|
||||
.base = STM32_TIM3_BASE,
|
||||
.psc = CONFIG_STM32L4_TIM3_QEPSC,
|
||||
.ti1cfg = GPIO_TIM3_CH1IN,
|
||||
.ti2cfg = GPIO_TIM3_CH2IN,
|
||||
|
|
@ -347,11 +347,11 @@ static struct stm32l4_lowerhalf_s g_tim3lower =
|
|||
static const struct stm32l4_qeconfig_s g_tim4config =
|
||||
{
|
||||
.timid = 4,
|
||||
.irq = STM32L4_IRQ_TIM4,
|
||||
.irq = STM32_IRQ_TIM4,
|
||||
#ifdef HAVE_MIXEDWIDTH_TIMERS
|
||||
.width = TIM4_BITWIDTH,
|
||||
#endif
|
||||
.base = STM32L4_TIM4_BASE,
|
||||
.base = STM32_TIM4_BASE,
|
||||
.psc = CONFIG_STM32L4_TIM4_QEPSC,
|
||||
.ti1cfg = GPIO_TIM4_CH1IN,
|
||||
.ti2cfg = GPIO_TIM4_CH2IN,
|
||||
|
|
@ -371,11 +371,11 @@ static struct stm32l4_lowerhalf_s g_tim4lower =
|
|||
static const struct stm32l4_qeconfig_s g_tim5config =
|
||||
{
|
||||
.timid = 5,
|
||||
.irq = STM32L4_IRQ_TIM5,
|
||||
.irq = STM32_IRQ_TIM5,
|
||||
#ifdef HAVE_MIXEDWIDTH_TIMERS
|
||||
.width = TIM5_BITWIDTH,
|
||||
#endif
|
||||
.base = STM32L4_TIM5_BASE,
|
||||
.base = STM32_TIM5_BASE,
|
||||
.psc = CONFIG_STM32L4_TIM5_QEPSC,
|
||||
.ti1cfg = GPIO_TIM5_CH1IN,
|
||||
.ti2cfg = GPIO_TIM5_CH2IN,
|
||||
|
|
@ -395,11 +395,11 @@ static struct stm32l4_lowerhalf_s g_tim5lower =
|
|||
static const struct stm32l4_qeconfig_s g_tim8config =
|
||||
{
|
||||
.timid = 8,
|
||||
.irq = STM32L4_IRQ_TIM8UP,
|
||||
.irq = STM32_IRQ_TIM8UP,
|
||||
#ifdef HAVE_MIXEDWIDTH_TIMERS
|
||||
.width = TIM8_BITWIDTH,
|
||||
#endif
|
||||
.base = STM32L4_TIM8_BASE,
|
||||
.base = STM32_TIM8_BASE,
|
||||
.psc = CONFIG_STM32L4_TIM8_QEPSC,
|
||||
.ti1cfg = GPIO_TIM8_CH1IN,
|
||||
.ti2cfg = GPIO_TIM8_CH2IN,
|
||||
|
|
@ -531,43 +531,43 @@ static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv,
|
|||
{
|
||||
sninfo("%s:\n", msg);
|
||||
sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n",
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET));
|
||||
stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_GTIM_CR2_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET));
|
||||
sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32
|
||||
" CCMR2: %08" PRIx32 "\n",
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CCMR2_OFFSET));
|
||||
stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_GTIM_EGR_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CCMR2_OFFSET));
|
||||
sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x"
|
||||
" ARR: %08" PRIx32 "\n",
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_ARR_OFFSET));
|
||||
stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_GTIM_PSC_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_ARR_OFFSET));
|
||||
sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n",
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CCR1_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CCR2_OFFSET));
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CCR1_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CCR2_OFFSET));
|
||||
sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n",
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CCR3_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32L4_GTIM_CCR4_OFFSET));
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CCR3_OFFSET),
|
||||
stm32l4_getreg32(priv, STM32_GTIM_CCR4_OFFSET));
|
||||
#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE)
|
||||
if (priv->config->timid == 1 || priv->config->timid == 8)
|
||||
{
|
||||
sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
|
||||
stm32l4_getreg16(priv, STM32L4_ATIM_RCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_ATIM_BDTR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_ATIM_DCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_ATIM_DMAR_OFFSET));
|
||||
stm32l4_getreg16(priv, STM32_ATIM_RCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_ATIM_BDTR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_ATIM_DCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_ATIM_DMAR_OFFSET));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
sninfo(" DCR: %04x DMAR: %04x\n",
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_DCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32L4_GTIM_DMAR_OFFSET));
|
||||
stm32l4_getreg16(priv, STM32_GTIM_DCR_OFFSET),
|
||||
stm32l4_getreg16(priv, STM32_GTIM_DMAR_OFFSET));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg)
|
|||
* Nothing else is expected.
|
||||
*/
|
||||
|
||||
regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET);
|
||||
regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET);
|
||||
DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
|
||||
|
||||
/* Clear the UIF interrupt bit */
|
||||
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF);
|
||||
|
||||
/* Check the direction bit in the CR1 register and add or subtract the
|
||||
* maximum value, as appropriate.
|
||||
*/
|
||||
|
||||
regval = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET);
|
||||
regval = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET);
|
||||
if ((regval & ATIM_CR1_DIR) != 0)
|
||||
{
|
||||
priv->position -= (int32_t)0x0000ffff;
|
||||
|
|
@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Timer base configuration */
|
||||
|
||||
cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET);
|
||||
cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET);
|
||||
|
||||
/* Clear the direction bit (0=count up) and select the Counter Mode
|
||||
* (0=Edge aligned)
|
||||
|
|
@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
*/
|
||||
|
||||
cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK);
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1);
|
||||
|
||||
/* Set the Autoreload value */
|
||||
|
||||
#if defined(HAVE_MIXEDWIDTH_TIMERS)
|
||||
if (priv->config->width == 32)
|
||||
{
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff);
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff);
|
||||
}
|
||||
#elif defined(HAVE_32BIT_TIMERS)
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff);
|
||||
#else
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff);
|
||||
#endif
|
||||
|
||||
/* Set the timer prescaler value.
|
||||
|
|
@ -737,14 +737,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
*/
|
||||
|
||||
stm32l4_putreg16(priv,
|
||||
STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc);
|
||||
STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc);
|
||||
|
||||
#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE)
|
||||
if (priv->config->timid == 1 || priv->config->timid == 8)
|
||||
{
|
||||
/* Clear the Repetition Counter value */
|
||||
|
||||
stm32l4_putreg16(priv, STM32L4_ATIM_RCR_OFFSET, 0);
|
||||
stm32l4_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -752,7 +752,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
* and the repetition counter (only for TIM1 and TIM8) value immediately
|
||||
*/
|
||||
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG);
|
||||
|
||||
/* GPIO pin configuration */
|
||||
|
||||
|
|
@ -761,27 +761,27 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Set the encoder Mode 3 */
|
||||
|
||||
smcr = stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET);
|
||||
smcr = stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET);
|
||||
smcr &= ~GTIM_SMCR_SMS_MASK;
|
||||
smcr |= GTIM_SMCR_ENCMD3;
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_SMCR_OFFSET, smcr);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr);
|
||||
|
||||
/* TI1 Channel Configuration */
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
|
||||
ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET);
|
||||
ccer &= ~GTIM_CCER_CC1E;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET);
|
||||
ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET);
|
||||
ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET);
|
||||
|
||||
/* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */
|
||||
|
||||
ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK);
|
||||
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT;
|
||||
ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT;
|
||||
ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT;
|
||||
|
||||
/* Select the Polarity=rising and set the CC1E Bit */
|
||||
|
||||
|
|
@ -790,34 +790,34 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Write to TIM CCMR1 and CCER registers */
|
||||
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
/* Set the Input Capture Prescaler value: Capture performed each time an
|
||||
* edge is detected on the capture input.
|
||||
*/
|
||||
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET);
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET);
|
||||
ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK;
|
||||
ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT);
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
|
||||
/* TI2 Channel Configuration */
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
|
||||
ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET);
|
||||
ccer &= ~GTIM_CCER_CC2E;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET);
|
||||
ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET);
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET);
|
||||
ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET);
|
||||
|
||||
/* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */
|
||||
|
||||
ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK);
|
||||
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT;
|
||||
ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT;
|
||||
ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT;
|
||||
|
||||
/* Select the Polarity=rising and set the CC2E Bit */
|
||||
|
||||
|
|
@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Write to TIM CCMR1 and CCER registers */
|
||||
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer);
|
||||
|
||||
/* Set the Input Capture Prescaler value: Capture performed each time an
|
||||
* edge is detected on the capture input.
|
||||
*/
|
||||
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET);
|
||||
ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET);
|
||||
ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK;
|
||||
ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT);
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
|
||||
|
||||
/* Disable the update interrupt */
|
||||
|
||||
dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET);
|
||||
dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET);
|
||||
dier &= ~GTIM_DIER_UIE;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier);
|
||||
|
||||
/* There is no need for interrupts with 32-bit timers */
|
||||
|
||||
|
|
@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Reset the Update Disable Bit */
|
||||
|
||||
cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET);
|
||||
cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET);
|
||||
cr1 &= ~GTIM_CR1_UDIS;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1);
|
||||
|
||||
/* Reset the URS Bit */
|
||||
|
||||
cr1 &= ~GTIM_CR1_URS;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1);
|
||||
|
||||
/* There is no need for interrupts with 32-bit timers */
|
||||
|
||||
|
|
@ -886,22 +886,22 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower)
|
|||
{
|
||||
/* Clear any pending update interrupts */
|
||||
|
||||
regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET);
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF);
|
||||
regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF);
|
||||
|
||||
/* Then enable the update interrupt */
|
||||
|
||||
dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET);
|
||||
dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET);
|
||||
dier |= GTIM_DIER_UIE;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable the TIM Counter */
|
||||
|
||||
cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET);
|
||||
cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET);
|
||||
cr1 |= GTIM_CR1_CEN;
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1);
|
||||
|
||||
stm32l4_dumpregs(priv, "After setup");
|
||||
|
||||
|
|
@ -943,8 +943,8 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Disable further interrupts and stop the timer */
|
||||
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, 0);
|
||||
stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, 0);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0);
|
||||
stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, 0);
|
||||
|
||||
/* Determine which timer to reset */
|
||||
|
||||
|
|
@ -952,37 +952,37 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower)
|
|||
{
|
||||
#ifdef CONFIG_STM32L4_TIM1_QE
|
||||
case 1:
|
||||
regaddr = STM32L4_RCC_APB2RSTR;
|
||||
regaddr = STM32_RCC_APB2RSTR;
|
||||
resetbit = RCC_APB2RSTR_TIM1RST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_TIM2_QE
|
||||
case 2:
|
||||
regaddr = STM32L4_RCC_APB1RSTR1;
|
||||
regaddr = STM32_RCC_APB1RSTR1;
|
||||
resetbit = RCC_APB1RSTR1_TIM2RST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_TIM3_QE
|
||||
case 3:
|
||||
regaddr = STM32L4_RCC_APB1RSTR1;
|
||||
regaddr = STM32_RCC_APB1RSTR1;
|
||||
resetbit = RCC_APB1RSTR1_TIM3RST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_TIM4_QE
|
||||
case 4:
|
||||
regaddr = STM32L4_RCC_APB1RSTR1;
|
||||
regaddr = STM32_RCC_APB1RSTR1;
|
||||
resetbit = RCC_APB1RSTR1_TIM4RST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_TIM5_QE
|
||||
case 5:
|
||||
regaddr = STM32L4_RCC_APB1RSTR1;
|
||||
regaddr = STM32_RCC_APB1RSTR1;
|
||||
resetbit = RCC_APB1RSTR1_TIM5RST;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32L4_TIM8_QE
|
||||
case 8:
|
||||
regaddr = STM32L4_RCC_APB2RSTR;
|
||||
regaddr = STM32_RCC_APB2RSTR;
|
||||
resetbit = RCC_APB2RSTR_TIM8RST;
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -1010,14 +1010,14 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower)
|
|||
/* Put the TI1 GPIO pin back to its default state */
|
||||
|
||||
pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
|
||||
pincfg |= STM32L4_GPIO_INPUT_FLOAT;
|
||||
pincfg |= STM32_GPIO_INPUT_FLOAT;
|
||||
|
||||
stm32l4_configgpio(pincfg);
|
||||
|
||||
/* Put the TI2 GPIO pin back to its default state */
|
||||
|
||||
pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
|
||||
pincfg |= STM32L4_GPIO_INPUT_FLOAT;
|
||||
pincfg |= STM32_GPIO_INPUT_FLOAT;
|
||||
|
||||
stm32l4_configgpio(pincfg);
|
||||
return OK;
|
||||
|
|
@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower,
|
|||
do
|
||||
{
|
||||
position = priv->position;
|
||||
count = stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET);
|
||||
count = stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET);
|
||||
verify = priv->position;
|
||||
}
|
||||
while (position != verify);
|
||||
|
|
@ -1062,7 +1062,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower,
|
|||
#else
|
||||
/* Return the counter value */
|
||||
|
||||
*pos = (int32_t)stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET);
|
||||
*pos = (int32_t)stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET);
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower)
|
|||
*/
|
||||
|
||||
flags = spin_lock_irqsave(&priv->lock);
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0);
|
||||
priv->position = 0;
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
#else
|
||||
|
|
@ -1099,7 +1099,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower)
|
|||
|
||||
/* Reset the counter to zero */
|
||||
|
||||
stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0);
|
||||
stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0);
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@
|
|||
|
||||
/* Can't have both interrupt-driven QSPI and DMA QSPI */
|
||||
|
||||
#if defined(STM32L4_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA)
|
||||
#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA)
|
||||
# error "Cannot enable both interrupt mode and DMA mode for QSPI"
|
||||
#endif
|
||||
|
||||
|
|
@ -162,7 +162,7 @@ struct stm32l4_qspidev_s
|
|||
mutex_t lock; /* Assures mutually exclusive access to QSPI */
|
||||
bool memmap; /* TRUE: Controller is in memory mapped mode */
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
xcpt_t handler; /* Interrupt handler */
|
||||
uint8_t irq; /* Interrupt number */
|
||||
sem_t op_sem; /* Block until complete */
|
||||
|
|
@ -220,7 +220,7 @@ struct qspi_xctnspec_s
|
|||
uint8_t isddr; /* true if 'double data rate' */
|
||||
uint8_t issioo; /* true if 'send instruction only once' mode */
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
uint8_t function; /* functional mode; to distinguish a read or write */
|
||||
int8_t disposition; /* how it all turned out */
|
||||
uint32_t idxnow; /* index into databuffer of current byte in transfer */
|
||||
|
|
@ -260,7 +260,7 @@ static void qspi_dumpgpioconfig(const char *msg);
|
|||
|
||||
/* Interrupts */
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
static int qspi0_interrupt(int irq, void *context, void *arg);
|
||||
|
||||
#endif
|
||||
|
|
@ -332,11 +332,11 @@ static struct stm32l4_qspidev_s g_qspi0dev =
|
|||
{
|
||||
.ops = &g_qspi0ops,
|
||||
},
|
||||
.base = STM32L4_QSPI_BASE,
|
||||
.base = STM32_QSPI_BASE,
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
.handler = qspi0_interrupt,
|
||||
.irq = STM32L4_IRQ_QUADSPI,
|
||||
.irq = STM32_IRQ_QUADSPI,
|
||||
.op_sem = SEM_INITIALIZER(0),
|
||||
#endif
|
||||
.intf = 0,
|
||||
|
|
@ -478,7 +478,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
|
|||
* output.
|
||||
*/
|
||||
|
||||
regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */
|
||||
regval = getreg32(priv->base + STM32_QUADSPI_CR_OFFSET); /* Control Register */
|
||||
spiinfo("CR:%08" PRIx32 "\n", regval);
|
||||
spiinfo(" EN:%1d ABORT:%1d DMAEN:%1d TCEN:%1d SSHIFT:%1d\n"
|
||||
" FTHRES: %d\n"
|
||||
|
|
@ -499,14 +499,14 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
|
|||
(regval & QSPI_CR_PMM) ? 1 : 0,
|
||||
(regval & QSPI_CR_PRESCALER_MASK) >> QSPI_CR_PRESCALER_SHIFT);
|
||||
|
||||
regval = getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET); /* Device Configuration Register */
|
||||
regval = getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET); /* Device Configuration Register */
|
||||
spiinfo("DCR:%08" PRIx32 "\n", regval);
|
||||
spiinfo(" CKMODE:%1d CSHT:%d FSIZE:%d\n",
|
||||
(regval & QSPI_DCR_CKMODE) ? 1 : 0,
|
||||
(regval & QSPI_DCR_CSHT_MASK) >> QSPI_DCR_CSHT_SHIFT,
|
||||
(regval & QSPI_DCR_FSIZE_MASK) >> QSPI_DCR_FSIZE_SHIFT);
|
||||
|
||||
regval = getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */
|
||||
regval = getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */
|
||||
spiinfo("CCR:%08" PRIx32 "\n", regval);
|
||||
spiinfo(" INST:%02x IMODE:%d ADMODE:%d ADSIZE:%d ABMODE:%d\n"
|
||||
" ABSIZE:%d DCYC:%d DMODE:%d FMODE:%d\n"
|
||||
|
|
@ -523,7 +523,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
|
|||
(regval & QSPI_CCR_SIOO) ? 1 : 0,
|
||||
(regval & QSPI_CCR_DDRM) ? 1 : 0);
|
||||
|
||||
regval = getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET); /* Status Register */
|
||||
regval = getreg32(priv->base + STM32_QUADSPI_SR_OFFSET); /* Status Register */
|
||||
spiinfo("SR:%08" PRIx32 "\n", regval);
|
||||
spiinfo(" TEF:%1d TCF:%1d FTF:%1d SMF:%1d TOF:%1d BUSY:%1d FLEVEL:%d\n",
|
||||
(regval & QSPI_SR_TEF) ? 1 : 0,
|
||||
|
|
@ -537,19 +537,19 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg)
|
|||
#else
|
||||
spiinfo(" CR:%08" PRIx32 " DCR:%08" PRIx32
|
||||
" CCR:%08" PRIx32 " SR:%08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET), /* Control Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET), /* Device Configuration Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET)); /* Status Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_CR_OFFSET), /* Control Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET), /* Device Configuration Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_SR_OFFSET)); /* Status Register */
|
||||
spiinfo(" DLR:%08" PRIx32 " ABR:%08" PRIx32
|
||||
" PSMKR:%08" PRIx32 " PSMAR:%08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_QUADSPI_DLR_OFFSET), /* Data Length Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_DLR_OFFSET), /* Data Length Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */
|
||||
spiinfo(" PIR:%08" PRIx32 " LPTR:%08" PRIx32 "\n",
|
||||
getreg32(priv->base + STM32L4_QUADSPI_PIR_OFFSET), /* Polling Interval Register */
|
||||
getreg32(priv->base + STM32L4_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_PIR_OFFSET), /* Polling Interval Register */
|
||||
getreg32(priv->base + STM32_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */
|
||||
UNUSED(regval);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -561,22 +561,22 @@ static void qspi_dumpgpioconfig(const char *msg)
|
|||
uint32_t regval;
|
||||
spiinfo("%s:\n", msg);
|
||||
|
||||
regval = getreg32(STM32L4_GPIOE_MODER);
|
||||
regval = getreg32(STM32_GPIOE_MODER);
|
||||
spiinfo("E_MODER:%08" PRIx32 "\n", regval);
|
||||
|
||||
regval = getreg32(STM32L4_GPIOE_OTYPER);
|
||||
regval = getreg32(STM32_GPIOE_OTYPER);
|
||||
spiinfo("E_OTYPER:%08" PRIx32 "\n", regval);
|
||||
|
||||
regval = getreg32(STM32L4_GPIOE_OSPEED);
|
||||
regval = getreg32(STM32_GPIOE_OSPEED);
|
||||
spiinfo("E_OSPEED:%08" PRIx32 "\n", regval);
|
||||
|
||||
regval = getreg32(STM32L4_GPIOE_PUPDR);
|
||||
regval = getreg32(STM32_GPIOE_PUPDR);
|
||||
spiinfo("E_PUPDR:%08" PRIx32 "\n", regval);
|
||||
|
||||
regval = getreg32(STM32L4_GPIOE_AFRL);
|
||||
regval = getreg32(STM32_GPIOE_AFRL);
|
||||
spiinfo("E_AFRL:%08" PRIx32 "\n", regval);
|
||||
|
||||
regval = getreg32(STM32L4_GPIOE_AFRH);
|
||||
regval = getreg32(STM32_GPIOE_AFRH);
|
||||
spiinfo("E_AFRH:%08" PRIx32 "\n", regval);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -787,7 +787,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn,
|
|||
xctn->isddr = 0;
|
||||
}
|
||||
|
||||
#if defined(STM32L4_QSPI_INTERRUPTS)
|
||||
#if defined(STM32_QSPI_INTERRUPTS)
|
||||
xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR
|
||||
: CCR_FMODE_INDRD;
|
||||
xctn->disposition = - EIO;
|
||||
|
|
@ -918,7 +918,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
|
|||
|
||||
xctn->isddr = 0;
|
||||
|
||||
#if defined(STM32L4_QSPI_INTERRUPTS)
|
||||
#if defined(STM32_QSPI_INTERRUPTS)
|
||||
xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR
|
||||
: CCR_FMODE_INDRD;
|
||||
xctn->disposition = - EIO;
|
||||
|
|
@ -951,12 +951,12 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv,
|
|||
|
||||
if (polarity)
|
||||
{
|
||||
while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET))
|
||||
while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET))
|
||||
& mask));
|
||||
}
|
||||
else
|
||||
{
|
||||
while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET))
|
||||
while (((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET))
|
||||
& mask));
|
||||
}
|
||||
}
|
||||
|
|
@ -979,9 +979,9 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv)
|
|||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= QSPI_CR_ABORT;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1010,14 +1010,14 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv,
|
|||
|
||||
if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn)
|
||||
{
|
||||
qspi_putreg(priv, xctn->datasize - 1, STM32L4_QUADSPI_DLR_OFFSET);
|
||||
qspi_putreg(priv, xctn->datasize - 1, STM32_QUADSPI_DLR_OFFSET);
|
||||
}
|
||||
|
||||
/* If we have alternate bytes, stick them in now */
|
||||
|
||||
if (CCR_ABMODE_NONE != xctn->altbytesmode)
|
||||
{
|
||||
qspi_putreg(priv, xctn->altbytes, STM32L4_QUADSPI_ABR_OFFSET);
|
||||
qspi_putreg(priv, xctn->altbytes, STM32_QUADSPI_ABR_OFFSET);
|
||||
}
|
||||
|
||||
/* Build the CCR value and set it */
|
||||
|
|
@ -1033,17 +1033,17 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv,
|
|||
QSPI_CCR_FMODE(fctn) |
|
||||
(xctn->isddr ? QSPI_CCR_SIOO : 0) |
|
||||
(xctn->issioo ? QSPI_CCR_DDRM : 0);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET);
|
||||
|
||||
/* If we have and need and address, set that now, too */
|
||||
|
||||
if (CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn)
|
||||
{
|
||||
qspi_putreg(priv, xctn->addr, STM32L4_QUADSPI_AR_OFFSET);
|
||||
qspi_putreg(priv, xctn->addr, STM32_QUADSPI_AR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(STM32L4_QSPI_INTERRUPTS)
|
||||
#if defined(STM32_QSPI_INTERRUPTS)
|
||||
/****************************************************************************
|
||||
* Name: qspi0_interrupt
|
||||
*
|
||||
|
|
@ -1068,22 +1068,22 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
|
||||
/* Let's find out what is going on */
|
||||
|
||||
status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET);
|
||||
cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
|
||||
status = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET);
|
||||
cr = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Is it 'FIFO Threshold'? */
|
||||
|
||||
if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE))
|
||||
{
|
||||
volatile uint32_t *datareg = (volatile uint32_t *)
|
||||
(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
|
||||
(g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET);
|
||||
|
||||
if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR)
|
||||
{
|
||||
/* Write data until we have no more or have no place to put it */
|
||||
|
||||
while ((regval = qspi_getreg(&g_qspi0dev,
|
||||
STM32L4_QUADSPI_SR_OFFSET))
|
||||
STM32_QUADSPI_SR_OFFSET))
|
||||
& QSPI_SR_FTF)
|
||||
{
|
||||
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
|
||||
|
|
@ -1105,7 +1105,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
/* Read data until we have no more or have no place to put it */
|
||||
|
||||
while ((regval = qspi_getreg(&g_qspi0dev,
|
||||
STM32L4_QUADSPI_SR_OFFSET))
|
||||
STM32_QUADSPI_SR_OFFSET))
|
||||
& QSPI_SR_FTF)
|
||||
{
|
||||
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
|
||||
|
|
@ -1131,27 +1131,27 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
{
|
||||
/* Acknowledge interrupt */
|
||||
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR);
|
||||
|
||||
/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer
|
||||
* complete Interrupts
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
|
||||
qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Do the last bit of read if needed */
|
||||
|
||||
if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
|
||||
{
|
||||
volatile uint32_t *datareg = (volatile uint32_t *)
|
||||
(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
|
||||
(g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET);
|
||||
|
||||
/* Read any remaining data */
|
||||
|
||||
while (((regval = qspi_getreg(&g_qspi0dev,
|
||||
STM32L4_QUADSPI_SR_OFFSET)) &
|
||||
STM32_QUADSPI_SR_OFFSET)) &
|
||||
QSPI_SR_FLEVEL_MASK) != 0)
|
||||
{
|
||||
if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize)
|
||||
|
|
@ -1189,7 +1189,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
{
|
||||
/* Acknowledge interrupt */
|
||||
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32_QUADSPI_FCR);
|
||||
|
||||
/* If 'automatic poll mode stop' is activated, we're done */
|
||||
|
||||
|
|
@ -1197,9 +1197,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
{
|
||||
/* Disable the QSPI Transfer Error and Status Match Interrupts */
|
||||
|
||||
regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE);
|
||||
qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Set success status */
|
||||
|
||||
|
|
@ -1223,14 +1223,14 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
{
|
||||
/* Acknowledge interrupt */
|
||||
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32_QUADSPI_FCR);
|
||||
|
||||
/* Disable all the QSPI Interrupts */
|
||||
|
||||
regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE |
|
||||
QSPI_CR_TOIE);
|
||||
qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Set error status; 'transfer error' means that, in 'indirect mode',
|
||||
* an invalid address is attempted to be accessed. 'Invalid' is
|
||||
|
|
@ -1251,7 +1251,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg)
|
|||
{
|
||||
/* Acknowledge interrupt */
|
||||
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR);
|
||||
|
||||
/* XXX this interrupt simply means that, in 'memory mapped mode',
|
||||
* the QSPI memory has not been accessed for a while, and the
|
||||
|
|
@ -1426,16 +1426,16 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
|
|||
}
|
||||
|
||||
stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv,
|
||||
STM32L4_QUADSPI_DR_OFFSET),
|
||||
STM32_QUADSPI_DR_OFFSET),
|
||||
(uint32_t)meminfo->buffer, meminfo->buflen, dmaflags);
|
||||
|
||||
qspi_dma_sample(priv, DMA_AFTER_SETUP);
|
||||
|
||||
/* Enable the memory transfer */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= QSPI_CR_DMAEN;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Set up the Communications Configuration Register as per command info */
|
||||
|
||||
|
|
@ -1481,9 +1481,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
|
|||
if (ret < 0)
|
||||
{
|
||||
DEBUGPANIC();
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~QSPI_CR_DMAEN;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1512,9 +1512,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
|
|||
|
||||
stm32l4_dmastop(priv->dmach);
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~QSPI_CR_DMAEN;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Complain if the DMA fails */
|
||||
|
||||
|
|
@ -1527,7 +1527,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv,
|
|||
}
|
||||
#endif
|
||||
|
||||
#if !defined(STM32L4_QSPI_INTERRUPTS)
|
||||
#if !defined(STM32_QSPI_INTERRUPTS)
|
||||
/****************************************************************************
|
||||
* Name: qspi_receive_blocking
|
||||
*
|
||||
|
|
@ -1548,12 +1548,12 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
|
|||
{
|
||||
int ret = OK;
|
||||
volatile uint32_t *datareg =
|
||||
(volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET);
|
||||
(volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET);
|
||||
uint8_t *dest = (uint8_t *)xctn->buffer;
|
||||
uint32_t addrval;
|
||||
uint32_t regval;
|
||||
|
||||
addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
|
||||
addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET);
|
||||
if (dest != NULL)
|
||||
{
|
||||
/* Counter of remaining data */
|
||||
|
|
@ -1562,14 +1562,14 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
|
|||
|
||||
/* Ensure CCR register specifies indirect read */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CCR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CCR_OFFSET);
|
||||
regval &= ~QSPI_CCR_FMODE_MASK;
|
||||
regval |= QSPI_CCR_FMODE(CCR_FMODE_INDRD);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET);
|
||||
|
||||
/* Start the transfer by re-writing the address in AR register */
|
||||
|
||||
qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
|
||||
qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET);
|
||||
|
||||
/* Transfer loop */
|
||||
|
||||
|
|
@ -1589,7 +1589,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv,
|
|||
/* Wait for transfer complete, then clear it */
|
||||
|
||||
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
|
||||
qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR);
|
||||
|
||||
/* Use Abort to clear the busy flag, and ditch any extra bytes in
|
||||
* fifo
|
||||
|
|
@ -1626,7 +1626,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
|
|||
{
|
||||
int ret = OK;
|
||||
volatile uint32_t *datareg =
|
||||
(volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET);
|
||||
(volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET);
|
||||
uint8_t *src = (uint8_t *)xctn->buffer;
|
||||
|
||||
if (src != NULL)
|
||||
|
|
@ -1652,7 +1652,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv,
|
|||
/* Wait for transfer complete, then clear it */
|
||||
|
||||
qspi_waitstatusflags(priv, QSPI_SR_TCF, 1);
|
||||
qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR);
|
||||
|
||||
/* Use Abort to clear the Busy flag */
|
||||
|
||||
|
|
@ -1765,7 +1765,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
|
|||
* prescaler = STL32L4_QSPI_CLOCK / frequency
|
||||
*
|
||||
* Where prescaler can have the range 1 to 256 and the
|
||||
* STM32L4_QUADSPI_CR_OFFSET register field holds prescaler - 1.
|
||||
* STM32_QUADSPI_CR_OFFSET register field holds prescaler - 1.
|
||||
* NOTE that a "ceiling" type of calculation is performed.
|
||||
* 'frequency' is treated as a not-to-exceed value.
|
||||
*/
|
||||
|
|
@ -1785,10 +1785,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency)
|
|||
|
||||
/* Save the new prescaler value (minus one) */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~(QSPI_CR_PRESCALER_MASK);
|
||||
regval |= (prescaler - 1) << QSPI_CR_PRESCALER_SHIFT;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Calculate the new actual frequency */
|
||||
|
||||
|
|
@ -1850,7 +1850,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
|
|||
* 3 1 1
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_DCR);
|
||||
regval &= ~(QSPI_DCR_CKMODE);
|
||||
|
||||
switch (mode)
|
||||
|
|
@ -1870,7 +1870,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
|
|||
return;
|
||||
}
|
||||
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_DCR);
|
||||
spiinfo("DCR=%08" PRIx32 "\n", regval);
|
||||
|
||||
/* Save the mode so that subsequent re-configurations will be faster */
|
||||
|
|
@ -1957,9 +1957,9 @@ static int qspi_command(struct qspi_dev_s *dev,
|
|||
|
||||
qspi_putreg(priv,
|
||||
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
|
||||
STM32L4_QUADSPI_FCR);
|
||||
STM32_QUADSPI_FCR);
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
/* interrupt mode will need access to the transaction context */
|
||||
|
||||
priv->xctn = &xctn;
|
||||
|
|
@ -1983,16 +1983,16 @@ static int qspi_command(struct qspi_dev_s *dev,
|
|||
* Complete' interrupts.
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t addrval;
|
||||
|
||||
addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
|
||||
addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET);
|
||||
|
||||
/* Set up the Communications Configuration Register as per command
|
||||
* info
|
||||
|
|
@ -2002,15 +2002,15 @@ static int qspi_command(struct qspi_dev_s *dev,
|
|||
|
||||
/* Start the transfer by re-writing the address in AR register */
|
||||
|
||||
qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
|
||||
qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET);
|
||||
|
||||
/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer
|
||||
* Complete' interrupts
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -2023,9 +2023,9 @@ static int qspi_command(struct qspi_dev_s *dev,
|
|||
|
||||
/* Enable 'Transfer Error' and 'Transfer Complete' interrupts */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Set up the Communications Configuration Register as per command
|
||||
* info
|
||||
|
|
@ -2139,9 +2139,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||
|
||||
qspi_putreg(priv,
|
||||
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
|
||||
STM32L4_QUADSPI_FCR);
|
||||
STM32_QUADSPI_FCR);
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
/* interrupt mode will need access to the transaction context */
|
||||
|
||||
priv->xctn = &xctn;
|
||||
|
|
@ -2163,16 +2163,16 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||
* interrupts
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t addrval;
|
||||
|
||||
addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
|
||||
addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET);
|
||||
|
||||
/* Set up the Communications Configuration Register as per command
|
||||
* info
|
||||
|
|
@ -2182,15 +2182,15 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||
|
||||
/* Start the transfer by re-writing the address in AR register */
|
||||
|
||||
qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
|
||||
qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET);
|
||||
|
||||
/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
|
||||
* interrupts
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
}
|
||||
|
||||
/* Wait for the interrupt routine to finish it's magic */
|
||||
|
|
@ -2356,7 +2356,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
|
|||
|
||||
regval = 0;
|
||||
regval &= ~(QSPI_CR_EN);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Wait till BUSY flag reset */
|
||||
|
||||
|
|
@ -2364,7 +2364,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
|
|||
|
||||
/* Disable all interrupt sources for starters */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE |
|
||||
QSPI_CR_TOIE);
|
||||
|
||||
|
|
@ -2373,7 +2373,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
|
|||
regval &= ~(QSPI_CR_FTHRES_MASK);
|
||||
regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) <<
|
||||
QSPI_CR_FTHRES_SHIFT);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Wait till BUSY flag reset */
|
||||
|
||||
|
|
@ -2381,15 +2381,15 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
|
|||
|
||||
/* Configure QSPI Clock Prescaler and Sample Shift */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~(QSPI_CR_PRESCALER_MASK | QSPI_CR_SSHIFT);
|
||||
regval |= (0x01 << QSPI_CR_PRESCALER_SHIFT);
|
||||
regval |= (0x00);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Configure QSPI Flash Size, CS High Time and Clock Mode */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET);
|
||||
regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK);
|
||||
regval |= (0x00);
|
||||
regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT);
|
||||
|
|
@ -2406,13 +2406,13 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv)
|
|||
regval |= ((nlog2size - 1) << QSPI_DCR_FSIZE_SHIFT);
|
||||
}
|
||||
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_DCR_OFFSET);
|
||||
|
||||
/* Enable QSPI */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= QSPI_CR_EN;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
|
||||
/* Wait till BUSY flag reset */
|
||||
|
||||
|
|
@ -2467,18 +2467,18 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
|
|||
|
||||
/* Enable clocking to the QSPI peripheral */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_AHB3ENR);
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
regval |= RCC_AHB3ENR_QSPIEN;
|
||||
putreg32(regval, STM32L4_RCC_AHB3ENR);
|
||||
regval = getreg32(STM32L4_RCC_AHB3ENR);
|
||||
putreg32(regval, STM32_RCC_AHB3ENR);
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
|
||||
/* Reset the QSPI peripheral */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_AHB3RSTR);
|
||||
regval = getreg32(STM32_RCC_AHB3RSTR);
|
||||
regval |= RCC_AHB3RSTR_QSPIRST;
|
||||
putreg32(regval, STM32L4_RCC_AHB3RSTR);
|
||||
putreg32(regval, STM32_RCC_AHB3RSTR);
|
||||
regval &= ~RCC_AHB3RSTR_QSPIRST;
|
||||
putreg32(regval, STM32L4_RCC_AHB3RSTR);
|
||||
putreg32(regval, STM32_RCC_AHB3RSTR);
|
||||
|
||||
/* Configure multiplexed pins as connected on the board. */
|
||||
|
||||
|
|
@ -2515,7 +2515,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
/* Attach the interrupt handler */
|
||||
|
||||
ret = irq_attach(priv->irq, priv->handler, NULL);
|
||||
|
|
@ -2541,7 +2541,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
|
|||
|
||||
priv->initialized = true;
|
||||
priv->memmap = false;
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
up_enable_irq(priv->irq);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -2549,7 +2549,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
|
|||
return &priv->qspi;
|
||||
|
||||
errout_with_irq:
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
irq_detach(priv->irq);
|
||||
|
||||
errout_with_dmach:
|
||||
|
|
@ -2614,32 +2614,32 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev,
|
|||
* CS if memory is not accessed for a while)
|
||||
*/
|
||||
|
||||
qspi_putreg(priv, lpto, STM32L4_QUADSPI_LPTR_OFFSET);
|
||||
qspi_putreg(priv, lpto, STM32_QUADSPI_LPTR_OFFSET);
|
||||
|
||||
/* Clear Timeout interrupt */
|
||||
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR);
|
||||
qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR);
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
/* Enable Timeout interrupt */
|
||||
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval |= (QSPI_CR_TCEN | QSPI_CR_TOIE);
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||
regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET);
|
||||
regval &= ~QSPI_CR_TCEN;
|
||||
qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
|
||||
qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET);
|
||||
}
|
||||
|
||||
/* create a transaction object */
|
||||
|
||||
qspi_setupxctnfrommem(&xctn, meminfo);
|
||||
|
||||
#ifdef STM32L4_QSPI_INTERRUPTS
|
||||
#ifdef STM32_QSPI_INTERRUPTS
|
||||
priv->xctn = NULL;
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -108,14 +108,14 @@ static inline void rcc_resetbkp(void)
|
|||
init_stat = stm32l4_rtc_is_initialized();
|
||||
if (!init_stat)
|
||||
{
|
||||
uint32_t bkregs[STM32L4_RTC_BKCOUNT];
|
||||
uint32_t bkregs[STM32_RTC_BKCOUNT];
|
||||
int i;
|
||||
|
||||
/* Backup backup-registers before RTC reset. */
|
||||
|
||||
for (i = 0; i < STM32L4_RTC_BKCOUNT; i++)
|
||||
for (i = 0; i < STM32_RTC_BKCOUNT; i++)
|
||||
{
|
||||
bkregs[i] = getreg32(STM32L4_RTC_BKR(i));
|
||||
bkregs[i] = getreg32(STM32_RTC_BKR(i));
|
||||
}
|
||||
|
||||
/* Enable write access to the backup domain (RTC registers, RTC
|
||||
|
|
@ -128,19 +128,19 @@ static inline void rcc_resetbkp(void)
|
|||
* reset the backup domain (having backed up the RTC_MAGIC token)
|
||||
*/
|
||||
|
||||
modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST);
|
||||
modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0);
|
||||
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
|
||||
|
||||
/* Restore backup-registers, except RTC related. */
|
||||
|
||||
for (i = 0; i < STM32L4_RTC_BKCOUNT; i++)
|
||||
for (i = 0; i < STM32_RTC_BKCOUNT; i++)
|
||||
{
|
||||
if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i))
|
||||
if (RTC_MAGIC_REG == STM32_RTC_BKR(i))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
putreg32(bkregs[i], STM32L4_RTC_BKR(i));
|
||||
putreg32(bkregs[i], STM32_RTC_BKR(i));
|
||||
}
|
||||
|
||||
stm32l4_pwr_enablebkp(false);
|
||||
|
|
|
|||
|
|
@ -88,10 +88,10 @@ static inline void stm32l4_mcoconfig(uint32_t source)
|
|||
|
||||
/* Set MCO source */
|
||||
|
||||
regval = getreg32(STM32L4_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~(RCC_CFGR_MCO_MASK);
|
||||
regval |= (source & RCC_CFGR_MCO_MASK);
|
||||
putreg32(regval, STM32L4_RCC_CFGR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static int stm32l4_rng_initialize(void)
|
|||
{
|
||||
_info("Initializing RNG\n");
|
||||
|
||||
if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL))
|
||||
if (irq_attach(STM32_IRQ_RNG, stm32l4_rnginterrupt, NULL))
|
||||
{
|
||||
/* We could not attach the ISR to the interrupt */
|
||||
|
||||
|
|
@ -113,24 +113,24 @@ static void stm32l4_rngenable(void)
|
|||
|
||||
/* Enable generation and interrupts */
|
||||
|
||||
regval = getreg32(STM32L4_RNG_CR);
|
||||
regval = getreg32(STM32_RNG_CR);
|
||||
regval |= RNG_CR_RNGEN;
|
||||
regval |= RNG_CR_IE;
|
||||
putreg32(regval, STM32L4_RNG_CR);
|
||||
putreg32(regval, STM32_RNG_CR);
|
||||
|
||||
up_enable_irq(STM32L4_IRQ_RNG);
|
||||
up_enable_irq(STM32_IRQ_RNG);
|
||||
}
|
||||
|
||||
static void stm32l4_rngdisable(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
up_disable_irq(STM32L4_IRQ_RNG);
|
||||
up_disable_irq(STM32_IRQ_RNG);
|
||||
|
||||
regval = getreg32(STM32L4_RNG_CR);
|
||||
regval = getreg32(STM32_RNG_CR);
|
||||
regval &= ~RNG_CR_IE;
|
||||
regval &= ~RNG_CR_RNGEN;
|
||||
putreg32(regval, STM32L4_RNG_CR);
|
||||
putreg32(regval, STM32_RNG_CR);
|
||||
}
|
||||
|
||||
static int stm32l4_rnginterrupt(int irq, void *context, void *arg)
|
||||
|
|
@ -138,12 +138,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg)
|
|||
uint32_t rngsr;
|
||||
uint32_t data;
|
||||
|
||||
rngsr = getreg32(STM32L4_RNG_SR);
|
||||
rngsr = getreg32(STM32_RNG_SR);
|
||||
if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */
|
||||
{
|
||||
/* Clear it, we will try again. */
|
||||
|
||||
putreg32(rngsr & ~RNG_SR_CEIS, STM32L4_RNG_SR);
|
||||
putreg32(rngsr & ~RNG_SR_CEIS, STM32_RNG_SR);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -153,12 +153,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear seed error, then disable/enable the rng and try again. */
|
||||
|
||||
putreg32(rngsr & ~RNG_SR_SEIS, STM32L4_RNG_SR);
|
||||
crval = getreg32(STM32L4_RNG_CR);
|
||||
putreg32(rngsr & ~RNG_SR_SEIS, STM32_RNG_SR);
|
||||
crval = getreg32(STM32_RNG_CR);
|
||||
crval &= ~RNG_CR_RNGEN;
|
||||
putreg32(crval, STM32L4_RNG_CR);
|
||||
putreg32(crval, STM32_RNG_CR);
|
||||
crval |= RNG_CR_RNGEN;
|
||||
putreg32(crval, STM32L4_RNG_CR);
|
||||
putreg32(crval, STM32_RNG_CR);
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
@ -169,7 +169,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg)
|
|||
return OK;
|
||||
}
|
||||
|
||||
data = getreg32(STM32L4_RNG_DR);
|
||||
data = getreg32(STM32_RNG_DR);
|
||||
|
||||
/* As required by the FIPS PUB (Federal Information Processing Standard
|
||||
* Publication) 140-2, the first random number generated after setting the
|
||||
|
|
|
|||
|
|
@ -142,23 +142,23 @@ static inline void rtc_enable_alarm(void);
|
|||
static void rtc_dumpregs(const char *msg)
|
||||
{
|
||||
rtcinfo("%s:\n", msg);
|
||||
rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TR));
|
||||
rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_DR));
|
||||
rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CR));
|
||||
rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ISR));
|
||||
rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32L4_RTC_PRER));
|
||||
rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_WUTR));
|
||||
rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR));
|
||||
rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR));
|
||||
rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR));
|
||||
rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR));
|
||||
rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER));
|
||||
rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR));
|
||||
|
||||
rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR));
|
||||
rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR));
|
||||
rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_SHIFTR));
|
||||
rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSTR));
|
||||
rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSDR));
|
||||
rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSSSR));
|
||||
rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CALR));
|
||||
rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TAMPCR));
|
||||
rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMASSR));
|
||||
rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBSSR));
|
||||
rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR));
|
||||
rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR));
|
||||
rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR));
|
||||
rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR));
|
||||
rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR));
|
||||
rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR));
|
||||
rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR));
|
||||
rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR));
|
||||
rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR));
|
||||
rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR));
|
||||
rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG));
|
||||
}
|
||||
#else
|
||||
|
|
@ -220,8 +220,8 @@ static void rtc_wprunlock(void)
|
|||
* Writing a wrong key re-activates the write protection.
|
||||
*/
|
||||
|
||||
putreg32(0xca, STM32L4_RTC_WPR);
|
||||
putreg32(0x53, STM32L4_RTC_WPR);
|
||||
putreg32(0xca, STM32_RTC_WPR);
|
||||
putreg32(0x53, STM32_RTC_WPR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -242,7 +242,7 @@ static inline void rtc_wprlock(void)
|
|||
{
|
||||
/* Writing any wrong key re-activates the write protection. */
|
||||
|
||||
putreg32(0xff, STM32L4_RTC_WPR);
|
||||
putreg32(0xff, STM32_RTC_WPR);
|
||||
|
||||
/* Disable write access to the backup domain. */
|
||||
|
||||
|
|
@ -272,16 +272,16 @@ static int rtc_synchwait(void)
|
|||
|
||||
/* Clear Registers synchronization flag (RSF) */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
regval &= ~RTC_ISR_RSF;
|
||||
putreg32(regval, STM32L4_RTC_ISR);
|
||||
putreg32(regval, STM32_RTC_ISR);
|
||||
|
||||
/* Now wait the registers to become synchronised */
|
||||
|
||||
ret = -ETIMEDOUT;
|
||||
for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++)
|
||||
{
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
if ((regval & RTC_ISR_RSF) != 0)
|
||||
{
|
||||
/* Synchronized */
|
||||
|
|
@ -316,21 +316,21 @@ static int rtc_enterinit(void)
|
|||
|
||||
/* Check if the Initialization mode is already set */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
|
||||
ret = OK;
|
||||
if ((regval & RTC_ISR_INITF) == 0)
|
||||
{
|
||||
/* Set the Initialization mode */
|
||||
|
||||
putreg32(RTC_ISR_INIT, STM32L4_RTC_ISR);
|
||||
putreg32(RTC_ISR_INIT, STM32_RTC_ISR);
|
||||
|
||||
/* Wait until the RTC is in the INIT state (or a timeout occurs) */
|
||||
|
||||
ret = -ETIMEDOUT;
|
||||
for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++)
|
||||
{
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
if ((regval & RTC_ISR_INITF) != 0)
|
||||
{
|
||||
ret = OK;
|
||||
|
|
@ -360,9 +360,9 @@ static void rtc_exitinit(void)
|
|||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
regval &= ~(RTC_ISR_INIT);
|
||||
putreg32(regval, STM32L4_RTC_ISR);
|
||||
putreg32(regval, STM32_RTC_ISR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -434,13 +434,13 @@ static void rtc_resume(void)
|
|||
|
||||
/* Clear the RTC alarm flags */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF);
|
||||
putreg32(regval, STM32L4_RTC_ISR);
|
||||
putreg32(regval, STM32_RTC_ISR);
|
||||
|
||||
/* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */
|
||||
|
||||
putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR);
|
||||
putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -478,10 +478,10 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context,
|
|||
|
||||
/* Check for EXTI from Alarm A or B and handle according */
|
||||
|
||||
cr = getreg32(STM32L4_RTC_CR);
|
||||
cr = getreg32(STM32_RTC_CR);
|
||||
if ((cr & RTC_CR_ALRAIE) != 0)
|
||||
{
|
||||
isr = getreg32(STM32L4_RTC_ISR);
|
||||
isr = getreg32(STM32_RTC_ISR);
|
||||
if ((isr & RTC_ISR_ALRAF) != 0)
|
||||
{
|
||||
cbinfo = &g_alarmcb[RTC_ALARMA];
|
||||
|
|
@ -500,17 +500,17 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context,
|
|||
|
||||
/* note, bits 8-13 do /not/ require the write enable procedure */
|
||||
|
||||
isr = getreg32(STM32L4_RTC_ISR);
|
||||
isr = getreg32(STM32_RTC_ISR);
|
||||
isr &= ~RTC_ISR_ALRAF;
|
||||
putreg32(isr, STM32L4_RTC_ISR);
|
||||
putreg32(isr, STM32_RTC_ISR);
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG_RTC_NALARMS > 1
|
||||
cr = getreg32(STM32L4_RTC_CR);
|
||||
cr = getreg32(STM32_RTC_CR);
|
||||
if ((cr & RTC_CR_ALRBIE) != 0)
|
||||
{
|
||||
isr = getreg32(STM32L4_RTC_ISR);
|
||||
isr = getreg32(STM32_RTC_ISR);
|
||||
if ((isr & RTC_ISR_ALRBF) != 0)
|
||||
{
|
||||
cbinfo = &g_alarmcb[RTC_ALARMB];
|
||||
|
|
@ -529,9 +529,9 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context,
|
|||
|
||||
/* note, bits 8-13 do /not/ require the write enable procedure */
|
||||
|
||||
isr = getreg32(STM32L4_RTC_ISR);
|
||||
isr = getreg32(STM32_RTC_ISR);
|
||||
isr &= ~RTC_ISR_ALRBF;
|
||||
putreg32(isr, STM32L4_RTC_ISR);
|
||||
putreg32(isr, STM32_RTC_ISR);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -574,7 +574,7 @@ static int rtchw_check_alrawf(void)
|
|||
|
||||
for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++)
|
||||
{
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
if ((regval & RTC_ISR_ALRAWF) != 0)
|
||||
{
|
||||
ret = OK;
|
||||
|
|
@ -600,7 +600,7 @@ static int rtchw_check_alrbwf(void)
|
|||
|
||||
for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++)
|
||||
{
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
if ((regval & RTC_ISR_ALRBWF) != 0)
|
||||
{
|
||||
ret = OK;
|
||||
|
|
@ -639,12 +639,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg)
|
|||
|
||||
/* Disable RTC alarm A & Interrupt A */
|
||||
|
||||
modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0);
|
||||
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0);
|
||||
|
||||
/* Ensure Alarm A flag reset; this is edge triggered */
|
||||
|
||||
isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF;
|
||||
putreg32(isr, STM32L4_RTC_ISR);
|
||||
isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF;
|
||||
putreg32(isr, STM32_RTC_ISR);
|
||||
|
||||
/* Wait for Alarm A to be writable */
|
||||
|
||||
|
|
@ -656,13 +656,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg)
|
|||
|
||||
/* Set the RTC Alarm A register */
|
||||
|
||||
putreg32(alarmreg, STM32L4_RTC_ALRMAR);
|
||||
putreg32(0, STM32L4_RTC_ALRMASSR);
|
||||
rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR));
|
||||
putreg32(alarmreg, STM32_RTC_ALRMAR);
|
||||
putreg32(0, STM32_RTC_ALRMASSR);
|
||||
rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR));
|
||||
|
||||
/* Enable RTC alarm A */
|
||||
|
||||
modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
|
||||
modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
|
||||
|
||||
errout_with_wprunlock:
|
||||
rtc_wprlock();
|
||||
|
|
@ -682,12 +682,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
|
|||
|
||||
/* Disable RTC alarm B & Interrupt B */
|
||||
|
||||
modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0);
|
||||
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0);
|
||||
|
||||
/* Ensure Alarm B flag reset; this is edge triggered */
|
||||
|
||||
isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF;
|
||||
putreg32(isr, STM32L4_RTC_ISR);
|
||||
isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF;
|
||||
putreg32(isr, STM32_RTC_ISR);
|
||||
|
||||
/* Wait for Alarm B to be writable */
|
||||
|
||||
|
|
@ -699,13 +699,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
|
|||
|
||||
/* Set the RTC Alarm B register */
|
||||
|
||||
putreg32(alarmreg, STM32L4_RTC_ALRMBR);
|
||||
putreg32(0, STM32L4_RTC_ALRMBSSR);
|
||||
rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR));
|
||||
putreg32(alarmreg, STM32_RTC_ALRMBR);
|
||||
putreg32(0, STM32_RTC_ALRMBSSR);
|
||||
rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR));
|
||||
|
||||
/* Enable RTC alarm B */
|
||||
|
||||
modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
|
||||
modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
|
||||
|
||||
rtchw_set_alrmbr_exit:
|
||||
rtc_wprlock();
|
||||
|
|
@ -870,13 +870,13 @@ int up_rtc_initialize(void)
|
|||
stm32l4_pwr_enablebkp(true);
|
||||
|
||||
#if defined(CONFIG_STM32L4_RTC_HSECLOCK)
|
||||
modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK,
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK,
|
||||
RCC_BDCR_RTCSEL_HSE);
|
||||
#elif defined(CONFIG_STM32L4_RTC_LSICLOCK)
|
||||
modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK,
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK,
|
||||
RCC_BDCR_RTCSEL_LSI);
|
||||
#elif defined(CONFIG_STM32L4_RTC_LSECLOCK)
|
||||
modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK,
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK,
|
||||
RCC_BDCR_RTCSEL_LSE);
|
||||
#else
|
||||
# error "No clock for RTC!"
|
||||
|
|
@ -884,7 +884,7 @@ int up_rtc_initialize(void)
|
|||
|
||||
/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
|
||||
|
||||
modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN);
|
||||
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
|
||||
|
||||
/* Disable the write protection for RTC registers */
|
||||
|
||||
|
|
@ -912,9 +912,9 @@ int up_rtc_initialize(void)
|
|||
{
|
||||
/* Clear RTC_CR FMT, OSEL and POL Bits */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_CR);
|
||||
regval = getreg32(STM32_RTC_CR);
|
||||
regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL);
|
||||
putreg32(regval, STM32L4_RTC_CR);
|
||||
putreg32(regval, STM32_RTC_CR);
|
||||
|
||||
/* Configure RTC pre-scaler with the required values */
|
||||
|
||||
|
|
@ -930,7 +930,7 @@ int up_rtc_initialize(void)
|
|||
|
||||
putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) |
|
||||
((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT),
|
||||
STM32L4_RTC_PRER);
|
||||
STM32_RTC_PRER);
|
||||
#elif defined(CONFIG_STM32L4_RTC_LSICLOCK)
|
||||
/* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz,
|
||||
* though)
|
||||
|
|
@ -938,13 +938,13 @@ int up_rtc_initialize(void)
|
|||
|
||||
putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) |
|
||||
((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT),
|
||||
STM32L4_RTC_PRER);
|
||||
STM32_RTC_PRER);
|
||||
#else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */
|
||||
/* Correct values for 32.768 KHz LSE clock */
|
||||
|
||||
putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) |
|
||||
((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT),
|
||||
STM32L4_RTC_PRER);
|
||||
STM32_RTC_PRER);
|
||||
#endif
|
||||
|
||||
/* Exit Initialization mode */
|
||||
|
|
@ -1038,18 +1038,18 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp,
|
|||
|
||||
do
|
||||
{
|
||||
dr = getreg32(STM32L4_RTC_DR);
|
||||
tr = getreg32(STM32L4_RTC_TR);
|
||||
dr = getreg32(STM32_RTC_DR);
|
||||
tr = getreg32(STM32_RTC_TR);
|
||||
#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS
|
||||
ssr = getreg32(STM32L4_RTC_SSR);
|
||||
tmp = getreg32(STM32L4_RTC_TR);
|
||||
ssr = getreg32(STM32_RTC_SSR);
|
||||
tmp = getreg32(STM32_RTC_TR);
|
||||
if (tmp != tr)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
tmp = getreg32(STM32L4_RTC_DR);
|
||||
tmp = getreg32(STM32_RTC_DR);
|
||||
if (tmp == dr)
|
||||
{
|
||||
break;
|
||||
|
|
@ -1108,7 +1108,7 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp,
|
|||
uint32_t prediv_s;
|
||||
uint32_t usecs;
|
||||
|
||||
prediv_s = getreg32(STM32L4_RTC_PRER) & RTC_PRER_PREDIV_S_MASK;
|
||||
prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK;
|
||||
prediv_s >>= RTC_PRER_PREDIV_S_SHIFT;
|
||||
|
||||
ssr &= RTC_SSR_MASK;
|
||||
|
|
@ -1255,8 +1255,8 @@ int stm32l4_rtc_setdatetime(const struct tm *tp)
|
|||
{
|
||||
/* Set the RTC TR and DR registers */
|
||||
|
||||
putreg32(tr, STM32L4_RTC_TR);
|
||||
putreg32(dr, STM32L4_RTC_DR);
|
||||
putreg32(tr, STM32_RTC_TR);
|
||||
putreg32(dr, STM32_RTC_DR);
|
||||
|
||||
/* Exit Initialization mode and wait for the RTC Time and Date
|
||||
* registers to be synchronized with RTC APB clock.
|
||||
|
|
@ -1452,7 +1452,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
|
|||
|
||||
/* Disable RTC alarm and interrupt */
|
||||
|
||||
modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0);
|
||||
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0);
|
||||
|
||||
ret = rtchw_check_alrawf();
|
||||
if (ret < 0)
|
||||
|
|
@ -1462,8 +1462,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
|
|||
|
||||
/* Unset the alarm */
|
||||
|
||||
putreg32(-1, STM32L4_RTC_ALRMAR);
|
||||
modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0);
|
||||
putreg32(-1, STM32_RTC_ALRMAR);
|
||||
modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0);
|
||||
rtc_wprlock();
|
||||
ret = OK;
|
||||
}
|
||||
|
|
@ -1483,7 +1483,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
|
|||
|
||||
/* Disable RTC alarm and interrupt */
|
||||
|
||||
modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0);
|
||||
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0);
|
||||
|
||||
ret = rtchw_check_alrbwf();
|
||||
if (ret < 0)
|
||||
|
|
@ -1493,8 +1493,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid)
|
|||
|
||||
/* Unset the alarm */
|
||||
|
||||
putreg32(-1, STM32L4_RTC_ALRMBR);
|
||||
modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0);
|
||||
putreg32(-1, STM32_RTC_ALRMBR);
|
||||
modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0);
|
||||
rtc_wprlock();
|
||||
ret = OK;
|
||||
}
|
||||
|
|
@ -1541,7 +1541,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo)
|
|||
{
|
||||
case RTC_ALARMA:
|
||||
{
|
||||
alarmreg = STM32L4_RTC_ALRMAR;
|
||||
alarmreg = STM32_RTC_ALRMAR;
|
||||
ret = stm32l4_rtc_getalarmdatetime(alarmreg,
|
||||
(struct tm *)alminfo->ar_time);
|
||||
}
|
||||
|
|
@ -1550,7 +1550,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo)
|
|||
#if CONFIG_RTC_NALARMS > 1
|
||||
case RTC_ALARMB:
|
||||
{
|
||||
alarmreg = STM32L4_RTC_ALRMBR;
|
||||
alarmreg = STM32_RTC_ALRMBR;
|
||||
ret = stm32l4_rtc_getalarmdatetime(alarmreg,
|
||||
(struct tm *)alminfo->ar_time);
|
||||
}
|
||||
|
|
@ -1588,9 +1588,9 @@ static int stm32l4_rtc_wakeup_handler(int irq, void *context,
|
|||
|
||||
stm32l4_pwr_enablebkp(true);
|
||||
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
regval &= ~RTC_ISR_WUTF;
|
||||
putreg32(regval, STM32L4_RTC_ISR);
|
||||
putreg32(regval, STM32_RTC_ISR);
|
||||
|
||||
stm32l4_pwr_enablebkp(false);
|
||||
|
||||
|
|
@ -1636,10 +1636,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel)
|
|||
{
|
||||
uint32_t regval = 0;
|
||||
|
||||
regval = getreg32(STM32L4_RTC_CR);
|
||||
regval = getreg32(STM32_RTC_CR);
|
||||
regval &= ~RTC_CR_WUCKSEL_MASK;
|
||||
regval |= wucksel;
|
||||
putreg32(regval, STM32L4_RTC_CR);
|
||||
putreg32(regval, STM32_RTC_CR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1675,7 +1675,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period,
|
|||
# error "Periodic wakeup not available for LSI (and it is too inaccurate!)"
|
||||
#elif defined(CONFIG_STM32L4_RTC_LSECLOCK)
|
||||
const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu /
|
||||
STM32L4_LSE_FREQUENCY;
|
||||
STM32_LSE_FREQUENCY;
|
||||
#else
|
||||
# error "No clock for RTC!"
|
||||
#endif
|
||||
|
|
@ -1713,9 +1713,9 @@ int stm32l4_rtc_setperiodic(const struct timespec *period,
|
|||
|
||||
/* Clear WUTE in RTC_CR to disable the wakeup timer */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_CR);
|
||||
regval = getreg32(STM32_RTC_CR);
|
||||
regval &= ~RTC_CR_WUTE;
|
||||
putreg32(regval, STM32L4_RTC_CR);
|
||||
putreg32(regval, STM32_RTC_CR);
|
||||
|
||||
/* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK
|
||||
* clock cycles)
|
||||
|
|
@ -1724,7 +1724,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period,
|
|||
ret = -ETIMEDOUT;
|
||||
for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++)
|
||||
{
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
if ((regval & RTC_ISR_WUTWF) != 0)
|
||||
{
|
||||
/* Synchronized */
|
||||
|
|
@ -1748,7 +1748,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period,
|
|||
|
||||
/* Get number of ticks. */
|
||||
|
||||
ticks = millisecs * STM32L4_LSE_FREQUENCY / (16 * 1000);
|
||||
ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000);
|
||||
|
||||
/* Wake-up is after WUT+1 ticks. */
|
||||
|
||||
|
|
@ -1769,17 +1769,17 @@ int stm32l4_rtc_setperiodic(const struct timespec *period,
|
|||
* selection.
|
||||
*/
|
||||
|
||||
putreg32(wutr_val, STM32L4_RTC_WUTR);
|
||||
putreg32(wutr_val, STM32_RTC_WUTR);
|
||||
|
||||
regval = getreg32(STM32L4_RTC_CR);
|
||||
regval = getreg32(STM32_RTC_CR);
|
||||
regval |= RTC_CR_WUTIE | RTC_CR_WUTE;
|
||||
putreg32(regval, STM32L4_RTC_CR);
|
||||
putreg32(regval, STM32_RTC_CR);
|
||||
|
||||
/* Just in case resets the WUTF flag in RTC_ISR */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
regval &= ~RTC_ISR_WUTF;
|
||||
putreg32(regval, STM32L4_RTC_ISR);
|
||||
putreg32(regval, STM32_RTC_ISR);
|
||||
|
||||
rtc_wprlock();
|
||||
|
||||
|
|
@ -1811,9 +1811,9 @@ int stm32l4_rtc_cancelperiodic(void)
|
|||
|
||||
/* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_CR);
|
||||
regval = getreg32(STM32_RTC_CR);
|
||||
regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE);
|
||||
putreg32(regval, STM32L4_RTC_CR);
|
||||
putreg32(regval, STM32_RTC_CR);
|
||||
|
||||
/* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK
|
||||
* clock cycles)
|
||||
|
|
@ -1822,7 +1822,7 @@ int stm32l4_rtc_cancelperiodic(void)
|
|||
ret = -ETIMEDOUT;
|
||||
for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++)
|
||||
{
|
||||
regval = getreg32(STM32L4_RTC_ISR);
|
||||
regval = getreg32(STM32_RTC_ISR);
|
||||
if ((regval & RTC_ISR_WUTWF) != 0)
|
||||
{
|
||||
/* Synchronized */
|
||||
|
|
@ -1834,9 +1834,9 @@ int stm32l4_rtc_cancelperiodic(void)
|
|||
|
||||
/* Clears RTC_WUTR register */
|
||||
|
||||
regval = getreg32(STM32L4_RTC_WUTR);
|
||||
regval = getreg32(STM32_RTC_WUTR);
|
||||
regval &= ~RTC_WUTR_MASK;
|
||||
putreg32(regval, STM32L4_RTC_WUTR);
|
||||
putreg32(regval, STM32_RTC_WUTR);
|
||||
|
||||
rtc_wprlock();
|
||||
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
|
||||
#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
|
||||
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
|
||||
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
|
||||
|
||||
#if !defined(CONFIG_STM32L4_RTC_MAGIC)
|
||||
# define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee)
|
||||
|
|
@ -55,7 +55,7 @@
|
|||
|
||||
#define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC
|
||||
#define RTC_MAGIC_TIME_SET CONFIG_STM32L4_RTC_MAGIC_TIME_SET
|
||||
#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG)
|
||||
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32L4_NALARMS 2
|
||||
#define STM32_NALARMS 2
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
|
|
@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s
|
|||
#ifdef CONFIG_RTC_ALARM
|
||||
/* Alarm callback information */
|
||||
|
||||
struct stm32l4_cbinfo_s cbinfo[STM32L4_NALARMS];
|
||||
struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTC_PERIODIC
|
||||
|
|
|
|||
|
|
@ -233,9 +233,9 @@ static const struct i2s_ops_s g_i2sops =
|
|||
static struct stm32l4_sai_s g_sai1a_priv =
|
||||
{
|
||||
.dev.ops = &g_i2sops,
|
||||
.base = STM32L4_SAI1_A_BASE,
|
||||
.base = STM32_SAI1_A_BASE,
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
.frequency = STM32L4_SAI1_FREQUENCY,
|
||||
.frequency = STM32_SAI1_FREQUENCY,
|
||||
#ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B
|
||||
.syncen = SAI_CR1_SYNCEN_SYNC_INT,
|
||||
#else
|
||||
|
|
@ -254,9 +254,9 @@ static struct stm32l4_sai_s g_sai1a_priv =
|
|||
static struct stm32l4_sai_s g_sai1b_priv =
|
||||
{
|
||||
.dev.ops = &g_i2sops,
|
||||
.base = STM32L4_SAI1_B_BASE,
|
||||
.base = STM32_SAI1_B_BASE,
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
.frequency = STM32L4_SAI1_FREQUENCY,
|
||||
.frequency = STM32_SAI1_FREQUENCY,
|
||||
#ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A
|
||||
.syncen = SAI_CR1_SYNCEN_SYNC_INT,
|
||||
#else
|
||||
|
|
@ -277,9 +277,9 @@ static struct stm32l4_sai_s g_sai1b_priv =
|
|||
static struct stm32l4_sai_s g_sai2a_priv =
|
||||
{
|
||||
.dev.ops = &g_i2sops,
|
||||
.base = STM32L4_SAI2_A_BASE,
|
||||
.base = STM32_SAI2_A_BASE,
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
.frequency = STM32L4_SAI2_FREQUENCY,
|
||||
.frequency = STM32_SAI2_FREQUENCY,
|
||||
#ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B
|
||||
.syncen = SAI_CR1_SYNCEN_SYNC_INT,
|
||||
#else
|
||||
|
|
@ -298,9 +298,9 @@ static struct stm32l4_sai_s g_sai2a_priv =
|
|||
static struct stm32l4_sai_s g_sai2b_priv =
|
||||
{
|
||||
.dev.ops = &g_i2sops,
|
||||
.base = STM32L4_SAI2_B_BASE,
|
||||
.base = STM32_SAI2_B_BASE,
|
||||
.lock = NXMUTEX_INITIALIZER,
|
||||
.frequency = STM32L4_SAI2_FREQUENCY,
|
||||
.frequency = STM32_SAI2_FREQUENCY,
|
||||
#ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A
|
||||
.syncen = SAI_CR1_SYNCEN_SYNC_INT,
|
||||
#else
|
||||
|
|
@ -433,14 +433,14 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg)
|
|||
|
||||
i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32
|
||||
" FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n",
|
||||
sai_getreg(priv, STM32L4_SAI_CR1_OFFSET),
|
||||
sai_getreg(priv, STM32L4_SAI_CR2_OFFSET),
|
||||
sai_getreg(priv, STM32L4_SAI_FRCR_OFFSET),
|
||||
sai_getreg(priv, STM32L4_SAI_SLOTR_OFFSET));
|
||||
sai_getreg(priv, STM32_SAI_CR1_OFFSET),
|
||||
sai_getreg(priv, STM32_SAI_CR2_OFFSET),
|
||||
sai_getreg(priv, STM32_SAI_FRCR_OFFSET),
|
||||
sai_getreg(priv, STM32_SAI_SLOTR_OFFSET));
|
||||
i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n",
|
||||
sai_getreg(priv, STM32L4_SAI_IM_OFFSET),
|
||||
sai_getreg(priv, STM32L4_SAI_SR_OFFSET),
|
||||
sai_getreg(priv, STM32L4_SAI_CLRFR_OFFSET));
|
||||
sai_getreg(priv, STM32_SAI_IM_OFFSET),
|
||||
sai_getreg(priv, STM32_SAI_SR_OFFSET),
|
||||
sai_getreg(priv, STM32_SAI_CLRFR_OFFSET));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -474,7 +474,7 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv)
|
|||
|
||||
mckdiv = priv->frequency / (priv->samplerate * 2 * 256);
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK,
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK,
|
||||
mckdiv << SAI_CR1_MCKDIV_SHIFT);
|
||||
}
|
||||
|
||||
|
|
@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv)
|
|||
|
||||
DEBUGASSERT(ntransfers > 0);
|
||||
|
||||
stm32l4_dmasetup(priv->dma, priv->base + STM32L4_SAI_DR_OFFSET,
|
||||
stm32l4_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET,
|
||||
samp, ntransfers, priv->dma_ccr);
|
||||
|
||||
/* Add the container to the list of active DMAs */
|
||||
|
|
@ -634,7 +634,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv)
|
|||
|
||||
/* Enable the transmitter */
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN);
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN);
|
||||
|
||||
/* Start a watchdog to catch DMA timeouts */
|
||||
|
||||
|
|
@ -901,9 +901,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits)
|
|||
return 0;
|
||||
}
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits);
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits);
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET,
|
||||
sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET,
|
||||
SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK,
|
||||
SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2));
|
||||
|
||||
|
|
@ -981,7 +981,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
|
|||
}
|
||||
|
||||
mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX;
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode);
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode);
|
||||
priv->rxenab = true;
|
||||
|
||||
/* Add a reference to the audio buffer */
|
||||
|
|
@ -1086,7 +1086,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
|
|||
}
|
||||
|
||||
mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX;
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode);
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode);
|
||||
priv->txenab = true;
|
||||
|
||||
/* Add a reference to the audio buffer */
|
||||
|
|
@ -1275,21 +1275,21 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv)
|
|||
priv->dma = stm32l4_dmachannel(priv->dma_ch);
|
||||
DEBUGASSERT(priv->dma);
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN);
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN);
|
||||
#endif
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK,
|
||||
sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK,
|
||||
priv->syncen);
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK,
|
||||
sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK,
|
||||
SAI_CR2_FTH_1QF);
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET,
|
||||
sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET,
|
||||
SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF,
|
||||
SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW |
|
||||
SAI_FRCR_FSOFF_BFB);
|
||||
|
||||
sai_modifyreg(priv, STM32L4_SAI_SLOTR_OFFSET,
|
||||
sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET,
|
||||
SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK,
|
||||
SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 |
|
||||
SAI_SLOTR_SLOTEN_1);
|
||||
|
|
|
|||
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Reference in a new issue