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!arch/stm32wl5: unify non-standard hardware definition prefixes
BREAKING CHANGE: STM32WL5 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
Alan C. Assis
parent
61e6b87dde
commit
28c02dea3e
39 changed files with 1471 additions and 1471 deletions
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@ -34,28 +34,28 @@
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****************************************************************************/
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#if defined(CONFIG_STM32WL5_STM32WL5XXX)
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# define STM32WL5_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */
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# define STM32WL5_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */
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# define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L5 chip"
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#endif
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#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1)
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# define STM32WL5_NATIM 1 /* One advanced timer TIM1 */
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# define STM32WL5_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32WL5_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */
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# define STM32WL5_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */
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# define STM32WL5_NRNG 1 /* Random number generator (RNG) */
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# define STM32WL5_NUSART 2 /* USART 1-2 */
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# define STM32WL5_NLPUART 1 /* LPUART 1 */
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# define STM32WL5_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */
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# define STM32WL5_NI2C 3 /* I2C1-3 */
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# define STM32WL5_NDMA 2 /* Two DMA channels DMA1-2 */
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# define STM32WL5_NPORTS 4 /* GPIO{A,B,C,H} */
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# define STM32WL5_NADC 1 /* ADC1 */
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# define STM32WL5_NDAC 1 /* DAC1 */
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# define STM32WL5_NCRC 1 /* CRC1 */
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# define STM32WL5_NCOMP 1 /* COMP1 */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */
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# define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUSART 2 /* USART 1-2 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */
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# define STM32_NI2C 3 /* I2C1-3 */
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# define STM32_NDMA 2 /* Two DMA channels DMA1-2 */
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# define STM32_NPORTS 4 /* GPIO{A,B,C,H} */
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 1 /* DAC1 */
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# define STM32_NCRC 1 /* CRC1 */
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# define STM32_NCOMP 1 /* COMP1 */
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#endif /* CONFIG_STM32WL5_STM32WL5XXX */
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/* NVIC priority levels *****************************************************/
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@ -44,26 +44,26 @@
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/* Processor Exceptions (vectors 0-15) */
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#define STM32WL5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define STM32WL5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define STM32WL5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define STM32WL5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define STM32WL5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define STM32WL5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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/* Vectors 7-10: Reserved */
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#define STM32WL5_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define STM32WL5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define STM32WL5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define STM32WL5_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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/* Vectors 7-10: Reserved */
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#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are
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* chip-specific
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*/
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#define STM32WL5_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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/****************************************************************************
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* Included Files
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@ -48,80 +48,80 @@
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* External interrupts (vectors >= 16)
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*/
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#define STM32WL5_IRQ_WWDG (STM32WL5_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */
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#define STM32WL5_IRQ_PVD (STM32WL5_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */
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#define STM32WL5_IRQ_PVM (STM32WL5_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */
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#define STM32WL5_IRQ_TAMPER (STM32WL5_IRQ_FIRST + 2) /* 2: Tamper */
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#define STM32WL5_IRQ_LSE_CSS (STM32WL5_IRQ_FIRST + 2) /* 2: LSECSS */
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#define STM32WL5_IRQ_RTC_STAMP (STM32WL5_IRQ_FIRST + 2) /* 2: timestamp */
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#define STM32WL5_IRQ_RTC_SSRU (STM32WL5_IRQ_FIRST + 2) /* 2: RTC SSR underflow */
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#define STM32WL5_IRQ_RTC_WKUP (STM32WL5_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */
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#define STM32WL5_IRQ_FLASH (STM32WL5_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */
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#define STM32WL5_IRQ_RCC (STM32WL5_IRQ_FIRST + 5) /* 5: RCC global interrupt */
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#define STM32WL5_IRQ_EXTI0 (STM32WL5_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */
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#define STM32WL5_IRQ_EXTI1 (STM32WL5_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */
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#define STM32WL5_IRQ_EXTI2 (STM32WL5_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */
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#define STM32WL5_IRQ_EXTI3 (STM32WL5_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */
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#define STM32WL5_IRQ_EXTI4 (STM32WL5_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */
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#define STM32WL5_IRQ_DMA1CH1 (STM32WL5_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */
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#define STM32WL5_IRQ_DMA1CH2 (STM32WL5_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */
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#define STM32WL5_IRQ_DMA1CH3 (STM32WL5_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */
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#define STM32WL5_IRQ_DMA1CH4 (STM32WL5_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */
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#define STM32WL5_IRQ_DMA1CH5 (STM32WL5_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */
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#define STM32WL5_IRQ_DMA1CH6 (STM32WL5_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */
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#define STM32WL5_IRQ_DMA1CH7 (STM32WL5_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */
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#define STM32WL5_IRQ_ADC (STM32WL5_IRQ_FIRST + 18) /* 18: ADC global interrupt */
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#define STM32WL5_IRQ_DAC (STM32WL5_IRQ_FIRST + 19) /* 19: DAC global interrupt */
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#define STM32WL5_IRQ_C2SEV (STM32WL5_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */
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#define STM32WL5_IRQ_PWRC2H (STM32WL5_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */
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#define STM32WL5_IRQ_COMP (STM32WL5_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */
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#define STM32WL5_IRQ_EXTI95 (STM32WL5_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */
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#define STM32WL5_IRQ_TIM1BRK (STM32WL5_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */
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#define STM32WL5_IRQ_TIM1UP (STM32WL5_IRQ_FIRST + 24) /* 24: Timer 1 Update */
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#define STM32WL5_IRQ_TIM1TRG_COM (STM32WL5_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */
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#define STM32WL5_IRQ_TIM1CC (STM32WL5_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */
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#define STM32WL5_IRQ_TIM2 (STM32WL5_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */
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#define STM32WL5_IRQ_TIM16 (STM32WL5_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */
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#define STM32WL5_IRQ_TIM17 (STM32WL5_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */
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#define STM32WL5_IRQ_I2C1EV (STM32WL5_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */
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#define STM32WL5_IRQ_I2C1ER (STM32WL5_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */
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#define STM32WL5_IRQ_I2C2EV (STM32WL5_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */
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#define STM32WL5_IRQ_I2C2ER (STM32WL5_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */
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#define STM32WL5_IRQ_SPI1 (STM32WL5_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */
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#define STM32WL5_IRQ_SPI2S2 (STM32WL5_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */
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#define STM32WL5_IRQ_USART1 (STM32WL5_IRQ_FIRST + 36) /* 36: USART1 global interrupt */
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#define STM32WL5_IRQ_USART2 (STM32WL5_IRQ_FIRST + 37) /* 37: USART2 global interrupt */
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#define STM32WL5_IRQ_LPUART1 (STM32WL5_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */
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#define STM32WL5_IRQ_LPTIM1 (STM32WL5_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */
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#define STM32WL5_IRQ_LPTIM2 (STM32WL5_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */
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#define STM32WL5_IRQ_EXTI1510 (STM32WL5_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */
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#define STM32WL5_IRQ_RTCALRM (STM32WL5_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */
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#define STM32WL5_IRQ_LPTIM3 (STM32WL5_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */
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/* 44: Reserved */
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#define STM32WL5_IRQ_IPCC_C1_RX_IT (STM32WL5_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */
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#define STM32WL5_IRQ_IPCC_C1_TX_IT (STM32WL5_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */
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#define STM32WL5_IRQ_HSEM (STM32WL5_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */
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#define STM32WL5_IRQ_I2C3EV (STM32WL5_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */
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#define STM32WL5_IRQ_I2C3ER (STM32WL5_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */
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#define STM32WL5_IRQ_RADIO (STM32WL5_IRQ_FIRST + 50) /* 50: Radio */
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#define STM32WL5_IRQ_RFBUSY (STM32WL5_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */
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#define STM32WL5_IRQ_AES (STM32WL5_IRQ_FIRST + 51) /* 51: AES global interrupt */
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#define STM32WL5_IRQ_RNG (STM32WL5_IRQ_FIRST + 52) /* 52: True random number generator interrupt */
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#define STM32WL5_IRQ_PKA (STM32WL5_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */
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#define STM32WL5_IRQ_DMA2CH1 (STM32WL5_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */
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#define STM32WL5_IRQ_DMA2CH2 (STM32WL5_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */
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#define STM32WL5_IRQ_DMA2CH3 (STM32WL5_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */
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#define STM32WL5_IRQ_DMA2CH4 (STM32WL5_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */
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#define STM32WL5_IRQ_DMA2CH5 (STM32WL5_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */
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#define STM32WL5_IRQ_DMA2CH6 (STM32WL5_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */
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#define STM32WL5_IRQ_DMA2CH7 (STM32WL5_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */
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#define STM32WL5_IRQ_DMAMUX1_OVR (STM32WL5_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */
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#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */
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#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */
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#define STM32_IRQ_PVM (STM32_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */
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#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper */
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#define STM32_IRQ_LSE_CSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS */
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#define STM32_IRQ_RTC_STAMP (STM32_IRQ_FIRST + 2) /* 2: timestamp */
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#define STM32_IRQ_RTC_SSRU (STM32_IRQ_FIRST + 2) /* 2: RTC SSR underflow */
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#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */
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#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
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#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */
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#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */
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#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */
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#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */
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#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */
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#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */
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#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */
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#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */
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#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */
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#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */
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#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */
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#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */
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#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC global interrupt */
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#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 19) /* 19: DAC global interrupt */
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#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */
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#define STM32_IRQ_PWRC2H (STM32_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */
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#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */
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#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */
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#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */
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#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 24) /* 24: Timer 1 Update */
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#define STM32_IRQ_TIM1TRG_COM (STM32_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */
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#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */
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#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */
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#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */
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#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */
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#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */
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#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */
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#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */
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#define STM32_IRQ_SPI2S2 (STM32_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 37) /* 37: USART2 global interrupt */
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#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */
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#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */
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#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */
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#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */
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#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */
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#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */
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/* 44: Reserved */
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#define STM32_IRQ_IPCC_C1_RX_IT (STM32_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */
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#define STM32_IRQ_IPCC_C1_TX_IT (STM32_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */
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#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */
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#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */
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#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */
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#define STM32_IRQ_RADIO (STM32_IRQ_FIRST + 50) /* 50: Radio */
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#define STM32_IRQ_RFBUSY (STM32_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */
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#define STM32_IRQ_AES (STM32_IRQ_FIRST + 51) /* 51: AES global interrupt */
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#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 52) /* 52: True random number generator interrupt */
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#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */
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#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */
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#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */
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#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */
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#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */
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#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */
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#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */
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#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */
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#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */
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|
||||
#define STM32WL5_IRQ_NEXTINTS 62
|
||||
#define STM32_IRQ_NEXTINTS 62
|
||||
|
||||
/* (EXTI interrupts do not use IRQ numbers) */
|
||||
|
||||
#define NR_IRQS (STM32WL5_IRQ_FIRST + STM32WL5_IRQ_NEXTINTS)
|
||||
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@
|
|||
* arch/stm32wl5/chip.h header file.
|
||||
*/
|
||||
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WL5_IRQ_NEXTINTS
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
|
||||
|
||||
/* Cache line sizes (in bytes) for the STM32WL5 */
|
||||
|
||||
|
|
|
|||
|
|
@ -34,48 +34,48 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32WL5_NEXTI1 31
|
||||
#define STM32WL5_EXTI1_MASK 0xffffffff
|
||||
#define STM32WL5_NEXTI2 9
|
||||
#define STM32WL5_EXTI2_MASK 0x000001ff
|
||||
#define STM32_NEXTI1 31
|
||||
#define STM32_EXTI1_MASK 0xffffffff
|
||||
#define STM32_NEXTI2 9
|
||||
#define STM32_EXTI2_MASK 0x000001ff
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */
|
||||
#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */
|
||||
#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */
|
||||
#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */
|
||||
#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */
|
||||
#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */
|
||||
#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */
|
||||
#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */
|
||||
#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */
|
||||
#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */
|
||||
#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */
|
||||
#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */
|
||||
#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */
|
||||
#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */
|
||||
#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */
|
||||
#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */
|
||||
#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */
|
||||
#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */
|
||||
#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */
|
||||
#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending 1 */
|
||||
#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */
|
||||
#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */
|
||||
#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */
|
||||
#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending 2 */
|
||||
#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */
|
||||
#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */
|
||||
#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */
|
||||
#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */
|
||||
#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */
|
||||
#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */
|
||||
#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */
|
||||
#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET)
|
||||
#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET)
|
||||
#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET)
|
||||
#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET)
|
||||
#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET)
|
||||
#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET)
|
||||
#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET)
|
||||
#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET)
|
||||
#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET)
|
||||
#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET)
|
||||
#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET)
|
||||
#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET)
|
||||
#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET)
|
||||
#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET)
|
||||
#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET)
|
||||
#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET)
|
||||
#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE+STM32_EXTI_RTSR1_OFFSET)
|
||||
#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE+STM32_EXTI_FTSR1_OFFSET)
|
||||
#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE+STM32_EXTI_SWIER1_OFFSET)
|
||||
#define STM32_EXTI_PR1 (STM32_EXTI_BASE+STM32_EXTI_PR1_OFFSET)
|
||||
#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE+STM32_EXTI_RTSR2_OFFSET)
|
||||
#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE+STM32_EXTI_FTSR2_OFFSET)
|
||||
#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE+STM32_EXTI_SWIER2_OFFSET)
|
||||
#define STM32_EXTI_PR2 (STM32_EXTI_BASE+STM32_EXTI_PR2_OFFSET)
|
||||
#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE+STM32_EXTI_C1IMR1_OFFSET)
|
||||
#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE+STM32_EXTI_C1EMR1_OFFSET)
|
||||
#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE+STM32_EXTI_C1IMR2_OFFSET)
|
||||
#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE+STM32_EXTI_C1EMR2_OFFSET)
|
||||
#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE+STM32_EXTI_C2IMR1_OFFSET)
|
||||
#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE+STM32_EXTI_C2EMR1_OFFSET)
|
||||
#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE+STM32_EXTI_C2IMR2_OFFSET)
|
||||
#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE+STM32_EXTI_C2EMR2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -86,71 +86,71 @@
|
|||
/* Define the valid configuration */
|
||||
|
||||
#if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */
|
||||
# define STM32WL5_FLASH_NPAGES 32
|
||||
# define STM32WL5_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 32
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */
|
||||
# define STM32WL5_FLASH_NPAGES 64
|
||||
# define STM32WL5_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 64
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */
|
||||
# define STM32WL5_FLASH_NPAGES 128
|
||||
# define STM32WL5_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 128
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */
|
||||
# define STM32WL5_FLASH_NPAGES 256
|
||||
# define STM32WL5_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 256
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */
|
||||
# define STM32WL5_FLASH_NPAGES 512
|
||||
# define STM32WL5_FLASH_PAGESIZE 2048
|
||||
# define STM32_FLASH_NPAGES 512
|
||||
# define STM32_FLASH_PAGESIZE 2048
|
||||
#else
|
||||
# error "unknown flash configuration!"
|
||||
#endif
|
||||
|
||||
#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE)
|
||||
#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32WL5_FLASH_ACR2_OFFSET 0x0004
|
||||
#define STM32WL5_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32WL5_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32WL5_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32WL5_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32WL5_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32WL5_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32WL5_FLASH_PCROP1ASR_OFFSET 0x0024
|
||||
#define STM32WL5_FLASH_PCROP1AER_OFFSET 0x0028
|
||||
#define STM32WL5_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32WL5_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#define STM32WL5_FLASH_PCROP1BSR_OFFSET 0x0034
|
||||
#define STM32WL5_FLASH_PCROP1BER_OFFSET 0x0038
|
||||
#define STM32WL5_FLASH_IPCCBR_OFFSET 0x003c
|
||||
#define STM32WL5_FLASH_C2ACR_OFFSET 0x005c
|
||||
#define STM32WL5_FLASH_C2SR_OFFSET 0x0060
|
||||
#define STM32WL5_FLASH_C2CR_OFFSET 0x0064
|
||||
#define STM32WL5_FLASH_SFR_OFFSET 0x0080
|
||||
#define STM32WL5_FLASH_SRRVR_OFFSET 0x0084
|
||||
#define STM32_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32_FLASH_ACR2_OFFSET 0x0004
|
||||
#define STM32_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024
|
||||
#define STM32_FLASH_PCROP1AER_OFFSET 0x0028
|
||||
#define STM32_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034
|
||||
#define STM32_FLASH_PCROP1BER_OFFSET 0x0038
|
||||
#define STM32_FLASH_IPCCBR_OFFSET 0x003c
|
||||
#define STM32_FLASH_C2ACR_OFFSET 0x005c
|
||||
#define STM32_FLASH_C2SR_OFFSET 0x0060
|
||||
#define STM32_FLASH_C2CR_OFFSET 0x0064
|
||||
#define STM32_FLASH_SFR_OFFSET 0x0080
|
||||
#define STM32_FLASH_SRRVR_OFFSET 0x0084
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET)
|
||||
#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET)
|
||||
#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET)
|
||||
#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET)
|
||||
#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET)
|
||||
#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET)
|
||||
#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET)
|
||||
#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET)
|
||||
#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET)
|
||||
#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET)
|
||||
#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET)
|
||||
#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET)
|
||||
#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET)
|
||||
#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET)
|
||||
#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET)
|
||||
#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET)
|
||||
#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET)
|
||||
#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET)
|
||||
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
|
||||
#define STM32_FLASH_ACR2 (STM32_FLASHIF_BASE+STM32_FLASH_ACR2_OFFSET)
|
||||
#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
|
||||
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
|
||||
#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
|
||||
#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
|
||||
#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1ASR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1AER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1AER_OFFSET)
|
||||
#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1BSR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BSR_OFFSET)
|
||||
#define STM32_FLASH_PCROP1BER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET)
|
||||
#define STM32_FLASH_IPCCBR (STM32_FLASHIF_BASE+STM32_FLASH_IPCCBR_OFFSET)
|
||||
#define STM32_FLASH_C2ACR (STM32_FLASHIF_BASE+STM32_FLASH_C2ACR_OFFSET)
|
||||
#define STM32_FLASH_C2SR (STM32_FLASHIF_BASE+STM32_FLASH_C2SR_OFFSET)
|
||||
#define STM32_FLASH_C2CR (STM32_FLASHIF_BASE+STM32_FLASH_C2CR_OFFSET)
|
||||
#define STM32_FLASH_SFR (STM32_FLASHIF_BASE+STM32_FLASH_SFR_OFFSET)
|
||||
#define STM32_FLASH_SRRVR (STM32_FLASHIF_BASE+STM32_FLASH_SRRVR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -36,71 +36,71 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32WL5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32WL5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32WL5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32WL5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32WL5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32WL5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32WL5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32WL5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32WL5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32WL5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
|
||||
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
|
||||
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
|
||||
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
|
||||
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
|
||||
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
|
||||
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
|
||||
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
|
||||
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
|
||||
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
|
||||
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_GPIOA_MODER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_MODER_OFFSET)
|
||||
#define STM32WL5_GPIOA_OTYPER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OTYPER_OFFSET)
|
||||
#define STM32WL5_GPIOA_OSPEED (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OSPEED_OFFSET)
|
||||
#define STM32WL5_GPIOA_PUPDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_PUPDR_OFFSET)
|
||||
#define STM32WL5_GPIOA_IDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_IDR_OFFSET)
|
||||
#define STM32WL5_GPIOA_ODR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ODR_OFFSET)
|
||||
#define STM32WL5_GPIOA_BSRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BSRR_OFFSET)
|
||||
#define STM32WL5_GPIOA_LCKR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_LCKR_OFFSET)
|
||||
#define STM32WL5_GPIOA_AFRL (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRL_OFFSET)
|
||||
#define STM32WL5_GPIOA_AFRH (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRH_OFFSET)
|
||||
#define STM32WL5_GPIOA_BRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BRR_OFFSET)
|
||||
#define STM32WL5_GPIOA_ASCR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ASCR_OFFSET)
|
||||
#define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
#define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
#define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
|
||||
#define STM32WL5_GPIOB_MODER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_MODER_OFFSET)
|
||||
#define STM32WL5_GPIOB_OTYPER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OTYPER_OFFSET)
|
||||
#define STM32WL5_GPIOB_OSPEED (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OSPEED_OFFSET)
|
||||
#define STM32WL5_GPIOB_PUPDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_PUPDR_OFFSET)
|
||||
#define STM32WL5_GPIOB_IDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_IDR_OFFSET)
|
||||
#define STM32WL5_GPIOB_ODR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ODR_OFFSET)
|
||||
#define STM32WL5_GPIOB_BSRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BSRR_OFFSET)
|
||||
#define STM32WL5_GPIOB_LCKR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_LCKR_OFFSET)
|
||||
#define STM32WL5_GPIOB_AFRL (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRL_OFFSET)
|
||||
#define STM32WL5_GPIOB_AFRH (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRH_OFFSET)
|
||||
#define STM32WL5_GPIOB_BRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BRR_OFFSET)
|
||||
#define STM32WL5_GPIOB_ASCR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ASCR_OFFSET)
|
||||
#define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
#define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
#define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
|
||||
#define STM32WL5_GPIOC_MODER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_MODER_OFFSET)
|
||||
#define STM32WL5_GPIOC_OTYPER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OTYPER_OFFSET)
|
||||
#define STM32WL5_GPIOC_OSPEED (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OSPEED_OFFSET)
|
||||
#define STM32WL5_GPIOC_PUPDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_PUPDR_OFFSET)
|
||||
#define STM32WL5_GPIOC_IDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_IDR_OFFSET)
|
||||
#define STM32WL5_GPIOC_ODR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ODR_OFFSET)
|
||||
#define STM32WL5_GPIOC_BSRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BSRR_OFFSET)
|
||||
#define STM32WL5_GPIOC_LCKR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_LCKR_OFFSET)
|
||||
#define STM32WL5_GPIOC_AFRL (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRL_OFFSET)
|
||||
#define STM32WL5_GPIOC_AFRH (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRH_OFFSET)
|
||||
#define STM32WL5_GPIOC_BRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BRR_OFFSET)
|
||||
#define STM32WL5_GPIOC_ASCR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ASCR_OFFSET)
|
||||
#define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
#define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
#define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
|
||||
#define STM32WL5_GPIOH_MODER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_MODER_OFFSET)
|
||||
#define STM32WL5_GPIOH_OTYPER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OTYPER_OFFSET)
|
||||
#define STM32WL5_GPIOH_OSPEED (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OSPEED_OFFSET)
|
||||
#define STM32WL5_GPIOH_PUPDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_PUPDR_OFFSET)
|
||||
#define STM32WL5_GPIOH_IDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_IDR_OFFSET)
|
||||
#define STM32WL5_GPIOH_ODR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ODR_OFFSET)
|
||||
#define STM32WL5_GPIOH_BSRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BSRR_OFFSET)
|
||||
#define STM32WL5_GPIOH_LCKR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_LCKR_OFFSET)
|
||||
#define STM32WL5_GPIOH_AFRL (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRL_OFFSET)
|
||||
#define STM32WL5_GPIOH_AFRH (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRH_OFFSET)
|
||||
#define STM32WL5_GPIOH_BRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BRR_OFFSET)
|
||||
#define STM32WL5_GPIOH_ASCR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ASCR_OFFSET)
|
||||
#define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET)
|
||||
#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET)
|
||||
#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET)
|
||||
#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET)
|
||||
#define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET)
|
||||
#define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET)
|
||||
#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET)
|
||||
#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET)
|
||||
#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET)
|
||||
#define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET)
|
||||
#define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET)
|
||||
#define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -34,48 +34,48 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32WL5_IPCC_CPU1_OFFSET 0x00
|
||||
#define STM32WL5_IPCC_CPU2_OFFSET 0x10
|
||||
#define STM32_IPCC_CPU1_OFFSET 0x00
|
||||
#define STM32_IPCC_CPU2_OFFSET 0x10
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_IPCC_CR_OFFSET 0x00 /* IPCC control register */
|
||||
#define STM32WL5_IPCC_MR_OFFSET 0x04 /* IPCC mask register */
|
||||
#define STM32WL5_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */
|
||||
#define STM32WL5_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */
|
||||
#define STM32_IPCC_CR_OFFSET 0x00 /* IPCC control register */
|
||||
#define STM32_IPCC_MR_OFFSET 0x04 /* IPCC mask register */
|
||||
#define STM32_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */
|
||||
#define STM32_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_IPCC_C1CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET)
|
||||
#define STM32WL5_IPCC_C1MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET)
|
||||
#define STM32WL5_IPCC_C1SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET)
|
||||
#define STM32WL5_IPCC_C1TOC2SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET)
|
||||
#define STM32WL5_IPCC_C2CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET)
|
||||
#define STM32WL5_IPCC_C2MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET)
|
||||
#define STM32WL5_IPCC_C2SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET)
|
||||
#define STM32WL5_IPCC_C2TOC1SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET)
|
||||
#define STM32_IPCC_C1CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU1_OFFSET)
|
||||
#define STM32_IPCC_C1MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU1_OFFSET)
|
||||
#define STM32_IPCC_C1SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU1_OFFSET)
|
||||
#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU1_OFFSET)
|
||||
#define STM32_IPCC_C2CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU2_OFFSET)
|
||||
#define STM32_IPCC_C2MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU2_OFFSET)
|
||||
#define STM32_IPCC_C2SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU2_OFFSET)
|
||||
#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU2_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
#define STM32WL5_IPCC_TX_SHIFT (16) /* TX shift for all registers */
|
||||
#define STM32_IPCC_TX_SHIFT (16) /* TX shift for all registers */
|
||||
|
||||
/* IPCC control register */
|
||||
|
||||
#define STM32WL5_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */
|
||||
#define STM32WL5_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */
|
||||
#define STM32_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */
|
||||
#define STM32_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */
|
||||
|
||||
/* IPCC mask register */
|
||||
|
||||
#define STM32WL5_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */
|
||||
#define STM32WL5_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */
|
||||
#define STM32_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */
|
||||
#define STM32_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */
|
||||
|
||||
/* IPCC status set clear register */
|
||||
|
||||
#define STM32WL5_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */
|
||||
#define STM32WL5_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */
|
||||
#define STM32_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */
|
||||
#define STM32_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */
|
||||
|
||||
/* IPCC processor to processor status register */
|
||||
|
||||
#define STM32WL5_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */
|
||||
#define STM32_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H */
|
||||
|
|
|
|||
|
|
@ -29,40 +29,40 @@
|
|||
|
||||
/* STM32WL5XXX Address Blocks ***********************************************/
|
||||
|
||||
#define STM32WL5_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */
|
||||
#define STM32WL5_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32WL5_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */
|
||||
/* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */
|
||||
#define STM32WL5_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */
|
||||
#define STM32_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */
|
||||
#define STM32_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */
|
||||
/* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */
|
||||
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */
|
||||
|
||||
#define STM32WL5_REGION_MASK 0xf0000000
|
||||
#define STM32WL5_IS_SRAM(a) ((((uint32_t)(a)) & STM32WL5_REGION_MASK) == STM32WL5_SRAM_BASE)
|
||||
#define STM32_REGION_MASK 0xf0000000
|
||||
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
|
||||
|
||||
/* Code Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */
|
||||
/* 0x0004 0000-0x07ff ffff: Reserved */
|
||||
#define STM32WL5_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */
|
||||
/* 0x0804 0000-0x0fff ffff: Reserved */
|
||||
#define STM32WL5_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
|
||||
/* 0x1000 0000-0x1ffe 6fff: Reserved */
|
||||
#define STM32WL5_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */
|
||||
#define STM32WL5_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */
|
||||
#define STM32WL5_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */
|
||||
#define STM32WL5_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */
|
||||
/* 0x1fff 8000-0x1fff ffff: reserved */
|
||||
#define STM32WL5_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */
|
||||
#define STM32_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */
|
||||
/* 0x0004 0000-0x07ff ffff: Reserved */
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */
|
||||
/* 0x0804 0000-0x0fff ffff: Reserved */
|
||||
#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
|
||||
/* 0x1000 0000-0x1ffe 6fff: Reserved */
|
||||
#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */
|
||||
#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */
|
||||
#define STM32_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */
|
||||
#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */
|
||||
/* 0x1fff 8000-0x1fff ffff: reserved */
|
||||
#define STM32_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */
|
||||
|
||||
/* System Memory Addresses **************************************************/
|
||||
|
||||
#define STM32WL5_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
|
||||
#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
|
||||
* type.
|
||||
* 0: UFBGA73
|
||||
* 2: WLCSP59
|
||||
* 10: UFQFPN48
|
||||
*/
|
||||
#define STM32WL5_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32WL5_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of
|
||||
#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
|
||||
#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of
|
||||
* the device Flash memory expressed in
|
||||
* Kbytes. Example: 0x0400 corresponds
|
||||
* to 1024 Kbytes.
|
||||
|
|
@ -70,92 +70,92 @@
|
|||
|
||||
/* SRAM Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
|
||||
#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
|
||||
|
||||
/* Peripheral Base Addresses ************************************************/
|
||||
|
||||
#define STM32WL5_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */
|
||||
/* 0x4000 B400-0x4000 ffff: Reserved */
|
||||
#define STM32WL5_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */
|
||||
/* 0x4001 4c00-0x4001 ffff: Reserved */
|
||||
#define STM32WL5_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */
|
||||
/* 0x4260 0000-0x47ff ffff: Reserved */
|
||||
#define STM32WL5_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */
|
||||
/* 0x4800 2000-0x57ff ffff: Reserved */
|
||||
#define STM32WL5_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */
|
||||
/* 0x5800 40c0-0x5800 ffff: Reserved */
|
||||
#define STM32_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */
|
||||
/* 0x4000 B400-0x4000 ffff: Reserved */
|
||||
#define STM32_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */
|
||||
/* 0x4001 4c00-0x4001 ffff: Reserved */
|
||||
#define STM32_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */
|
||||
/* 0x4260 0000-0x47ff ffff: Reserved */
|
||||
#define STM32_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */
|
||||
/* 0x4800 2000-0x57ff ffff: Reserved */
|
||||
#define STM32_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */
|
||||
/* 0x5800 40c0-0x5800 ffff: Reserved */
|
||||
|
||||
/* Radio Base Addresses *****************************************************/
|
||||
|
||||
#define STM32WL5_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */
|
||||
/* 0x5801 0400-0x5801 ffff: Reserved */
|
||||
#define STM32_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */
|
||||
/* 0x5801 0400-0x5801 ffff: Reserved */
|
||||
|
||||
/* in datasheet order */
|
||||
|
||||
/* APB1 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_TAMP_BASE 0x4000B000
|
||||
#define STM32WL5_LPTIM3_BASE 0x40009800
|
||||
#define STM32WL5_LPTIM2_BASE 0x40009400
|
||||
#define STM32WL5_LPUART1_BASE 0x40008000
|
||||
#define STM32WL5_LPTIM1_BASE 0x40007C00
|
||||
#define STM32WL5_DAC_BASE 0x40007400
|
||||
#define STM32WL5_I2C3_BASE 0x40005C00
|
||||
#define STM32WL5_I2C2_BASE 0x40005800
|
||||
#define STM32WL5_I2C1_BASE 0x40005400
|
||||
#define STM32WL5_USART2_BASE 0x40004400
|
||||
#define STM32WL5_SPI2S2_BASE 0x40003800
|
||||
#define STM32WL5_IWDG_BASE 0x40003000
|
||||
#define STM32WL5_WWDG_BASE 0x40002C00
|
||||
#define STM32WL5_RTC_BASE 0x40002800
|
||||
#define STM32WL5_TIM2_BASE 0x40000000
|
||||
#define STM32_TAMP_BASE 0x4000B000
|
||||
#define STM32_LPTIM3_BASE 0x40009800
|
||||
#define STM32_LPTIM2_BASE 0x40009400
|
||||
#define STM32_LPUART1_BASE 0x40008000
|
||||
#define STM32_LPTIM1_BASE 0x40007C00
|
||||
#define STM32_DAC_BASE 0x40007400
|
||||
#define STM32_I2C3_BASE 0x40005C00
|
||||
#define STM32_I2C2_BASE 0x40005800
|
||||
#define STM32_I2C1_BASE 0x40005400
|
||||
#define STM32_USART2_BASE 0x40004400
|
||||
#define STM32_SPI2S2_BASE 0x40003800
|
||||
#define STM32_IWDG_BASE 0x40003000
|
||||
#define STM32_WWDG_BASE 0x40002C00
|
||||
#define STM32_RTC_BASE 0x40002800
|
||||
#define STM32_TIM2_BASE 0x40000000
|
||||
|
||||
/* APB2 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_TIM17_BASE 0x40014800
|
||||
#define STM32WL5_TIM16_BASE 0x40014400
|
||||
#define STM32WL5_USART1_BASE 0x40013800
|
||||
#define STM32WL5_SPI1_BASE 0x40013000
|
||||
#define STM32WL5_TIM1_BASE 0x40012C00
|
||||
#define STM32WL5_ADC_BASE 0x40012400
|
||||
#define STM32WL5_COMP_BASE 0x40010200
|
||||
#define STM32WL5_SYSCFG2_BASE 0x40010100
|
||||
#define STM32WL5_VREFBUF_BASE 0x40010030
|
||||
#define STM32WL5_SYSCFG_BASE 0x40010000
|
||||
#define STM32_TIM17_BASE 0x40014800
|
||||
#define STM32_TIM16_BASE 0x40014400
|
||||
#define STM32_USART1_BASE 0x40013800
|
||||
#define STM32_SPI1_BASE 0x40013000
|
||||
#define STM32_TIM1_BASE 0x40012C00
|
||||
#define STM32_ADC_BASE 0x40012400
|
||||
#define STM32_COMP_BASE 0x40010200
|
||||
#define STM32_SYSCFG2_BASE 0x40010100
|
||||
#define STM32_VREFBUF_BASE 0x40010030
|
||||
#define STM32_SYSCFG_BASE 0x40010000
|
||||
|
||||
/* AHB1 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_CRC_BASE 0x40023000
|
||||
#define STM32WL5_DMAMUX1_BASE 0x40200800
|
||||
#define STM32WL5_DMA2_BASE 0x40200400
|
||||
#define STM32WL5_DMA1_BASE 0x40020000
|
||||
#define STM32_CRC_BASE 0x40023000
|
||||
#define STM32_DMAMUX1_BASE 0x40200800
|
||||
#define STM32_DMA2_BASE 0x40200400
|
||||
#define STM32_DMA1_BASE 0x40020000
|
||||
|
||||
/* AHB2 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_GPIOH_BASE 0x48001C00
|
||||
#define STM32WL5_GPIOC_BASE 0x48000800
|
||||
#define STM32WL5_GPIOB_BASE 0x48000400
|
||||
#define STM32WL5_GPIOA_BASE 0x48000000
|
||||
#define STM32_GPIOH_BASE 0x48001C00
|
||||
#define STM32_GPIOC_BASE 0x48000800
|
||||
#define STM32_GPIOB_BASE 0x48000400
|
||||
#define STM32_GPIOA_BASE 0x48000000
|
||||
|
||||
/* AHB3 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_GTZC_TZIC_BASE 0x58004800
|
||||
#define STM32WL5_GTZC_TZSC_BASE 0x58004400
|
||||
#define STM32WL5_FLASHIF_BASE 0x58004000
|
||||
#define STM32WL5_PKA2_BASE 0x58003400
|
||||
#define STM32WL5_PKARAM_BASE 0x58002400
|
||||
#define STM32WL5_PKA_BASE 0x58002000
|
||||
#define STM32WL5_AES_BASE 0x58001800
|
||||
#define STM32WL5_HSEM_BASE 0x58001400
|
||||
#define STM32WL5_RNG_BASE 0x58001000
|
||||
#define STM32WL5_IPCC_BASE 0x58000C00
|
||||
#define STM32WL5_EXTI_BASE 0x58000800
|
||||
#define STM32WL5_PWR_BASE 0x58000400
|
||||
#define STM32WL5_RCC_BASE 0x58000000
|
||||
#define STM32_GTZC_TZIC_BASE 0x58004800
|
||||
#define STM32_GTZC_TZSC_BASE 0x58004400
|
||||
#define STM32_FLASHIF_BASE 0x58004000
|
||||
#define STM32_PKA2_BASE 0x58003400
|
||||
#define STM32_PKARAM_BASE 0x58002400
|
||||
#define STM32_PKA_BASE 0x58002000
|
||||
#define STM32_AES_BASE 0x58001800
|
||||
#define STM32_HSEM_BASE 0x58001400
|
||||
#define STM32_RNG_BASE 0x58001000
|
||||
#define STM32_IPCC_BASE 0x58000C00
|
||||
#define STM32_EXTI_BASE 0x58000800
|
||||
#define STM32_PWR_BASE 0x58000400
|
||||
#define STM32_RCC_BASE 0x58000000
|
||||
|
||||
/* APB3 Base Addresses ******************************************************/
|
||||
|
||||
#define STM32WL5_SUBGHZSPI_BASE 0x58010000
|
||||
#define STM32_SUBGHZSPI_BASE 0x58010000
|
||||
|
||||
/* Cortex-M4 Base Addresses *************************************************/
|
||||
|
||||
|
|
@ -163,7 +163,7 @@
|
|||
* this address range
|
||||
*/
|
||||
|
||||
#define STM32WL5_SCS_BASE 0xe000e000
|
||||
#define STM32WL5_DEBUGMCU_BASE 0xe0042000
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H */
|
||||
|
|
|
|||
|
|
@ -36,53 +36,53 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32WL5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32WL5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32WL5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32WL5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32WL5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32WL5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32WL5_PWR_CR5_OFFSET 0x001C /* Power control register 5 */
|
||||
#define STM32WL5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32WL5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32WL5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32WL5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32WL5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32WL5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32WL5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32WL5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32WL5_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */
|
||||
#define STM32WL5_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */
|
||||
#define STM32WL5_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */
|
||||
#define STM32WL5_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */
|
||||
#define STM32WL5_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */
|
||||
#define STM32WL5_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */
|
||||
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
|
||||
#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
|
||||
#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
|
||||
#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
|
||||
#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
|
||||
#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
|
||||
#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
|
||||
#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */
|
||||
#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
|
||||
#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
|
||||
#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
|
||||
#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
|
||||
#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
|
||||
#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
|
||||
#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
|
||||
#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
|
||||
#define STM32_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */
|
||||
#define STM32_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */
|
||||
#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */
|
||||
#define STM32_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */
|
||||
#define STM32_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */
|
||||
#define STM32_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_PWR_CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR1_OFFSET)
|
||||
#define STM32WL5_PWR_CR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR2_OFFSET)
|
||||
#define STM32WL5_PWR_CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR3_OFFSET)
|
||||
#define STM32WL5_PWR_CR4 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR4_OFFSET)
|
||||
#define STM32WL5_PWR_SR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR1_OFFSET)
|
||||
#define STM32WL5_PWR_SR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR2_OFFSET)
|
||||
#define STM32WL5_PWR_SCR (STM32WL5_PWR_BASE+STM32WL5_PWR_SCR_OFFSET)
|
||||
#define STM32WL5_PWR_CR5 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR5_OFFSET)
|
||||
#define STM32WL5_PWR_PUCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRA_OFFSET)
|
||||
#define STM32WL5_PWR_PDCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRA_OFFSET)
|
||||
#define STM32WL5_PWR_PUCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRB_OFFSET)
|
||||
#define STM32WL5_PWR_PDCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRB_OFFSET)
|
||||
#define STM32WL5_PWR_PUCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRC_OFFSET)
|
||||
#define STM32WL5_PWR_PDCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRC_OFFSET)
|
||||
#define STM32WL5_PWR_PUCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRH_OFFSET)
|
||||
#define STM32WL5_PWR_PDCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRH_OFFSET)
|
||||
#define STM32WL5_PWR_C2CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR1_OFFSET)
|
||||
#define STM32WL5_PWR_C2CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR3_OFFSET)
|
||||
#define STM32WL5_PWR_EXTSCR (STM32WL5_PWR_BASE+STM32WL5_PWR_EXTSCR_OFFSET)
|
||||
#define STM32WL5_PWR_SECCFGR (STM32WL5_PWR_BASE+STM32WL5_PWR_SECCFGR_OFFSET)
|
||||
#define STM32WL5_PWR_SUBGHZSPICR (STM32WL5_PWR_BASE+STM32WL5_PWR_SUBGHZSPICR_OFFSET)
|
||||
#define STM32WL5_PWR_RSSCMDR (STM32WL5_PWR_BASE+STM32WL5_PWR_RSSCMDR_OFFSET)
|
||||
#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
|
||||
#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
|
||||
#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET)
|
||||
#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET)
|
||||
#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET)
|
||||
#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET)
|
||||
#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET)
|
||||
#define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET)
|
||||
#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET)
|
||||
#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET)
|
||||
#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET)
|
||||
#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET)
|
||||
#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET)
|
||||
#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET)
|
||||
#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET)
|
||||
#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET)
|
||||
#define STM32_PWR_C2CR1 (STM32_PWR_BASE+STM32_PWR_C2CR1_OFFSET)
|
||||
#define STM32_PWR_C2CR3 (STM32_PWR_BASE+STM32_PWR_C2CR3_OFFSET)
|
||||
#define STM32_PWR_EXTSCR (STM32_PWR_BASE+STM32_PWR_EXTSCR_OFFSET)
|
||||
#define STM32_PWR_SECCFGR (STM32_PWR_BASE+STM32_PWR_SECCFGR_OFFSET)
|
||||
#define STM32_PWR_SUBGHZSPICR (STM32_PWR_BASE+STM32_PWR_SUBGHZSPICR_OFFSET)
|
||||
#define STM32_PWR_RSSCMDR (STM32_PWR_BASE+STM32_PWR_RSSCMDR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -35,95 +35,95 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32WL5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32WL5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32WL5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32WL5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32WL5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32WL5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32WL5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32WL5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32WL5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32WL5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32WL5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32WL5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32WL5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32WL5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32WL5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32WL5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32WL5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32WL5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32WL5_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32WL5_RCC_EXTCFGR_OFFSET 0x0108
|
||||
#define STM32WL5_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32WL5_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32WL5_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */
|
||||
#define STM32WL5_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32WL5_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32WL5_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32WL5_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
|
||||
#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
|
||||
#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
|
||||
#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
|
||||
#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
|
||||
#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
|
||||
#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
|
||||
#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
|
||||
#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */
|
||||
#define STM32_RCC_EXTCFGR_OFFSET 0x0108
|
||||
#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */
|
||||
#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */
|
||||
#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */
|
||||
#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */
|
||||
#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */
|
||||
#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */
|
||||
#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_RCC_CR (STM32WL5_RCC_BASE + STM32WL5_RCC_CR_OFFSET)
|
||||
#define STM32WL5_RCC_ICSCR (STM32WL5_RCC_BASE + STM32WL5_RCC_ICSCR_OFFSET)
|
||||
#define STM32WL5_RCC_CFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_CFGR_OFFSET)
|
||||
#define STM32WL5_RCC_PLLCFG (STM32WL5_RCC_BASE + STM32WL5_RCC_PLLCFG_OFFSET)
|
||||
#define STM32WL5_RCC_CIER (STM32WL5_RCC_BASE + STM32WL5_RCC_CIER_OFFSET)
|
||||
#define STM32WL5_RCC_CIFR (STM32WL5_RCC_BASE + STM32WL5_RCC_CIFR_OFFSET)
|
||||
#define STM32WL5_RCC_CICR (STM32WL5_RCC_BASE + STM32WL5_RCC_CICR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB1RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB3RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32WL5_RCC_APB1RSTR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32WL5_RCC_APB1RSTR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32WL5_RCC_APB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32WL5_RCC_APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32WL5_RCC_APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32WL5_RCC_APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2ENR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32WL5_RCC_APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32WL5_RCC_APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_CCIPR (STM32WL5_RCC_BASE + STM32WL5_RCC_CCIPR_OFFSET)
|
||||
#define STM32WL5_RCC_BDCR (STM32WL5_RCC_BASE + STM32WL5_RCC_BDCR_OFFSET)
|
||||
#define STM32WL5_RCC_CSR (STM32WL5_RCC_BASE + STM32WL5_RCC_CSR_OFFSET)
|
||||
#define STM32WL5_RCC_EXTCFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_EXTCFGR_OFFSET)
|
||||
#define STM32WL5_RCC_C2AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1ENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2ENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3ENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR1_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR2_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2ENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3ENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR1_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR2_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2SMENR_OFFSET)
|
||||
#define STM32WL5_RCC_C2APB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3SMENR_OFFSET)
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET)
|
||||
#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET)
|
||||
#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET)
|
||||
#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET)
|
||||
#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET)
|
||||
#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET)
|
||||
#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET)
|
||||
#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET)
|
||||
#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET)
|
||||
#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET)
|
||||
#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET)
|
||||
#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET)
|
||||
#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET)
|
||||
#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET)
|
||||
#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET)
|
||||
#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET)
|
||||
#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET)
|
||||
#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET)
|
||||
#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET)
|
||||
#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
#undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */
|
||||
#undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */
|
||||
|
||||
#if defined(STM32WL5_HAVE_IP_SPI_V2)
|
||||
#if defined(STM32_HAVE_IP_SPI_V2)
|
||||
# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */
|
||||
# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */
|
||||
# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */
|
||||
#endif
|
||||
|
||||
#if defined(STM32WL5_HAVE_IP_SPI_V3)
|
||||
#if defined(STM32_HAVE_IP_SPI_V3)
|
||||
# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */
|
||||
# undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */
|
||||
# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
# undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */
|
||||
#endif
|
||||
|
||||
#if defined(STM32WL5_HAVE_IP_SPI_V4)
|
||||
#if defined(STM32_HAVE_IP_SPI_V4)
|
||||
# define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */
|
||||
# define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */
|
||||
# define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */
|
||||
|
|
@ -75,65 +75,65 @@
|
|||
/* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
#if defined(CONFIG_STM32WL5_STM32F4XXX)
|
||||
# define STM32WL5_SPI_CLK_MAX 37500000UL
|
||||
# define STM32_SPI_CLK_MAX 37500000UL
|
||||
#else
|
||||
# define STM32WL5_SPI_CLK_MAX 18000000UL
|
||||
# define STM32_SPI_CLK_MAX 18000000UL
|
||||
#endif
|
||||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32WL5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32WL5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32WL5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32WL5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32WL5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32WL5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
#if defined(HAVE_SPI_I2S)
|
||||
# define STM32WL5_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
|
||||
# define STM32WL5_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
|
||||
# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
|
||||
# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
|
||||
#endif
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#if STM32WL5_NSPI > 0
|
||||
# define STM32WL5_SPI1_CR1 \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_CR1_OFFSET)
|
||||
# define STM32WL5_SPI1_CR2 \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_CR2_OFFSET)
|
||||
# define STM32WL5_SPI1_SR \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_SR_OFFSET)
|
||||
# define STM32WL5_SPI1_DR \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_DR_OFFSET)
|
||||
# define STM32WL5_SPI1_CRCPR \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_CRCPR_OFFSET)
|
||||
# define STM32WL5_SPI1_RXCRCR \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_RXCRCR_OFFSET)
|
||||
# define STM32WL5_SPI1_TXCRCR \
|
||||
(STM32WL5_SPI1_BASE + STM32WL5_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 0
|
||||
# define STM32_SPI1_CR1 \
|
||||
(STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 \
|
||||
(STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR \
|
||||
(STM32_SPI1_BASE + STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR \
|
||||
(STM32_SPI1_BASE + STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR \
|
||||
(STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR \
|
||||
(STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR \
|
||||
(STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32WL5_NSPI > 1
|
||||
# define STM32WL5_SPI2S2_CR1 \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR1_OFFSET)
|
||||
# define STM32WL5_SPI2S2_CR2 \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR2_OFFSET)
|
||||
# define STM32WL5_SPI2S2_SR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_SR_OFFSET)
|
||||
# define STM32WL5_SPI2S2_DR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_DR_OFFSET)
|
||||
# define STM32WL5_SPI2S2_CRCPR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CRCPR_OFFSET)
|
||||
# define STM32WL5_SPI2S2_RXCRCR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_RXCRCR_OFFSET)
|
||||
# define STM32WL5_SPI2S2_TXCRCR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_TXCRCR_OFFSET)
|
||||
#if STM32_NSPI > 1
|
||||
# define STM32_SPI2S2_CR1 \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2S2_CR2 \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2S2_SR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2S2_DR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2S2_CRCPR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2S2_RXCRCR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2S2_TXCRCR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_TXCRCR_OFFSET)
|
||||
# if defined(HAVE_SPI_I2S)
|
||||
# define STM32WL5_SPI2S2_I2SCFGR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32WL5_SPI2S2_I2SPR \
|
||||
(STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SPR_OFFSET)
|
||||
# define STM32_SPI2S2_I2SCFGR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_I2SCFGR_OFFSET)
|
||||
# define STM32_SPI2S2_I2SPR \
|
||||
(STM32_SPI2S2_BASE + STM32_SPI_I2SPR_OFFSET)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -36,43 +36,43 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32WL5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
|
||||
#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
|
||||
|
||||
#define STM32WL5_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
|
||||
|
||||
#define STM32WL5_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32WL5_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32WL5_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32WL5_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32WL5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32WL5_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32WL5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32WL5_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32WL5_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */
|
||||
#define STM32WL5_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */
|
||||
#define STM32WL5_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */
|
||||
#define STM32WL5_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */
|
||||
#define STM32WL5_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */
|
||||
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
|
||||
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
|
||||
#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
|
||||
#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
|
||||
#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
|
||||
#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
|
||||
#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
|
||||
#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
|
||||
#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */
|
||||
#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */
|
||||
#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */
|
||||
#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */
|
||||
#define STM32_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_SYSCFG_MEMRMP (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32WL5_SYSCFG_CFGR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32WL5_SYSCFG_EXTICR(p) (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32WL5_SYSCFG_EXTICR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR1)
|
||||
#define STM32WL5_SYSCFG_EXTICR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR2)
|
||||
#define STM32WL5_SYSCFG_EXTICR3 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR3)
|
||||
#define STM32WL5_SYSCFG_EXTICR4 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR4)
|
||||
#define STM32WL5_SYSCFG_SCSR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SCSR)
|
||||
#define STM32WL5_SYSCFG_CFGR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR2)
|
||||
#define STM32WL5_SYSCFG_SWPR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SWPR)
|
||||
#define STM32WL5_SYSCFG_SKR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SKR)
|
||||
#define STM32WL5_SYSCFG_IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR1)
|
||||
#define STM32WL5_SYSCFG_IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR2)
|
||||
#define STM32WL5_SYSCFG_C2IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR1)
|
||||
#define STM32WL5_SYSCFG_C2IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR2)
|
||||
#define STM32WL5_SYSCFG_RFDCR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_RFDCR)
|
||||
#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET)
|
||||
#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
|
||||
#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
|
||||
#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1)
|
||||
#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2)
|
||||
#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3)
|
||||
#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4)
|
||||
#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR)
|
||||
#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2)
|
||||
#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR)
|
||||
#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR)
|
||||
#define STM32_SYSCFG_IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR1)
|
||||
#define STM32_SYSCFG_IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR2)
|
||||
#define STM32_SYSCFG_C2IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR1)
|
||||
#define STM32_SYSCFG_C2IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR2)
|
||||
#define STM32_SYSCFG_RFDCR (STM32_SYSCFG_BASE+STM32_SYSCFG_RFDCR)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -31,166 +31,166 @@
|
|||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32WL5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32WL5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32WL5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32WL5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32WL5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32WL5_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */
|
||||
#define STM32WL5_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */
|
||||
#define STM32WL5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32WL5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32WL5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */
|
||||
#define STM32_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */
|
||||
#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
|
||||
/* 32-bit General Timers - TIM2
|
||||
* TIM2 and 5 are 32-bit.
|
||||
* TIM15, 16 and 17 are 16-bit.
|
||||
*/
|
||||
|
||||
#define STM32WL5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32WL5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32WL5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */
|
||||
#define STM32WL5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32WL5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32WL5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32WL5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */
|
||||
#define STM32WL5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */
|
||||
#define STM32WL5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32WL5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32WL5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32WL5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32WL5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32WL5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */
|
||||
#define STM32WL5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32WL5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32WL5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32WL5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32WL5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */
|
||||
#define STM32WL5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */
|
||||
#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */
|
||||
#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */
|
||||
#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */
|
||||
#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */
|
||||
#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */
|
||||
#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */
|
||||
|
||||
/* TIM15, 16, and 17 only.
|
||||
*/
|
||||
|
||||
#define STM32WL5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */
|
||||
#define STM32WL5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */
|
||||
#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */
|
||||
#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */
|
||||
|
||||
/* Advanced Timers - TIM1 */
|
||||
|
||||
#define STM32WL5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32WL5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */
|
||||
#define STM32WL5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32WL5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32WL5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */
|
||||
#define STM32WL5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32WL5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */
|
||||
#define STM32WL5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */
|
||||
#define STM32WL5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */
|
||||
#define STM32WL5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32WL5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32WL5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32WL5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
|
||||
#define STM32WL5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32WL5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32WL5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32WL5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32WL5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */
|
||||
#define STM32WL5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32WL5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32WL5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */
|
||||
#define STM32WL5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */
|
||||
#define STM32WL5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32WL5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */
|
||||
#define STM32WL5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */
|
||||
#define STM32WL5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */
|
||||
#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */
|
||||
#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */
|
||||
#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */
|
||||
#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */
|
||||
#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */
|
||||
#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
|
||||
#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */
|
||||
#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */
|
||||
#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */
|
||||
#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */
|
||||
#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */
|
||||
#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#define STM32WL5_TIM1_CR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR1_OFFSET)
|
||||
#define STM32WL5_TIM1_CR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR2_OFFSET)
|
||||
#define STM32WL5_TIM1_SMCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SMCR_OFFSET)
|
||||
#define STM32WL5_TIM1_DIER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DIER_OFFSET)
|
||||
#define STM32WL5_TIM1_SR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SR_OFFSET)
|
||||
#define STM32WL5_TIM1_EGR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_EGR_OFFSET)
|
||||
#define STM32WL5_TIM1_CCMR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR1_OFFSET)
|
||||
#define STM32WL5_TIM1_CCMR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR2_OFFSET)
|
||||
#define STM32WL5_TIM1_CCER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCER_OFFSET)
|
||||
#define STM32WL5_TIM1_CNT (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CNT_OFFSET)
|
||||
#define STM32WL5_TIM1_PSC (STM32WL5_TIM1_BASE+STM32WL5_ATIM_PSC_OFFSET)
|
||||
#define STM32WL5_TIM1_ARR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_ARR_OFFSET)
|
||||
#define STM32WL5_TIM1_RCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_RCR_OFFSET)
|
||||
#define STM32WL5_TIM1_CCR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR1_OFFSET)
|
||||
#define STM32WL5_TIM1_CCR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR2_OFFSET)
|
||||
#define STM32WL5_TIM1_CCR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR3_OFFSET)
|
||||
#define STM32WL5_TIM1_CCR4 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR4_OFFSET)
|
||||
#define STM32WL5_TIM1_BDTR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_BDTR_OFFSET)
|
||||
#define STM32WL5_TIM1_DCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DCR_OFFSET)
|
||||
#define STM32WL5_TIM1_DMAR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DMAR_OFFSET)
|
||||
#define STM32WL5_TIM1_OR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR1_OFFSET)
|
||||
#define STM32WL5_TIM1_CCMR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR3_OFFSET)
|
||||
#define STM32WL5_TIM1_CCR5 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR5_OFFSET)
|
||||
#define STM32WL5_TIM1_CCR6 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR6_OFFSET)
|
||||
#define STM32WL5_TIM1_OR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR2_OFFSET)
|
||||
#define STM32WL5_TIM1_OR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR3_OFFSET)
|
||||
#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
|
||||
#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET)
|
||||
#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET)
|
||||
#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET)
|
||||
#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET)
|
||||
#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET)
|
||||
#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET)
|
||||
|
||||
/* 16-/32-bit General Timers - TIM2, TIM16-17.
|
||||
* TIM2 is 32-bit.
|
||||
* TIM16 and 17 are 16-bit.
|
||||
*/
|
||||
|
||||
#define STM32WL5_TIM2_CR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR1_OFFSET)
|
||||
#define STM32WL5_TIM2_CR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR2_OFFSET)
|
||||
#define STM32WL5_TIM2_SMCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SMCR_OFFSET)
|
||||
#define STM32WL5_TIM2_DIER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DIER_OFFSET)
|
||||
#define STM32WL5_TIM2_SR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SR_OFFSET)
|
||||
#define STM32WL5_TIM2_EGR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_EGR_OFFSET)
|
||||
#define STM32WL5_TIM2_CCMR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR1_OFFSET)
|
||||
#define STM32WL5_TIM2_CCMR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR2_OFFSET)
|
||||
#define STM32WL5_TIM2_CCER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCER_OFFSET)
|
||||
#define STM32WL5_TIM2_CNT (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CNT_OFFSET)
|
||||
#define STM32WL5_TIM2_PSC (STM32WL5_TIM2_BASE+STM32WL5_GTIM_PSC_OFFSET)
|
||||
#define STM32WL5_TIM2_ARR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_ARR_OFFSET)
|
||||
#define STM32WL5_TIM2_CCR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR1_OFFSET)
|
||||
#define STM32WL5_TIM2_CCR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR2_OFFSET)
|
||||
#define STM32WL5_TIM2_CCR3 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR3_OFFSET)
|
||||
#define STM32WL5_TIM2_CCR4 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR4_OFFSET)
|
||||
#define STM32WL5_TIM2_DCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DCR_OFFSET)
|
||||
#define STM32WL5_TIM2_DMAR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DMAR_OFFSET)
|
||||
#define STM32WL5_TIM2_OR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_OR_OFFSET)
|
||||
#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET)
|
||||
|
||||
#define STM32WL5_TIM16_CR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR1_OFFSET)
|
||||
#define STM32WL5_TIM16_CR2 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR2_OFFSET)
|
||||
#define STM32WL5_TIM16_DIER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DIER_OFFSET)
|
||||
#define STM32WL5_TIM16_SR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_SR_OFFSET)
|
||||
#define STM32WL5_TIM16_EGR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_EGR_OFFSET)
|
||||
#define STM32WL5_TIM16_CCMR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCMR1_OFFSET)
|
||||
#define STM32WL5_TIM16_CCER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCER_OFFSET)
|
||||
#define STM32WL5_TIM16_CNT (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CNT_OFFSET)
|
||||
#define STM32WL5_TIM16_PSC (STM32WL5_TIM16_BASE+STM32WL5_GTIM_PSC_OFFSET)
|
||||
#define STM32WL5_TIM16_ARR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_ARR_OFFSET)
|
||||
#define STM32WL5_TIM16_RCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_RCR_OFFSET)
|
||||
#define STM32WL5_TIM16_CCR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCR1_OFFSET)
|
||||
#define STM32WL5_TIM16_BDTR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_BDTR_OFFSET)
|
||||
#define STM32WL5_TIM16_DCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DCR_OFFSET)
|
||||
#define STM32WL5_TIM16_DMAR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DMAR_OFFSET)
|
||||
#define STM32WL5_TIM16_OR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_OR_OFFSET)
|
||||
#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET)
|
||||
#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET)
|
||||
#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET)
|
||||
|
||||
#define STM32WL5_TIM17_CR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR1_OFFSET)
|
||||
#define STM32WL5_TIM17_CR2 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR2_OFFSET)
|
||||
#define STM32WL5_TIM17_DIER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DIER_OFFSET)
|
||||
#define STM32WL5_TIM17_SR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_SR_OFFSET)
|
||||
#define STM32WL5_TIM17_EGR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_EGR_OFFSET)
|
||||
#define STM32WL5_TIM17_CCMR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCMR1_OFFSET)
|
||||
#define STM32WL5_TIM17_CCER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCER_OFFSET)
|
||||
#define STM32WL5_TIM17_CNT (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CNT_OFFSET)
|
||||
#define STM32WL5_TIM17_PSC (STM32WL5_TIM17_BASE+STM32WL5_GTIM_PSC_OFFSET)
|
||||
#define STM32WL5_TIM17_ARR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_ARR_OFFSET)
|
||||
#define STM32WL5_TIM17_RCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_RCR_OFFSET)
|
||||
#define STM32WL5_TIM17_CCR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCR1_OFFSET)
|
||||
#define STM32WL5_TIM17_BDTR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_BDTR_OFFSET)
|
||||
#define STM32WL5_TIM17_DCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DCR_OFFSET)
|
||||
#define STM32WL5_TIM17_DMAR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DMAR_OFFSET)
|
||||
#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
|
||||
#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
|
||||
#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
|
||||
#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -37,57 +37,57 @@
|
|||
|
||||
/* Register Offsets *********************************************************/
|
||||
|
||||
#define STM32WL5_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32WL5_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32WL5_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32WL5_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32WL5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32WL5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32WL5_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32WL5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32WL5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32WL5_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32WL5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
#define STM32WL5_USART_PRESC_OFFSET 0x002c /* Prescaler */
|
||||
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
|
||||
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
|
||||
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
|
||||
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
|
||||
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
|
||||
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
|
||||
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
|
||||
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
|
||||
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define STM32WL5_USART1_CR1 (STM32WL5_USART1_BASE+STM32WL5_USART_CR1_OFFSET)
|
||||
#define STM32WL5_USART1_CR2 (STM32WL5_USART1_BASE+STM32WL5_USART_CR2_OFFSET)
|
||||
#define STM32WL5_USART1_CR3 (STM32WL5_USART1_BASE+STM32WL5_USART_CR3_OFFSET)
|
||||
#define STM32WL5_USART1_BRR (STM32WL5_USART1_BASE+STM32WL5_USART_BRR_OFFSET)
|
||||
#define STM32WL5_USART1_GTPR (STM32WL5_USART1_BASE+STM32WL5_USART_GTPR_OFFSET)
|
||||
#define STM32WL5_USART1_RTOR (STM32WL5_USART1_BASE+STM32WL5_USART_RTOR_OFFSET)
|
||||
#define STM32WL5_USART1_RQR (STM32WL5_USART1_BASE+STM32WL5_USART_RQR_OFFSET)
|
||||
#define STM32WL5_USART1_ISR (STM32WL5_USART1_BASE+STM32WL5_USART_ISR_OFFSET)
|
||||
#define STM32WL5_USART1_ICR (STM32WL5_USART1_BASE+STM32WL5_USART_ICR_OFFSET)
|
||||
#define STM32WL5_USART1_RDR (STM32WL5_USART1_BASE+STM32WL5_USART_RDR_OFFSET)
|
||||
#define STM32WL5_USART1_TDR (STM32WL5_USART1_BASE+STM32WL5_USART_TDR_OFFSET)
|
||||
#define STM32WL5_USART1_PRESC (STM32WL5_USART1_BASE+STM32WL5_USART_PRESC_OFFSET)
|
||||
#define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
#define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
#define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
#define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
#define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
#define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
#define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
#define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
#define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
#define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#define STM32_USART1_PRESC (STM32_USART1_BASE+STM32_USART_PRESC_OFFSET)
|
||||
|
||||
#define STM32WL5_USART2_CR1 (STM32WL5_USART2_BASE+STM32WL5_USART_CR1_OFFSET)
|
||||
#define STM32WL5_USART2_CR2 (STM32WL5_USART2_BASE+STM32WL5_USART_CR2_OFFSET)
|
||||
#define STM32WL5_USART2_CR3 (STM32WL5_USART2_BASE+STM32WL5_USART_CR3_OFFSET)
|
||||
#define STM32WL5_USART2_BRR (STM32WL5_USART2_BASE+STM32WL5_USART_BRR_OFFSET)
|
||||
#define STM32WL5_USART2_GTPR (STM32WL5_USART2_BASE+STM32WL5_USART_GTPR_OFFSET)
|
||||
#define STM32WL5_USART2_RTOR (STM32WL5_USART2_BASE+STM32WL5_USART_RTOR_OFFSET)
|
||||
#define STM32WL5_USART2_RQR (STM32WL5_USART2_BASE+STM32WL5_USART_RQR_OFFSET)
|
||||
#define STM32WL5_USART2_ISR (STM32WL5_USART2_BASE+STM32WL5_USART_ISR_OFFSET)
|
||||
#define STM32WL5_USART2_ICR (STM32WL5_USART2_BASE+STM32WL5_USART_ICR_OFFSET)
|
||||
#define STM32WL5_USART2_RDR (STM32WL5_USART2_BASE+STM32WL5_USART_RDR_OFFSET)
|
||||
#define STM32WL5_USART2_TDR (STM32WL5_USART2_BASE+STM32WL5_USART_TDR_OFFSET)
|
||||
#define STM32WL5_USART2_PRESC (STM32WL5_USART2_BASE+STM32WL5_USART_PRESC_OFFSET)
|
||||
#define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
#define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
#define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
#define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
#define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
#define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
#define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
#define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
#define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
#define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
#define STM32_USART2_PRESC (STM32_USART2_BASE+STM32_USART_PRESC_OFFSET)
|
||||
|
||||
#define STM32WL5_LPUART1_CR1 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR1_OFFSET)
|
||||
#define STM32WL5_LPUART1_CR2 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR2_OFFSET)
|
||||
#define STM32WL5_LPUART1_CR3 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR3_OFFSET)
|
||||
#define STM32WL5_LPUART1_BRR (STM32WL5_LPUART1_BASE+STM32WL5_USART_BRR_OFFSET)
|
||||
#define STM32WL5_LPUART1_RQR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RQR_OFFSET)
|
||||
#define STM32WL5_LPUART1_ISR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ISR_OFFSET)
|
||||
#define STM32WL5_LPUART1_ICR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ICR_OFFSET)
|
||||
#define STM32WL5_LPUART1_RDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RDR_OFFSET)
|
||||
#define STM32WL5_LPUART1_TDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_TDR_OFFSET)
|
||||
#define STM32WL5_LPUART1_PRESC (STM32WL5_LPUART1_BASE+STM32WL5_USART_PRESC_OFFSET)
|
||||
#define STM32_LPUART1_CR1 (STM32_LPUART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
#define STM32_LPUART1_CR2 (STM32_LPUART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
#define STM32_LPUART1_CR3 (STM32_LPUART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
#define STM32_LPUART1_BRR (STM32_LPUART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
#define STM32_LPUART1_RQR (STM32_LPUART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
#define STM32_LPUART1_ISR (STM32_LPUART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
#define STM32_LPUART1_ICR (STM32_LPUART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
#define STM32_LPUART1_RDR (STM32_LPUART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
#define STM32_LPUART1_TDR (STM32_LPUART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#define STM32_LPUART1_PRESC (STM32_LPUART1_BASE+STM32_USART_PRESC_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -66,17 +66,17 @@
|
|||
|
||||
/* Set the range of system SRAM */
|
||||
|
||||
#define SRAM1_START STM32WL5_SRAM_BASE
|
||||
#define SRAM1_END (SRAM1_START + STM32WL5_SRAM1_SIZE)
|
||||
#define SRAM1_START STM32_SRAM_BASE
|
||||
#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE)
|
||||
|
||||
/* Set the range of SRAM2 as well, requires a second memory region */
|
||||
|
||||
#ifdef CONFIG_IPCC
|
||||
# define SRAM2_START IPCC_END
|
||||
#else
|
||||
# define SRAM2_START STM32WL5_SRAM2_BASE
|
||||
# define SRAM2_START STM32_SRAM2_BASE
|
||||
#endif
|
||||
#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE)
|
||||
#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
|
||||
|
||||
/* Some sanity checking. If multiple memory regions are defined, verify
|
||||
* that CONFIG_MM_REGIONS is set to match the number of memory regions
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0001, STM32WL5_EXTI_PR1);
|
||||
putreg32(0x0001, STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -93,7 +93,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0002, STM32WL5_EXTI_PR1);
|
||||
putreg32(0x0002, STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -114,7 +114,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0004, STM32WL5_EXTI_PR1);
|
||||
putreg32(0x0004, STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -135,7 +135,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0008, STM32WL5_EXTI_PR1);
|
||||
putreg32(0x0008, STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg)
|
|||
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(0x0010, STM32WL5_EXTI_PR1);
|
||||
putreg32(0x0010, STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -180,7 +180,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg,
|
|||
|
||||
/* Examine the state of each pin in the group */
|
||||
|
||||
pr = getreg32(STM32WL5_EXTI_PR1);
|
||||
pr = getreg32(STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -193,7 +193,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg,
|
|||
{
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(mask, STM32WL5_EXTI_PR1);
|
||||
putreg32(mask, STM32_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
|
|
@ -267,7 +267,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
|
||||
if (pin < 5)
|
||||
{
|
||||
irq = pin + STM32WL5_IRQ_EXTI0;
|
||||
irq = pin + STM32_IRQ_EXTI0;
|
||||
nshared = 1;
|
||||
shared_cbs = &g_gpio_handlers[pin];
|
||||
switch (pin)
|
||||
|
|
@ -295,14 +295,14 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
}
|
||||
else if (pin < 10)
|
||||
{
|
||||
irq = STM32WL5_IRQ_EXTI95;
|
||||
irq = STM32_IRQ_EXTI95;
|
||||
handler = stm32wl5_exti95_isr;
|
||||
shared_cbs = &g_gpio_handlers[5];
|
||||
nshared = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
irq = STM32WL5_IRQ_EXTI1510;
|
||||
irq = STM32_IRQ_EXTI1510;
|
||||
handler = stm32wl5_exti1510_isr;
|
||||
shared_cbs = &g_gpio_handlers[10];
|
||||
nshared = 6;
|
||||
|
|
@ -353,19 +353,19 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
|||
|
||||
/* Configure rising/falling edges */
|
||||
|
||||
modifyreg32(STM32WL5_EXTI_RTSR1,
|
||||
modifyreg32(STM32_EXTI_RTSR1,
|
||||
risingedge ? 0 : exti,
|
||||
risingedge ? exti : 0);
|
||||
modifyreg32(STM32WL5_EXTI_FTSR1,
|
||||
modifyreg32(STM32_EXTI_FTSR1,
|
||||
fallingedge ? 0 : exti,
|
||||
fallingedge ? exti : 0);
|
||||
|
||||
/* Enable Events and Interrupts */
|
||||
|
||||
modifyreg32(STM32WL5_EXTI_C1EMR1,
|
||||
modifyreg32(STM32_EXTI_C1EMR1,
|
||||
event ? 0 : exti,
|
||||
event ? exti : 0);
|
||||
modifyreg32(STM32WL5_EXTI_C1IMR1,
|
||||
modifyreg32(STM32_EXTI_C1IMR1,
|
||||
func ? 0 : exti,
|
||||
func ? exti : 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@
|
|||
#define OPTBYTES_KEY1 0x08192A3B
|
||||
#define OPTBYTES_KEY2 0x4C5D6E7F
|
||||
|
||||
#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4)
|
||||
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
|
||||
#define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
|
||||
|
|
@ -93,35 +93,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS];
|
|||
|
||||
static void flash_unlock(void)
|
||||
{
|
||||
while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32wl5_waste();
|
||||
}
|
||||
|
||||
if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_LOCK)
|
||||
if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK)
|
||||
{
|
||||
/* Unlock sequence */
|
||||
|
||||
putreg32(FLASH_KEY1, STM32WL5_FLASH_KEYR);
|
||||
putreg32(FLASH_KEY2, STM32WL5_FLASH_KEYR);
|
||||
putreg32(FLASH_KEY1, STM32_FLASH_KEYR);
|
||||
putreg32(FLASH_KEY2, STM32_FLASH_KEYR);
|
||||
}
|
||||
}
|
||||
|
||||
static void flash_lock(void)
|
||||
{
|
||||
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_LOCK);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
|
||||
}
|
||||
|
||||
static void flash_optbytes_unlock(void)
|
||||
{
|
||||
flash_unlock();
|
||||
|
||||
if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_OPTLOCK)
|
||||
if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK)
|
||||
{
|
||||
/* Unlock Option Bytes sequence */
|
||||
|
||||
putreg32(OPTBYTES_KEY1, STM32WL5_FLASH_OPTKEYR);
|
||||
putreg32(OPTBYTES_KEY2, STM32WL5_FLASH_OPTKEYR);
|
||||
putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR);
|
||||
putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -138,17 +138,17 @@ static inline void flash_erase(size_t page)
|
|||
{
|
||||
finfo("erase page %u\n", (unsigned int)page);
|
||||
|
||||
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
|
||||
modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK,
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK,
|
||||
FLASH_CR_PNB(page & 0xff));
|
||||
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_START);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START);
|
||||
|
||||
while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32wl5_waste();
|
||||
}
|
||||
|
||||
modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -227,20 +227,20 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
|
|||
|
||||
/* Modify Option Bytes in register. */
|
||||
|
||||
regval = getreg32(STM32WL5_FLASH_OPTR);
|
||||
regval = getreg32(STM32_FLASH_OPTR);
|
||||
|
||||
finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval);
|
||||
|
||||
regval = (regval & ~clrbits) | setbits;
|
||||
putreg32(regval, STM32WL5_FLASH_OPTR);
|
||||
putreg32(regval, STM32_FLASH_OPTR);
|
||||
|
||||
finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval);
|
||||
|
||||
/* Start Option Bytes programming and wait for completion. */
|
||||
|
||||
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_OPTSTRT);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT);
|
||||
|
||||
while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32wl5_waste();
|
||||
}
|
||||
|
|
@ -253,42 +253,42 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
|
|||
|
||||
size_t up_progmem_pagesize(size_t page)
|
||||
{
|
||||
return STM32WL5_FLASH_PAGESIZE;
|
||||
return STM32_FLASH_PAGESIZE;
|
||||
}
|
||||
|
||||
size_t up_progmem_erasesize(size_t block)
|
||||
{
|
||||
return STM32WL5_FLASH_PAGESIZE;
|
||||
return STM32_FLASH_PAGESIZE;
|
||||
}
|
||||
|
||||
ssize_t up_progmem_getpage(size_t addr)
|
||||
{
|
||||
if (addr >= STM32WL5_FLASH_BASE)
|
||||
if (addr >= STM32_FLASH_BASE)
|
||||
{
|
||||
addr -= STM32WL5_FLASH_BASE;
|
||||
addr -= STM32_FLASH_BASE;
|
||||
}
|
||||
|
||||
if (addr >= STM32WL5_FLASH_SIZE)
|
||||
if (addr >= STM32_FLASH_SIZE)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return addr / STM32WL5_FLASH_PAGESIZE;
|
||||
return addr / STM32_FLASH_PAGESIZE;
|
||||
}
|
||||
|
||||
size_t up_progmem_getaddress(size_t page)
|
||||
{
|
||||
if (page >= STM32WL5_FLASH_NPAGES)
|
||||
if (page >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
return SIZE_MAX;
|
||||
}
|
||||
|
||||
return page * STM32WL5_FLASH_PAGESIZE + STM32WL5_FLASH_BASE;
|
||||
return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE;
|
||||
}
|
||||
|
||||
size_t up_progmem_neraseblocks(void)
|
||||
{
|
||||
return STM32WL5_FLASH_NPAGES;
|
||||
return STM32_FLASH_NPAGES;
|
||||
}
|
||||
|
||||
bool up_progmem_isuniform(void)
|
||||
|
|
@ -300,7 +300,7 @@ ssize_t up_progmem_eraseblock(size_t block)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (block >= STM32WL5_FLASH_NPAGES)
|
||||
if (block >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
|
@ -338,7 +338,7 @@ ssize_t up_progmem_ispageerased(size_t page)
|
|||
size_t count;
|
||||
size_t bwritten = 0;
|
||||
|
||||
if (page >= STM32WL5_FLASH_NPAGES)
|
||||
if (page >= STM32_FLASH_NPAGES)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
|
@ -372,12 +372,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
/* Check for valid address range. */
|
||||
|
||||
offset = addr;
|
||||
if (addr >= STM32WL5_FLASH_BASE)
|
||||
if (addr >= STM32_FLASH_BASE)
|
||||
{
|
||||
offset -= STM32WL5_FLASH_BASE;
|
||||
offset -= STM32_FLASH_BASE;
|
||||
}
|
||||
|
||||
if (offset + buflen > STM32WL5_FLASH_SIZE)
|
||||
if (offset + buflen > STM32_FLASH_SIZE)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
|
@ -447,7 +447,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
|
||||
/* Write the page. Must be with double-words. */
|
||||
|
||||
modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PG);
|
||||
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
|
||||
set_pg_bit = true;
|
||||
|
||||
for (i = 0; i < FLASH_PAGE_WORDS; i += 2)
|
||||
|
|
@ -455,14 +455,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
*dest++ = *src++;
|
||||
*dest++ = *src++;
|
||||
|
||||
while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY)
|
||||
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
|
||||
{
|
||||
stm32wl5_waste();
|
||||
}
|
||||
|
||||
/* Verify */
|
||||
|
||||
if (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
|
||||
if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
|
||||
{
|
||||
ret = -EROFS;
|
||||
goto out;
|
||||
|
|
@ -476,7 +476,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
}
|
||||
}
|
||||
|
||||
modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
|
||||
set_pg_bit = false;
|
||||
|
||||
/* Adjust pointers and counts for the next time through the loop */
|
||||
|
|
@ -492,7 +492,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
|
|||
out:
|
||||
if (set_pg_bit)
|
||||
{
|
||||
modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0);
|
||||
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
|
||||
}
|
||||
|
||||
/* If there was an error, clear all error flags in status register (rc_w1
|
||||
|
|
@ -502,9 +502,9 @@ out:
|
|||
if (ret != OK)
|
||||
{
|
||||
ferr("flash write error: %d, status: 0x%" PRIx32 "\n",
|
||||
ret, getreg32(STM32WL5_FLASH_SR));
|
||||
ret, getreg32(STM32_FLASH_SR));
|
||||
|
||||
modifyreg32(STM32WL5_FLASH_SR, 0, FLASH_SR_ALLERRS);
|
||||
modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS);
|
||||
}
|
||||
|
||||
flash_lock();
|
||||
|
|
|
|||
|
|
@ -55,19 +55,19 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED;
|
|||
|
||||
/* Base addresses for each GPIO block */
|
||||
|
||||
const uint32_t g_gpiobase[STM32WL5_NPORTS] =
|
||||
const uint32_t g_gpiobase[STM32_NPORTS] =
|
||||
{
|
||||
#if STM32WL5_NPORTS > 0
|
||||
STM32WL5_GPIOA_BASE,
|
||||
#if STM32_NPORTS > 0
|
||||
STM32_GPIOA_BASE,
|
||||
#endif
|
||||
#if STM32WL5_NPORTS > 1
|
||||
STM32WL5_GPIOB_BASE,
|
||||
#if STM32_NPORTS > 1
|
||||
STM32_GPIOB_BASE,
|
||||
#endif
|
||||
#if STM32WL5_NPORTS > 2
|
||||
STM32WL5_GPIOC_BASE,
|
||||
#if STM32_NPORTS > 2
|
||||
STM32_GPIOC_BASE,
|
||||
#endif
|
||||
#if STM32WL5_NPORTS > 3
|
||||
STM32WL5_GPIOH_BASE,
|
||||
#if STM32_NPORTS > 3
|
||||
STM32_GPIOH_BASE,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -130,7 +130,7 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
/* Verify that this hardware supports the select GPIO port */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port >= STM32WL5_NPORTS)
|
||||
if (port >= STM32_NPORTS)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -179,10 +179,10 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
|
||||
/* Now apply the configuration to the mode register */
|
||||
|
||||
regval = getreg32(base + STM32WL5_GPIO_MODER_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
|
||||
regval &= ~GPIO_MODER_MASK(pin);
|
||||
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
|
||||
putreg32(regval, base + STM32WL5_GPIO_MODER_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
|
||||
|
||||
/* Set up the pull-up/pull-down configuration (all but analog pins) */
|
||||
|
||||
|
|
@ -205,10 +205,10 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
}
|
||||
}
|
||||
|
||||
regval = getreg32(base + STM32WL5_GPIO_PUPDR_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
|
||||
regval &= ~GPIO_PUPDR_MASK(pin);
|
||||
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
|
||||
putreg32(regval, base + STM32WL5_GPIO_PUPDR_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
|
||||
|
||||
/* Set the alternate function (Only alternate function pins) */
|
||||
|
||||
|
|
@ -223,12 +223,12 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
|
||||
if (pin < 8)
|
||||
{
|
||||
regoffset = STM32WL5_GPIO_AFRL_OFFSET;
|
||||
regoffset = STM32_GPIO_AFRL_OFFSET;
|
||||
pos = pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
regoffset = STM32WL5_GPIO_AFRH_OFFSET;
|
||||
regoffset = STM32_GPIO_AFRH_OFFSET;
|
||||
pos = pin - 8;
|
||||
}
|
||||
|
||||
|
|
@ -266,14 +266,14 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
setting = 0;
|
||||
}
|
||||
|
||||
regval = getreg32(base + STM32WL5_GPIO_OSPEED_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
|
||||
regval &= ~GPIO_OSPEED_MASK(pin);
|
||||
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
|
||||
putreg32(regval, base + STM32WL5_GPIO_OSPEED_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
|
||||
|
||||
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
|
||||
|
||||
regval = getreg32(base + STM32WL5_GPIO_OTYPER_OFFSET);
|
||||
regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
|
||||
setting = GPIO_OTYPER_OD(pin);
|
||||
|
||||
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
|
||||
|
|
@ -286,7 +286,7 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
regval &= ~setting;
|
||||
}
|
||||
|
||||
putreg32(regval, base + STM32WL5_GPIO_OTYPER_OFFSET);
|
||||
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
|
||||
|
||||
/* Otherwise, it is an input pin. Should it configured as an
|
||||
* EXTI interrupt?
|
||||
|
|
@ -303,7 +303,7 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
|||
|
||||
/* Set the bits in the SYSCFG EXTICR register */
|
||||
|
||||
regaddr = STM32WL5_SYSCFG_EXTICR(pin);
|
||||
regaddr = STM32_SYSCFG_EXTICR(pin);
|
||||
regval = getreg32(regaddr);
|
||||
shift = SYSCFG_EXTICR_EXTI_SHIFT(pin);
|
||||
regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
|
||||
|
|
@ -365,7 +365,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value)
|
|||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < STM32WL5_NPORTS)
|
||||
if (port < STM32_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
|
|
@ -386,7 +386,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value)
|
|||
bit = GPIO_BSRR_RESET(pin);
|
||||
}
|
||||
|
||||
putreg32(bit, base + STM32WL5_GPIO_BSRR_OFFSET);
|
||||
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -405,7 +405,7 @@ bool stm32wl5_gpioread(uint32_t pinset)
|
|||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < STM32WL5_NPORTS)
|
||||
if (port < STM32_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
|
|
@ -414,7 +414,7 @@ bool stm32wl5_gpioread(uint32_t pinset)
|
|||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(base + STM32WL5_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
|
||||
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -237,7 +237,7 @@ extern "C"
|
|||
|
||||
/* Base addresses for each GPIO block */
|
||||
|
||||
EXTERN const uint32_t g_gpiobase[STM32WL5_NPORTS];
|
||||
EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
|
|
|
|||
|
|
@ -225,8 +225,8 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
|
|||
UNUSED(arg);
|
||||
UNUSED(irq);
|
||||
|
||||
mr = getreg32(STM32WL5_IPCC_C1MR) >> STM32WL5_IPCC_TX_SHIFT;
|
||||
sr = getreg32(STM32WL5_IPCC_C1TOC2SR);
|
||||
mr = getreg32(STM32_IPCC_C1MR) >> STM32_IPCC_TX_SHIFT;
|
||||
sr = getreg32(STM32_IPCC_C1TOC2SR);
|
||||
|
||||
/* Consider only channels that have tx memory free and are unmasked */
|
||||
|
||||
|
|
@ -266,7 +266,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
|
|||
/* Yes, tell another CPU that data is available to read */
|
||||
|
||||
txmem->len = nwritten;
|
||||
modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(chan));
|
||||
modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(chan));
|
||||
}
|
||||
|
||||
if (circbuf_used(&priv->ipcc->txbuf) == 0)
|
||||
|
|
@ -276,7 +276,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
|
|||
* will be constantly interrupted by tx free irq.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan));
|
||||
modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan));
|
||||
}
|
||||
#else /* CONFIG_IPCC_BUFFERED */
|
||||
/* In unbuffered operations we never write anything to IPCC
|
||||
|
|
@ -284,7 +284,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg)
|
|||
* or else we will constantly get TX interrupts
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan));
|
||||
modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan));
|
||||
#endif /* CONFIG_IPCC_BUFFERED */
|
||||
/* Wake up all blocked writers that there is free space available
|
||||
* in IPCC memory (or txbuffer) to write.
|
||||
|
|
@ -324,7 +324,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
|
|||
struct stm32wl5_ipcc_chan_mem_s *txmem;
|
||||
uint32_t sr;
|
||||
|
||||
sr = getreg32(STM32WL5_IPCC_C1TOC2SR);
|
||||
sr = getreg32(STM32_IPCC_C1TOC2SR);
|
||||
|
||||
if ((sr & (1 << ipcc->chan)))
|
||||
{
|
||||
|
|
@ -334,7 +334,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
|
|||
* so we are notified when we can write to memory.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -343,7 +343,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
|
|||
|
||||
/* Disable TX interrupt since we will modify shared data */
|
||||
|
||||
up_disable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT);
|
||||
up_disable_irq(STM32_IRQ_IPCC_C1_TX_IT);
|
||||
|
||||
/* Copy as much as we can into IPCC memory */
|
||||
|
||||
|
|
@ -353,12 +353,12 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc,
|
|||
|
||||
/* Tell another CPU that data is available to read */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(ipcc->chan));
|
||||
modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(ipcc->chan));
|
||||
|
||||
/* Re-enable interrupts */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0);
|
||||
up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0);
|
||||
up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT);
|
||||
|
||||
/* Return number of successfully copied bytes to IPCC memory */
|
||||
|
||||
|
|
@ -404,8 +404,8 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg)
|
|||
UNUSED(arg);
|
||||
UNUSED(irq);
|
||||
|
||||
mr = getreg32(STM32WL5_IPCC_C1MR);
|
||||
sr = getreg32(STM32WL5_IPCC_C2TOC1SR);
|
||||
mr = getreg32(STM32_IPCC_C1MR);
|
||||
sr = getreg32(STM32_IPCC_C2TOC1SR);
|
||||
|
||||
/* Consider only channels that have data in rx memory and are unmasked */
|
||||
|
||||
|
|
@ -446,7 +446,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg)
|
|||
* we have to mask rxirq so we don't get that irq again.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan));
|
||||
modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -485,7 +485,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
|
|||
struct stm32wl5_ipcc_s *priv;
|
||||
struct stm32wl5_ipcc_chan_mem_s *rxmem;
|
||||
|
||||
sr = getreg32(STM32WL5_IPCC_C2TOC1SR);
|
||||
sr = getreg32(STM32_IPCC_C2TOC1SR);
|
||||
|
||||
if (!(sr & (1 << ipcc->chan)))
|
||||
{
|
||||
|
|
@ -502,7 +502,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
|
|||
|
||||
/* Disable RX interrupt since we will modify shared data */
|
||||
|
||||
up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT);
|
||||
up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT);
|
||||
|
||||
/* This function may be called multiple times to get only part
|
||||
* of data from IPCC memory, ie. There are 8 bytes of data in
|
||||
|
|
@ -525,17 +525,17 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc,
|
|||
|
||||
/* Tell another CPU that IPCC rx buffer is free to be populated */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1SCR, 0,
|
||||
STM32WL5_IPCC_SCR_CHNC(ipcc->chan));
|
||||
modifyreg32(STM32_IPCC_C1SCR, 0,
|
||||
STM32_IPCC_SCR_CHNC(ipcc->chan));
|
||||
|
||||
/* Unmask RX interrupt to know when second CPU sends us a message */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(ipcc->chan), 0);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(ipcc->chan), 0);
|
||||
}
|
||||
|
||||
/* Re-enable interrupt */
|
||||
|
||||
up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT);
|
||||
up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT);
|
||||
|
||||
return to_copy;
|
||||
}
|
||||
|
|
@ -569,7 +569,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
|
|||
struct stm32wl5_ipcc_chan_mem_s *rxmem;
|
||||
uint32_t sr;
|
||||
|
||||
sr = getreg32(STM32WL5_IPCC_C2TOC1SR);
|
||||
sr = getreg32(STM32_IPCC_C2TOC1SR);
|
||||
|
||||
if (!(sr & (1 << chan)))
|
||||
{
|
||||
|
|
@ -609,7 +609,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
|
|||
* this one.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan));
|
||||
modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan));
|
||||
}
|
||||
|
||||
/* Buffer data. This function cannot really fail us if we
|
||||
|
|
@ -629,11 +629,11 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan,
|
|||
|
||||
/* Tell another CPU that IPCC rx buffer is free to be populated */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNC(chan));
|
||||
modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNC(chan));
|
||||
|
||||
/* Unmask RX interrupt to know when second CPU sends us a message */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0);
|
||||
}
|
||||
|
||||
return to_copy;
|
||||
|
|
@ -665,7 +665,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
|
|||
|
||||
/* Disable RX interrupt since we will modify shared data */
|
||||
|
||||
up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT);
|
||||
up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT);
|
||||
|
||||
/* Copy data to buffer */
|
||||
|
||||
|
|
@ -673,7 +673,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
|
|||
|
||||
/* Re-enable interrupt */
|
||||
|
||||
up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT);
|
||||
up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT);
|
||||
|
||||
/* Return number of bytes that were successfully buffered */
|
||||
|
||||
|
|
@ -701,7 +701,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc,
|
|||
#ifdef CONFIG_IPCC_BUFFERED
|
||||
static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc)
|
||||
{
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -728,8 +728,8 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc)
|
|||
|
||||
/* Mask interrupts for given channel */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNFM(ipcc->chan));
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNOM(ipcc->chan));
|
||||
modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNFM(ipcc->chan));
|
||||
modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNOM(ipcc->chan));
|
||||
|
||||
/* Free allocated ipcc memory */
|
||||
|
||||
|
|
@ -798,8 +798,8 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan)
|
|||
|
||||
/* Unmask channel interrupt */
|
||||
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(chan), 0);
|
||||
modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(chan), 0);
|
||||
modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0);
|
||||
|
||||
if (ipcc_fti)
|
||||
{
|
||||
|
|
@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan)
|
|||
* interrupt functions
|
||||
*/
|
||||
|
||||
ret = irq_attach(STM32WL5_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL);
|
||||
ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL);
|
||||
if (ret)
|
||||
{
|
||||
kmm_free(ipcc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ret = irq_attach(STM32WL5_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL);
|
||||
ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL);
|
||||
if (ret)
|
||||
{
|
||||
kmm_free(ipcc);
|
||||
|
|
@ -829,11 +829,11 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan)
|
|||
* - CPU2 has read message from us and TX memory is free to be used again
|
||||
*/
|
||||
|
||||
putreg32(STM32WL5_IPCC_CR_RXOIE | STM32WL5_IPCC_CR_TXFIE,
|
||||
STM32WL5_IPCC_C1CR);
|
||||
putreg32(STM32_IPCC_CR_RXOIE | STM32_IPCC_CR_TXFIE,
|
||||
STM32_IPCC_C1CR);
|
||||
|
||||
up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT);
|
||||
up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT);
|
||||
up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT);
|
||||
up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT);
|
||||
|
||||
ipcc_fti = 1;
|
||||
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@
|
|||
* of SRAM2. SRAM2 region will be right after IPCC reserved memory
|
||||
*/
|
||||
|
||||
#define IPCC_START STM32WL5_SRAM2_BASE
|
||||
#define IPCC_START STM32_SRAM2_BASE
|
||||
#define IPCC_NCHAN (IPCC_CHAN1 + IPCC_CHAN2 + IPCC_CHAN3 + \
|
||||
IPCC_CHAN4 + IPCC_CHAN5 + IPCC_CHAN6)
|
||||
#define IPCC_END (IPCC_START + IPCC_CHAN1_SIZE + IPCC_CHAN2_SIZE + \
|
||||
|
|
|
|||
|
|
@ -202,13 +202,13 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
|||
{
|
||||
int n;
|
||||
|
||||
DEBUGASSERT(irq >= STM32WL5_IRQ_NMI && irq < NR_IRQS);
|
||||
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= STM32WL5_IRQ_FIRST)
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
n = irq - STM32WL5_IRQ_FIRST;
|
||||
n = irq - STM32_IRQ_FIRST;
|
||||
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
|
||||
*bit = (uint32_t)1 << (n & 0x1f);
|
||||
}
|
||||
|
|
@ -218,19 +218,19 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
|||
else
|
||||
{
|
||||
*regaddr = NVIC_SYSHCON;
|
||||
if (irq == STM32WL5_IRQ_MEMFAULT)
|
||||
if (irq == STM32_IRQ_MEMFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_MEMFAULTENA;
|
||||
}
|
||||
else if (irq == STM32WL5_IRQ_BUSFAULT)
|
||||
else if (irq == STM32_IRQ_BUSFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_BUSFAULTENA;
|
||||
}
|
||||
else if (irq == STM32WL5_IRQ_USAGEFAULT)
|
||||
else if (irq == STM32_IRQ_USAGEFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_USGFAULTENA;
|
||||
}
|
||||
else if (irq == STM32WL5_IRQ_SYSTICK)
|
||||
else if (irq == STM32_IRQ_SYSTICK)
|
||||
{
|
||||
*regaddr = NVIC_SYSTICK_CTRL;
|
||||
*bit = NVIC_SYSTICK_CTRL_ENABLE;
|
||||
|
|
@ -260,7 +260,7 @@ void up_irqinitialize(void)
|
|||
|
||||
/* Disable all interrupts */
|
||||
|
||||
for (i = 0; i < NR_IRQS - STM32WL5_IRQ_FIRST; i += 32)
|
||||
for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32)
|
||||
{
|
||||
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
|
||||
}
|
||||
|
|
@ -314,13 +314,13 @@ void up_irqinitialize(void)
|
|||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(STM32WL5_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(STM32WL5_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(STM32WL5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
|
||||
stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
|
||||
|
|
@ -330,23 +330,23 @@ void up_irqinitialize(void)
|
|||
*/
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(STM32WL5_IRQ_MEMFAULT);
|
||||
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(STM32_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(STM32WL5_IRQ_NMI, stm32wl5_nmi, NULL);
|
||||
irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL);
|
||||
#ifndef CONFIG_ARM_MPU
|
||||
irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
#endif
|
||||
irq_attach(STM32WL5_IRQ_BUSFAULT, arm_busfault, NULL);
|
||||
irq_attach(STM32WL5_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
||||
irq_attach(STM32WL5_IRQ_PENDSV, stm32wl5_pendsv, NULL);
|
||||
irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL);
|
||||
irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
||||
irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL);
|
||||
arm_enable_dbgmonitor();
|
||||
irq_attach(STM32WL5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
|
||||
irq_attach(STM32WL5_IRQ_RESERVED, stm32wl5_reserved, NULL);
|
||||
irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
|
||||
irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL);
|
||||
#endif
|
||||
|
||||
stm32wl5_dumpnvic("initial", NR_IRQS);
|
||||
|
|
@ -382,7 +382,7 @@ void up_disable_irq(int irq)
|
|||
* clear the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= STM32WL5_IRQ_FIRST)
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
|
|
@ -417,7 +417,7 @@ void up_enable_irq(int irq)
|
|||
* set the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= STM32WL5_IRQ_FIRST)
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
|
|
@ -460,10 +460,10 @@ int up_prioritize_irq(int irq, int priority)
|
|||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= STM32WL5_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
if (irq < STM32WL5_IRQ_FIRST)
|
||||
if (irq < STM32_IRQ_FIRST)
|
||||
{
|
||||
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
||||
* registers (0-3 are invalid)
|
||||
|
|
@ -476,7 +476,7 @@ int up_prioritize_irq(int irq, int priority)
|
|||
{
|
||||
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
||||
|
||||
irq -= STM32WL5_IRQ_FIRST;
|
||||
irq -= STM32_IRQ_FIRST;
|
||||
regaddr = NVIC_IRQ_PRIORITY(irq);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -47,70 +47,70 @@
|
|||
|
||||
#ifdef HAVE_CONSOLE
|
||||
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
|
||||
# define STM32WL5_CONSOLE_BASE STM32WL5_LPUART1_BASE
|
||||
# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY
|
||||
# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR2
|
||||
# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
|
||||
# define STM32WL5_CONSOLE_BAUD CONFIG_LPUART1_BAUD
|
||||
# define STM32WL5_CONSOLE_BITS CONFIG_LPUART1_BITS
|
||||
# define STM32WL5_CONSOLE_PARITY CONFIG_LPUART1_PARITY
|
||||
# define STM32WL5_CONSOLE_2STOP CONFIG_LPUART1_2STOP
|
||||
# define STM32WL5_CONSOLE_TX GPIO_LPUART1_TX
|
||||
# define STM32WL5_CONSOLE_RX GPIO_LPUART1_RX
|
||||
# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_LPUART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_LPUART1_RX
|
||||
# ifdef CONFIG_LPUART1_RS485
|
||||
# define STM32WL5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
|
||||
# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
|
||||
# define STM32WL5_CONSOLE_BASE STM32WL5_USART1_BASE
|
||||
# define STM32WL5_APBCLOCK STM32WL5_PCLK2_FREQUENCY
|
||||
# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB2ENR
|
||||
# define STM32WL5_CONSOLE_APBEN RCC_APB2ENR_USART1EN
|
||||
# define STM32WL5_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32WL5_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32WL5_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32WL5_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# define STM32WL5_CONSOLE_TX GPIO_USART1_TX
|
||||
# define STM32WL5_CONSOLE_RX GPIO_USART1_RX
|
||||
# define STM32_CONSOLE_BASE STM32_USART1_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
|
||||
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART1_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART1_RX
|
||||
# ifdef CONFIG_USART1_RS485
|
||||
# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
|
||||
# define STM32WL5_CONSOLE_BASE STM32WL5_USART2_BASE
|
||||
# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY
|
||||
# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR1
|
||||
# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
|
||||
# define STM32WL5_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32WL5_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32WL5_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32WL5_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# define STM32WL5_CONSOLE_TX GPIO_USART2_TX
|
||||
# define STM32WL5_CONSOLE_RX GPIO_USART2_RX
|
||||
# define STM32_CONSOLE_BASE STM32_USART2_BASE
|
||||
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
|
||||
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
|
||||
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
|
||||
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
|
||||
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
|
||||
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
|
||||
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
|
||||
# define STM32_CONSOLE_TX GPIO_USART2_TX
|
||||
# define STM32_CONSOLE_RX GPIO_USART2_RX
|
||||
# ifdef CONFIG_USART2_RS485
|
||||
# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY false
|
||||
# else
|
||||
# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true
|
||||
# define STM32_CONSOLE_RS485_DIR_POLARITY true
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* CR1 settings */
|
||||
|
||||
# if STM32WL5_CONSOLE_BITS == 9
|
||||
# if STM32_CONSOLE_BITS == 9
|
||||
# define USART_CR1_M0_VALUE USART_CR1_M0
|
||||
# define USART_CR1_M1_VALUE 0
|
||||
# elif STM32WL5_CONSOLE_BITS == 7
|
||||
# elif STM32_CONSOLE_BITS == 7
|
||||
# define USART_CR1_M0_VALUE 0
|
||||
# define USART_CR1_M1_VALUE USART_CR1_M1
|
||||
# else /* 8 bits */
|
||||
|
|
@ -118,9 +118,9 @@
|
|||
# define USART_CR1_M1_VALUE 0
|
||||
# endif
|
||||
|
||||
# if STM32WL5_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
|
||||
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
|
||||
# elif STM32WL5_CONSOLE_PARITY == 2 /* even parity */
|
||||
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
|
||||
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
|
||||
# else /* no parity */
|
||||
# define USART_CR1_PARITY_VALUE 0
|
||||
|
|
@ -136,7 +136,7 @@
|
|||
|
||||
/* CR2 settings */
|
||||
|
||||
# if STM32WL5_CONSOLE_2STOP != 0
|
||||
# if STM32_CONSOLE_2STOP != 0
|
||||
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
|
||||
# else
|
||||
# define USART_CR2_STOP2_VALUE 0
|
||||
|
|
@ -178,24 +178,24 @@
|
|||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
# define STM32WL5_USARTDIV8 \
|
||||
(((STM32WL5_APBCLOCK << 1) + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD)
|
||||
# define STM32WL5_USARTDIV16 \
|
||||
((STM32WL5_APBCLOCK + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small. But what is small? */
|
||||
|
||||
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
|
||||
/* lpuart has different formula for baud rate than normal uart */
|
||||
# define STM32WL5_BRR_VALUE \
|
||||
(((256ull * STM32WL5_APBCLOCK) / STM32WL5_CONSOLE_BAUD) & LPUART_BRR_MASK)
|
||||
# define STM32_BRR_VALUE \
|
||||
(((256ull * STM32_APBCLOCK) / STM32_CONSOLE_BAUD) & LPUART_BRR_MASK)
|
||||
# else /* CONFIG_LPUART1_SERIAL_CONSOLE */
|
||||
# if STM32WL5_USARTDIV8 > 2000
|
||||
# define STM32WL5_BRR_VALUE STM32WL5_USARTDIV16
|
||||
# if STM32_USARTDIV8 > 2000
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32WL5_BRR_VALUE \
|
||||
((STM32WL5_USARTDIV8 & 0xfff0) | ((STM32WL5_USARTDIV8 & 0x000f) >> 1))
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||
# endif
|
||||
# endif /* CONFIG_LPUART1_SERIAL_CONSOLE */
|
||||
|
||||
|
|
@ -238,22 +238,22 @@ void arm_lowputc(char ch)
|
|||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX data register is empty */
|
||||
|
||||
while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) &
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TXE) == 0);
|
||||
#ifdef STM32WL5_CONSOLE_RS485_DIR
|
||||
stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR,
|
||||
STM32WL5_CONSOLE_RS485_DIR_POLARITY);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32WL5_CONSOLE_BASE + STM32WL5_USART_TDR_OFFSET);
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#ifdef STM32WL5_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) &
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TC) == 0);
|
||||
stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR,
|
||||
!STM32WL5_CONSOLE_RS485_DIR_POLARITY);
|
||||
stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
!STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_CONSOLE */
|
||||
|
|
@ -279,7 +279,7 @@ void stm32wl5_lowsetup(void)
|
|||
#if defined(HAVE_CONSOLE)
|
||||
/* Enable USART APB1/2 clock */
|
||||
|
||||
modifyreg32(STM32WL5_CONSOLE_APBREG, 0, STM32WL5_CONSOLE_APBEN);
|
||||
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
|
||||
#endif
|
||||
|
||||
/* Enable the console USART and configure GPIO pins needed for rx/tx.
|
||||
|
|
@ -288,17 +288,17 @@ void stm32wl5_lowsetup(void)
|
|||
* stm32wl5_rcc.c
|
||||
*/
|
||||
|
||||
#ifdef STM32WL5_CONSOLE_TX
|
||||
stm32wl5_configgpio(STM32WL5_CONSOLE_TX);
|
||||
#ifdef STM32_CONSOLE_TX
|
||||
stm32wl5_configgpio(STM32_CONSOLE_TX);
|
||||
#endif
|
||||
#ifdef STM32WL5_CONSOLE_RX
|
||||
stm32wl5_configgpio(STM32WL5_CONSOLE_RX);
|
||||
#ifdef STM32_CONSOLE_RX
|
||||
stm32wl5_configgpio(STM32_CONSOLE_RX);
|
||||
#endif
|
||||
|
||||
#ifdef STM32WL5_CONSOLE_RS485_DIR
|
||||
stm32wl5_configgpio(STM32WL5_CONSOLE_RS485_DIR);
|
||||
stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR,
|
||||
!STM32WL5_CONSOLE_RS485_DIR_POLARITY);
|
||||
#ifdef STM32_CONSOLE_RS485_DIR
|
||||
stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR);
|
||||
stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR,
|
||||
!STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||
#endif
|
||||
|
||||
/* Enable and configure the selected console device */
|
||||
|
|
@ -306,42 +306,42 @@ void stm32wl5_lowsetup(void)
|
|||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Configure CR2 */
|
||||
|
||||
cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
cr &= ~USART_CR2_CLRBITS;
|
||||
cr |= USART_CR2_SETBITS;
|
||||
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr &= ~USART_CR1_CLRBITS;
|
||||
cr |= USART_CR1_SETBITS;
|
||||
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_CLRBITS;
|
||||
cr |= USART_CR3_SETBITS;
|
||||
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Configure the USART Baud Rate */
|
||||
|
||||
putreg32(STM32WL5_BRR_VALUE,
|
||||
STM32WL5_CONSOLE_BASE + STM32WL5_USART_BRR_OFFSET);
|
||||
putreg32(STM32_BRR_VALUE,
|
||||
STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#ifdef USE_OVER8
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET);
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
|
||||
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif /* HAVE_UART */
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ void stm32wl5_rcc_enablelse(void)
|
|||
* clock are already running.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_BDCR);
|
||||
regval = getreg32(STM32_RCC_BDCR);
|
||||
|
||||
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
|
||||
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) !=
|
||||
|
|
@ -117,7 +117,7 @@ void stm32wl5_rcc_enablelse(void)
|
|||
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
|
||||
regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
|
||||
RCC_BDCR_LSEDRV_SHIFT;
|
||||
putreg32(regval, STM32WL5_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
#endif
|
||||
|
||||
|
|
@ -126,11 +126,11 @@ void stm32wl5_rcc_enablelse(void)
|
|||
{
|
||||
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
|
||||
regval |= drives[drive++];
|
||||
putreg32(regval, STM32WL5_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE clock to be ready (or until a timeout elapsed)
|
||||
*/
|
||||
|
|
@ -139,7 +139,7 @@ void stm32wl5_rcc_enablelse(void)
|
|||
{
|
||||
/* Check if the LSERDY flag is the set in the BDCR */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_BDCR);
|
||||
regval = getreg32(STM32_RCC_BDCR);
|
||||
|
||||
if (regval & RCC_BDCR_LSERDY)
|
||||
{
|
||||
|
|
@ -167,11 +167,11 @@ void stm32wl5_rcc_enablelse(void)
|
|||
|
||||
regval |= RCC_BDCR_LSESYSEN;
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE system clock to be ready */
|
||||
|
||||
while (!((regval = getreg32(STM32WL5_RCC_BDCR)) &
|
||||
while (!((regval = getreg32(STM32_RCC_BDCR)) &
|
||||
RCC_BDCR_LSESYSRDY))
|
||||
{
|
||||
stm32wl5_waste();
|
||||
|
|
@ -184,7 +184,7 @@ void stm32wl5_rcc_enablelse(void)
|
|||
|
||||
regval &= ~RCC_BDCR_LSEDRV_MASK;
|
||||
regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT;
|
||||
putreg32(regval, STM32WL5_RCC_BDCR);
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
#endif
|
||||
|
||||
/* Disable backup domain access if it was disabled on entry */
|
||||
|
|
|
|||
|
|
@ -46,11 +46,11 @@ void stm32wl5_rcc_enablelsi(void)
|
|||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_RCC_CSR, 0, RCC_CSR_LSION);
|
||||
modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
|
||||
|
||||
/* Wait for the internal LSI oscillator to be stable. */
|
||||
|
||||
while ((getreg32(STM32WL5_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
|
||||
while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -67,7 +67,7 @@ void stm32wl5_rcc_disablelsi(void)
|
|||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_RCC_CSR, RCC_CSR_LSION, 0);
|
||||
modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
|
||||
|
||||
/* LSIRDY should go low after 3 LSI clock cycles */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,18 +42,18 @@
|
|||
|
||||
static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset)
|
||||
{
|
||||
return (uint16_t)getreg32(STM32WL5_PWR_BASE + (uint32_t)offset);
|
||||
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value)
|
||||
{
|
||||
putreg32((uint32_t)value, STM32WL5_PWR_BASE + (uint32_t)offset);
|
||||
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
|
||||
uint16_t setbits)
|
||||
{
|
||||
modifyreg32(STM32WL5_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits,
|
||||
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits,
|
||||
(uint32_t)setbits);
|
||||
}
|
||||
|
||||
|
|
@ -83,7 +83,7 @@ bool stm32wl5_pwr_enablebkp(bool writable)
|
|||
|
||||
/* Get the current state of the STM32WL5 PWR control register 1 */
|
||||
|
||||
regval = stm32wl5_pwr_getreg(STM32WL5_PWR_CR1_OFFSET);
|
||||
regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
waswritable = ((regval & PWR_CR1_DBP) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
|
@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable)
|
|||
/* Disable backup domain access */
|
||||
|
||||
regval &= ~PWR_CR1_DBP;
|
||||
stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval);
|
||||
stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
else if (!waswritable && writable)
|
||||
{
|
||||
/* Enable backup domain access */
|
||||
|
||||
regval |= PWR_CR1_DBP;
|
||||
stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval);
|
||||
stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
|
||||
/* Enable does not happen right away */
|
||||
|
||||
|
|
@ -121,5 +121,5 @@ bool stm32wl5_pwr_enablebkp(bool writable)
|
|||
|
||||
void stm32wl5_pwr_boot_c2(void)
|
||||
{
|
||||
modifyreg32(STM32WL5_PWR_CR4, 0, PWR_CR4_C2BOOT);
|
||||
modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -84,14 +84,14 @@ static inline void stm32wl5_rcc_resetbkp(void)
|
|||
init_stat = stm32wl5_rtc_is_initialized();
|
||||
if (!init_stat)
|
||||
{
|
||||
uint32_t bkregs[STM32WL5_RTC_BKCOUNT];
|
||||
uint32_t bkregs[STM32_RTC_BKCOUNT];
|
||||
int i;
|
||||
|
||||
/* Backup backup-registers before RTC reset. */
|
||||
|
||||
for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++)
|
||||
for (i = 0; i < STM32_RTC_BKCOUNT; i++)
|
||||
{
|
||||
bkregs[i] = getreg32(STM32WL5_RTC_BKR(i));
|
||||
bkregs[i] = getreg32(STM32_RTC_BKR(i));
|
||||
}
|
||||
|
||||
/* Enable write access to the backup domain (RTC registers, RTC
|
||||
|
|
@ -104,19 +104,19 @@ static inline void stm32wl5_rcc_resetbkp(void)
|
|||
* reset the backup domain (having backed up the RTC_MAGIC token)
|
||||
*/
|
||||
|
||||
modifyreg32(STM32WL5_RCC_BDCR, 0, RCC_BDCR_BDRST);
|
||||
modifyreg32(STM32WL5_RCC_BDCR, RCC_BDCR_BDRST, 0);
|
||||
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
|
||||
|
||||
/* Restore backup-registers, except RTC related. */
|
||||
|
||||
for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++)
|
||||
for (i = 0; i < STM32_RTC_BKCOUNT; i++)
|
||||
{
|
||||
if (RTC_MAGIC_REG == STM32WL5_RTC_BKR(i))
|
||||
if (RTC_MAGIC_REG == STM32_RTC_BKR(i))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
putreg32(bkregs[i], STM32WL5_RTC_BKR(i));
|
||||
putreg32(bkregs[i], STM32_RTC_BKR(i));
|
||||
}
|
||||
|
||||
(void)stm32wl5_pwr_enablebkp(false);
|
||||
|
|
@ -199,7 +199,7 @@ static void stm32wl5_rcc_enableahb1(void)
|
|||
* selected AHB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_AHB1ENR);
|
||||
regval = getreg32(STM32_RCC_AHB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32WL5_DMA1
|
||||
/* DMA 1 clock enable */
|
||||
|
|
@ -219,7 +219,7 @@ static void stm32wl5_rcc_enableahb1(void)
|
|||
regval |= RCC_AHB1ENR_CRCEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_AHB1ENR); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -238,25 +238,25 @@ static inline void stm32wl5_rcc_enableahb2(void)
|
|||
* selected AHB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_AHB2ENR);
|
||||
regval = getreg32(STM32_RCC_AHB2ENR);
|
||||
|
||||
/* Enable GPIOA, GPIOB, .... GPIOH */
|
||||
|
||||
#if STM32WL5_NPORTS > 0
|
||||
#if STM32_NPORTS > 0
|
||||
regval |= (RCC_AHB2ENR_GPIOAEN
|
||||
#if STM32WL5_NPORTS > 1
|
||||
#if STM32_NPORTS > 1
|
||||
| RCC_AHB2ENR_GPIOBEN
|
||||
#endif
|
||||
#if STM32WL5_NPORTS > 2
|
||||
#if STM32_NPORTS > 2
|
||||
| RCC_AHB2ENR_GPIOCEN
|
||||
#endif
|
||||
#if STM32WL5_NPORTS > 3
|
||||
#if STM32_NPORTS > 3
|
||||
| RCC_AHB2ENR_GPIOHEN
|
||||
#endif
|
||||
);
|
||||
#endif /* STM32WL5_NPORTS */
|
||||
#endif /* STM32_NPORTS */
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_AHB2ENR); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -275,7 +275,7 @@ static inline void stm32wl5_rcc_enableahb3(void)
|
|||
* selected AHB3 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_AHB3ENR);
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
|
||||
#ifdef CONFIG_STM32WL5_AES
|
||||
/* Cryptographic modules clock enable */
|
||||
|
|
@ -301,7 +301,7 @@ static inline void stm32wl5_rcc_enableahb3(void)
|
|||
regval |= RCC_AHB3ENR_IPCCEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_AHB3ENR); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -320,7 +320,7 @@ static inline void stm32wl5_rcc_enableapb1(void)
|
|||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_APB1ENR1);
|
||||
regval = getreg32(STM32_RCC_APB1ENR1);
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
/* TIM2 clock enable */
|
||||
|
|
@ -370,11 +370,11 @@ static inline void stm32wl5_rcc_enableapb1(void)
|
|||
regval |= RCC_APB1ENR1_LPTIM1EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_APB1ENR1); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */
|
||||
|
||||
/* Second APB1 register */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_APB1ENR2);
|
||||
regval = getreg32(STM32_RCC_APB1ENR2);
|
||||
|
||||
#ifdef CONFIG_STM32WL5_LPUART1
|
||||
/* Low power uart clock enable */
|
||||
|
|
@ -394,7 +394,7 @@ static inline void stm32wl5_rcc_enableapb1(void)
|
|||
regval |= RCC_APB1ENR2_LPTIM3EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_APB1ENR2); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -413,7 +413,7 @@ static inline void stm32wl5_rcc_enableapb2(void)
|
|||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_APB2ENR);
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#if defined(CONFIG_STM32WL5_ADC1)
|
||||
/* ADC clock enable */
|
||||
|
|
@ -451,7 +451,7 @@ static inline void stm32wl5_rcc_enableapb2(void)
|
|||
regval |= RCC_APB2ENR_TIM17EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_APB2ENR); /* Enable peripherals */
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -471,9 +471,9 @@ static inline void stm32wl5_rcc_enableccip(void)
|
|||
* will at least have a clock.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CCIPR);
|
||||
regval = getreg32(STM32_RCC_CCIPR);
|
||||
|
||||
#if defined(STM32WL5_I2C_USE_HSI16)
|
||||
#if defined(STM32_I2C_USE_HSI16)
|
||||
#ifdef CONFIG_STM32WL5_I2C1
|
||||
/* Select HSI16 as I2C1 clock source. */
|
||||
|
||||
|
|
@ -489,15 +489,15 @@ static inline void stm32wl5_rcc_enableccip(void)
|
|||
|
||||
regval |= RCC_CCIPR_I2C3SEL_HSI;
|
||||
#endif
|
||||
#endif /* STM32WL5_I2C_USE_HSI16 */
|
||||
#endif /* STM32_I2C_USE_HSI16 */
|
||||
|
||||
#if defined(STM32WL5_USE_CLK48)
|
||||
#if defined(STM32_USE_CLK48)
|
||||
/* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
|
||||
* and then we can also do away with STM32WL5_USE_CLK48, and give better
|
||||
* and then we can also do away with STM32_USE_CLK48, and give better
|
||||
* warning messages.
|
||||
*/
|
||||
|
||||
regval |= STM32WL5_CLK48_SEL;
|
||||
regval |= STM32_CLK48_SEL;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32WL5_ADC1)
|
||||
|
|
@ -518,19 +518,19 @@ static inline void stm32wl5_rcc_enableccip(void)
|
|||
regval |= RCC_CCIPR_DFSDMSEL_SYSCLK;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_CCIPR);
|
||||
putreg32(regval, STM32_RCC_CCIPR);
|
||||
|
||||
/* I2C4 alone has their clock selection in CCIPR2 register. */
|
||||
|
||||
#if defined(STM32WL5_I2C_USE_HSI16)
|
||||
#if defined(STM32_I2C_USE_HSI16)
|
||||
#ifdef CONFIG_STM32WL5_I2C4
|
||||
regval = getreg32(STM32WL5_RCC_CCIPR2);
|
||||
regval = getreg32(STM32_RCC_CCIPR2);
|
||||
|
||||
/* Select HSI16 as I2C4 clock source. */
|
||||
|
||||
regval |= RCC_CCIPR_I2C4SEL_HSI;
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_CCIPR2);
|
||||
putreg32(regval, STM32_RCC_CCIPR2);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
|
@ -610,12 +610,12 @@ void stm32wl5_stdclockconfig(void)
|
|||
{
|
||||
uint32_t regval;
|
||||
|
||||
#if defined(STM32WL5_BOARD_USEHSI) || defined(STM32WL5_I2C_USE_HSI16)
|
||||
#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16)
|
||||
/* Enable Internal High-Speed Clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSION; /* Enable HSI */
|
||||
putreg32(regval, STM32WL5_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI is ready */
|
||||
|
||||
|
|
@ -623,7 +623,7 @@ void stm32wl5_stdclockconfig(void)
|
|||
{
|
||||
/* Check if the HSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSIRDY) != 0)
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out */
|
||||
|
||||
|
|
@ -632,17 +632,17 @@ void stm32wl5_stdclockconfig(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(STM32WL5_BOARD_USEHSI)
|
||||
#if defined(STM32_BOARD_USEHSI)
|
||||
/* Already set above */
|
||||
|
||||
#elif defined(STM32WL5_BOARD_USEMSI)
|
||||
#elif defined(STM32_BOARD_USEMSI)
|
||||
/* Enable Internal Multi-Speed Clock (MSI) */
|
||||
|
||||
/* Wait until the MSI is either off or ready */
|
||||
|
||||
for (; ; )
|
||||
{
|
||||
if ((regval = getreg32(STM32WL5_RCC_CR)),
|
||||
if ((regval = getreg32(STM32_RCC_CR)),
|
||||
(regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
|
||||
{
|
||||
/* If so, then break-out */
|
||||
|
|
@ -653,9 +653,9 @@ void stm32wl5_stdclockconfig(void)
|
|||
|
||||
/* setting MSIRANGE */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CR);
|
||||
regval |= (STM32WL5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
|
||||
putreg32(regval, STM32WL5_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the MSI is ready */
|
||||
|
||||
|
|
@ -663,7 +663,7 @@ void stm32wl5_stdclockconfig(void)
|
|||
{
|
||||
/* Check if the MSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_MSIRDY) != 0)
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out */
|
||||
|
||||
|
|
@ -671,23 +671,23 @@ void stm32wl5_stdclockconfig(void)
|
|||
}
|
||||
}
|
||||
|
||||
#elif defined(STM32WL5_BOARD_USEHSE)
|
||||
#elif defined(STM32_BOARD_USEHSE)
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
#if defined(STM32WL5_BOARD_USETCXO)
|
||||
#if defined(STM32_BOARD_USETCXO)
|
||||
/* nucleo-wl55jc uses TCXO crystal, which needs to be first
|
||||
* powered up with PB0 pin - or more conveniently by setting
|
||||
* HSEBYPPWR register. This has to be done before HSE is enabled
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSEBYPPWR;
|
||||
putreg32(regval, STM32WL5_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
#endif
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32WL5_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready */
|
||||
|
||||
|
|
@ -695,7 +695,7 @@ void stm32wl5_stdclockconfig(void)
|
|||
{
|
||||
/* Check if the HSERDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then break-out */
|
||||
|
||||
|
|
@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void)
|
|||
}
|
||||
#else
|
||||
|
||||
# error stm32wl5_stdclockconfig(), must have one of STM32WL5_BOARD_USEHSI, STM32WL5_BOARD_USEMSI, STM32WL5_BOARD_USEHSE defined
|
||||
# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -714,10 +714,10 @@ void stm32wl5_stdclockconfig(void)
|
|||
|
||||
/* Select correct main regulator range */
|
||||
|
||||
regval = getreg32(STM32WL5_PWR_CR1);
|
||||
regval = getreg32(STM32_PWR_CR1);
|
||||
regval &= ~PWR_CR1_VOS_MASK;
|
||||
|
||||
if (STM32WL5_SYSCLK_FREQUENCY <= 16000000)
|
||||
if (STM32_SYSCLK_FREQUENCY <= 16000000)
|
||||
{
|
||||
/* set low power range for frequencies <= 16MHz */
|
||||
|
||||
|
|
@ -730,121 +730,121 @@ void stm32wl5_stdclockconfig(void)
|
|||
regval |= PWR_CR1_VOS_RANGE1;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32WL5_PWR_CR1);
|
||||
putreg32(regval, STM32_PWR_CR1);
|
||||
|
||||
/* Wait for voltage regulator to stabilize */
|
||||
|
||||
while (getreg32(STM32WL5_PWR_SR2) & PWR_SR2_VOSF)
|
||||
while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF)
|
||||
{
|
||||
}
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32WL5_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32WL5_RCC_CFGR);
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32WL5_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32WL5_RCC_CFGR);
|
||||
regval |= STM32_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32WL5_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32WL5_RCC_CFGR);
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_STM32WL5_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
||||
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
||||
putreg32(regval, STM32WL5_RCC_CFGR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
#endif
|
||||
|
||||
/* Set the PLL source and main divider */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_PLLCFG);
|
||||
regval = getreg32(STM32_RCC_PLLCFG);
|
||||
|
||||
/* Configure Main PLL */
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
regval = (STM32WL5_PLLCFG_PLLM | STM32WL5_PLLCFG_PLLN |
|
||||
STM32WL5_PLLCFG_PLLP | STM32WL5_PLLCFG_PLLQ |
|
||||
STM32WL5_PLLCFG_PLLR);
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |
|
||||
STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ |
|
||||
STM32_PLLCFG_PLLR);
|
||||
|
||||
#ifdef STM32WL5_PLLCFG_PLLP_ENABLED
|
||||
#ifdef STM32_PLLCFG_PLLP_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLPEN;
|
||||
#endif
|
||||
#ifdef STM32WL5_PLLCFG_PLLQ_ENABLED
|
||||
#ifdef STM32_PLLCFG_PLLQ_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLQEN;
|
||||
#endif
|
||||
#ifdef STM32WL5_PLLCFG_PLLR_ENABLED
|
||||
#ifdef STM32_PLLCFG_PLLR_ENABLED
|
||||
regval |= RCC_PLLCFG_PLLREN;
|
||||
#endif
|
||||
|
||||
/* XXX The choice of clock source to PLL (all three) is independent
|
||||
* of the sys clock source choice, review the STM32WL5_BOARD_USEHSI
|
||||
* of the sys clock source choice, review the STM32_BOARD_USEHSI
|
||||
* name; probably split it into two, one for PLL source and one
|
||||
* for sys clock source.
|
||||
*/
|
||||
|
||||
#ifdef STM32WL5_BOARD_USEHSI
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
regval |= RCC_PLLCFG_PLLSRC_HSI16;
|
||||
#elif defined(STM32WL5_BOARD_USEMSI)
|
||||
#elif defined(STM32_BOARD_USEMSI)
|
||||
regval |= RCC_PLLCFG_PLLSRC_MSI;
|
||||
#else /* if STM32WL5_BOARD_USEHSE */
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
regval |= RCC_PLLCFG_PLLSRC_HSE;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32WL5_RCC_PLLCFG);
|
||||
putreg32(regval, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Enable the main PLL */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CR);
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32WL5_RCC_CR);
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32WL5_RCC_CR) & RCC_CR_PLLRDY) == 0)
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure flash wait states according to manual */
|
||||
|
||||
if (STM32WL5_HCLK3_FREQUENCY <= 18000000 /* 18MHz */)
|
||||
if (STM32_HCLK3_FREQUENCY <= 18000000 /* 18MHz */)
|
||||
{
|
||||
regval = FLASH_ACR_LATENCY_0;
|
||||
}
|
||||
else if (STM32WL5_HCLK3_FREQUENCY <= 36000000 /* 36MHz */)
|
||||
else if (STM32_HCLK3_FREQUENCY <= 36000000 /* 36MHz */)
|
||||
{
|
||||
regval = FLASH_ACR_LATENCY_1;
|
||||
}
|
||||
else /* STM32WL5_HCLK3_FREQUENCY <= 48MHz */
|
||||
else /* STM32_HCLK3_FREQUENCY <= 48MHz */
|
||||
{
|
||||
regval = FLASH_ACR_LATENCY_2;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32WL5_FLASH_ACR);
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= RCC_CFGR_SW_PLL;
|
||||
putreg32(regval, STM32WL5_RCC_CFGR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32WL5_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -77,10 +77,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source)
|
|||
|
||||
/* Set MCO source */
|
||||
|
||||
regval = getreg32(STM32WL5_RCC_CFGR);
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~(RCC_CFGR_MCOSEL_MASK);
|
||||
regval |= (source & RCC_CFGR_MCOSEL_MASK);
|
||||
putreg32(regval, STM32WL5_RCC_CFGR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
|
|||
|
|
@ -418,13 +418,13 @@ static struct stm32wl5_serial_s g_lpuart1priv =
|
|||
.priv = &g_lpuart1priv,
|
||||
},
|
||||
|
||||
.irq = STM32WL5_IRQ_LPUART1,
|
||||
.irq = STM32_IRQ_LPUART1,
|
||||
.parity = CONFIG_LPUART1_PARITY,
|
||||
.bits = CONFIG_LPUART1_BITS,
|
||||
.stopbits2 = CONFIG_LPUART1_2STOP,
|
||||
.baud = CONFIG_LPUART1_BAUD,
|
||||
.apbclock = STM32WL5_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32WL5_LPUART1_BASE,
|
||||
.apbclock = STM32_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32_LPUART1_BASE,
|
||||
.tx_gpio = GPIO_LPUART1_TX,
|
||||
.rx_gpio = GPIO_LPUART1_RX,
|
||||
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
|
||||
|
|
@ -478,13 +478,13 @@ static struct stm32wl5_serial_s g_usart1priv =
|
|||
.priv = &g_usart1priv,
|
||||
},
|
||||
|
||||
.irq = STM32WL5_IRQ_USART1,
|
||||
.irq = STM32_IRQ_USART1,
|
||||
.parity = CONFIG_USART1_PARITY,
|
||||
.bits = CONFIG_USART1_BITS,
|
||||
.stopbits2 = CONFIG_USART1_2STOP,
|
||||
.baud = CONFIG_USART1_BAUD,
|
||||
.apbclock = STM32WL5_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32WL5_USART1_BASE,
|
||||
.apbclock = STM32_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32_USART1_BASE,
|
||||
.tx_gpio = GPIO_USART1_TX,
|
||||
.rx_gpio = GPIO_USART1_RX,
|
||||
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
|
||||
|
|
@ -540,13 +540,13 @@ static struct stm32wl5_serial_s g_usart2priv =
|
|||
.priv = &g_usart2priv,
|
||||
},
|
||||
|
||||
.irq = STM32WL5_IRQ_USART2,
|
||||
.irq = STM32_IRQ_USART2,
|
||||
.parity = CONFIG_USART2_PARITY,
|
||||
.bits = CONFIG_USART2_BITS,
|
||||
.stopbits2 = CONFIG_USART2_2STOP,
|
||||
.baud = CONFIG_USART2_BAUD,
|
||||
.apbclock = STM32WL5_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32WL5_USART2_BASE,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART2_BASE,
|
||||
.tx_gpio = GPIO_USART2_TX,
|
||||
.rx_gpio = GPIO_USART2_RX,
|
||||
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
|
||||
|
|
@ -577,7 +577,7 @@ static struct stm32wl5_serial_s g_usart2priv =
|
|||
/* This table lets us iterate over the configured USARTs */
|
||||
|
||||
static struct stm32wl5_serial_s * const
|
||||
g_uart_devs[STM32WL5_NLPUART + STM32WL5_NUSART] =
|
||||
g_uart_devs[STM32_NLPUART + STM32_NUSART] =
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
|
||||
[0] = &g_lpuart1priv,
|
||||
|
|
@ -647,15 +647,15 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie)
|
|||
* above)
|
||||
*/
|
||||
|
||||
cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
cr = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
cr &= ~(USART_CR1_USED_INTS);
|
||||
cr |= (ie & (USART_CR1_USED_INTS));
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr);
|
||||
|
||||
cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET);
|
||||
cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
|
||||
cr &= ~USART_CR3_EIE;
|
||||
cr |= (ie & USART_CR3_EIE);
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -710,8 +710,8 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv,
|
|||
* USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used)
|
||||
*/
|
||||
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
cr3 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET);
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
cr3 = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
|
||||
|
||||
/* Return the current interrupt mask value for the used interrupts.
|
||||
* Notice that this depends on the fact that none of the used interrupt
|
||||
|
|
@ -772,7 +772,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
|
|||
uint32_t cr1;
|
||||
uint32_t brr;
|
||||
|
||||
if (priv->usartbase == STM32WL5_LPUART1_BASE)
|
||||
if (priv->usartbase == STM32_LPUART1_BASE)
|
||||
{
|
||||
/* lpuart has different calculations baudrate, and there is not
|
||||
* oversampling:
|
||||
|
|
@ -804,7 +804,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
|
|||
* But what is small?
|
||||
*/
|
||||
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
if (usartdiv8 > 2000)
|
||||
{
|
||||
/* Use usartdiv16 */
|
||||
|
|
@ -828,14 +828,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
|
|||
cr1 |= USART_CR1_OVER8;
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_BRR_OFFSET, brr);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr);
|
||||
|
||||
/* Configure parity mode */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1);
|
||||
|
||||
if (priv->parity == 1) /* Odd parity */
|
||||
|
|
@ -873,11 +873,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
|
|||
* 1 start, 8 data (no parity), n stop.
|
||||
*/
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure STOP bits */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~(USART_CR2_STOP_MASK);
|
||||
|
||||
if (priv->stopbits2)
|
||||
|
|
@ -885,11 +885,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
|
|||
regval |= USART_CR2_STOP2;
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure hardware flow control */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
|
||||
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN)
|
||||
|
|
@ -906,7 +906,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
}
|
||||
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
|
||||
|
||||
|
|
@ -951,7 +951,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend)
|
|||
|
||||
/* Wait last Tx to complete. */
|
||||
|
||||
while ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) &
|
||||
while ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TC) == 0);
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
|
|
@ -1057,7 +1057,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend)
|
|||
|
||||
g_serialpm.serial_suspended = suspend;
|
||||
|
||||
for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++)
|
||||
for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++)
|
||||
{
|
||||
struct stm32wl5_serial_s *priv = g_uart_devs[n];
|
||||
|
||||
|
|
@ -1097,21 +1097,21 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on)
|
|||
default:
|
||||
return;
|
||||
#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER
|
||||
case STM32WL5_LPUART1_BASE:
|
||||
case STM32_LPUART1_BASE:
|
||||
rcc_en = RCC_APB1ENR2_LPUART1EN;
|
||||
regaddr = STM32WL5_RCC_APB1ENR2;
|
||||
regaddr = STM32_RCC_APB1ENR2;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER
|
||||
case STM32WL5_USART1_BASE:
|
||||
case STM32_USART1_BASE:
|
||||
rcc_en = RCC_APB2ENR_USART1EN;
|
||||
regaddr = STM32WL5_RCC_APB2ENR;
|
||||
regaddr = STM32_RCC_APB2ENR;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER
|
||||
case STM32WL5_USART2_BASE:
|
||||
case STM32_USART2_BASE:
|
||||
rcc_en = RCC_APB1ENR1_USART2EN;
|
||||
regaddr = STM32WL5_RCC_APB1ENR1;
|
||||
regaddr = STM32_RCC_APB1ENR1;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1198,7 +1198,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
|
|||
|
||||
/* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL |
|
||||
USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE);
|
||||
|
||||
|
|
@ -1209,26 +1209,26 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
|
|||
regval |= USART_CR2_STOP2;
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure CR1 */
|
||||
|
||||
/* Clear TE, REm and all interrupt enable bits */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS);
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure CR3 */
|
||||
|
||||
/* Clear CTSE, RTSE, and all interrupt enable bits */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE |
|
||||
USART_CR3_EIE);
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
/* Configure the USART line format and speed. */
|
||||
|
||||
|
|
@ -1236,9 +1236,9 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev)
|
|||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
|
||||
|
||||
|
|
@ -1291,7 +1291,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
|
|||
/* Configure for non-circular DMA reception into the RX FIFO */
|
||||
|
||||
stm32wl5_dmasetup(priv->rxdma,
|
||||
priv->usartbase + STM32WL5_USART_RDR_OFFSET,
|
||||
priv->usartbase + STM32_USART_RDR_OFFSET,
|
||||
(uint32_t)priv->rxfifo,
|
||||
RXDMA_BUFFER_SIZE,
|
||||
SERIAL_DMA_IFLOW_CONTROL_WORD);
|
||||
|
|
@ -1302,7 +1302,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
|
|||
/* Configure for circular DMA reception into the RX FIFO */
|
||||
|
||||
stm32wl5_dmasetup(priv->rxdma,
|
||||
priv->usartbase + STM32WL5_USART_RDR_OFFSET,
|
||||
priv->usartbase + STM32_USART_RDR_OFFSET,
|
||||
(uint32_t)priv->rxfifo,
|
||||
RXDMA_BUFFER_SIZE,
|
||||
SERIAL_DMA_CONTROL_WORD);
|
||||
|
|
@ -1316,9 +1316,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev)
|
|||
|
||||
/* Enable receive DMA for the UART */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
|
||||
regval |= USART_CR3_DMAR;
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
||||
if (priv->iflow)
|
||||
|
|
@ -1376,9 +1376,9 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev)
|
|||
|
||||
/* Disable Rx, Tx, and the UART */
|
||||
|
||||
regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Release pins. "If the serial-attached device is powered down, the TX
|
||||
* pin causes back-powering, potentially confusing the device to the point
|
||||
|
|
@ -1544,7 +1544,7 @@ static int stm32wl5serial_interrupt(int irq, void *context,
|
|||
|
||||
/* Get the masked USART status word. */
|
||||
|
||||
priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET);
|
||||
priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET);
|
||||
|
||||
/* USART interrupts:
|
||||
*
|
||||
|
|
@ -1612,7 +1612,7 @@ static int stm32wl5serial_interrupt(int irq, void *context,
|
|||
* interrupt clear register (ICR).
|
||||
*/
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET,
|
||||
stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET,
|
||||
(USART_ICR_NCF | USART_ICR_ORECF |
|
||||
USART_ICR_FECF));
|
||||
}
|
||||
|
|
@ -1685,19 +1685,19 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
|
||||
/* Get the original state of UE */
|
||||
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
cr1_ue = cr1 & USART_CR1_UE;
|
||||
cr1 &= ~USART_CR1_UE;
|
||||
|
||||
/* Disable UE, HDSEL can only be written when UE=0 */
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
|
||||
/* Change the TX port to be open-drain/push-pull and enable/disable
|
||||
* half-duplex mode.
|
||||
*/
|
||||
|
||||
uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET);
|
||||
uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET);
|
||||
|
||||
if ((arg & SER_SINGLEWIRE_ENABLED) != 0)
|
||||
{
|
||||
|
|
@ -1742,11 +1742,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
cr &= ~USART_CR3_HDSEL;
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr);
|
||||
|
||||
/* Re-enable UE if appropriate */
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1763,17 +1763,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
|
||||
/* Get the original state of UE */
|
||||
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
cr1_ue = cr1 & USART_CR1_UE;
|
||||
cr1 &= ~USART_CR1_UE;
|
||||
|
||||
/* Disable UE, {R,T}XINV can only be written when UE=0 */
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
|
||||
/* Enable/disable signal inversion. */
|
||||
|
||||
uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET);
|
||||
uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET);
|
||||
|
||||
if (arg & SER_INVERT_ENABLED_RX)
|
||||
{
|
||||
|
|
@ -1793,11 +1793,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
cr &= ~USART_CR2_TXINV;
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr);
|
||||
|
||||
/* Re-enable UE if appropriate */
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1814,17 +1814,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
|
||||
/* Get the original state of UE */
|
||||
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
cr1_ue = cr1 & USART_CR1_UE;
|
||||
cr1 &= ~USART_CR1_UE;
|
||||
|
||||
/* Disable UE, SWAP can only be written when UE=0 */
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1);
|
||||
|
||||
/* Enable/disable Swap mode. */
|
||||
|
||||
uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET);
|
||||
uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET);
|
||||
|
||||
if (arg == SER_SWAP_ENABLED)
|
||||
{
|
||||
|
|
@ -1835,11 +1835,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
cr &= ~USART_CR2_SWAP;
|
||||
}
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr);
|
||||
|
||||
/* Re-enable UE if appropriate */
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1996,8 +1996,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET,
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET,
|
||||
cr1 | USART_CR1_SBK);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
|
@ -2009,8 +2009,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd,
|
|||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET);
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET,
|
||||
cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET,
|
||||
cr1 & ~USART_CR1_SBK);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
|
@ -2046,7 +2046,7 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev,
|
|||
|
||||
/* Get the Rx byte */
|
||||
|
||||
rdr = stm32wl5serial_getreg(priv, STM32WL5_USART_RDR_OFFSET);
|
||||
rdr = stm32wl5serial_getreg(priv, STM32_USART_RDR_OFFSET);
|
||||
|
||||
/* Get the Rx byte plux error information. Return those in status */
|
||||
|
||||
|
|
@ -2133,7 +2133,7 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev)
|
|||
struct stm32wl5_serial_s *priv =
|
||||
(struct stm32wl5_serial_s *)dev->priv;
|
||||
|
||||
return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) &
|
||||
return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_RXNE) != 0);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -2296,7 +2296,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
|
|||
/* Configure for non-circular DMA reception into the RX FIFO */
|
||||
|
||||
stm32wl5_dmasetup(priv->rxdma,
|
||||
priv->usartbase + STM32WL5_USART_RDR_OFFSET,
|
||||
priv->usartbase + STM32_USART_RDR_OFFSET,
|
||||
(uint32_t)priv->rxfifo,
|
||||
RXDMA_BUFFER_SIZE,
|
||||
SERIAL_DMA_IFLOW_CONTROL_WORD);
|
||||
|
|
@ -2307,7 +2307,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv)
|
|||
/* Configure for circular DMA reception into the RX FIFO */
|
||||
|
||||
stm32wl5_dmasetup(priv->rxdma,
|
||||
priv->usartbase + STM32WL5_USART_RDR_OFFSET,
|
||||
priv->usartbase + STM32_USART_RDR_OFFSET,
|
||||
(uint32_t)priv->rxfifo,
|
||||
RXDMA_BUFFER_SIZE,
|
||||
SERIAL_DMA_CONTROL_WORD);
|
||||
|
|
@ -2476,7 +2476,7 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch)
|
|||
}
|
||||
#endif
|
||||
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_TDR_OFFSET, (uint32_t)ch);
|
||||
stm32wl5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -2561,7 +2561,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev)
|
|||
struct stm32wl5_serial_s *priv =
|
||||
(struct stm32wl5_serial_s *)dev->priv;
|
||||
|
||||
return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) &
|
||||
return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) &
|
||||
USART_ISR_TXE) != 0);
|
||||
}
|
||||
|
||||
|
|
@ -2603,11 +2603,11 @@ static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status,
|
|||
* will release Rx DMA.
|
||||
*/
|
||||
|
||||
priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET);
|
||||
priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET);
|
||||
|
||||
if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0)
|
||||
{
|
||||
stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET,
|
||||
stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET,
|
||||
(USART_ICR_NCF | USART_ICR_ORECF |
|
||||
USART_ICR_FECF));
|
||||
}
|
||||
|
|
@ -2743,7 +2743,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain,
|
|||
* buffers.
|
||||
*/
|
||||
|
||||
for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++)
|
||||
for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++)
|
||||
{
|
||||
struct stm32wl5_serial_s *priv = g_uart_devs[n];
|
||||
|
||||
|
|
@ -2813,7 +2813,7 @@ void arm_earlyserialinit(void)
|
|||
|
||||
/* Disable all USART interrupts */
|
||||
|
||||
for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++)
|
||||
for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++)
|
||||
{
|
||||
if (g_uart_devs[i])
|
||||
{
|
||||
|
|
@ -2882,7 +2882,7 @@ void arm_serialinit(void)
|
|||
|
||||
strlcpy(devname, "/dev/ttySx", sizeof(devname));
|
||||
|
||||
for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++)
|
||||
for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++)
|
||||
{
|
||||
/* Don't create a device for non-configured ports. */
|
||||
|
||||
|
|
|
|||
|
|
@ -316,10 +316,10 @@ static struct stm32wl5_spidev_s g_spi1dev =
|
|||
{
|
||||
.ops = &g_sp1iops,
|
||||
},
|
||||
.spibase = STM32WL5_SPI1_BASE,
|
||||
.spiclock = STM32WL5_PCLK2_FREQUENCY,
|
||||
.spibase = STM32_SPI1_BASE,
|
||||
.spiclock = STM32_PCLK2_FREQUENCY,
|
||||
#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS
|
||||
.spiirq = STM32WL5_IRQ_SPI1,
|
||||
.spiirq = STM32_IRQ_SPI1,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_SPI_DMA
|
||||
# ifdef CONFIG_STM32WL5_SPI1_DMA
|
||||
|
|
@ -386,10 +386,10 @@ static struct stm32wl5_spidev_s g_spi2s2dev =
|
|||
{
|
||||
&g_sp2iops
|
||||
},
|
||||
.spibase = STM32WL5_SPI2S2_BASE,
|
||||
.spiclock = STM32WL5_PCLK1_FREQUENCY,
|
||||
.spibase = STM32_SPI2S2_BASE,
|
||||
.spiclock = STM32_PCLK1_FREQUENCY,
|
||||
#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS
|
||||
.spiirq = STM32WL5_IRQ_SPI2S2,
|
||||
.spiirq = STM32_IRQ_SPI2S2,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_SPI_DMA
|
||||
# ifdef CONFIG_STM32WL5_SPI2S2_DMA
|
||||
|
|
@ -518,7 +518,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv)
|
|||
{
|
||||
/* Wait until the receive buffer is not empty */
|
||||
|
||||
while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0)
|
||||
while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -539,11 +539,11 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv)
|
|||
|
||||
if (priv->nbits < 9)
|
||||
{
|
||||
return (uint16_t)spi_getreg8(priv, STM32WL5_SPI_DR_OFFSET);
|
||||
return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
return spi_getreg(priv, STM32WL5_SPI_DR_OFFSET);
|
||||
return spi_getreg(priv, STM32_SPI_DR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -568,7 +568,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv,
|
|||
{
|
||||
/* Wait until the transmit buffer is empty */
|
||||
|
||||
while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0)
|
||||
while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -576,11 +576,11 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv,
|
|||
|
||||
if (priv->nbits < 9)
|
||||
{
|
||||
spi_putreg8(priv, STM32WL5_SPI_DR_OFFSET, (uint8_t)word);
|
||||
spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word);
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_putreg(priv, STM32WL5_SPI_DR_OFFSET, word);
|
||||
spi_putreg(priv, STM32_SPI_DR_OFFSET, word);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv,
|
|||
|
||||
/* Configure the RX DMA */
|
||||
|
||||
stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32WL5_SPI_DR_OFFSET,
|
||||
stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET,
|
||||
(uint32_t)rxbuffer, nwords, priv->rxccr);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv,
|
|||
|
||||
/* Setup the TX DMA */
|
||||
|
||||
stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32WL5_SPI_DR_OFFSET,
|
||||
stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET,
|
||||
(uint32_t)txbuffer, nwords, priv->txccr);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -875,12 +875,12 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv,
|
|||
uint16_t clrbits)
|
||||
{
|
||||
uint16_t cr1;
|
||||
cr1 = spi_getreg(priv, STM32WL5_SPI_CR1_OFFSET);
|
||||
cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET);
|
||||
cr1 &= ~clrbits;
|
||||
cr1 |= setbits;
|
||||
spi_putreg(priv, STM32WL5_SPI_CR1_OFFSET, cr1);
|
||||
spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1);
|
||||
|
||||
spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR1_OFFSET,
|
||||
spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR1_OFFSET,
|
||||
cr1);
|
||||
}
|
||||
|
||||
|
|
@ -904,11 +904,11 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits,
|
|||
uint16_t clrbits)
|
||||
{
|
||||
uint16_t cr2;
|
||||
cr2 = spi_getreg(priv, STM32WL5_SPI_CR2_OFFSET);
|
||||
cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET);
|
||||
cr2 &= ~clrbits;
|
||||
cr2 |= setbits;
|
||||
spi_putreg(priv, STM32WL5_SPI_CR2_OFFSET, cr2);
|
||||
spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR2_OFFSET,
|
||||
spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2);
|
||||
spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR2_OFFSET,
|
||||
cr2);
|
||||
}
|
||||
|
||||
|
|
@ -1314,7 +1314,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
|
|||
* (Reading from the SR clears the error flags)
|
||||
*/
|
||||
|
||||
regval = spi_getreg(priv, STM32WL5_SPI_SR_OFFSET);
|
||||
regval = spi_getreg(priv, STM32_SPI_SR_OFFSET);
|
||||
|
||||
spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32
|
||||
" Status: %02" PRIx32 "\n", wd, ret, regval);
|
||||
|
|
@ -1731,7 +1731,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv)
|
|||
|
||||
/* CRCPOLY configuration */
|
||||
|
||||
spi_putreg(priv, STM32WL5_SPI_CRCPR_OFFSET, 7);
|
||||
spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7);
|
||||
|
||||
#ifdef CONFIG_STM32WL5_SPI_DMA
|
||||
if (priv->rxch && priv->txch)
|
||||
|
|
|
|||
|
|
@ -60,8 +60,8 @@
|
|||
* 0x2000:8000 - Start of internal SRAM2
|
||||
*/
|
||||
|
||||
#define SRAM2_START STM32WL5_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE)
|
||||
#define SRAM2_START STM32_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
|
||||
|
||||
#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
|
||||
|
||||
|
|
|
|||
|
|
@ -306,16 +306,16 @@ static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim1_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM1_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM1_BASE,
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
struct stm32wl5_tim_priv_s stm32wl5_tim2_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM2_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM2_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -323,8 +323,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim2_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim3_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM3_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM3_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -332,8 +332,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim3_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim4_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM4_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM4_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -341,8 +341,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim4_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim5_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM5_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM5_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -350,8 +350,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim5_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim6_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM6_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM6_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -359,8 +359,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim6_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim7_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM7_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM7_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -368,8 +368,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim7_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim8_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM8_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM8_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -377,8 +377,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim8_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim15_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM15_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM15_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -386,8 +386,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim15_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim16_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM16_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM16_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -395,8 +395,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim16_priv =
|
|||
struct stm32wl5_tim_priv_s stm32wl5_tim17_priv =
|
||||
{
|
||||
.ops = &stm32wl5_tim_ops,
|
||||
.mode = STM32WL5_TIM_MODE_UNUSED,
|
||||
.base = STM32WL5_TIM17_BASE,
|
||||
.mode = STM32_TIM_MODE_UNUSED,
|
||||
.base = STM32_TIM17_BASE,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -484,9 +484,9 @@ static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev)
|
||||
{
|
||||
uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_EGR_OFFSET);
|
||||
uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_EGR_OFFSET);
|
||||
val |= GTIM_EGR_UG;
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_EGR_OFFSET, val);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -495,10 +495,10 @@ static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev)
|
|||
|
||||
static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev)
|
||||
{
|
||||
uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET);
|
||||
uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET);
|
||||
val |= GTIM_CR1_CEN;
|
||||
stm32wl5_tim_reload_counter(dev);
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -507,9 +507,9 @@ static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev)
|
|||
|
||||
static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev)
|
||||
{
|
||||
uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET);
|
||||
uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET);
|
||||
val &= ~GTIM_CR1_CEN;
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -523,7 +523,7 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev)
|
|||
|
||||
static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev)
|
||||
{
|
||||
((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_DISABLED;
|
||||
((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED;
|
||||
stm32wl5_tim_disable(dev);
|
||||
}
|
||||
|
||||
|
|
@ -541,7 +541,7 @@ static void stm32wl5_tim_gpioconfig(uint32_t cfg,
|
|||
{
|
||||
/* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
|
||||
|
||||
if (mode & STM32WL5_TIM_CH_MODE_MASK)
|
||||
if (mode & STM32_TIM_CH_MODE_MASK)
|
||||
{
|
||||
stm32wl5_configgpio(cfg);
|
||||
}
|
||||
|
|
@ -567,13 +567,13 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev,
|
|||
* disable it, simply set its clock to valid frequency or zero.
|
||||
*/
|
||||
|
||||
#if STM32WL5_NBTIM > 0
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE
|
||||
#if STM32_NBTIM > 0
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE
|
||||
#endif
|
||||
#if STM32WL5_NBTIM > 1
|
||||
|| ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE
|
||||
#if STM32_NBTIM > 1
|
||||
|| ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE
|
||||
#endif
|
||||
#if STM32WL5_NBTIM > 0
|
||||
#if STM32_NBTIM > 0
|
||||
)
|
||||
{
|
||||
return -EINVAL;
|
||||
|
|
@ -582,19 +582,19 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
/* Decode operational modes */
|
||||
|
||||
switch (mode & STM32WL5_TIM_MODE_MASK)
|
||||
switch (mode & STM32_TIM_MODE_MASK)
|
||||
{
|
||||
case STM32WL5_TIM_MODE_DISABLED:
|
||||
case STM32_TIM_MODE_DISABLED:
|
||||
val = 0;
|
||||
break;
|
||||
|
||||
case STM32WL5_TIM_MODE_DOWN:
|
||||
case STM32_TIM_MODE_DOWN:
|
||||
val |= GTIM_CR1_DIR;
|
||||
|
||||
case STM32WL5_TIM_MODE_UP:
|
||||
case STM32_TIM_MODE_UP:
|
||||
break;
|
||||
|
||||
case STM32WL5_TIM_MODE_UPDOWN:
|
||||
case STM32_TIM_MODE_UPDOWN:
|
||||
val |= GTIM_CR1_CENTER1;
|
||||
|
||||
/* Our default: Interrupts are generated on compare, when counting
|
||||
|
|
@ -603,7 +603,7 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
break;
|
||||
|
||||
case STM32WL5_TIM_MODE_PULSE:
|
||||
case STM32_TIM_MODE_PULSE:
|
||||
val |= GTIM_CR1_OPM;
|
||||
break;
|
||||
|
||||
|
|
@ -612,15 +612,15 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev,
|
|||
}
|
||||
|
||||
stm32wl5_tim_reload_counter(dev);
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val);
|
||||
|
||||
#if STM32WL5_NATIM > 0
|
||||
#if STM32_NATIM > 0
|
||||
/* Advanced registers require Main Output Enable */
|
||||
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM1_BASE ||
|
||||
((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM8_BASE)
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
|
||||
((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
|
||||
{
|
||||
stm32wl5_modifyreg16(dev, STM32WL5_ATIM_BDTR_OFFSET,
|
||||
stm32wl5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET,
|
||||
0, ATIM_BDTR_MOE);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -657,66 +657,66 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev,
|
|||
switch (((struct stm32wl5_tim_priv_s *)dev)->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_TIM1
|
||||
case STM32WL5_TIM1_BASE:
|
||||
case STM32_TIM1_BASE:
|
||||
freqin = BOARD_TIM1_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case STM32WL5_TIM2_BASE:
|
||||
case STM32_TIM2_BASE:
|
||||
freqin = BOARD_TIM2_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM3
|
||||
case STM32WL5_TIM3_BASE:
|
||||
case STM32_TIM3_BASE:
|
||||
freqin = BOARD_TIM3_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM4
|
||||
case STM32WL5_TIM4_BASE:
|
||||
case STM32_TIM4_BASE:
|
||||
freqin = BOARD_TIM4_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case STM32WL5_TIM5_BASE:
|
||||
case STM32_TIM5_BASE:
|
||||
freqin = BOARD_TIM5_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM6
|
||||
case STM32WL5_TIM6_BASE:
|
||||
case STM32_TIM6_BASE:
|
||||
freqin = BOARD_TIM6_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM7
|
||||
case STM32WL5_TIM7_BASE:
|
||||
case STM32_TIM7_BASE:
|
||||
freqin = BOARD_TIM7_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM8
|
||||
case STM32WL5_TIM8_BASE:
|
||||
case STM32_TIM8_BASE:
|
||||
freqin = BOARD_TIM8_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM15
|
||||
case STM32WL5_TIM15_BASE:
|
||||
case STM32_TIM15_BASE:
|
||||
freqin = BOARD_TIM15_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM16
|
||||
case STM32WL5_TIM16_BASE:
|
||||
case STM32_TIM16_BASE:
|
||||
freqin = BOARD_TIM16_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM17
|
||||
case STM32WL5_TIM17_BASE:
|
||||
case STM32_TIM17_BASE:
|
||||
freqin = BOARD_TIM17_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -747,7 +747,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev,
|
|||
prescaler = 0xffff;
|
||||
}
|
||||
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_PSC_OFFSET, prescaler);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler);
|
||||
stm32wl5_tim_enable(dev);
|
||||
|
||||
return prescaler;
|
||||
|
|
@ -772,64 +772,64 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev)
|
|||
switch (((struct stm32wl5_tim_priv_s *)dev)->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_TIM1
|
||||
case STM32WL5_TIM1_BASE:
|
||||
case STM32_TIM1_BASE:
|
||||
freqin = BOARD_TIM1_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case STM32WL5_TIM2_BASE:
|
||||
case STM32_TIM2_BASE:
|
||||
freqin = BOARD_TIM2_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM3
|
||||
case STM32WL5_TIM3_BASE:
|
||||
case STM32_TIM3_BASE:
|
||||
freqin = BOARD_TIM3_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM4
|
||||
case STM32WL5_TIM4_BASE:
|
||||
case STM32_TIM4_BASE:
|
||||
freqin = BOARD_TIM4_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case STM32WL5_TIM5_BASE:
|
||||
case STM32_TIM5_BASE:
|
||||
freqin = BOARD_TIM5_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM6
|
||||
case STM32WL5_TIM6_BASE:
|
||||
case STM32_TIM6_BASE:
|
||||
freqin = BOARD_TIM6_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM7
|
||||
case STM32WL5_TIM7_BASE:
|
||||
case STM32_TIM7_BASE:
|
||||
freqin = BOARD_TIM7_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM8
|
||||
case STM32WL5_TIM8_BASE:
|
||||
case STM32_TIM8_BASE:
|
||||
freqin = BOARD_TIM8_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM15
|
||||
case STM32WL5_TIM15_BASE:
|
||||
case STM32_TIM15_BASE:
|
||||
freqin = BOARD_TIM15_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM16
|
||||
case STM32WL5_TIM16_BASE:
|
||||
case STM32_TIM16_BASE:
|
||||
freqin = BOARD_TIM16_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM17
|
||||
case STM32WL5_TIM17_BASE:
|
||||
case STM32_TIM17_BASE:
|
||||
freqin = BOARD_TIM17_FREQUENCY;
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -839,7 +839,7 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev)
|
|||
|
||||
/* From chip datasheet, at page 1179. */
|
||||
|
||||
clock = freqin / (stm32wl5_getreg16(dev, STM32WL5_GTIM_PSC_OFFSET) + 1);
|
||||
clock = freqin / (stm32wl5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1);
|
||||
return clock;
|
||||
}
|
||||
|
||||
|
|
@ -851,7 +851,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev,
|
|||
uint32_t period)
|
||||
{
|
||||
DEBUGASSERT(dev != NULL);
|
||||
stm32wl5_putreg32(dev, STM32WL5_GTIM_ARR_OFFSET, period);
|
||||
stm32wl5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -861,7 +861,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev,
|
|||
static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev)
|
||||
{
|
||||
DEBUGASSERT(dev != NULL);
|
||||
return stm32wl5_getreg32 (dev, STM32WL5_GTIM_ARR_OFFSET);
|
||||
return stm32wl5_getreg32 (dev, STM32_GTIM_ARR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -871,7 +871,7 @@ static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev)
|
|||
static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev)
|
||||
{
|
||||
DEBUGASSERT(dev != NULL);
|
||||
uint32_t counter = stm32wl5_getreg32(dev, STM32WL5_GTIM_CNT_OFFSET);
|
||||
uint32_t counter = stm32wl5_getreg32(dev, STM32_GTIM_CNT_OFFSET);
|
||||
|
||||
/* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT.
|
||||
* reset it it result when not TIM2 or TIM5.
|
||||
|
|
@ -881,10 +881,10 @@ static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev)
|
|||
switch (((struct stm32wl5_tim_priv_s *)dev)->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case STM32WL5_TIM2_BASE:
|
||||
case STM32_TIM2_BASE:
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case STM32WL5_TIM5_BASE:
|
||||
case STM32_TIM5_BASE:
|
||||
#endif
|
||||
return counter;
|
||||
|
||||
|
|
@ -908,7 +908,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
uint16_t ccmr_val = 0;
|
||||
uint16_t ccmr_mask = 0xff;
|
||||
uint16_t ccer_val;
|
||||
uint8_t ccmr_offset = STM32WL5_GTIM_CCMR1_OFFSET;
|
||||
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
/* Assume that channel is disabled and polarity is active high */
|
||||
|
||||
ccer_val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CCER_OFFSET);
|
||||
ccer_val = stm32wl5_getreg16(dev, STM32_GTIM_CCER_OFFSET);
|
||||
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
|
||||
GTIM_CCER_CCXBASE(channel));
|
||||
|
||||
|
|
@ -929,13 +929,13 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
* disable it, simply set its clock to valid frequency or zero.
|
||||
*/
|
||||
|
||||
#if STM32WL5_NBTIM > 0
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE
|
||||
#if STM32_NBTIM > 0
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE
|
||||
#endif
|
||||
#if STM32WL5_NBTIM > 1
|
||||
|| ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE
|
||||
#if STM32_NBTIM > 1
|
||||
|| ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE
|
||||
#endif
|
||||
#if STM32WL5_NBTIM > 0
|
||||
#if STM32_NBTIM > 0
|
||||
)
|
||||
{
|
||||
return -EINVAL;
|
||||
|
|
@ -944,12 +944,12 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
/* Decode configuration */
|
||||
|
||||
switch (mode & STM32WL5_TIM_CH_MODE_MASK)
|
||||
switch (mode & STM32_TIM_CH_MODE_MASK)
|
||||
{
|
||||
case STM32WL5_TIM_CH_DISABLED:
|
||||
case STM32_TIM_CH_DISABLED:
|
||||
break;
|
||||
|
||||
case STM32WL5_TIM_CH_OUTPWM:
|
||||
case STM32_TIM_CH_OUTPWM:
|
||||
ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) +
|
||||
GTIM_CCMR1_OC1PE;
|
||||
ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
|
||||
|
|
@ -961,7 +961,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
/* Set polarity */
|
||||
|
||||
if (mode & STM32WL5_TIM_CH_POLARITY_NEG)
|
||||
if (mode & STM32_TIM_CH_POLARITY_NEG)
|
||||
{
|
||||
ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
|
||||
}
|
||||
|
|
@ -976,21 +976,21 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
if (channel > 1)
|
||||
{
|
||||
ccmr_offset = STM32WL5_GTIM_CCMR2_OFFSET;
|
||||
ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
|
||||
}
|
||||
|
||||
ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset);
|
||||
ccmr_orig &= ~ccmr_mask;
|
||||
ccmr_orig |= ccmr_val;
|
||||
stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig);
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_CCER_OFFSET, ccer_val);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
|
||||
|
||||
/* set GPIO */
|
||||
|
||||
switch (((struct stm32wl5_tim_priv_s *)dev)->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_TIM1
|
||||
case STM32WL5_TIM1_BASE:
|
||||
case STM32_TIM1_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM1_CH1OUT)
|
||||
|
|
@ -1023,7 +1023,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case STM32WL5_TIM2_BASE:
|
||||
case STM32_TIM2_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM2_CH1OUT)
|
||||
|
|
@ -1056,7 +1056,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM3
|
||||
case STM32WL5_TIM3_BASE:
|
||||
case STM32_TIM3_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM3_CH1OUT)
|
||||
|
|
@ -1089,7 +1089,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM4
|
||||
case STM32WL5_TIM4_BASE:
|
||||
case STM32_TIM4_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM4_CH1OUT)
|
||||
|
|
@ -1121,7 +1121,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case STM32WL5_TIM5_BASE:
|
||||
case STM32_TIM5_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM5_CH1OUT)
|
||||
|
|
@ -1154,7 +1154,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM8
|
||||
case STM32WL5_TIM8_BASE:
|
||||
case STM32_TIM8_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM8_CH1OUT)
|
||||
|
|
@ -1187,7 +1187,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM15
|
||||
case STM32WL5_TIM15_BASE:
|
||||
case STM32_TIM15_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM15_CH1OUT)
|
||||
|
|
@ -1220,7 +1220,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM16
|
||||
case STM32WL5_TIM16_BASE:
|
||||
case STM32_TIM16_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM16_CH1OUT)
|
||||
|
|
@ -1253,7 +1253,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev,
|
|||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM17
|
||||
case STM32WL5_TIM17_BASE:
|
||||
case STM32_TIM17_BASE:
|
||||
switch (channel)
|
||||
{
|
||||
#if defined(GPIO_TIM17_CH1OUT)
|
||||
|
|
@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev,
|
|||
switch (channel)
|
||||
{
|
||||
case 1:
|
||||
stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR1_OFFSET, compare);
|
||||
stm32wl5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR2_OFFSET, compare);
|
||||
stm32wl5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR3_OFFSET, compare);
|
||||
stm32wl5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR4_OFFSET, compare);
|
||||
stm32wl5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -1339,16 +1339,16 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev,
|
|||
switch (channel)
|
||||
{
|
||||
case 1:
|
||||
return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR1_OFFSET);
|
||||
return stm32wl5_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
|
||||
|
||||
case 2:
|
||||
return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR2_OFFSET);
|
||||
return stm32wl5_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
|
||||
|
||||
case 3:
|
||||
return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR3_OFFSET);
|
||||
return stm32wl5_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
|
||||
|
||||
case 4:
|
||||
return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR4_OFFSET);
|
||||
return stm32wl5_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
|
|
@ -1369,66 +1369,66 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev,
|
|||
switch (((struct stm32wl5_tim_priv_s *)dev)->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_TIM1
|
||||
case STM32WL5_TIM1_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM1UP;
|
||||
case STM32_TIM1_BASE:
|
||||
vectorno = STM32_IRQ_TIM1UP;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case STM32WL5_TIM2_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM2;
|
||||
case STM32_TIM2_BASE:
|
||||
vectorno = STM32_IRQ_TIM2;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM3
|
||||
case STM32WL5_TIM3_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM3;
|
||||
case STM32_TIM3_BASE:
|
||||
vectorno = STM32_IRQ_TIM3;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM4
|
||||
case STM32WL5_TIM4_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM4;
|
||||
case STM32_TIM4_BASE:
|
||||
vectorno = STM32_IRQ_TIM4;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case STM32WL5_TIM5_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM5;
|
||||
case STM32_TIM5_BASE:
|
||||
vectorno = STM32_IRQ_TIM5;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM6
|
||||
case STM32WL5_TIM6_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM6;
|
||||
case STM32_TIM6_BASE:
|
||||
vectorno = STM32_IRQ_TIM6;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM7
|
||||
case STM32WL5_TIM7_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM7;
|
||||
case STM32_TIM7_BASE:
|
||||
vectorno = STM32_IRQ_TIM7;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM8
|
||||
case STM32WL5_TIM8_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM8UP;
|
||||
case STM32_TIM8_BASE:
|
||||
vectorno = STM32_IRQ_TIM8UP;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM15
|
||||
case STM32WL5_TIM15_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM15;
|
||||
case STM32_TIM15_BASE:
|
||||
vectorno = STM32_IRQ_TIM15;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM16
|
||||
case STM32WL5_TIM16_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM16;
|
||||
case STM32_TIM16_BASE:
|
||||
vectorno = STM32_IRQ_TIM16;
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM17
|
||||
case STM32WL5_TIM17_BASE:
|
||||
vectorno = STM32WL5_IRQ_TIM17;
|
||||
case STM32_TIM17_BASE:
|
||||
vectorno = STM32_IRQ_TIM17;
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -1461,7 +1461,7 @@ static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev,
|
|||
int source)
|
||||
{
|
||||
DEBUGASSERT(dev != NULL);
|
||||
stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE);
|
||||
stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1472,7 +1472,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev,
|
|||
int source)
|
||||
{
|
||||
DEBUGASSERT(dev != NULL);
|
||||
stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0);
|
||||
stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1481,7 +1481,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev,
|
|||
|
||||
static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source)
|
||||
{
|
||||
stm32wl5_putreg16(dev, STM32WL5_GTIM_SR_OFFSET, ~GTIM_SR_UIF);
|
||||
stm32wl5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
|
@ -1491,7 +1491,7 @@ static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source)
|
|||
static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev,
|
||||
int source)
|
||||
{
|
||||
uint16_t regval = stm32wl5_getreg16(dev, STM32WL5_GTIM_SR_OFFSET);
|
||||
uint16_t regval = stm32wl5_getreg16(dev, STM32_GTIM_SR_OFFSET);
|
||||
return (regval & GTIM_SR_UIF) ? 1 : 0;
|
||||
}
|
||||
|
||||
|
|
@ -1514,76 +1514,76 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer)
|
|||
#ifdef CONFIG_STM32WL5_TIM1
|
||||
case 1:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case 2:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM3
|
||||
case 3:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM4
|
||||
case 4:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case 5:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM6
|
||||
case 6:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM7
|
||||
case 7:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN);
|
||||
modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM8
|
||||
case 8:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM15
|
||||
case 15:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM16
|
||||
case 16:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM17
|
||||
case 17:
|
||||
dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv;
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
|
||||
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -1593,7 +1593,7 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer)
|
|||
|
||||
/* Is device already allocated */
|
||||
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32WL5_TIM_MODE_UNUSED)
|
||||
if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -1619,67 +1619,67 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev)
|
|||
switch (((struct stm32wl5_tim_priv_s *)dev)->base)
|
||||
{
|
||||
#ifdef CONFIG_STM32WL5_TIM1
|
||||
case STM32WL5_TIM1_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
|
||||
case STM32_TIM1_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM2
|
||||
case STM32WL5_TIM2_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0);
|
||||
case STM32_TIM2_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM3
|
||||
case STM32WL5_TIM3_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0);
|
||||
case STM32_TIM3_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM4
|
||||
case STM32WL5_TIM4_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0);
|
||||
case STM32_TIM4_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM5
|
||||
case STM32WL5_TIM5_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0);
|
||||
case STM32_TIM5_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM6
|
||||
case STM32WL5_TIM6_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0);
|
||||
case STM32_TIM6_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM7
|
||||
case STM32WL5_TIM7_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0);
|
||||
case STM32_TIM7_BASE:
|
||||
modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM8
|
||||
case STM32WL5_TIM8_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
|
||||
case STM32_TIM8_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM15
|
||||
case STM32WL5_TIM15_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
|
||||
case STM32_TIM15_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32WL5_TIM16
|
||||
case STM32WL5_TIM16_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
|
||||
case STM32_TIM16_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32WL5_TIM17
|
||||
case STM32WL5_TIM17_BASE:
|
||||
modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
|
||||
case STM32_TIM17_BASE:
|
||||
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
|
@ -1689,7 +1689,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev)
|
|||
|
||||
/* Mark it as free */
|
||||
|
||||
((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_UNUSED;
|
||||
((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED;
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -38,20 +38,20 @@
|
|||
|
||||
/* Helpers ******************************************************************/
|
||||
|
||||
#define STM32WL5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define STM32WL5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
#define STM32WL5_TIM_GETCLOCK(d) ((d)->ops->getclock(d))
|
||||
#define STM32WL5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
|
||||
#define STM32WL5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d))
|
||||
#define STM32WL5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
|
||||
#define STM32WL5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
|
||||
#define STM32WL5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
|
||||
#define STM32WL5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
|
||||
#define STM32WL5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
|
||||
#define STM32WL5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
|
||||
#define STM32WL5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
|
||||
#define STM32WL5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
#define STM32WL5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
|
||||
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d))
|
||||
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
|
||||
#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d))
|
||||
#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
|
||||
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
|
||||
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
|
||||
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
|
||||
#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
|
||||
#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
|
||||
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
|
||||
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
|
||||
#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d))
|
||||
#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d))
|
||||
|
||||
|
|
@ -81,34 +81,34 @@ struct stm32wl5_tim_dev_s
|
|||
|
||||
enum stm32wl5_tim_mode_e
|
||||
{
|
||||
STM32WL5_TIM_MODE_UNUSED = -1,
|
||||
STM32_TIM_MODE_UNUSED = -1,
|
||||
|
||||
/* One of the following */
|
||||
|
||||
STM32WL5_TIM_MODE_MASK = 0x0310,
|
||||
STM32WL5_TIM_MODE_DISABLED = 0x0000,
|
||||
STM32WL5_TIM_MODE_UP = 0x0100,
|
||||
STM32WL5_TIM_MODE_DOWN = 0x0110,
|
||||
STM32WL5_TIM_MODE_UPDOWN = 0x0200,
|
||||
STM32WL5_TIM_MODE_PULSE = 0x0300,
|
||||
STM32_TIM_MODE_MASK = 0x0310,
|
||||
STM32_TIM_MODE_DISABLED = 0x0000,
|
||||
STM32_TIM_MODE_UP = 0x0100,
|
||||
STM32_TIM_MODE_DOWN = 0x0110,
|
||||
STM32_TIM_MODE_UPDOWN = 0x0200,
|
||||
STM32_TIM_MODE_PULSE = 0x0300,
|
||||
|
||||
/* One of the following */
|
||||
|
||||
STM32WL5_TIM_MODE_CK_INT = 0x0000,
|
||||
STM32_TIM_MODE_CK_INT = 0x0000,
|
||||
#if 0
|
||||
STM32WL5_TIM_MODE_CK_INT_TRIG = 0x0400,
|
||||
STM32WL5_TIM_MODE_CK_EXT = 0x0800,
|
||||
STM32WL5_TIM_MODE_CK_EXT_TRIG = 0x0c00,
|
||||
STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
|
||||
STM32_TIM_MODE_CK_EXT = 0x0800,
|
||||
STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00,
|
||||
#endif
|
||||
|
||||
/* Clock sources, OR'ed with CK_EXT */
|
||||
|
||||
#if 0
|
||||
STM32WL5_TIM_MODE_CK_CHINVALID = 0x0000,
|
||||
STM32WL5_TIM_MODE_CK_CH1 = 0x0001,
|
||||
STM32WL5_TIM_MODE_CK_CH2 = 0x0002,
|
||||
STM32WL5_TIM_MODE_CK_CH3 = 0x0003,
|
||||
STM32WL5_TIM_MODE_CK_CH4 = 0x0004
|
||||
STM32_TIM_MODE_CK_CHINVALID = 0x0000,
|
||||
STM32_TIM_MODE_CK_CH1 = 0x0001,
|
||||
STM32_TIM_MODE_CK_CH2 = 0x0002,
|
||||
STM32_TIM_MODE_CK_CH3 = 0x0003,
|
||||
STM32_TIM_MODE_CK_CH4 = 0x0004
|
||||
#endif
|
||||
|
||||
/* Todo: external trigger block */
|
||||
|
|
@ -118,22 +118,22 @@ enum stm32wl5_tim_mode_e
|
|||
|
||||
enum stm32wl5_tim_channel_e
|
||||
{
|
||||
STM32WL5_TIM_CH_DISABLED = 0x00,
|
||||
STM32_TIM_CH_DISABLED = 0x00,
|
||||
|
||||
/* Common configuration */
|
||||
|
||||
STM32WL5_TIM_CH_POLARITY_POS = 0x00,
|
||||
STM32WL5_TIM_CH_POLARITY_NEG = 0x01,
|
||||
STM32_TIM_CH_POLARITY_POS = 0x00,
|
||||
STM32_TIM_CH_POLARITY_NEG = 0x01,
|
||||
|
||||
/* MODES: */
|
||||
|
||||
STM32WL5_TIM_CH_MODE_MASK = 0x06,
|
||||
STM32_TIM_CH_MODE_MASK = 0x06,
|
||||
|
||||
/* Output Compare Modes */
|
||||
|
||||
STM32WL5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */
|
||||
STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */
|
||||
#if 0
|
||||
STM32WL5_TIM_CH_OUTCOMPARE = 0x06,
|
||||
STM32_TIM_CH_OUTCOMPARE = 0x06,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -52,17 +52,17 @@
|
|||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32WL5_TIM1_RES 16
|
||||
#define STM32WL5_TIM2_RES 32
|
||||
#define STM32WL5_TIM3_RES 16
|
||||
#define STM32WL5_TIM4_RES 16
|
||||
#define STM32WL5_TIM5_RES 32
|
||||
#define STM32WL5_TIM6_RES 16
|
||||
#define STM32WL5_TIM7_RES 16
|
||||
#define STM32WL5_TIM8_RES 16
|
||||
#define STM32WL5_TIM15_RES 16
|
||||
#define STM32WL5_TIM16_RES 16
|
||||
#define STM32WL5_TIM17_RES 16
|
||||
#define STM32_TIM1_RES 16
|
||||
#define STM32_TIM2_RES 32
|
||||
#define STM32_TIM3_RES 16
|
||||
#define STM32_TIM4_RES 16
|
||||
#define STM32_TIM5_RES 32
|
||||
#define STM32_TIM6_RES 16
|
||||
#define STM32_TIM7_RES 16
|
||||
#define STM32_TIM8_RES 16
|
||||
#define STM32_TIM15_RES 16
|
||||
#define STM32_TIM16_RES 16
|
||||
#define STM32_TIM17_RES 16
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
|
|
@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops =
|
|||
static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM1_RES,
|
||||
.resolution = STM32_TIM1_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -130,7 +130,7 @@ static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM2_RES,
|
||||
.resolution = STM32_TIM2_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -138,7 +138,7 @@ static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM3_RES,
|
||||
.resolution = STM32_TIM3_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -146,7 +146,7 @@ static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM4_RES,
|
||||
.resolution = STM32_TIM4_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -154,7 +154,7 @@ static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM5_RES,
|
||||
.resolution = STM32_TIM5_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -162,7 +162,7 @@ static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM6_RES,
|
||||
.resolution = STM32_TIM6_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -170,7 +170,7 @@ static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM7_RES,
|
||||
.resolution = STM32_TIM7_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -178,7 +178,7 @@ static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM8_RES,
|
||||
.resolution = STM32_TIM8_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -186,7 +186,7 @@ static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM15_RES,
|
||||
.resolution = STM32_TIM15_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -194,7 +194,7 @@ static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM16_RES,
|
||||
.resolution = STM32_TIM16_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -202,7 +202,7 @@ static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf =
|
|||
static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf =
|
||||
{
|
||||
.ops = &g_timer_ops,
|
||||
.resolution = STM32WL5_TIM17_RES,
|
||||
.resolution = STM32_TIM17_RES,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -228,13 +228,13 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg)
|
|||
(struct stm32wl5_lowerhalf_s *)arg;
|
||||
uint32_t next_interval_us = 0;
|
||||
|
||||
STM32WL5_TIM_ACKINT(lower->tim, 0);
|
||||
STM32_TIM_ACKINT(lower->tim, 0);
|
||||
|
||||
if (lower->callback(&next_interval_us, lower->arg))
|
||||
{
|
||||
if (next_interval_us > 0)
|
||||
{
|
||||
STM32WL5_TIM_SETPERIOD(lower->tim, next_interval_us);
|
||||
STM32_TIM_SETPERIOD(lower->tim, next_interval_us);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -267,12 +267,12 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower)
|
|||
|
||||
if (!priv->started)
|
||||
{
|
||||
STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_UP);
|
||||
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP);
|
||||
|
||||
if (priv->callback != NULL)
|
||||
{
|
||||
STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0);
|
||||
STM32WL5_TIM_ENABLEINT(priv->tim, 0);
|
||||
STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0);
|
||||
STM32_TIM_ENABLEINT(priv->tim, 0);
|
||||
}
|
||||
|
||||
priv->started = true;
|
||||
|
|
@ -306,9 +306,9 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower)
|
|||
|
||||
if (priv->started)
|
||||
{
|
||||
STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_DISABLED);
|
||||
STM32WL5_TIM_DISABLEINT(priv->tim, 0);
|
||||
STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0);
|
||||
STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED);
|
||||
STM32_TIM_DISABLEINT(priv->tim, 0);
|
||||
STM32_TIM_SETISR(priv->tim, NULL, NULL, 0);
|
||||
priv->started = false;
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -363,8 +363,8 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower,
|
|||
/* Get timeout */
|
||||
|
||||
maxtimeout = (1 << priv->resolution) - 1;
|
||||
clock = STM32WL5_TIM_GETCLOCK(priv->tim);
|
||||
period = STM32WL5_TIM_GETPERIOD(priv->tim);
|
||||
clock = STM32_TIM_GETCLOCK(priv->tim);
|
||||
period = STM32_TIM_GETPERIOD(priv->tim);
|
||||
|
||||
if (clock == 1000000)
|
||||
{
|
||||
|
|
@ -380,7 +380,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower,
|
|||
/* Get the time remaining until the timer expires (in microseconds) */
|
||||
|
||||
clock_factor = (clock == 1000000)? 1: (clock / 1000000);
|
||||
status->timeleft = (timeout - STM32WL5_TIM_GETCOUNTER(priv->tim)) *
|
||||
status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) *
|
||||
clock_factor;
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -417,13 +417,13 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower,
|
|||
if (timeout > maxtimeout)
|
||||
{
|
||||
uint64_t freq = (maxtimeout * 1000000) / timeout;
|
||||
STM32WL5_TIM_SETCLOCK(priv->tim, freq);
|
||||
STM32WL5_TIM_SETPERIOD(priv->tim, maxtimeout);
|
||||
STM32_TIM_SETCLOCK(priv->tim, freq);
|
||||
STM32_TIM_SETPERIOD(priv->tim, maxtimeout);
|
||||
}
|
||||
else
|
||||
{
|
||||
STM32WL5_TIM_SETCLOCK(priv->tim, 1000000);
|
||||
STM32WL5_TIM_SETPERIOD(priv->tim, timeout);
|
||||
STM32_TIM_SETCLOCK(priv->tim, 1000000);
|
||||
STM32_TIM_SETPERIOD(priv->tim, timeout);
|
||||
}
|
||||
|
||||
return OK;
|
||||
|
|
@ -463,13 +463,13 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower,
|
|||
|
||||
if (callback != NULL && priv->started)
|
||||
{
|
||||
STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0);
|
||||
STM32WL5_TIM_ENABLEINT(priv->tim, 0);
|
||||
STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0);
|
||||
STM32_TIM_ENABLEINT(priv->tim, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
STM32WL5_TIM_DISABLEINT(priv->tim, 0);
|
||||
STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0);
|
||||
STM32_TIM_DISABLEINT(priv->tim, 0);
|
||||
STM32_TIM_SETISR(priv->tim, NULL, NULL, 0);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
|
|
|||
|
|
@ -62,9 +62,9 @@
|
|||
#undef CONFIG_STM32WL5_SYSTICK_HCLKd8
|
||||
|
||||
#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8
|
||||
# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
|
||||
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
|
||||
#else
|
||||
# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / CLK_TCK) - 1)
|
||||
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
|
||||
#endif
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
|
|
@ -138,7 +138,7 @@ void up_timer_initialize(void)
|
|||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(STM32WL5_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL);
|
||||
(void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL);
|
||||
|
||||
/* Enable SysTick interrupts */
|
||||
|
||||
|
|
@ -147,5 +147,5 @@ void up_timer_initialize(void)
|
|||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(STM32WL5_IRQ_SYSTICK);
|
||||
up_enable_irq(STM32_IRQ_SYSTICK);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
#include "hardware/stm32wl5_memorymap.h"
|
||||
#include "stm32wl5_uid.h"
|
||||
|
||||
#ifdef STM32WL5_SYSMEM_UID
|
||||
#ifdef STM32_SYSMEM_UID
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
|
|
@ -56,8 +56,8 @@ void stm32wl5_get_uniqueid(uint8_t uniqueid[12])
|
|||
|
||||
for (i = 0; i < 12; i++)
|
||||
{
|
||||
uniqueid[i] = *((uint8_t *)(STM32WL5_SYSMEM_UID)+i);
|
||||
uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* STM32WL5_SYSMEM_UID */
|
||||
#endif /* STM32_SYSMEM_UID */
|
||||
|
|
|
|||
|
|
@ -36,72 +36,72 @@
|
|||
|
||||
/* nucleo-wl55jc has installed 32Mhz HSE oscillator */
|
||||
|
||||
#define STM32WL5_XTAL_FREQ 32000000ul
|
||||
#define STM32_XTAL_FREQ 32000000ul
|
||||
|
||||
/* Use the HSE */
|
||||
|
||||
#define STM32WL5_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
|
||||
/* HSE source is a TCXO crystal which needs to be first powered on */
|
||||
|
||||
#define STM32WL5_BOARD_USETCXO
|
||||
#define STM32_BOARD_USETCXO
|
||||
|
||||
/* Prescaler common to all PLL inputs */
|
||||
|
||||
#define STM32WL5_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */
|
||||
|
||||
/* 'main' PLL config; we use this to generate our system clock */
|
||||
|
||||
/* disable unused pll clocks */
|
||||
|
||||
#define STM32WL5_PLLCFG_PLLP 0
|
||||
#undef STM32WL5_PLLCFG_PLLP_ENABLED
|
||||
#define STM32WL5_PLLCFG_PLLQ 0
|
||||
#undef STM32WL5_PLLCFG_PLLQ_ENABLED
|
||||
#define STM32_PLLCFG_PLLP 0
|
||||
#undef STM32_PLLCFG_PLLP_ENABLED
|
||||
#define STM32_PLLCFG_PLLQ 0
|
||||
#undef STM32_PLLCFG_PLLQ_ENABLED
|
||||
|
||||
/* further multiplicate source for system clock */
|
||||
|
||||
#define STM32WL5_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */
|
||||
#define STM32WL5_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */
|
||||
#define STM32WL5_PLLCFG_PLLR_ENABLED
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */
|
||||
#define STM32_PLLCFG_PLLR_ENABLED
|
||||
|
||||
/* Resulting system clock is 48MHz */
|
||||
#define STM32WL5_SYSCLK_FREQUENCY 48000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 48000000ul
|
||||
|
||||
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
|
||||
|
||||
#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32WL5_HCLK_FREQUENCY STM32WL5_SYSCLK_FREQUENCY
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
|
||||
/* Configure the HCLK3 divisor (for flash and sram2) */
|
||||
#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */
|
||||
#define STM32WL5_HCLK3_FREQUENCY STM32WL5_SYSCLK_FREQUENCY
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */
|
||||
#define STM32_HCLK3_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
|
||||
/* Configure the APB1 prescaler */
|
||||
|
||||
#define STM32WL5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
||||
#define STM32WL5_PCLK1_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
|
||||
|
||||
/* The timer clock frequencies are automatically defined by hardware.
|
||||
* If the APB prescaler equals 1, the timer clock frequencies are set to the
|
||||
* same frequency as that of the APB domain. Otherwise they are set to twice.
|
||||
*/
|
||||
|
||||
#define STM32WL5_APB1_TIM2_CLKIN (STM32WL5_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* Configure the APB2 prescaler */
|
||||
|
||||
#define STM32WL5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
||||
#define STM32WL5_PCLK2_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
|
||||
|
||||
/* The timer clock frequencies are automatically defined by hardware.
|
||||
* If the APB prescaler equals 1, the timer clock frequencies are set to the
|
||||
* same frequency as that of the APB domain. Otherwise they are set to twice.
|
||||
*/
|
||||
|
||||
#define STM32WL5_APB2_TIM1_CLKIN STM32WL5_PCLK2_FREQUENCY
|
||||
#define STM32WL5_APB2_TIM16_CLKIN STM32WL5_PCLK2_FREQUENCY
|
||||
#define STM32WL5_APB2_TIM17_CLKIN STM32WL5_PCLK2_FREQUENCY
|
||||
#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY
|
||||
#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY
|
||||
#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY
|
||||
|
||||
/* The timer clock frequencies are automatically defined by hardware. If the
|
||||
* APB prescaler equals 1, the timer clock frequencies are set to the same
|
||||
|
|
@ -109,13 +109,13 @@
|
|||
* Note: TIM1,15,16 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
#define BOARD_TIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_TIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_TIM16_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_TIM17_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM3_FREQUENCY STM32WL5_HCLK_FREQUENCY
|
||||
#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@
|
|||
# warning "There is unused space on flash"
|
||||
#endif
|
||||
|
||||
#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE
|
||||
#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE
|
||||
|
||||
/****************************************************************************
|
||||
* Private Definitions
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue