Aksal/nuttx
3
1
Fork 1
mirror of https://github.com/apache/nuttx.git synced 2026-08-01 20:28:58 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

arm64/common: enable EL1 GICv3 sysreg access from EL2

Browse source 
AM62x enters NuttX through EL2 before dropping to EL1. Enable the
GICv3 system register interface for lower exception levels during the
EL2 handoff so EL1 can use the CPU interface without depending on
firmware state.

Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
This commit is contained in:
Piyush Patle 2026-05-20 08:01:01 +05:30 • committed by Xiang Xiao
parent 331caeb475
commit fd2fe246cc
2 changed files with 13 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
arch/arm64/src/common/arm64_arch.h
View file

@ -214,7 +214,8 @@
#define ICC_SRE_ELX_SRE_BIT BIT(0)
#define ICC_SRE_ELX_DFB_BIT BIT(1)
#define ICC_SRE_ELX_DIB_BIT BIT(2)
#define ICC_SRE_EL3_EN_BIT BIT(3)
#define ICC_SRE_ELX_EN_BIT BIT(3)
#define ICC_SRE_EL3_EN_BIT ICC_SRE_ELX_EN_BIT
#define ICC_CTLR_EOIMODE_BIT BIT(1)
/* ICC SGI macros */

11
arch/arm64/src/common/arm64_boot.c
View file

@ -152,6 +152,17 @@ void arm64_boot_el2_init(void)
write_sysreg(reg, hcr_el2);
#if CONFIG_ARM64_GIC_VERSION > 2
/* Enable EL1 access to the GICv3 system register interface. */
reg = read_sysreg(ICC_SRE_EL2);
reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */
ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */
ICC_SRE_ELX_SRE_BIT | /* System register interface is used */
ICC_SRE_ELX_EN_BIT); /* Enable lower EL access */
write_sysreg(reg, ICC_SRE_EL2);
#endif
reg = 0U; /* RES0 */
reg |= CPTR_EL2_RES1; /* RES1 */
reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */