Commit graph

141 commits

Author SHA1 Message Date
Alan Carvalho de Assis
c027e7c3e4 tools: fix stale archive members surviving a Kconfig-driven CSRCS change
During the Toybox port to NuttX, Claude noticed that changes in the
menuconfig weren't taking affect. This issue exists for a long time on
NuttX, in fact BayLibre's presentation from 2017 make jokes about our
building system not been reliable:
https://www.youtube.com/watch?v=XUJK2htXxKw&t=320s

Stale archive members from $(AR)'s additive-only behavior can linger
after Kconfig toggles change which files provide a symbol, causing dead
weight or "multiple definition" link errors on incremental builds.
Fixed by splitting ARCHIVE into two macros: ARCHIVE keeps the original
additive behavior for apps/libapps.a, which many independent
subdirectories contribute to across a build, while the new
ARCHIVE_REBUILD deletes then archives for the far more common case
of a single Makefile building its own self-contained $(OBJS)
- all 39 such call sites now use it.

Assisted-By: Claude Sonnet 5
Signed-off-by: Alan C. Assis <acassis@gmail.com>
2026-07-28 21:26:03 -03:00
simbit18
c92db4440e arch/tricore: nxstyle fix Relative files path
- fix Relative file path does not match actual file.

Signed-off-by: simbit18 <simbit18@gmail.com>
2026-07-27 09:44:30 +08:00
zhangyu117
c858f3cc44 arch/tricore: Add hardware debug breakpoint and watchpoint support.
Implement hardware breakpoint and watchpoint support for TriCore
architecture using the Trigger Event (TREVT) registers. This enables
the standard NuttX debugpoint API (up_debugpoint_add/remove) on TriCore
processors, supporting read/write/execute watchpoints and breakpoints
via the on-chip debug unit.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-05-22 15:38:36 +08:00
zhangyu117
02833038fd arch/tricore: Full implementation of setjmp and longjmp.
1. The original method of restoring the register context relies on
   the ret instruction, which does not conform to the semantics of
   longjmp not returning.
2. There are csa leak during longjmp and need recycle.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-05-22 00:38:02 +08:00
zhangyuan29
e087d0f79d arch/tricore: Support setjmp and longjmp.
Add setjmp/longjmp support for TriCore architecture using iLLD
intrinsics to save and restore the CSA (Context Save Area) chain.

This implementation saves upper/lower context registers and walks
the CSA linked list to restore the full call context on longjmp.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-05-22 00:38:02 +08:00
liwenxiang1
bb27808631 arch/tricore: Improve up_backtrace implementation
1. Make tricore_backtrace.c conditional on CONFIG_SCHED_BACKTRACE,
   consistent with RISC-V and ARM architectures.
2. Add NULL return address check to terminate early on invalid entries.
3. Fix non-current task backtrace to use regs[REG_LPCXI] which
   preserves the UL bit needed for correct CSA type identification.

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2026-05-21 11:38:31 +08:00
zhangyu117
356f7c7b47 arch/tricore: Fix up_fpucmp to compare correct CSA region.
up_fpucmp was comparing lower CSA registers (offset 0) using upper CSA
register definitions (REG_D8-D15). Since up_saveusercontext stores:
  - Lower CSA at saveregs[0..15]
  - Upper CSA at saveregs[16..31]

The fix adds TC_CONTEXT_REGS offset to point to the upper CSA and
compares only D8-D15 which are the FPU data registers on TriCore.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-05-21 11:34:14 +08:00
zhangyu117
4e648c1693 tricore/fpu: Support tricore fpucmp for float.
Implement up_fpucmp to compare FPU register state between two
saved contexts. This is used by the ostest FPU test to verify
that FPU registers are properly preserved across context switches.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-05-21 11:34:14 +08:00
zhangyuan29
51ebb21474 tricore: Add fpu init to open FZ trap.
Initialize the FPU and enable the FZ (flush-to-zero) trap for
TriCore TC4xx processors. This ensures floating-point divide-by-zero
exceptions are properly caught and reported via the trap handler.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-05-21 11:34:14 +08:00
zhangyu117
a4e9584715 arch/tricore: optimize perf counter conversion with fast integer division
for tc3xx, without div64 hw inst:
gcc toolchain software way: 684ns
tasking toolchain software way: 3516ns.
invdiv_u64: 182ns

for tc4xx, with div64 hw inst:
div64 hw inst cost 182ns.
invdiv_u64: 125ns

Although there is a delay of tens of nanoseconds for tc4xx, the impact
on performance is minimal, but for simplicity, invdiv_u64 is used.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-05-21 06:29:18 +08:00
zhangyuan29
4f98bb32ae arch/tricore: add up_perf function for tricore
Add performance counter support for TriCore architecture using the
CPU clock counter (CCNT). Implements up_perf_init, up_perf_getfreq,
up_perf_gettime and up_perf_convert interfaces.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-05-21 06:29:18 +08:00
panzihao
191e250cc3 arch/tricore: Suspend stm when CPU stops
Fix break point cause suspend stm still running cause timer paused.

Signed-off-by: panzihao <panzihao@xiaomi.com>
2026-05-20 21:25:28 +08:00
donghaokun
f401467a94 arch/tricore: add TriCore up_backtrace() support
Implement up_backtrace() for TriCore by walking the CSA chain and
collecting return addresses from upper CSA A11 register.

Signed-off-by: LukeKun <donghaokun@lixiang.com>
2026-05-20 09:20:33 +08:00
Piyush Patle
0dccc8ba21 include/debug.h: Move to include/nuttx/debug.h
debug.h is a NuttX-specific, non-POSIX header. Placing it in the
top-level include/ directory creates naming conflicts with external
projects that define their own debug.h.
This commit moves the canonical header to include/nuttx/debug.h,
following the NuttX convention for non-POSIX/non-standard headers,
and updates all in-tree references.

A backward-compatibility shim is left at include/debug.h that
emits a deprecation #warning and re-includes <nuttx/debug.h>,
allowing out-of-tree code to continue building while migrating.

Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
2026-04-07 07:50:06 -03:00
trns1997
219a5ce09e build/cmake/stdlib: guard include/cxx by LIBMINIABI, fix div_t conflict
include/cxx contains NuttX's mini C++ ABI shims and must only be added
to the include path when CONFIG_LIBMINIABI is selected.  tools/Config.mk
was adding it unconditionally for every non-LIBCXX/non-UCLIBCXX build,
and the platform.cmake files for arm, arm64, risc-v, x86_64 and tricore
were adding it inside the CONFIG_LIBCXXTOOLCHAIN block.

With an unpatched downloaded ARM GNU Toolchain, <cstdlib> uses
newlib's stdlib.h, defining div_t as an anonymous struct.  A later
inclusion of NuttX's stdlib.h via <cstdio>->stdio.h->kmalloc.h then
redefines div_t with struct tag div_s, causing a conflicting declaration
error.

Guard the div_t/ldiv_t/lldiv_t definitions in stdlib.h with
redefinitions when a toolchain stdlib.h was already processed.

Also fix lldiv_s members typed as long instead of long long.

Signed-off-by: trns1997 <trns1997@gmail.com>
2026-03-29 16:45:29 -03:00
Lup Yuen Lee
ebc75b0ed5 arch/tricore: Fix --help-- in Kconfig
This PR fixes a typo at `--help--` that causes NuttX Builds to fail, it should have been `---help---`. This is a recurring problem, NuttX CI uses a different way of handling NuttX Configs (it doesn't use `tools/configure.sh`)

https://github.com/lupyuen/nuttx-riscv64/actions/runs/22929878852/job/66548808341#step:5:161
```
$ tools/configure.sh rv-virt:nsh
arch/tricore/Kconfig:124: syntax error
arch/tricore/Kconfig:123: unknown option "--help--"
arch/tricore/Kconfig:124:warning: ignoring unsupported character ','
arch/tricore/Kconfig:124: unknown option "In"
```

Signed-off-by: Lup Yuen Lee <luppy@appkaki.com>
2026-03-11 13:06:13 +08:00
zhangyu117
72be575b1a arch/tricore: support tc4evb board.
add new chip named tc4xx and board tc4evb

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
4be3075a5c arch/tricore: change heap symbol to support multi config
Let the linker script decide the location of the heap.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
5349a0ebc0 tricore/cmake: change tc3xx.cmake to chip.cmake
rename tc3xx.cmake to chip.cmake

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyu117
5b18435f96 arch/tricore: Adjust the related structures of arch and chip.
support tc4evb board, so need adjust some Kconfig

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyu117
c98eccf08d arch/tricore: adjust arch-related irq.h
tc3 and tc4 use common irq.h

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
cb161c2ae3 arch/tricore: include arch.h in irq.h
add arch.h in irq.h

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
zhangyuan29
22db8fbc71 arch/tricore: fixed cxx build issue
perform type conversion to eliminate warnings

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-03-10 10:38:19 +01:00
Maarten Zanders
65207ae1c5 serial/uart_rpmsg: add _raw version of driver
Mainline Linux doesn't use data encapsuation or flow control in its
tty_rpmsg driver. Create a NuttX counterpart which matches this
implementation.
This driver uses the static "rpmsg-tty" name to connect with the
remote service.

Signed-off-by: Maarten Zanders <maarten@zanders.be>
2026-02-23 09:19:57 -03:00
SPRESENSE
72b67832ea Makefile: Remove make depend files by make distclean
Intermediate files of make depend like .ddc and .dds may remain
when make is interrupted. Remove them using make distclean.

Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
2026-02-16 16:27:57 +01:00
donghaokun
cbe13affa1 arch/tricore: initialize spinlock used by tricore systimer
Add explicit spin_lock_init in tricore_systimer_initialize() for the lock used by tricore systimer.

Signed-off-by: Haokun Dong <donghaokun@lixiang.com>
2026-02-11 11:28:52 -03:00
wangzhi16
364a633ec3 sched/signal: Optimize code logic
Adjust the up_schedule_sigaction function to facilitate subsequent spinlock optimization work.

Signed-off-by: wangzhi16 <wangzhi16@xiaomi.com>
2026-01-27 21:24:31 +08:00
liwenxiang1
6d9ed4217a shced/irq: Add up_irq_to_ndx interface
Use architecture-specific up_irq_to_ndx() interface to map IRQ numbers to vector table indices

Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
2026-01-27 10:34:13 +08:00
yukangzhi
b7fd8a268d arch/tricore: add NMI trap handler (weak)
Add support for handling non-maskable interrupts (NMI) on TriCore
platforms. The NMI trap handler `tricore_nmitrap()` is provided as a weak
function that prints diagnostic information and invokes a panic with
register context. The main trap dispatcher will invoke `tricore_nmitrap`
when an NMI trap class is detected.

This change improves diagnostics when watchdog-induced NMIs or other
non-maskable exceptions occur during runtime.

Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
2026-01-24 23:32:03 +08:00
trns1997
9159f6e353 build/cmake: Add toolchain C++ library linking for all platforms.
Extend CONFIG_LIBCXXTOOLCHAIN support to all remaining platforms
in CMake builds by explicitly locating and linking libstdc++.a
from the toolchain. This prevents build failures caused by STL
header/library mismatches where toolchain headers are included
without the corresponding library.
* Adds nuttx_find_toolchain_lib() calls for all platforms.
* Aligns CMake behavior with Make build system.

Signed-off-by: trns1997 <trns1997@gmail.com>
2026-01-24 19:30:21 +08:00
yukangzhi
b82ad5c495 arch/tricore: disable CPU and system watchdogs during startup
Some Aurix Boot-FW configurations leave watchdogs enabled by default,
which can cause unexpected resets during early bring-up. This change
explicitly disables the CPU and system watchdogs during core0 startup to
ensure reliable system initialization.

- For TC3XX chips, call `IfxScuWdt_disableCpuWatchdog()` and
  `IfxScuWdt_disableSafetyWatchdog()`.
- For TC4XX chips, call `IfxWtu_disableCpuWatchdog()` and
  `IfxWtu_disableSystemWatchdog()`.

This is a low-risk startup change and does not alter watchdog behavior
after system initialization.

Signed-off-by: yukangzhi <yukangzhi@xiaomi.com>
2026-01-24 19:29:31 +08:00
hujun5
a3273e6a96 arch: Add stack alignment and stack size checking when CONFIG_TLS_ALIGNED=y
Add validation to ensure allocated stack size does not exceed TLS_MAXSTACK when
CONFIG_TLS_ALIGNED is enabled, and verify proper stack alignment using STACK_ALIGN_MASK
across all architectures. This improves stack safety and prevents potential TLS overflow conditions.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2026-01-22 22:18:11 +08:00
pangzhen1
14efe537bd arch/tricore: add tricore mpu driver
tricore mpu driver code

Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
2026-01-22 16:45:58 +08:00
hujun5
6f03601169 arch: rename STACK_ALIGNMENT to STACKFRAME_ALIGN across all architectures
Rename STACK_ALIGNMENT macro to STACKFRAME_ALIGN throughout the codebase
to provide clearer naming semantics. The new name better reflects the macro's
purpose of frame alignment rather than general stack alignment.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2026-01-22 15:37:24 +08:00
hujun5
63e59e26c0 arch: move some macros to public code.
Move stack alignment and kernel stack macros from architecture-specific internal
headers to public include/nuttx/irq.h. Consolidates duplicate definitions across
17 architecture families, reducing code duplication while enabling common code
to access these core alignment utilities without architecture dependencies.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2026-01-20 01:53:08 +08:00
zhangyu117
9685403038 arch/tricore: modify gpsr init process
for some chips like tc4xx there also corecs, so need init it too.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-01-19 17:51:48 +08:00
zhangyuan29
4775d6dceb arch/tricore: support up_trigger_irq
Enable gpsr and use gpsr to support multicore irq trigger.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-01-19 17:51:48 +08:00
zhangyuan29
f44060ca9f arch/tricore: support minimal vectortalbe in tricore
The SRN number in TriCore far exceeds the PN number.
Using IRQ as the PN number would result in an overflow.
Therefore, MINIMAL_VECTORTABLE is used to ensure that
the PN number does not overflow.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-01-19 17:51:48 +08:00
hujun5
8bb250a4c0 arch: move STACK_ALIGNMENT to irq.h
Move STACK_ALIGNMENT macro definitions from architecture-specific internal
headers to public irq.h headers. This enables common code to directly access
STACK_ALIGNMENT without requiring internal header inclusion, improving code
organization and reducing header dependencies. Applies to all architectures:
ARM, ARM64, AVR, HC, MIPS, or1k, Renesas, RISC-V, SIM, SPARC, TriCore, x86,
x86_64, Xtensa, Z16, and Z80.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2026-01-19 14:43:43 +08:00
makejian
38ba0abc49 arch/tricore: support cache function
Add cache operation support for TriCore architecture including:
- Instruction cache (I-Cache) enable/disable functionality
- Data cache (D-Cache) enable/disable functionality
- Cache configuration and management interfaces
- Performance events integration with cache operations

Signed-off-by: makejian <makejian@xiaomi.com>
Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-01-19 14:13:27 +08:00
makejian
35537cb1a7 tricore/csrm: bringup cpucs in tricore
Add CPUCS bring-up support for TriCore secure core (CSRM) module.
Enables core6 initialization for secure core operations.

Signed-off-by: makejian <makejian@xiaomi.com>
2026-01-18 08:27:38 -03:00
wangchengdong
92f097e354 arch/tricore: Add support to disable signals actions related data struct
Add support to disable signals actions related struct

Co-authored-by: guoshichao <guoshichao@xiaomi.com>
Signed-off-by: Chengdong Wang <wangchengdong@lixiang.com>
2026-01-18 08:24:13 -03:00
hujun5
657ac8317e arch: fix addrenv_switch changing this_task causing exceptions
After addrenv_switch(), the current running task (this_task) may change due to
deferred work execution. Update all architecture interrupt, syscall, and exit
handlers to re-fetch tcb = this_task() after addrenv_switch(). Ensures scheduler
and context operations use the correct TCB, preventing context corruption and
exceptions across SMP and memory-protected builds.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2026-01-17 18:23:06 -03:00
ligd
113bb02568 checkstack: fix access overflow when checkstack
We should check length first, and then check the value

Signed-off-by: ligd <liguiding1@xiaomi.com>
2026-01-17 18:04:28 -03:00
zhangyu117
4e40393cc4 arch/tricore: record trapinfo for coredump
use global var record trap type and reason info for coredump

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-01-15 16:09:13 -03:00
zhangyuan29
31adcde41b arch/tricore: use PRId32 to fixed the correct int type
remove some compilation warnings.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
2026-01-15 16:09:13 -03:00
zhangyu117
2a76bc9d5b arch/tricore: dump special registers about trap
In addition to general-purpose registers, tricore also provides special trap registers to record exception scenarios.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-01-15 16:09:13 -03:00
zhangyu117
909e63b63b arch/tricore: upcsa/lowcsa process && dumpinfo
tricore csa is not continuous. when assert prints information, we need to handle the regs specially in order to dump all the registers.

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-01-15 16:09:13 -03:00
liwenxiang1
641d52fefa arch/tricore: Adapt to Trap Exception Display
When an exception occurs, print the exception type and reason.

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
2026-01-15 16:09:13 -03:00
zhangyu117
8786c814f0 arch/tricore: syscall SYS_switch_context and SYS_restore_context use 0 para
after task switch optimization, we can just use g_running_tasks and this_task() without pass params

Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
2026-01-15 11:37:12 +08:00