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arch/tricore: use PRId32 to fixed the correct int type

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remove some compilation warnings.

Signed-off-by: zhangyuan29 <zhangyuan29@xiaomi.com>
This commit is contained in:
zhangyuan29 2025-03-13 22:51:09 +08:00 • committed by Alan C. Assis
parent 2a76bc9d5b
commit 31adcde41b
2 changed files with 30 additions and 20 deletions
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36
arch/tricore/src/common/tricore_registerdump.c
View file

@ -45,13 +45,17 @@
void tricore_dump_upcsa(volatile uint32_t *regs)
{
_alert("UPCXI:%08x PSW:%08x SP:%08x PC:%08x\n",
_alert("UPCXI:%-13.8" PRIX32 "PSW:%-15.8" PRIX32
"SP:%-16.8" PRIX32 "A11:%-15.8" PRIX32 "\n",
regs[REG_UPCXI], regs[REG_PSW], regs[REG_A10], regs[REG_UA11]);
_alert("D8:%08x D9:%08x D10:%08x D11:%08x\n",
_alert("D8:%-16.8" PRIX32 "D9:%-16.8" PRIX32
"D10:%-15.8" PRIX32 "D11:%-15.8" PRIX32 "\n",
regs[REG_D8], regs[REG_D9], regs[REG_D10], regs[REG_D11]);
_alert("A12:%08x A13:%08x A14:%08x A15:%08x\n",
_alert("A12:%-15.8" PRIX32 "A13:%-15.8" PRIX32
"A14:%-15.8" PRIX32 "A15:%-15.8" PRIX32 "\n",
regs[REG_A12], regs[REG_A13], regs[REG_A14], regs[REG_A15]);
_alert("D12:%08x D13:%08x D14:%08x D15:%08x\n\n",
_alert("D12:%-15.8" PRIX32 "D13:%-15.8" PRIX32
"D14:%-15.8" PRIX32 "D15:%-15.8" PRIX32 "\n\n",
regs[REG_D12], regs[REG_D13], regs[REG_D14], regs[REG_D15]);
}
@ -61,14 +65,18 @@ void tricore_dump_upcsa(volatile uint32_t *regs)
void tricore_dump_lowcsa(volatile uint32_t *regs)
{
_alert("LPCXI:%08x A11:%08x A2:%08x A3:%08x\n",
_alert("LPCXI:%-13.8" PRIX32 "PC:%-16.8" PRIX32
"A2:%-16.8" PRIX32 "A3:%-16.8" PRIX32 "\n",
regs[REG_LPCXI] | PCXI_UL, regs[REG_LA11],
regs[REG_A2], regs[REG_A3]);
_alert("D0:%08x D1:%08x D2:%08x D3:%08x\n",
_alert("D0:%-16.8" PRIX32 "D1:%-16.8" PRIX32
"D2:%-16.8" PRIX32 "D3:%-16.8" PRIX32 "\n",
regs[REG_D0], regs[REG_D1], regs[REG_D2], regs[REG_D3]);
_alert("A4:%08x A5:%08x A6:%08x A7:%08x\n",
_alert("A4:%-16.8" PRIX32 "A5:%-16.8" PRIX32
"A6:%-16.8" PRIX32 "A7:%-16.8" PRIX32 "\n",
regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
_alert("D4:%08x D5:%08x D6:%08x D7:%08x\n\n",
_alert("D4:%-16.8" PRIX32 "D5:%-16.8" PRIX32
"D6:%-16.8" PRIX32 "D7:%-16.8" PRIX32 "\n\n",
regs[REG_D4], regs[REG_D5], regs[REG_D6], regs[REG_D7]);
}
@ -80,25 +88,25 @@ void tricore_dump_trapctrl(void)
{
_alert("PSTR:%-14.8" PRIX32 "DSTR:%-14.8" PRIX32
"DATR:%-14.8" PRIX32 "DEADD:%-13.8" PRIX32 "\n\n",
__mfcr(CPU_PSTR), __mfcr(CPU_DSTR),
__mfcr(CPU_DATR), __mfcr(CPU_DEADD));
(uint32_t)__mfcr(CPU_PSTR), (uint32_t)__mfcr(CPU_DSTR),
(uint32_t)__mfcr(CPU_DATR), (uint32_t)__mfcr(CPU_DEADD));
}
/****************************************************************************
* Name: tricore_csachain_dump
* Name: tricore_dump_csachain
****************************************************************************/
void tricore_csachain_dump(uintptr_t pcxi)
void tricore_dump_csachain(uintptr_t pcxi)
{
while (pcxi & FCX_FREE)
{
if (pcxi & PCXI_UL)
{
tricore_dump_upcsa(tricore_csa2addr(pcxi));
tricore_dump_upcsa((uint32_t *)tricore_csa2addr(pcxi));
}
else
{
tricore_dump_lowcsa(tricore_csa2addr(pcxi));
tricore_dump_lowcsa((uint32_t *)tricore_csa2addr(pcxi));
}
pcxi = tricore_csa2addr(pcxi)[0];

14
arch/tricore/src/common/tricore_trapcall.c
View file

@ -51,7 +51,8 @@
int tricore_mmutrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! MMU Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n", IfxCpu_Trap_Class_memoryManagement,
_alert("\tClass %d TID: %" PRId32 " regs: %p\n",
IfxCpu_Trap_Class_memoryManagement,
tid, context);
_alert("MMU Trap Reason:\n");
@ -73,7 +74,7 @@ int tricore_mmutrap(uint32_t tid, void *context, void *arg)
int tricore_internalprotrape(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Internal Protection Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n",
_alert("\tClass %d TID: %" PRId32 " regs: %p\n",
IfxCpu_Trap_Class_internalProtection, tid, context);
_alert("Internal Protection Reason:\n");
@ -121,7 +122,7 @@ int tricore_internalprotrape(uint32_t tid, void *context, void *arg)
int tricore_insterrorstrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Instruction Errors Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n",
_alert("\tClass %d TID: %" PRId32 " regs: %p\n",
IfxCpu_Trap_Class_instructionErrors, tid, context);
_alert("Instruction Errors Trap Reason:\n");
@ -158,7 +159,7 @@ int tricore_insterrorstrap(uint32_t tid, void *context, void *arg)
int tricore_contexmnttrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Context Management Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n",
_alert("\tClass %d TID: %" PRId32 " regs: %p\n",
IfxCpu_Trap_Class_contextManagement, tid, context);
_alert("Context Management Reason:\n");
@ -205,7 +206,7 @@ int tricore_contexmnttrap(uint32_t tid, void *context, void *arg)
int tricore_bustrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! System Bus Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n", IfxCpu_Trap_Class_bus,
_alert("\tClass %d TID: %" PRId32 " regs: %p\n", IfxCpu_Trap_Class_bus,
tid, context);
_alert("System Bus Reason:\n");
@ -252,7 +253,8 @@ int tricore_bustrap(uint32_t tid, void *context, void *arg)
int tricore_assertiontrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Assertion Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n", IfxCpu_Trap_Class_assertion,
_alert("\tClass %d TID: %" PRId32 " regs: %p\n",
IfxCpu_Trap_Class_assertion,
tid, context);
_alert("System Bus Reason:\n");