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arch/tricore: Adapt to Trap Exception Display

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When an exception occurs, print the exception type and reason.

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
This commit is contained in:
liwenxiang1 2024-11-19 15:19:18 +08:00 • committed by Alan C. Assis
parent 2662473b83
commit 641d52fefa
2 changed files with 272 additions and 0 deletions
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10
arch/tricore/src/common/tricore_registerdump.c
View file

@ -45,4 +45,14 @@
void up_dump_register(void *dumpregs)
{
volatile uint32_t *regs = dumpregs;
_alert("PCXI:%08x PSW:%08x SP:%08x PC:%08x\n",
regs[REG_UPCXI], regs[REG_PSW], regs[REG_A10], regs[REG_UA11]);
_alert("D8:%08x D9:%08x D10:%08x D11:%08x\n",
regs[REG_D8], regs[REG_D9], regs[REG_D10], regs[REG_D11]);
_alert("A12:%08x A13:%08x A14:%08x A15:%08x\n",
regs[REG_A12], regs[REG_A13], regs[REG_A14], regs[REG_A15]);
_alert("D12:%08x D13:%08x D14:%08x D15:%08x\n\n",
regs[REG_D12], regs[REG_D13], regs[REG_D14], regs[REG_D15]);
}

262
arch/tricore/src/common/tricore_trapcall.c
View file

@ -48,6 +48,229 @@
* Public Functions
****************************************************************************/
int tricore_mmutrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! MMU Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n", IfxCpu_Trap_Class_memoryManagement,
tid, context);
_alert("MMU Trap Reason:\n");
if (tid == IfxCpu_Trap_MemoryManagement_Id_virtualAddressFill)
{
_alert("\tVirtual Address Fill\n");
}
if (tid == IfxCpu_Trap_MemoryManagement_Id_virtualAddressProtection)
{
_alert("\tVirtual Address Protection\n");
}
up_irq_save();
PANIC_WITH_REGS("panic", context);
return OK;
}
int tricore_internalprotrape(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Internal Protection Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n",
IfxCpu_Trap_Class_internalProtection, tid, context);
_alert("Internal Protection Reason:\n");
if (tid == IfxCpu_Trap_InternalProtection_Id_privilegeViolation)
{
_alert("\tPrivileged Instruction\n");
}
if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionRead)
{
_alert("\tMemory Protection Read\n");
}
if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionWrite)
{
_alert("\tMemory Proteciton Write\n");
}
if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionExecute)
{
_alert("\tMemory Protection Execution\n");
}
if (tid ==
IfxCpu_Trap_InternalProtection_Id_memoryProtectionPeripheralAccess)
{
_alert("\tMemory Protection Peripheral Access\n");
}
if (tid == IfxCpu_Trap_InternalProtection_Id_memoryProtectionNullAddress)
{
_alert("\tMemory Protection Null Address\n");
}
if (tid == IfxCpu_Trap_InternalProtection_Id_globalRegisterWriteProtection)
{
_alert("\tGlobal Register Write Protection\n");
}
up_irq_save();
PANIC_WITH_REGS("panic", context);
return OK;
}
int tricore_insterrorstrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Instruction Errors Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n",
IfxCpu_Trap_Class_instructionErrors, tid, context);
_alert("Instruction Errors Trap Reason:\n");
if (tid == IfxCpu_Trap_InstructionErrors_Id_illegalOpcode)
{
_alert("\tIllegal Opcode\n");
}
if (tid == IfxCpu_Trap_InstructionErrors_Id_unimplementedOpcode)
{
_alert("\tUnimplemented Opcode\n");
}
if (tid == IfxCpu_Trap_InstructionErrors_Id_invalidOperand)
{
_alert("\tInvalid Operand Specification\n");
}
if (tid == IfxCpu_Trap_InstructionErrors_Id_dataAddressAlignment)
{
_alert("\tData Address Alignment\n");
}
if (tid == IfxCpu_Trap_InstructionErrors_Id_invalidMemoryAddress)
{
_alert("\tInvalid Local Memory Address\n");
}
up_irq_save();
PANIC_WITH_REGS("panic", context);
return OK;
}
int tricore_contexmnttrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Context Management Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n",
IfxCpu_Trap_Class_contextManagement, tid, context);
_alert("Context Management Reason:\n");
if (tid == IfxCpu_Trap_ContextManagement_Id_freeContextListDepletion)
{
_alert("\tFree Context List Depletion\n");
}
if (tid == IfxCpu_Trap_ContextManagement_Id_callDepthOverflow)
{
_alert("\tCall Depth Overflow\n");
}
if (tid == IfxCpu_Trap_ContextManagement_Id_callDepthUnderflow)
{
_alert("\tCall Depth Underflow\n");
}
if (tid == IfxCpu_Trap_ContextManagement_Id_freeContextListUnderflow)
{
_alert("\tFree Context List Underflow\n");
}
if (tid == IfxCpu_Trap_ContextManagement_Id_callStackUnderflow)
{
_alert("\tCall Stack Underflow\n");
}
if (tid == IfxCpu_Trap_ContextManagement_Id_contextType)
{
_alert("\tContext Type\n");
}
if (tid == IfxCpu_Trap_ContextManagement_Id_nestingError)
{
_alert("\tNesting Error:RFE with non-zero call depth\n");
}
up_irq_save();
PANIC_WITH_REGS("panic", context);
return OK;
}
int tricore_bustrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! System Bus Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n", IfxCpu_Trap_Class_bus,
tid, context);
_alert("System Bus Reason:\n");
if (tid == IfxCpu_Trap_Bus_Id_programFetchSynchronousError)
{
_alert("\tProgram Fetch Synchronous Error\n");
}
if (tid == IfxCpu_Trap_Bus_Id_dataAccessSynchronousError)
{
_alert("\tData Access Synchronous Error\n");
}
if (tid == IfxCpu_Trap_Bus_Id_dataAccessAsynchronousError)
{
_alert("\tData Access Asysnchronous Error\n");
}
if (tid == IfxCpu_Trap_Bus_Id_CoprocessorTrapAsynchronousError)
{
_alert("\tCoprocessor Trap Asynchronous Error\n");
}
if (tid == IfxCpu_Trap_Bus_Id_programMemoryIntegrityError)
{
_alert("\tProgram Memory Integrity Error\n");
}
if (tid == IfxCpu_Trap_Bus_Id_dataMemoryIntegrityError)
{
_alert("\tData Memory Integrity Error\n");
}
if (tid == IfxCpu_Trap_Bus_Id_temporalAsynchronousError)
{
_alert("\tTemporal Asynchronous Error\n");
}
up_irq_save();
PANIC_WITH_REGS("panic", context);
return OK;
}
int tricore_assertiontrap(uint32_t tid, void *context, void *arg)
{
_alert("PANIC!!! Assertion Trap:\n");
_alert("\tClass %d TID: %d regs: %p\n", IfxCpu_Trap_Class_assertion,
tid, context);
_alert("System Bus Reason:\n");
if (tid == IfxCpu_Trap_Assertion_Id_arithmeticOverflow)
{
_alert("\tArithmetic Overflow\n");
}
if (tid == IfxCpu_Trap_Assertion_Id_stickyArithmeticOverflow)
{
_alert("\tSticky Arithmetic Overflow\n");
}
up_irq_save();
PANIC_WITH_REGS("panic", context);
return OK;
}
/****************************************************************************
* Name: tricore_trapcall
*
@ -59,11 +282,50 @@
void tricore_trapcall(volatile void *trap)
{
uintptr_t *regs;
IfxCpu_Trap *ctrap = (IfxCpu_Trap *)trap;
IfxCpu_Trap_Class tclass = (IfxCpu_Trap_Class)ctrap->tClass;
unsigned int tid = ctrap->tId;
regs = tricore_csa2addr(__mfcr(CPU_PCXI));
up_set_interrupt_context(true);
if (tclass == IfxCpu_Trap_Class_memoryManagement)
{
tricore_mmutrap(tid, regs, NULL);
return;
}
if (tclass == IfxCpu_Trap_Class_internalProtection)
{
tricore_internalprotrape(tid, regs, NULL);
return;
}
if (tclass == IfxCpu_Trap_Class_instructionErrors)
{
tricore_insterrorstrap(tid, regs, NULL);
return;
}
if (tclass == IfxCpu_Trap_Class_contextManagement)
{
tricore_contexmnttrap(tid, regs, NULL);
return;
}
if (tclass == IfxCpu_Trap_Class_bus)
{
tricore_bustrap(tid, regs, NULL);
return;
}
if (tclass == IfxCpu_Trap_Class_assertion)
{
tricore_assertiontrap(tid, regs, NULL);
return;
}
up_irq_save();
PANIC_WITH_REGS("Trap", regs);
}