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On U5 LSION is in RCC_BDCR, which is write-protected after reset. Without PWR DBP set the LSION write is ignored and stm32_rcc_enablelsi() waits forever for LSIRDY. - Add STM32_HAVE_IP_PWR_M33_V1 (U5) to the common PWR register dispatcher and the common stm32_pwr.h, so common code can reach the U5 PWR definitions and stm32_pwr_enablebkp(). - Rename stm32u5/hardware/stm32_pwr.h to stm32u5xx_pwr.h, so the common dispatcher can include it. - In stm32_lsi.c enable backup domain write access around the BDCR update, as the common LSE drivers do. Signed-off-by: raiden00pl <raiden00@railab.me> Assisted-by: Claude Code |
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| CMakeLists.txt | ||
| Kconfig | ||