nuttx/arch/mips
Daniel P. Carvalho ecfe2ed4d3 arch/mips/pic32mz: support GPIO interrupts on the PIC32MZ-W1.
The change notification code assumed the EC/EF layout: the IRQ of an
I/O port was PIC32MZ_IRQ_PORTA plus the port index, and initialization
reset the change notification registers of every port index.  The
PIC32MZ-W1 only implements PORTA, PORTB, PORTC and PORTK, its change
notification vectors are PIC32MZ_IRQ_CNA/CNB/CNC/CNK, and the addresses
of the missing ports D-J belong to other peripherals (I2C1 is at the
PORTE address).

Map the port index to its IRQ through a table on the W1, skip the
unimplemented ports during initialization, and pass the port index to
the common handler as its argument instead of deriving it from the IRQ
number.  Hide the PORTD-PORTJ interrupt options on the W1.

Assisted-by: Claude Code:claude-opus-5-5
Signed-off-by: Daniel P. Carvalho <danieloak@gmail.com>
2026-10-09 17:55:25 +08:00
..
include arch/mips/pic32mz: add PIC32MZ-W1 (WFI32E01) support. 2026-10-08 16:17:04 -03:00
src arch/mips/pic32mz: support GPIO interrupts on the PIC32MZ-W1. 2026-10-09 17:55:25 +08:00
Kconfig !sched/arch/libc: Give fork() and vfork() their real, separate semantics. 2026-08-10 08:57:30 -03:00