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nuttx/arch/arm
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raiden00pl db514c3e63 arch/arm/src/common/stm32: enable backup domain access for LSI on U5 
On U5 LSION is in RCC_BDCR, which is write-protected after reset.
Without PWR DBP set the LSION write is ignored and stm32_rcc_enablelsi()
waits forever for LSIRDY.

- Add STM32_HAVE_IP_PWR_M33_V1 (U5) to the common PWR register
  dispatcher and the common stm32_pwr.h, so common code can reach the
  U5 PWR definitions and stm32_pwr_enablebkp().
- Rename stm32u5/hardware/stm32_pwr.h to stm32u5xx_pwr.h, so the common
  dispatcher can include it.
- In stm32_lsi.c enable backup domain write access around the BDCR
  update, as the common LSE drivers do.

Signed-off-by: raiden00pl <raiden00@railab.me>
Assisted-by: Claude Code
2026-10-10 02:11:46 +08:00
..
include arch/arm/rp23xx: Add suspend to RAM in the POWMAN P1.0 state. 2026-10-09 06:17:57 -03:00
src arch/arm/src/common/stm32: enable backup domain access for LSI on U5 2026-10-10 02:11:46 +08:00
CMakeLists.txt
Kconfig arch/arm/rp23xx: Add the PM standby and dormant states. 2026-10-09 06:17:57 -03:00